Semiconductor device package and method of manufacturing the same

Abstract

A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a circuit layer and an antenna module. The circuit layer has a first surface, a second surface opposite to the first surface, and a side surface. The side surface extends between the first surface and the second surface. The circuit layer has an interconnection structure. The antenna module has an antenna pattern layer and is disposed on the first surface of the circuit layer. The side surface of the circuit layer is substantially coplanar with a side surface of the antenna module.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device package and a method for manufacturing the same, and specifically to a semiconductor device package including an antenna module and a method for manufacturing the same. Background Technology

[0002] For example, wireless communication devices such as mobile phones typically include antennas for transmitting and receiving radio frequency (RF) signals. In recent years, with the continuous development of mobile communications and the urgent need for high data rates and stable communication quality, relatively high-frequency wireless transmissions (such as 28 GHz or 60 GHz) have become one of the most important topics in the mobile communications industry.

[0003] In comparative wireless communication devices, antennas and circuitry (e.g., radio frequency (RF) reference circuitry or digital circuitry) are mounted on a printed circuit board (PCB) or substrate. However, fine-tuning the antenna is difficult. Furthermore, the overall size of wireless communication devices is relatively large, thus limiting flexibility in RF design. Summary of the Invention

[0004] According to some embodiments of this disclosure, a semiconductor device package is provided. The semiconductor device package includes a circuit layer, an antenna module, metal pillars, and an encapsulation body. The circuit layer has a first surface and a second surface opposite to the first surface. The antenna module has an antenna pattern layer and is disposed on the first surface of the circuit layer. The metal pillars are electrically connected between the antenna pattern layer and the first surface of the circuit layer. The encapsulation body covers at least a portion of the sidewalls of the metal pillars. A passivation layer is disposed between the encapsulation body and the antenna pattern layer.

[0005] According to some embodiments of this disclosure, a semiconductor device package is provided. The semiconductor device package includes an encapsulation body, a circuit layer, and an antenna patterning layer. The encapsulation body has a first surface and a second surface opposite to the first surface. The circuit layer is disposed on the first surface. The antenna patterning layer is disposed on the second surface. The encapsulation body has a notch from the first surface.

[0006] According to some embodiments of this disclosure, a method for manufacturing a semiconductor device is provided. The method includes: forming an antenna pattern layer; forming conductive pillars on the antenna pattern layer; forming an encapsulation to cover the conductive pillars and expose the top surface of the conductive pillars; forming a ground layer on the top surface of the conductive pillars exposed from the encapsulation; and forming a circuit layer on the ground layer. Attached Figure Description

[0007] When read in conjunction with the accompanying drawings, various aspects of this disclosure will be readily understood from the following detailed description. It should be noted that the features may not be drawn to scale, and the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1 A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is provided.

[0009] Figure 2 This illustration shows a cross-sectional view of a portion of a semiconductor device package according to some embodiments of the present disclosure.

[0010] Figure 3 A cross-sectional view of a semiconductor device package 3 according to some embodiments of the present disclosure is shown.

[0011] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J , Figure 4K , Figure 4L , Figure 4M as well as Figure 4N This invention describes a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0012] Figure 5A , Figure 5B , Figure 5C , Figure 5D as well as Figure 5E This invention describes a method for manufacturing a portion of a semiconductor device package according to some embodiments of the present disclosure.

[0013] Figure 6A , Figure 6B , Figure 6C as well as Figure 6D This invention describes a method for manufacturing a portion of a semiconductor device package according to some embodiments of the present disclosure. Detailed Implementation

[0014] This disclosure provides a semiconductor device package and a method for manufacturing the same. Embodiments of the semiconductor device package and method described herein provide semiconductor device packages that reduce the thickness of the semiconductor device package. The design of the semiconductor device package of this disclosure increases the flexibility of RF design. In the semiconductor device package of this disclosure, seals, printed circuit boards, or package substrates can be omitted, and therefore better X / Y dimensional tolerances can be achieved. The design of the semiconductor device package of this disclosure can shorten RF and single transmit paths. The final chip design of the semiconductor device package can improve yield.

[0015] Figure 1 A cross-sectional view of a semiconductor device package 1 according to some embodiments of the present disclosure is shown. The semiconductor device package 1 includes a circuit layer 11, an antenna module 12, electronic components 13, and electrical contacts 14. In some embodiments, the semiconductor device package 1 may be a wireless communication device or a part of a wireless communication device.

[0016] The circuit layer 11 has a surface 111, a surface 112, and side surfaces 11s. Surface 112 is opposite to surface 111. Side surfaces 11s extend between surface 111 and surface 112. The circuit layer 11 has an interconnect structure 11i (or electrical connection), such as a redistribution layer (RDL). The circuit layer 11 includes a dielectric layer 11d. A portion of the interconnect layer 11i is covered or encapsulated by the dielectric layer 11d, while another portion of the interconnect layer 11i is exposed from the dielectric layer 11d to provide electrical connections. In some embodiments, the dielectric layer 11d may comprise an organic material, solder mask, polyimide (PI), epoxy resin, Ajinomoto deposited film (ABF), one or more molding materials, one or more prepreg composite fibers (e.g., prepreg fibers), borosilicate glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, undoped silicate glass (USG), any combination thereof, or the like. Examples of molding materials may include, but are not limited to, epoxy resins containing fillers dispersed therein. Examples of prepreg fibers may include, but are not limited to, multilayer structures formed by stacking or laminating one or more prepreg materials or sheets. In some embodiments, dielectric layer 11d may comprise inorganic materials, such as silicon, ceramics, or the like. In some embodiments, depending on design specifications, any number of interconnect layers 11i may be present. Circuit layer 11 may include one or more conductive pads that are adjacent to, embedded in, or exposed on surfaces 112 or 111 of circuit layer 11.

[0017] Antenna module 12 is disposed on and electrically connected to the circuit layer 11, surface 111. In some embodiments, antenna module 12 is in contact with circuit layer 11. For example, there is no gap between antenna module 12 and circuit layer 11. Antenna module 12 has surface 121, surface 122, and side surface 12s. Surface 122 is opposite to surface 121. Side surface 12s extends between surface 121 and surface 122. Side surface 11s of circuit layer 11 and side surface 12s of antenna module 12 are substantially coplanar. In some embodiments, antenna module 12 has an antenna pattern layer 12a, a ground layer 12g, metal pillars 12p, an encapsulation body 12e, and a passivation layer 12d. Antenna pattern layer 12a is disposed adjacent to surface 121 of antenna module 12. Ground layer 12g is disposed adjacent to surface 122 of antenna module 12. Ground layer 12g of antenna module 12 is in contact with first surface 111 of circuit layer 11. The ground plane 12g of the antenna module 12 is electrically connected to the circuit plane 11.

[0018] The antenna pattern layer 12a is or comprises a conductive material, such as a metal or metal alloy. Examples of conductive materials include gold (Au), silver (Ag), aluminum (Al), copper (Cu), or alloys thereof. In some embodiments, the antenna pattern layer 12a may comprise a single antenna element. In some embodiments, the antenna pattern layer 12a may comprise multiple antenna elements. For example, the antenna pattern layer 12a may comprise an M×N array of antenna elements, where M or N is an integer greater than 1. In some embodiments, depending on design specifications, M may be the same as or different from N. In some embodiments, the antenna pattern 12a may be a patch antenna, a dipole antenna, a horn antenna, a loop antenna, a planar inverted-F antenna (PIFA), or any other antenna.

[0019] In some embodiments, the ground layer 12g is in contact with the circuit layer 11. For example, there is no gap between the ground layer 12g and the circuit layer 11. For example, the ground layer 12g may be covered by the dielectric layer 11d of the circuit layer 11. The ground layer 12g is or comprises a conductive material such as a metal or metal alloy. Examples of conductive materials include Au, Ag, Al, Cu, or alloys thereof.

[0020] Metal pillars 12p (e.g., Cu pillars) are electrically connected between the antenna pattern layer 12a and the ground layer 12g. For example, the metal pillars 12p penetrate the enclosure 12e to electrically connect the antenna pattern layer 12a and the ground layer 12g. In some embodiments, the metal pillars 12 are electrically connected to the feed point of the antenna pattern layer 12a for signal transmission between the antenna pattern layer 12a and the ground layer 12g and / or other electronic components (e.g., RF circuitry, passive components, or circuit boards). In some embodiments, the number of metal pillars 12 may be adjusted depending on different design requirements.

[0021] Encapsulation 12e is disposed between antenna pattern layer 12a and ground layer 12g. Encapsulation 12e covers at least a portion of the side surface of metal post 12p and exposes the upper and lower surfaces of metal post 12 for electrical connection. Encapsulation 12e comprises a material having a relatively low dielectric constant. In some embodiments, encapsulation 12e comprises epoxy resin with filler, molding material (e.g., epoxy molding material or other molding material), polyimide, phenolic compound or material, material wherein silicone is dispersed, or a combination thereof.

[0022] A passivation layer 12d is disposed on two surfaces (e.g., top and bottom surfaces) of the encapsulation 12e. The passivation layer 12d covers at least a portion of the antenna pattern layer 12a and the ground layer 12g. In some embodiments, the passivation layer 12d comprises a material having relatively low Dk and Df. For example, the passivation layer 12d may comprise a dielectric material such as polyimide (PI) or a photosensitive material.

[0023] Electronic component 13 is disposed on surface 112 of circuit layer 11 and electrically connected to circuit layer 11 (e.g., electrically connected to interconnect structure 11i of circuit layer 11). In some embodiments, antenna module 12 is electrically connected to antenna module 12 via interconnect structure 11i within circuit layer 11. In other embodiments, electronic component 13 may be electrically connected to antenna module 12 via electromagnetic coupling. Electronic component 13 may be a chip or die containing a semiconductor substrate, one or more integrated circuit devices, and one or more overlying interconnect structures. Integrated circuit devices may include active devices such as transistors and / or passive devices such as resistors, capacitors, inductors, or combinations thereof. For example, electronic component 13 may include RF circuitry, digital circuitry, and / or mixed-signal circuitry. In some embodiments, the number or type of electronic component 13 may vary depending on different design requirements.

[0024] Electrical contacts 14 (e.g., solder balls) are disposed on surface 112 of circuit layer 11 and electrically connected to circuit layer 11 (e.g., electrically connected to interconnect structure 11i of circuit layer 11). Electrical contacts 14 provide electrical connections between semiconductor device package 1 and external components (e.g., external circuitry or circuit board). In some embodiments, electrical contacts 14 include controlled collapse chip connection (C4) bumps, ball grid array (BGA), or land grid array (LGA).

[0025] In some comparative wireless communication devices, RF and digital circuitry are mounted on a PCB or substrate, and the antenna pattern is formed on the PCB or substrate. However, if the performance of the antenna pattern fails to meet expectations, it is difficult to adjust (fine-tune) the antenna pattern's performance. Furthermore, even if one of the antennas or circuitry fails, the entire wireless communication device will be considered faulty, which will reduce the yield rate of manufacturing wireless communication devices. According to... Figure 1 In the embodiment shown, antenna module 12 is a separate module, and its performance can be adjusted (fine-tuned). Furthermore, if either antenna module 1 or electronic component 21 is defective, it can be individually changed or replaced. This improves the yield rate of manufacturing wireless communication devices. Furthermore, according to... Figure 1 In the embodiments shown, the antenna module 12 does not need to be mounted on a seal, printed circuit board, or package substrate. Therefore, the overall thickness of the semiconductor device package according to embodiments of this disclosure can be reduced.

[0026] Furthermore, since the antenna module 12 is in direct contact with the circuit layer 11, the transmission path between the antenna module 12 and the circuit layer 11 (or between the antenna module 12 and the electronic component 13) is shortened. This reduces the transmission loss of signals transmitted between the antenna module 12 and the circuit layer 11 (or between the antenna module 12 and the electronic component 13), and in turn improves the performance of the semiconductor device package 1.

[0027] Figure 2 This illustration shows a cross-sectional view of a portion of a semiconductor device package according to some embodiments of the present disclosure. For example, Figure 2 The structure shown is enclosed by a dotted line rectangle. Figure 1 The image shows an enlarged view of part 2 of the semiconductor device package 1.

[0028] See Figure 2 The metal pillar 12p has a surface 12p1 adjacent to the ground layer 12g. In some embodiments, surface 12p1 is non-planar. For example, a portion of surface 12p1 of the metal pillar 12p is recessed from surface 12e1 of the encapsulation 12e facing the circuit layer 11. A portion of surface 12p1 of the metal pillar 12p has a curved surface. The curved surface is positioned adjacent to the interface between the metal pillar 12p and the encapsulation 12e. A gap G is defined between the encapsulation 12e and the metal pillar 12p. The gap G is filled by a passivation layer 12d.

[0029] The passivation layer 12d of the antenna module 12 covers a portion of the encapsulation 12e and a portion of the metal pillar 12p. For example, the passivation layer 12d covers the surface 12e1 of the encapsulation 12e and the surface 12p1 of the metal pillar 12p. The passivation layer 12d is disposed within the gap G. The passivation layer 12d covers the curved surface of the metal pillar 12p.

[0030] Because the surface 12p1 of the metal pillar 12p has a curved surface, it allows the antenna module 12 to mitigate / reduce / avoid parasitic effects. Because the surface 12p1 of the metal pillar 12p has a relatively small surface roughness, it improves the RF transmission loss problem of the antenna module 12.

[0031] Figure 3 This illustration shows a cross-sectional view of a semiconductor device package 3 according to some embodiments of the present disclosure. The semiconductor device package 3 is similar to... Figure 1 The semiconductor device package 1 is described below, and the differences therebetween are further explained.

[0032] The encapsulation 12e has a protrusion 12m extending from surface 12e2 of the encapsulation 12e. The protrusion 12m extends into the passivation layer 12d. The protrusion 12m has surfaces 12m1 and 12m2. Surface 12m1 contacts surface 12e2. Surface 12m1 and surface 12e2 are opposite each other. Figure 3 As shown in the diagram, the width of surface 12m1 is greater than the width of surface 12m2. In some embodiments, multiple protrusions may be present in the molded locking structure, and the number of protrusions may be adjusted or changed depending on different design requirements. The protrusions of the encapsulation can increase the connection reliability / stability of the semiconductor device package 3.

[0033] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J , Figure 4K , Figure 4L , Figure 4M as well as Figure 4N This invention describes a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. In some embodiments, Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J , Figure 4K , Figure 4L , Figure 4M as well as Figure 4N The methods described can be used to manufacture, for example... Figure 1 The semiconductor device package 1 shown is illustrated in the figure. In other embodiments, [the following is also mentioned:] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J , Figure 4K , Figure 4L , Figure 4M as well as Figure 4N The methods described can be used to manufacture other semiconductor device packages.

[0034] See Figure 4A A carrier 401 is provided. In some embodiments, the carrier 401 has an adhesive layer (e.g., tape or adhesive film) disposed on the carrier 401. The material of the carrier 401 may be determined depending on different design requirements. In some embodiments, the material of the carrier may comprise glass. (e.g., corresponding to...) Figure 1 The passivation layer 402 (passivation layer 12d) is formed / placed on the carrier 401.

[0035] See Figure 4B , (for example, corresponding to Figure 1 Antenna pattern layer 403 (of antenna pattern layer 12a) is formed on passivation layer 402. Antenna pattern layer 403 covers a portion of passivation layer 402. Antenna pattern layer 403 has one or more openings to expose a portion of passivation layer 402.

[0036] See Figure 4C A passivation layer 404 is formed on the antenna pattern layer 403 and within openings to contact the passivation layer 402 exposed from the antenna pattern layer 403. The passivation layer 404 has one or more openings to expose a portion of the antenna pattern layer 403. Each opening in the passivation layer 404 has a first surface in contact with the antenna pattern layer 403 and a second surface opposite to the first surface. Figure 4C As shown, the width of the second surface is greater than the width of the first surface of the passivation layer 404 opening.

[0037] See Figure 4D , (for example, corresponding to Figure 1 The antenna metal pillars 12p (metal pillars 405) are formed on the antenna patterned layer 403 exposed from the passivation layer 404. Considering the impedance matching, height, and feed point size of the metal pillars 405, the openings for contacting the antenna patterned layer 403 and the metal pillars 405 will be limited. Therefore, smaller openings can be defined by the passivation layer (e.g., a PI layer), and wider openings can be defined by photoresist, allowing the metal pillars 405 to fill the wider openings.

[0038] See Figure 4E, (for example, corresponding to Figure 1 Encapsulation 406 (of encapsulation 12e) is then formed on a portion of passivation layer 404. Encapsulation 406 may completely cover metal pillar 405 (e.g., top and side surfaces of metal pillar 405). Encapsulation 406 may be formed by molding techniques such as transfer molding, compression molding, or any other suitable process.

[0039] See Figure 4F A portion of the encapsulation 406 is removed to expose the top surface 4u of the metal pillar 405. In some embodiments, a portion of the metal pillar 405 may also be removed. In some embodiments, the encapsulation 406 may be removed by, for example, grinding or any other suitable process. In this embodiment, the metal pillar 405 is first formed (e.g., Figure 4D (as shown in the image), then an encapsulation 406 is formed to cover the metal pillar 405 (as shown in the image). Figure 4E (As shown in the illustration). In some other embodiments, the encapsulation 406 may first be formed on the passivation layer 404, and then the encapsulation may be laser-etched to form a via. Next, the via is filled with a conductive material to form a metal pillar 405. Figures 4D to 4F The bonding between the metal pillar 405 and the encapsulation 406 in the embodiment shown is better than in the other embodiments described above.

[0040] See Figure 4G A passivation layer 407 is formed on a portion of the top surface 4u of the encapsulation 406 and the metal pillar 405. The passivation layer 407 has one or more openings to expose a portion of the top surface 4u of the metal pillar 405.

[0041] See Figure 4H , (for example, corresponding to Figure 1 The ground layer 12g) RDL 408 is formed on a portion of the top surface 4u of the metal pillar 405 exposed from the passivation layer 407. RDL 408 covers a portion of the passivation layer 407. RDL 408 has one or more openings to expose a portion of the passivation layer 407.

[0042] See Figure 4I , (for example, corresponding to Figure 1 Dielectric layer 409 (of dielectric layer 11d) is formed on RDL 408 and within openings to contact the passivation layer 407 exposed from RDL 408. Dielectric layer 409 has one or more openings to expose a portion of RDL 408. Each opening of dielectric layer 409 has a first surface contacting RDL 408 and a second surface opposite the first surface. Figure 4I As shown, the width of the second surface is greater than the width of the first surface of the opening in dielectric layer 409. See also Figure 4JThis forms a multi-RDL layer 410. The top surface of the multi-RDL layer 410 has one or more openings.

[0043] See Figure 4K The gasket 411 is formed on a portion of the top surface of the multi-RDL layer 410 and on the openings of the multi-RDL layer 410. See also Figure 4L Electrical contact 412 is disposed on pad 411. In some embodiments, electrical contact 412 includes a controllable collapse chip connection (C4) bump, a ball grid array (BGA), or a connection disk grid array (LGA). See also Figure 4M , (for example, corresponding to Figure 1 Electronic component 413 of electronic component 13 is electrically connected to the multi-RDL layer 410. See also Figure 4N Next, carrier 401 is removed to form such Figure 1 The semiconductor device package shown in the figure 1.

[0044] Figure 5A , Figure 5B , Figure 5C , Figure 5D as well as Figure 5E This describes a method for manufacturing a portion of a semiconductor device package according to some embodiments of the present disclosure. In some embodiments, Figure 5A , Figure 5B , Figure 5C , Figure 5D as well as Figure 5E The methods described can be used to manufacture, for example... Figure 2 Structure 2 is shown in the figure.

[0045] See Figure 5A Set structure 51. Figure 5A Structure 51 and Figure 4E The structure shown in the previous section is the same, and therefore the detailed steps used to form structure 51 will not be repeated here.

[0046] See Figure 5B A portion of the encapsulation is removed to expose the top surface of the metal pillar. In some embodiments, the encapsulation can be removed by, for example, a grinding process, and thus the top surface of the metal pillar can be stretched. The stretched top surface of the metal pillar may cause short-circuit problems.

[0047] See Figure 5C The top surface of the metal pillar is etched / micro-etched, thereby removing the stretched top surface of the metal pillar and forming a gap between the encapsulation and the metal pillar. A portion of the top surface of the etched metal pillar has a curved surface. The top surface of the etched metal pillar is lower than the top surface of the encapsulation.

[0048] See Figure 5DA passivation layer is formed on a portion of the top surface of the encapsulation and the metal pillar. The passivation layer has one or more openings to expose a portion of the top surface of the metal pillar. The passivation layer is then filled into... Figure 5C In the gaps. See Figure 5E RDL408 is formed on the top surface of the metal pillar exposed from the passivation layer.

[0049] Figure 6A , Figure 6B , Figure 6C as well as Figure 6D This describes a method for manufacturing a portion of a semiconductor device package according to some embodiments of the present disclosure. In some embodiments, Figure 6A , Figure 6B , Figure 6C as well as Figure 6D The methods described can be used to manufacture, for example... Figure 3 The protruding portion 12m of the semiconductor device package 3 shown in the figure.

[0050] See Figure 6A A structure 61 is provided having a carrier 401, a passivation layer 402, and an antenna pattern layer 403. Figure 6A Structure 61 and Figure 4B The structure shown in the previous section is the same, and therefore the detailed steps used to form structure 61 will not be repeated here.

[0051] See Figure 6B A passivation layer 404 is formed on the antenna pattern layer 403 and within openings to contact the passivation layer 402 exposed from the antenna pattern layer 403. The passivation layer 404 has one or more openings to expose a portion of the antenna pattern layer 403 and a portion of the passivation layer 402. Figure 6B As shown, the depth of the openings formed in the passivation layer 401 is greater than the depth of the openings formed in the antenna pattern layer 403. Each of the openings in the passivation layer 404 has a first surface that contacts or is adjacent to the passivation layer 401 and a second surface opposite to the first surface. Figure 4C As shown, the width of the second surface is greater than the width of the first surface of the passivation layer 404 opening.

[0052] See Figure 6C , (for example, corresponding to Figure 1 The antenna metal pillars 12p are formed on the antenna pattern layer 403 exposed from the passivation layer 404.

[0053] See Figure 6D , (for example, corresponding to Figure 1Encapsulation 406 (of encapsulation 12e) is then formed on a portion of passivation layer 404 and a portion of passivation layer 401 exposed from an opening in passivation layer 404. Encapsulation 406 may completely cover metal pillar 405 (e.g., the top and sides of metal pillar 405). Encapsulation 406 may be formed by molding techniques such as transfer molding, compression molding, or any other suitable process.

[0054] As used herein, the terms “substantially,” “substantially,” “approximately,” and “about” are used to indicate and explain small variations. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the stated value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. As another example, the thickness of a film or layer being “substantially uniform” may refer to a standard deviation of the average thickness of the film or layer less than or equal to ±10%, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" can refer to two surfaces that lie within a few micrometers along the same plane, for example, within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm along the same plane. If the angle between two surfaces or components is, for example, 90° ± 10°, or ± 5°, ± 4°, ± 3°, ± 2°, ± 1°, ± 0.5°, ± 0.1°, or ± 0.05°, then the two surfaces or components can be considered "substantially perpendicular." When used in conjunction with an event or situation, the terms "substantially," "substantially," "approximately," and "about" can refer to examples where the event or situation occurs precisely, and examples where the event or situation occurs very approximately.

[0055] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include plural indicators. In the description of some embodiments, a component disposed “on” or “above” another component may cover the case where the preceding component is directly on the following component (e.g., in physical contact with the following component), and the case where one or more intermediate components are located between the preceding and following components.

[0056] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to conduct electric current. Conductive materials are generally those that exhibit minimal or zero resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, conductive materials have a conductivity greater than approximately 10. 4 S / m (e.g., at least 10) 5 S / m or at least 10 6 A material with an electrical conductivity of (S / m). The electrical conductivity of the material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of the material is measured at room temperature.

[0057] Additionally, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that this range format is used for convenience and brevity purposes and should be interpreted flexibly to include not only the numerical values ​​explicitly specified as the limits of the range, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0058] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between process reproductions in this disclosure and actual apparatuses due to variations in manufacturing processes, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to be within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not a limitation of this disclosure.

Claims

1. A semiconductor device package comprising: A circuit layer having a first surface; as well as Antenna module, which is disposed on the first surface of the circuit layer and includes: A ground plane that directly contacts the first surface of the circuit layer; Antenna pattern layer; A metal pillar electrically connected between the antenna pattern layer and the ground layer and having a surface facing the first surface of the circuit layer; and An encapsulation covering at least a portion of the side surface of the metal pillar and having a first surface facing the first surface of the circuit layer; and A first passivation layer is disposed between the surface of the encapsulation and the ground layer; The surface of the metal pillar is recessed from the first surface of the encapsulation, such that the surface of the metal pillar has a curved surface and the gap is defined between the encapsulation and the side surface of the metal pillar.

2. The semiconductor device package of claim 1, wherein the circuit layer further includes a second surface opposite to the first surface and a side surface extending between the first surface and the second surface, wherein the side surface of the circuit layer is substantially coplanar with the side surface of the antenna module.

3. The semiconductor device package of claim 1, wherein the first passivation layer fills the gap and covers the curved surface.

4. The semiconductor device package according to claim 3, further comprising: A second passivation layer is disposed between the antenna pattern layer and the metal pillar, wherein the encapsulation has a second surface facing away from the circuit layer and a plurality of protrusions protruding from the second surface, and wherein the plurality of protrusions pass through the second passivation layer to form a molded locking structure.

5. The semiconductor device package of claim 1, further comprising an electronic component disposed on a second surface of the circuit layer and electrically connected to the antenna module via an interconnect structure within the circuit layer.

6. A semiconductor device package comprising: An encapsulation having a first surface and a second surface opposite to the first surface; A circuit layer disposed on the first surface; An antenna pattern layer is disposed on the second surface; The ground plane is in direct contact with the circuit layer; as well as A metal pillar is disposed within the enclosure and electrically connected between the antenna pattern layer and the ground layer; The encapsulation body has a notch from the first surface; and The metal pillar has a surface adjacent to the grounding layer, the first surface of the encapsulation is adjacent to the grounding layer, and a portion of the surface of the metal pillar is recessed from the first surface of the encapsulation, such that the portion of the surface of the metal pillar has a curved surface and a gap is defined between the encapsulation and the metal pillar.

7. The semiconductor device package of claim 6, further comprising: A first passivation layer covers the first surface of the encapsulation and is disposed within the gap; as well as A second passivation layer covers the second surface of the encapsulation.

8. The semiconductor device package of claim 7, wherein the encapsulation has a plurality of protrusions extending from the second surface, and wherein the plurality of protrusions extend through the second passivation layer to form a molded locking structure.

9. The semiconductor device package of claim 6, further comprising an electronic component disposed on a surface of the circuit layer opposite to the package and electrically connected to the antenna pattern layer via interconnection structures within the circuit layer.

10. A method for manufacturing a semiconductor device, comprising: Forming an antenna pattern layer; Conductive pillars are formed on the antenna pattern layer; An encapsulation is formed to cover the conductive post and expose the top surface of the conductive post; A grounding layer is formed on the top surface of the conductive post exposed from the encapsulation. as well as A circuit layer is formed directly on the grounding layer; The conductive post has a surface adjacent to the ground layer, the encapsulation has a surface adjacent to the ground layer, and a portion of the surface of the conductive post is recessed from the surface of the encapsulation, such that the portion of the surface of the conductive post has a curved surface and a gap is defined between the encapsulation and the conductive post.

11. The method of claim 10, wherein the formation of the encapsulation further comprises The encapsulation is formed to completely cover the conductive post; Remove a portion of the encapsulation to expose the top surface of the conductive post; as well as The top surface of the conductive pillar exposed from the encapsulation is etched.

12. The method of claim 10, further comprising: Electronic components are placed on the surface of the circuit layer opposite to the antenna pattern layer.

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