Semiconductor package and manufacturing method

Abstract

An embodiment of the present application provides a semiconductor package including: a plug-in structure without any active devices. The plug-in structure includes: an interconnect device; a dielectric film surrounding the interconnect device; and a first metallization pattern bonded to the interconnect device. The package also includes: a first device die bonded to the side of the first metallization pattern opposite to the interconnect device; and a second device die bonded to the same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die. An embodiment of the present application also provides a method for manufacturing a semiconductor package.

Description

Technical Field

[0001] Embodiments of the present application provide a semiconductor package and a manufacturing method. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, iterative reductions in minimum feature size can increase integration density, thereby allowing more components to be integrated into a given area. With the growth of demand for shrinking electronic devices, there has been a demand for smaller and more creative semiconductor die packaging technology. An example of such a packaging system is package-on-package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology is typically capable of producing semiconductor devices with enhanced functionality and a small footprint on a printed circuit board (PCB). Summary of the invention

[0003] According to some embodiments, a package includes: a plug-in structure without any active devices. The plug-in structure includes: an interconnect device; a dielectric film surrounding the interconnect device; and a first metallization pattern bonded to the interconnect device. The package also includes: a first device die bonded to a side of the first metallization pattern opposite to the interconnect device; and a second device die bonded to the same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die. In some embodiments, the plug-in structure also includes: a passive device bonded to the same side of the first metallization pattern as the interconnect device, wherein the passive device is electrically connected to the first device die or the second device die.

[0004] According to some embodiments, a package includes: a plug-in without active devices; the plug-in includes: an interconnect device, the interconnect device including: a semiconductor substrate; and a first interconnect structure located on the semiconductor substrate; a passive device; a dielectric film, burying the interconnect device and the passive device; and a first metallization pattern located above the dielectric film, the interconnect device, and the passive device, wherein the interconnect device is bonded to a first surface of the first metallization pattern through a first solder area, and the passive device is bonded to the first surface of the first metallization pattern through a second solder area; a first device die is directly bonded to a second surface of the first metallization pattern through a third solder area, wherein the first surface of the first metallization pattern is opposite to the second surface of the first metallization pattern; a second device die is directly bonded to the second surface of the first metallization pattern through a fourth solder area, wherein electrical wiring in the first interconnect structure routes signals between the first device die and the second device die; and a center substrate is directly bonded to a side of the plug-in opposite to the first device die and the second device die.

[0005] According to some embodiments, a method includes: bonding an interconnect device to a first surface of a first metallization pattern, the interconnect device having no active devices; bonding a passive device to the first surface of the first metallization pattern, the passive device having no active devices; burying the interconnect device and the passive device in a dielectric film; bonding a first device die to a second surface of the first metallization pattern, the second surface being opposite to the first surface; bonding a second device die to the second surface of the first metallization pattern, wherein the interconnect device routes signals between the first device die and the second device die. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 shows a cross-sectional view of an interconnect device according to some embodiments;

[0008] Figure 2 , Figure 3 , Figure 4 , Figure 5A , Figure 5B , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 ,and Fig.11 A cross-sectional view showing an intermediate step in fabricating an interposer structure incorporating an interconnect device according to some embodiments;

[0009] Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A Fig. 14B ,and Fig.16 Variations showing intermediate steps in manufacturing a package incorporating an interposer structure according to some embodiments;

[0010] Fig.15 A cross-sectional view of a device die is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or structures discussed.

[0012] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0013] In the present disclosure, various aspects of packages and their formation are described. Various embodiments can use heterogeneous integration to provide packages with device dies, interconnects, and passive devices. A three-dimensional (3D) package includes a plug-in structure with an internal interconnect device. The interconnect device provides electrical interconnection between device dies (e.g., system on chip (SoC), other functional dies, hybrid memory data sets (HBM), other memory dies, multi-function dies, etc.) directly bonded to the plug-in structure. The plug-in structure may further include passive devices (e.g., integrated passive devices (IPDs)). In various embodiments, the plug-in structure electrically connects the device die to another component (e.g., motherboard, etc.) through a central substrate. By directly bonding the device die to the plug-in structure, the yield loss of expensive device dies packaged separately can be reduced. In addition, by integrating passive devices in the plug-in structure, power / insertion loss can be reduced, and / or circuit speed can be increased, thereby improving the performance of the package. By placing the passive device die closer to the device die, gain can also be achieved. According to some embodiments, an intermediate stage of forming a package is shown. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numerals are used to designate like elements formed using like processes.

[0014] Figure 1 FIG. 5 shows a cross-sectional view of an interconnect device 50 according to some embodiments. The interconnect device 50 will be bonded to the plug structure 200 (see FIG. 2 ) in subsequent processing. Fig.11 ) to form a semiconductor package 250 (see Fig.14A and Fig. 14B ). The interconnect device 50 is directly bonded to the devices of the interposer structure 200 in the semiconductor package 250, such as the logic die 54A and the memory die 54B (see Fig.14A and Fig. 14B ) between the interconnect 50 and the transistor 52 to provide an electrical connection. The interconnect 50 may be formed using an applicable manufacturing process. The interconnect 50 may have no active devices and / or no passive devices. For example, the interconnect 50 may have no transistors, diodes, and / or the like. In addition, the interconnect 50 may have no or no capacitors, resistors, inductors, and / or the like. In some embodiments, the interconnect 50 may have a thickness between about 10 μm and about 300 μm. In some embodiments, the interconnect 50 may have a lateral size between about 1 mm by 1 mm and about 10 mm by 100 mm.

[0015] Still reference Figure 1 , the interconnect device 50 may include an interconnect structure 62 formed on a substrate 60. The substrate 60 may be, for example, a glass substrate, a ceramic substrate, a semiconductor substrate, or the like. In some embodiments, the substrate 60 may be a silicon wafer or an active layer of a semiconductor on insulator (SOI) substrate, or the like. The substrate 60 may include a semiconductor material such as doped or undoped silicon, or may include other semiconductor materials, for example: germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates may also be used, such as a multilayer substrate or a gradient substrate. In some embodiments, a plurality of interconnect devices 50 may be formed on a single substrate 60 and singulated to form individual interconnect devices 50, for example Figure 1 The substrate 60 may be referred to as having a front side or front surface (e.g., Figure 1 the side facing upward), and the back or back surface (e.g. Figure 1 In embodiments where substrate 60 comprises silicon, interconnect device 50 may also be referred to as a silicon bus or a silicon bridge.

[0016] In some embodiments, the interconnect device 50 includes one or more layers of electrical wiring 64 (e.g., wires and / or vias) formed in an interconnect structure 62 above the substrate 60. The electrical wiring 64 can be formed by one or more layers of wires in a dielectric (e.g., a low-k dielectric material) material, and has conductive vias that interconnect the wire layers. For example, the electrical wiring 64 may include one to three wire layers. In other embodiments, the electrical wiring 64 may include different numbers of wire layers. The conductive vias may extend through the dielectric to provide vertical connections between the wire layers. The electrical wiring 64 may be formed by any suitable process (e.g., deposition, inlay, dual inlay, etc.).

[0017] In some embodiments, the electrical wiring 64 is formed using a damascene process, in which the corresponding dielectric layer is patterned and etched using photolithography techniques to form grooves corresponding to the desired pattern of the metallization layer and / or vias. An optional diffusion barrier layer and / or an optional adhesion layer may be deposited, and the grooves may be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, or other alternatives; and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, combinations thereof, and the like. In one embodiment, the metallization layer may be formed by depositing a seed layer of copper or a copper alloy and filling the grooves by electroplating. A chemical mechanical planarization (CMP) process or the like may be used to remove excess conductive material from the surface of the corresponding dielectric layer and to planarize the surface for subsequent processing.

[0018] In some embodiments, the use of a damascene or dual damascene process can allow the formation of electrical wiring 64 having a smaller pitch (e.g., "fine pitch wiring"), which can increase the density of the electrical wiring 64 and can also allow for improved conduction and connection reliability within the interconnect device 50. For example, the electrical wiring 64 can have a pitch (e.g., the spacing between adjacent wires) in the range of about 0.1 μm to about 5 μm. In some cases, during high-speed operations (e.g., greater than about 2 Gbit / second), electrical signals can be conducted near the surface of the conductive component. Fine pitch wiring can have a smaller surface roughness than other types of wiring, and thus can reduce the resistance experienced by high-speed signals, and can also reduce signal losses (e.g., insertion loss) during high-speed operations. This can improve the high-speed operating performance of, for example, serializer / deserializer ("SerDes") circuits or other circuits that can operate at higher speeds. In this way, when the interconnect structure 50 is integrated into the plug-in device 200, the interconnect structure 50 can be bonded to the plug-in structure 200 (see Fig.14A and Fig. 14B ) provides high-speed signal routing between device dies.

[0019] In some embodiments, the interconnect device 50 further includes a pad 68, such as an aluminum pad, to which an external connection is made. The pad 68 can be formed on the interconnect structure 62 and electrically connected to the electrical wiring 64. In some embodiments, one or more passivation films 66 are formed on portions of the interconnect structure 62 and the pad 68. An opening extends through the passivation film 66 to the pad 68, and a conductive connector 71 extends through the opening in the passivation film 66 to contact the pad 68.

[0020] In some embodiments, the conductive connector 71 includes a metal pad or a metal pillar (e.g., a copper pillar) 70, on which a solder area 72 is disposed. In some embodiments, the metal pillar 70 may have substantially vertical sidewalls. Alternatively, the metal pillar 70 may be omitted and the solder area 72 may be disposed directly on the pad 68. The solder area 72 may facilitate testing of the interconnect device 50.

[0021] In some embodiments, the conductive connector 71 may include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, a metal cover layer is formed on top of the metal pillar 70. The metal cover layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and may be formed by a plating process. In some embodiments, the conductive connector 71 is formed using a plating process.

[0022] Figures 2 to 11 1 shows a cross-sectional view of an intermediate step during a process for forming an interposer structure 200 incorporating an interconnect device 50 in accordance with some embodiments. Figure 2 In the embodiment, a carrier substrate 100 is provided. The carrier substrate 100 may be a glass carrier substrate, a ceramic carrier substrate, a wafer (eg, a silicon wafer), etc. Figure 2 As shown, the peeling layer 102 can be formed above the carrier substrate 100. The peeling layer 102 can be formed by a polymer-based material, which can be removed from the upper structure to be formed in a subsequent step together with the carrier substrate 100. In some embodiments, the peeling layer 102 is an epoxy-based thermal peeling material that loses its adhesive properties when heated, such as a light-to-heat conversion (LTHC) peeling coating. In other embodiments, the peeling layer 102 can be an ultraviolet (UV) glue that loses its adhesive properties when exposed to UV light. The peeling layer 102 can be dispensed in the form of a fluid and cured, can be a laminated film laminated to the first carrier substrate 100, or can be the like. The top surface of the peeling layer 102 can be horizontal and can have a high degree of flatness.

[0023] Still reference Figure 2, a seed layer 104 is formed on the peeling layer 102. In some embodiments, the seed layer 104 is a metal layer, which may be a single layer, or may be a composite layer including a plurality of sub-layers formed of different materials. In a specific embodiment, the seed layer 104 includes a titanium layer and a copper layer above the titanium layer. The seed layer 104 may be formed using, for example, physical vapor deposition (PVD) or the like.

[0024] exist Figure 3 , an optional dielectric layer 106 may be formed on the seed layer 104. The bottom surface of the dielectric layer 106 may contact the top surface of the seed layer 104. In some embodiments, the dielectric layer 106 is formed of a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. In other embodiments, the dielectric layer 106 is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc., or the like. The dielectric layer 106 may be formed by any acceptable deposition process such as spin coating, CVD, lamination, etc., or a combination thereof.

[0025] Then, the dielectric layer 106 is patterned to form an opening 108 exposing a portion of the seed layer 104. The patterning can be formed by an acceptable process, such as by exposing the dielectric layer 106 to light when the dielectric layer 106 is a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layer 106 is a photosensitive material, the dielectric layer 106 can be developed after exposure. After the opening 108 is formed, a curing process can be applied to harden the dielectric layer 106. Alternatively, another method, such as etching, laser drilling, etc., can be used to pattern the dielectric layer 106.

[0026] exist Figure 4 In the embodiment of the present invention, an optional pre-solder area 110 is formed in the opening 108. In some embodiments, the pre-solder area 110 may include Sn-Ag, Sn-Cu, Sn-Ag-Cu, combinations thereof, etc. The pre-solder area 110 may be formed by electroplating in the opening 108 using an exposed portion of the seed layer 104. Alternatively, the pre-solder area 110 may be formed using a ball drop process, a mounting process, etc. using a pick-and-place tool. In such an embodiment, the seed layer 104 may be omitted.

[0027] exist Figure 5AIn the embodiment, a dielectric layer 112 and a metallization pattern 114 are formed over the dielectric layer 106 and the pre-solder area 110. The metallization pattern 114 may include a conductive pillar 114A within the dielectric layer 112 and a conductive pad 114B on the dielectric layer 112. In some embodiments, the metallization pattern 114 further includes a redistribution line (RDL) electrically connected to the conductive pad. In such an embodiment, the RDL of the metallization pattern 114 redistributes electrical signals, power signals, or ground signals on the top surface of the dielectric layer 112.

[0028] In some embodiments, dielectric layer 112 is formed of a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. In other embodiments, dielectric layer 112 is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc., or the like. Dielectric layer 112 can be formed by any acceptable deposition process such as spin coating, CVD, lamination, etc., or a combination thereof. The material of dielectric layer 112 can be the same as or different from the material of dielectric layer 106.

[0029] After formation, the dielectric layer 112 may then be patterned to form openings that expose portions of the pre-solder region 110. The patterning may be performed by an acceptable process, such as by exposing the dielectric layer 112 to light when the dielectric layer 112 is a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layer 112 is a photosensitive material, the dielectric layer 112 may be developed after exposure. After the openings are formed, a curing process may be applied to harden the dielectric layer 112. Alternatively, another method, such as etching, laser drilling, etc., may be used to pattern the dielectric layer 112.

[0030] Then form metallization pattern 114. As an example for forming metallization pattern 114, a seed layer (not shown) is formed above dielectric layer 112. The seed layer may be further formed on the sidewalls and bottom surface of the opening in dielectric layer 112. In some embodiments, the seed layer is a metal layer, which may be a single layer, or may be a composite layer including a plurality of sublayers formed by different materials. In a specific embodiment, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer may be formed using, for example, PVD, etc. A photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating, etc., and may be exposed for patterning. The pattern of the photoresist corresponds to metallization pattern 114. Patterning forms an opening through the photoresist, thereby exposing the seed layer. A conductive material is formed in the opening of the photoresist, and on the exposed portion of the seed layer. The conductive material may be formed by plating such as electroplating or chemical plating. The conductive material may include metals, such as copper, titanium, tungsten, aluminum, etc. The photoresist and the portion of the seed layer where the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing process or a stripping process such as using an oxygen plasma. Once the photoresist is removed, the exposed portion of the seed layer can be removed, for example, by using an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the seed layer and the conductive material forms the metallization pattern 114.

[0031] Figure 5B An alternative embodiment is shown in which the dielectric layer 106 and the pre-solder area 110 are omitted. In such an embodiment, the dielectric layer 112 and the metallization pattern 114 can be formed directly on the seed layer 104. The metallization pattern 114 can be formed as described above with respect to Figure 5A Alternatively, dielectric layer 106 can be formed directly on lift-off layer 102, and after dielectric layer 112 is deposited and patterned, seed layer 104 can be deposited over and within dielectric layer 112. In such an embodiment, seed layer 104 serves as a seed layer for forming metallization pattern 114, thereby eliminating the need for a separate seed layer.

[0032] exist Figure 6 In one or more interconnect devices 50 (see for example Figure 1 ) is bonded to the metallization pattern 114 through the conductive connector 71. For example, the solder area of ​​the conductive connector 71 can be bonded to the metallization pattern 114 using a flip chip bonding process. A reflow process can be applied to make the solder area of ​​the conductive connector 71 adhere to the metallization pattern 114. Although Figure 6 The conductive connector 71 is shown as including only a solder area, but in other embodiments, the conductive connector 71 can have a different configuration. For example, the conductive connector 71 can include a solder area disposed on a conductive post (see, e.g., Figure 1 and Fig. 14BThe interconnect device 50 may be used to provide a solder area 72 on the conductive pillar 70 of the embodiment of the present invention. Fig.14A and Fig. 14B )'s electrical connections between device dies.

[0033] Likewise Figure 6 As shown, the passive device 52 can also be bonded to the metallization pattern 114 via a conductive connector 116. For example, the conductive connector 116 can include a solder region that is bonded to the metallization pattern 114 using a flip chip bonding process. A reflow process can be applied to allow the solder region of the conductive connector 116 to adhere to the metallization pattern 114.

[0034] Passive device 52 may be similar to interconnect device 50. For example, passive device 52 may include a substrate (e.g., similar to substrate 60), an interconnect structure (e.g., similar to interconnect structure 62) formed on the substrate, and a conductive connector 116 (e.g., similar to conductive connector 71). Conductive connector 116 may provide electrical wiring in the interconnect structure that is electrically connected to passive device 52. The electrical wiring in the interconnect structure of passive device 52 may be patterned to provide one or more passive circuit elements, such as (some) capacitors, (some) resistors, (some) inductors, etc., or a combination thereof. Passive device 52 may not have any active devices (e.g., transistors).

[0035] Although in Figure 6 Only one interconnect device 50 and one passive device 52 are shown in the figure, but any number of interconnect devices 50 and / or passive devices 52 can be bonded to the metallization pattern 114. In addition, the passive device 52 is optional and can be omitted depending on the configuration of the package. For example, in other embodiments, the passive device 52 can be replaced by another interconnect device 50.

[0036] Still reference Figure 6 , the bottom filler 118 can be deposited around the conductive connectors 71 and 116. The bottom filler 118 can be formed by a capillary flow process after the interconnect device 50 and the passive device 52 are connected, or can be formed by a suitable deposition method before the interconnect device 50 and the passive device 52 are connected. The bottom filler 118 can be disposed between the interconnect device 50 and the metallization pattern 114 / dielectric layer 112. The bottom filler 118 can also be disposed between the passive device 52 and the metallization pattern 114 / dielectric layer 112. Although Figure 6 Separate portions of underfill 118 are shown between each interconnect device 50 and passive device 52 , but in other embodiments, underfill 118 may extend continuously under interconnect devices 50 and passive devices 52 .

[0037] exist Figure 7 In, a through via 120 is formed above the metallization pattern 114. As an example for forming the through via 120, a photoresist is formed and patterned on the metallization pattern 114. The photoresist can bury the interconnect device 50 and the passive device 52. The photoresist can be formed by spin coating, etc., and can be exposed for patterning. The pattern of the photoresist corresponds to the through via 120. Patterning forms an opening through the photoresist, thereby exposing the metallization pattern 114. A conductive material is formed in the opening of the photoresist and on the exposed portion of the metallization pattern 114. The conductive material can be formed by plating such as electroplating or chemical plating. The conductive material can include a metal, such as copper, titanium, tungsten, aluminum, etc. The photoresist is then removed. The photoresist can be removed by an acceptable ashing process or a stripping process such as using oxygen plasma. The conductive material forms the through via 120. In Figure 7 In FIG. 5 , the through via 120 extends above the top surfaces of the interconnect device 50 and the passive device 52. Other configurations are also possible.

[0038] exist Figure 8 , a dielectric film 122 is formed over and around the interconnect device 50, the passive device 52, and the through via 120. The dielectric film 122 may fill the gaps between the interconnect device 50, the passive device 52, and the through via 120, and the dielectric film 122 may also bury the interconnect device 50, the passive device 52, and the through via 120. In some embodiments, the dielectric film 122 is formed by a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. In other embodiments, the dielectric film 122 is an underfill, which may or may not include a filling material (e.g., silicon oxide). In other embodiments, the dielectric film 122 is formed by a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc., or the like. The dielectric film 122 may be formed by any acceptable deposition process such as lamination, spin coating, CVD, etc., or a combination thereof. Optionally, the dielectric film 122 may be cured after being deposited.In further embodiments, the dielectric film 122 may be replaced with a molding compound, epoxy, or the like, which may be applied by compression molding, transfer molding, lamination, or the like.

[0039] exist Fig. 9In the embodiment of the present invention, a planarization process is performed on the dielectric film 122 to expose the through via 120. The planarization process may also remove material of the through via 120. The top surfaces of the through via 120 and the dielectric film 122 may be coplanar after the planarization process. The planarization process may be, for example, a chemical mechanical polishing (CMP), a grinding process, etc. In some embodiments, for example, if the through via 120 is already exposed after the dielectric film 122 is deposited, the planarization may be omitted.

[0040] exist Fig.10 , an interconnect structure 136 is formed over the dielectric film 122, the through vias 120, the interconnect device 50, and the passive device 52. In the illustrated embodiment, the interconnect structure 136 includes dielectric layers 124, 128, 132, and 138, and metallization patterns 126, 130, and 134 (sometimes referred to as redistribution layers or redistribution lines). Specifically, the dielectric layer 124 is formed over the dielectric film 122; the dielectric layer 128 is formed over the dielectric layer 124 and the metallization pattern 126; the dielectric layer 132 is formed over the dielectric layer 128 and the metallization pattern 130; and the dielectric layer 138 is formed over the dielectric layer 132 and the metallization pattern 134. In addition, a via portion of the metallization pattern 134 extends through the dielectric layer 132; a via portion of the metallization pattern 130 extends through the dielectric layer 128; and a via portion of the metallization pattern 126 extends through the dielectric layer 124.

[0041] Dielectric layers 124 , 128 , 132 , and 138 may be formed using similar materials and similar processes as dielectric layer 112 , and further description of dielectric layers 124 , 128 , and 132 is omitted for the sake of brevity.

[0042] The metallization patterns 126, 130, and 134 may be formed using similar materials and similar processes as the metallization pattern 114, and further description of the metallization patterns 126, 130, and 134 is omitted for brevity. The metallization patterns 126, 130, and 134 may be electrically connected to the through vias 120, which electrically connect the metallization patterns 126, 130, and 134 to the metallization pattern 114, the interconnect device 50, and the passive device 52. The metallization patterns 126, 130, and 134 may provide conductive lines that may be connected to the finished package 250 (see FIG. 2 ). Fig.14A and Fig. 14B ) provide signal wiring, power lines, and / or ground lines. In some embodiments, one or more metallization patterns 126, 130, or 134 may provide fine pitch wires for fine pitch wiring. For example, the pitch of one or more metallization patterns 126, 130, or 134 may be in the range of 20 μm to 100 μm.

[0043] It should be understood that the second interconnect structure 136 can include any number of dielectric layers and metallization patterns. If more dielectric layers and metallization patterns are to be formed, steps and processes similar to those discussed above can be repeated. The metallization pattern can include wires and conductive vias. The conductive vias can be formed during the formation of the metallization pattern by forming a seed layer and conductive material of the metallization pattern in the opening of the underlying dielectric layer. Therefore, the conductive vias can interconnect and electrically connect various wires.

[0044] exist Fig.11 In some embodiments, an under-bump metallization (UBM) 140 and a conductive connector 142 are formed for external connection to the second interconnect structure 136. In an example of forming the UBM 140, the dielectric layer 138 is first patterned to form an opening that exposes a portion of the metallization pattern 134. The patterning can be implemented by an acceptable process, such as by exposing the dielectric layer 138 to light when the dielectric layer 138 is a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layer 138 is a photosensitive material, the dielectric layer 138 can be developed after exposure.

[0045] The UBM 140 has a bump portion located on and extending along the main surface of the dielectric layer 138, and also has a via portion extending through the dielectric layer 138 to physically and electrically connect the metallization pattern 134. As a result, the UBM 140 is electrically connected to the metallization pattern 134. The UBM 140 can be formed of the same material as the metallization pattern 134 and can be formed using a similar process (e.g., plating). In some embodiments, the UBM 140 has a different size (e.g., width, thickness, etc.) than the metallization pattern 134.

[0046] According to some embodiments, the conductive connector 142 is then formed on the UBM 140. The conductive connector 142 can be, for example, a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by chemical nickel plating-chemical palladium-immersion gold technology (ENEPIG), etc. The conductive connector 142 may include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the conductive connector 142 is formed by first forming a solder layer by evaporation, electroplating, printing, solder transfer, solder ball placement, etc. Once the solder layer is formed on the structure, reflow can be implemented to shape the material into the desired bump shape. In another embodiment, the conductive connector 142 includes a metal column (e.g., a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal capping layer is formed on the top of the metal column. The metal cover layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and may be formed by a plating process. In some embodiments, the conductive connector 142 may be larger than the solder area 72 (e.g., have a larger pitch than the solder area 72). Thus, a plug-in structure 200 combining the interconnect device 50 and the passive device 52 is formed. In some embodiments, the entire plug-in structure 200 may be free of active devices.

[0047] FIG. 12A to FIG. 14B Intermediate steps are shown of bonding the interposer structure 200 to the core substrate 152 and bonding the device die to the interposer structure 200. Thus, a semiconductor package 250 is formed.

[0048] exist Fig. 12A and Fig. 12B In the embodiment, carrier substrate peeling is performed to separate (or "peel off") carrier substrate 100 from plug structure 200. According to some embodiments, peeling includes projecting light such as laser or UV light on peeling layer 102 so that peeling layer 102 decomposes under the heat of the light and carrier substrate 100 can be removed.

[0049] Then, the structure is flipped over and bonded to the center substrate 152. The center substrate 152 can be a metal-clad insulating base material, such as a copper-clad epoxy-impregnated glass cloth laminate, a copper-clad polyimide-impregnated glass cloth laminate, etc. For example, the center substrate 152 can include metal cladding layers 146 and 148 located on opposite sides of the base material 144. The metal cladding layers 146 and 148 can be patterned to provide electrical wiring on the top and bottom surfaces of the base material 144. The patterning of the metal cladding layers 146 and 148 can be performed using any suitable process such as wet etching, laser etching, etc. The conductive connector 142 can be directly bonded to the metal cladding layer 146 using, for example, a flip chip bonding process. In some embodiments, no intermediate layer (e.g., a build-up layer) is formed between the metal cladding layer 146 of the center substrate 152 and the conductive connector 142 of the plug-in structure 200.

[0050] The center substrate 152 may further include a through-via 150 extending through the base material 144. As an example of forming the through-via 150, an opening is formed through the base material, including using a mechanical drilling or milling process. Next, the opening may be plated with a metallic material, for example, using an electrochemical plating process. In some embodiments, the metallic material may include copper. The plating of the opening may form a through-via 150 for providing an electrical connection from one side of the center substrate 152 to the other side. After plating, the remaining portion of the opening through the base material may optionally be filled with an insulating material.

[0051] The flipped interposer structure 200 exposes the seed layer 104 . Fig. 12A An embodiment is shown in which the dielectric layer 106 and the pre-solder region 110 are incorporated into the interposer structure 200 . Fig. 12B An alternative embodiment is shown in which the dielectric layer 106 and the pre-solder region 110 are omitted, such that the seed layer 104 contacts the dielectric layer 112 and the metallization pattern 114 .

[0052] exist Fig.13A and 13B In the process, the seed layer 104 and the dielectric layer 106 (if present) are removed using a suitable process, such as a plasma etching process, a wet etching process, etc. Fig. 12A The corresponding embodiment Fig.13A In the embodiment, the dielectric layer 106 is removed to expose the pre-solder area 110. In this embodiment, the removal of the dielectric layer 106 may use an etching process that selectively etches the dielectric layer 106 at a faster rate than the pre-solder area 110. Fig. 12B The corresponding embodiment Fig. 13B In the embodiment, the seed layer 104 is removed to expose the metallization pattern 114 .

[0053] exist Fig.14A and Fig. 14B , device dies 54A and 54B are bonded to metallization pattern 114 via conductive connectors 99. For example, conductive connectors 99 may include solder regions that are bonded to metallization pattern 114 using a flip chip bonding process. A reflow process may be applied to adhere the solder regions of conductive connectors 99 to metallization pattern 114. In some embodiments, conductive connectors 99 may be the same size as solder regions 72 (e.g., have the same pitch as solder regions 72). In some embodiments, conductive connectors 99 may be smaller than conductive connectors 142 (e.g., have a smaller pitch than conductive connectors 142). Fig.14A An embodiment is shown in which the conductive connector 71 of the interconnect device 50 includes only the solder region 72 . Fig. 14B An alternative embodiment is shown in which a conductive connector 71 of an interconnect device includes a solder region 72 disposed on a conductive pillar 70 .

[0054] Device dies 54A and 54B may be similar to interconnect device 50. For example, Fig.15 A detailed view of device die 54 (e.g., device die 54A and 54B) is shown. Device die 54 may include substrate 82 (e.g., similar to substrate 60), interconnect structure 90 (e.g., similar to interconnect structure 62) formed on substrate 82, pads 92 (e.g., similar to pads 68), passivation layer 94 (e.g., similar to passivation layer 66), and conductive connectors 99 (e.g., similar to conductive connectors 71). However, unlike interconnect device 50, device die 54 includes active devices 84 (e.g., transistors) on the top surface of substrate 82. Active devices 84 are formed in dielectric layer 86, and active devices 84 are electrically connected to electrical wiring 91 through conductive vias 88. Electrical wiring 91 in interconnect structure 90 may provide a circuit structure. For example, the device die 54 can be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system on chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc., a multi-function die, or a combination thereof.

[0055] Return to reference Fig.14A, the logic die 54A and the memory die 54B are flip chips bonded to the metallization pattern 114. The interconnect device 50 is electrically connected to both the logic die 54A and the memory die 54B, and the interconnect device 50 provides a fine pitch electrical interconnection between the logic die 54A and the memory die 54B. In various embodiments, the interconnect device 50 can allow high-speed routing between adjacent device dies 54 bonded to the plug-in structure 200. In addition, the passive device 52 is electrically connected to the logic die 54A and / or the memory die 54B. By placing the passive device 52 within the plug-in structure 200, the distance between the passive device 52 and the device die 54 can be reduced, thereby improving the electrical performance in the completed package.

[0056] Although in Fig.14A and 14B Only one logic die 54A and one memory die 54B are shown in FIG. 1 , but any number of device dies 54 may be bonded to the metallization pattern 114. In addition, other types of device dies 54 may also be bonded to the metallization pattern 114. For example, Fig.16 A top view of a die 54 bonded to an interposer structure 200 is shown. The die 54 includes a logic die 54A, a memory die 54B, a multi-function die 54C, etc. In further embodiments, other configurations are possible. One or more interconnect devices 50 may provide electrical interconnection between adjacent device dies 54 bonded to the interposer structure 200.

[0057] Return to reference Fig.14A and Fig. 14B , bottom filler 156 may be deposited around conductive connector 99. Bottom filler 156 may be formed by a capillary flow process after device die 54 is connected, or may be formed by a suitable deposition method before device die 54 is connected. Bottom filler 156 may be disposed between device die 54 and plug structure 200. Although Fig.14A and Fig. 14B Separate portions of underfill 156 are shown beneath each device die 54 , but in further embodiments, underfill 156 may extend continuously beneath multiple device dies 54 .

[0058] Likewise Fig.14A and Fig. 14BAs shown, the conductive connector 154 is formed on the metal cladding layer 148 of the center substrate 152. The conductive connector 154 can be used to make the completed package 250 bonded to another structure, such as a package substrate, a motherboard, etc. The conductive connector 154 can be, for example, a BGA connector, a solder ball, a metal column, a C4 bump, a microbump, a bump formed by ENEPIG, etc. The conductive connector 154 can include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the conductive connector 154 is formed by first forming a solder layer by evaporation, electroplating, printing, solder transfer, solder ball placement, etc. Once the solder layer is formed on the structure, reflow can be implemented to shape the material into the desired bump shape. In another embodiment, the conductive connector 154 includes a metal column (e.g., a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal covering layer is formed on the top of the metal column. The metal cover layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and may be formed by a plating process. In some embodiments, the conductive connector 154 may be larger than the conductive connector 142 (e.g., have a larger pitch than the conductive connector 142). Thus, the package 250 may be formed according to various embodiments.

[0059] Other features and processes may also be included. For example, a test structure may be included to assist in verification testing of 3D packages or 3DIC devices. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows the 3D package or 3DIC to be tested using a probe and / or a probe card, etc. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method for intermediate verification of known good dies to increase yield and reduce costs.

[0060] Package 250 allows the incorporation of interconnect devices 50 to provide improved high-speed transmission of electrical signals between components (e.g., device die 54) bonded to the plug-in structure. The incorporation of interconnect devices 50 can improve the high-speed operation of package 250. By directly bonding the device die to the plug-in structure, the yield loss of individually packaged expensive device dies can be reduced. In addition, by integrating passive devices into the plug-in structure, power / insertion losses can be reduced, and / or circuit speed can be increased, thereby improving the performance of the package. Gain can also be achieved by placing the passive device die closer to the device die.

[0061] According to some embodiments, a package includes: a plug-in structure without any active devices. The plug-in structure includes: an interconnect device; a dielectric film surrounding the interconnect device; and a first metallization pattern bonded to the interconnect device. The package also includes: a first device die bonded to the side of the first metallization pattern opposite to the interconnect device; and a second device die bonded to the same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die. In some embodiments, the plug-in structure also includes: a passive device bonded to the same side of the first metallization pattern as the interconnect device, wherein the passive device is electrically connected to the first device die or the second device die. In some embodiments, the interconnect device is a flip chip bonded to the first metallization pattern. In some embodiments, the interconnect device includes: a semiconductor substrate; and a first interconnect structure located on the semiconductor substrate, wherein the first interconnect structure includes electrical wiring for routing signals between the first device die and the second device die. In some embodiments, the pitch of the electrical wiring is in the range of 0.1 μm to 5 μm. In some embodiments, the plug-in structure further includes: a second interconnect structure located on a side of the dielectric film opposite to the first metallization pattern; and a through via extending through the dielectric film, wherein the through via electrically connects the second interconnect structure to the first metallization pattern. In some embodiments, the first device die and the second device die are each directly bonded to the first metallization pattern.

[0062] According to some embodiments, a package includes: an insert without active devices; the insert includes: an interconnect device, the interconnect device including: a semiconductor substrate; and a first interconnect structure located on the semiconductor substrate; a passive device; a dielectric film, burying the interconnect device and the passive device; and a first metallization pattern located above the dielectric film, the interconnect device, and the passive device, wherein the interconnect device is bonded to a first surface of the first metallization pattern through a first solder area, and the passive device is bonded to a first surface of the first metallization pattern through a second solder area; a first device die is directly bonded to a second surface of the first metallization pattern through a third solder area, wherein the first surface of the first metallization pattern is opposite to the second surface of the first metallization pattern; a second device die is directly bonded to the second surface of the first metallization pattern through a fourth solder area, wherein the electrical wiring in the first interconnect structure routes signals between the first device die and the second device die; and a center substrate is directly bonded to a side of the insert opposite to the first device die and the second device die. In some embodiments, the passive device is electrically connected to the first device die or the second device die. In some embodiments, the plug-in further comprises: a second interconnect structure located on a side of the dielectric film opposite to the first metallization pattern; a first through-via extending through the dielectric film, wherein the first through-via electrically connects the second interconnect structure to the first metallization pattern; and a fifth solder region located on a side of the second interconnect structure opposite to the first through-via. In some embodiments, the core substrate comprises: an insulating core material; a first metal cladding layer located on a first side of the insulating core material; a second metal cladding layer located on a second side of the insulating core material opposite to the first side of the insulating core material; a second through-via extending through the insulating core material, wherein the second through-via electrically connects the first metal cladding layer to the second metal cladding layer. In some embodiments, the fifth solder region of the plug-in is directly bonded to the first metal cladding layer. In some embodiments, the package further comprises: a sixth solder region directly contacting the second metal cladding layer. In some embodiments, the plug-in further comprises: a first bottom filler surrounding the first solder region; and a second bottom filler surrounding the second solder region. In some embodiments, the first bottom filler is physically separated from the second bottom filler. In some embodiments, the package further includes: a third underfill surrounding the third solder region; and a fourth underfill surrounding the fourth solder region.

[0063] According to some embodiments, a method includes: bonding an interconnect device to a first surface of a first metallization pattern, the interconnect device having no active devices; bonding a passive device to a first surface of a first metallization pattern, the passive device having no active devices; burying the interconnect device and the passive device in a dielectric film; bonding a first device die to a second surface of the first metallization pattern, the second surface being opposite to the first surface; bonding a second device die to a second surface of the first metallization pattern, wherein the interconnect device electrically routes signals between the first device die and the second device die. In some embodiments, the method further includes: forming a through via on the first metallization pattern; burying the through via in a dielectric film; forming an interconnect structure above the dielectric film, wherein the through via electrically connects the first metallization pattern to the interconnect structure. In some embodiments, the method further includes: bonding a center substrate to a side of the interconnect structure opposite to the dielectric film. In some embodiments, the core substrate includes: an insulating core material; a first metal cladding layer located on a first side of the insulating core material, wherein the interconnect structure is directly bonded to the first metal cladding layer; a second metal cladding layer located on a second side of the insulating core material opposite to the first side of the insulating core material; and a second through via extending through the insulating core material, wherein the second through via electrically connects the first metal cladding layer to the second metal cladding layer.

[0064] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor package, comprising: A plug-in structure without any active devices, the plug-in structure comprising: Interconnect devices; a dielectric film surrounding the interconnect device; a first metallization pattern bonded to the interconnect device; a second interconnect structure on a side of the dielectric film opposite the first metallization pattern; and a first through via extending through the dielectric film, wherein the first through via electrically connects the second interconnect structure to the first metallization pattern; a first device die bonded to a side of the first metallization pattern opposite the interconnect device; a second device die bonded to the same side of the first metallization pattern as the first device die, wherein the interconnect device electrically connects the first device die to the second device die, wherein the first metallization pattern comprises: a first conductor extending continuously from a first connection of the first device die to a second connection of the interconnect device; and a second conductor extending continuously from a third connection of the second device die to a fourth connection of the interconnect device; and a central substrate bonded to a side of the second interconnect structure opposite the dielectric film, wherein the central substrate comprises: Insulation core material; a first metal cladding layer disposed on a first side of the insulating core material; and A second metal cladding layer is located on a second side of the insulating core material opposite the first side of the insulating core material.

2. The semiconductor package according to claim 1, wherein: The interposer structure further includes a passive device bonded to the same side of the first metallization pattern as the interconnect device, wherein the passive device is electrically connected to the first device die or the second device die.

3. The semiconductor package according to claim 1, wherein: The interconnect device is a flip chip bonded to the first metallization pattern.

4. The semiconductor package according to claim 1, wherein: The interconnect device comprises: a semiconductor substrate; and A first interconnect structure is located on the semiconductor substrate, wherein the first interconnect structure includes electrical routing of circuit signals between the first device die and the second device die.

5. The semiconductor package according to claim 4, wherein: The pitch of the electrical wiring is in the range of 0.1 μm to 5 μm.

6. The semiconductor package according to claim 1, wherein: The core substrate further includes a second through via extending through the insulating core material, wherein the second through via electrically connects the first metal cladding layer to the second metal cladding layer.

7. The semiconductor package according to claim 1, wherein: The first device die and the second device die are each directly bonded to the first metallization pattern.

8. A semiconductor package, comprising: A plug-in, without active components, comprising: An interconnect device, the interconnect device comprising: a semiconductor substrate; and A first interconnect structure, located on the semiconductor substrate; Passive components; a dielectric film burying the interconnection device and the passive device; and a first metallization pattern located above the dielectric film, the interconnect device, and the passive device, wherein the interconnect device is bonded to a first surface of the first metallization pattern through a first solder region, and the passive device is bonded to the first surface of the first metallization pattern through a second solder region; a first device die directly bonded to the second surface of the first metallization pattern through a third solder region, wherein the first surface of the first metallization pattern is opposite to the second surface of the first metallization pattern; a second device die directly bonded to the second surface of the first metallization pattern through a fourth solder region, wherein the electrical traces in the first interconnect structure electrically route signals between the first device die and the second device die; and a center substrate bonded directly to a side of the interposer opposite the first device die and the second device die, wherein the center substrate comprises: Insulation core material; a first metal cladding layer disposed on a first side of the insulating core material; and A second metal cladding layer is located on a second side of the insulating core material opposite the first side of the insulating core material.

9. The semiconductor package according to claim 8, wherein: The passive device is electrically connected to the first device die or the second device die.

10. The semiconductor package according to claim 8, wherein: The plugin also includes: a second interconnect structure located on a side of the dielectric film opposite the first metallization pattern; a first through via extending through the dielectric film, wherein the first through via electrically connects the second interconnect structure to the first metallization pattern; and A fifth solder region is located on a side of the second interconnect structure opposite to the first through via.

11. The semiconductor package according to claim 8, wherein: The central substrate further comprises: A second through via extends through the insulating core material, wherein the second through via electrically connects the first metal cladding layer to the second metal cladding layer.

12. The semiconductor package according to claim 8, wherein: The fifth solder region of the insert is directly bonded to the first metal cladding.

13. The semiconductor package according to claim 8, further comprising: The sixth solder region directly contacts the second metal cladding layer.

14. The semiconductor package according to claim 11, wherein The plugin also includes: a first underfill surrounding the first solder region; and A second underfill surrounds the second solder area.

15. The semiconductor package according to claim 14, wherein: The first underfill is physically separated from the second underfill.

16. The semiconductor package according to claim 11, further comprising: a third underfill surrounding the third solder region; as well as A fourth underfill surrounds the fourth solder area.

17. A method for manufacturing a semiconductor package, comprising: bonding an interconnect device to the first surface of the first metallization pattern, the interconnect device being free of any active devices; bonding a passive device to the first surface of the first metallization pattern, the passive device being free of any active devices; burying the interconnect device and the passive device in a dielectric film; bonding a first device die to a second surface of the first metallization pattern, the second surface being opposite to the first surface; as well as bonding a second device die to the second surface of the first metallization pattern, wherein the interconnect device routes signals between the first device die and the second device die, wherein the core substrate comprises: Insulation core material; a first metal cladding layer on a first side of the insulating core material, wherein the interconnect structure is directly bonded to the first metal cladding layer; and A second metal cladding layer is located on a second side of the insulating core material opposite the first side of the insulating core material.

18. The method according to claim 17, further comprising: forming a through via hole on the first metallization pattern; burying the through via in the dielectric film; as well as An interconnect structure is formed over the dielectric film, wherein the through via electrically connects the first metallization pattern to the interconnect structure.

19. The method according to claim 18, further comprising: A core substrate is bonded to a side of the interconnect structure opposite the dielectric film.

20. The method according to claim 19, wherein: The central substrate further comprises: A second through via extends through the insulating core material, wherein the second through via electrically connects the first metal cladding layer to the second metal cladding layer.

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