Semiconductor device structure and method of forming the same

Abstract

Provided is a semiconductor device structure and a method of forming the same. The semiconductor device structure includes semiconductor fins on a substrate, and a plurality of semiconductor nanostructures suspended over the semiconductor fins. The semiconductor device structure also includes a gate stack extending across the semiconductor fins, and the gate stack surrounds each semiconductor nanostructure. The semiconductor device structure further includes a first epitaxial structure and a second epitaxial structure sandwiching the semiconductor nanostructures. Each of the first epitaxial structure and the second epitaxial structure extends beyond a top surface of the semiconductor fins. In addition, the semiconductor device structure includes an isolation structure between the semiconductor fins and the gate stack. The isolation structure further extends beyond sidewalls of both sides of the first epitaxial structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to integrated circuits and methods of forming the same, and particularly to the formation of nanostructures. Background Art

[0002] Semiconductor integrated circuits (ICs) have experienced rapid growth. Technological advances in integrated circuit materials and design have produced several generations of integrated circuits. Each generation has smaller and more complex circuits than the previous one.

[0003] In the evolution of integrated circuits, overall, the functional density (e.g., the number of interconnect elements per unit area of the chip) has increased, while the geometric dimensions (e.g., the smallest components (or traces) that can be created using the manufacturing process) have decreased. This miniaturization process generally provides profit by increasing mass production efficiency and reducing related costs.

[0004] However, these advancements have increased the complexity of the integrated circuit manufacturing process. As the component sizes continue to decrease, it has become increasingly difficult to carry out the manufacturing process. Therefore, forming reliable semiconductor elements with increasingly smaller sizes is a challenge. Summary of the Invention

[0005] A semiconductor device structure includes: a semiconductor fin on a substrate; a plurality of semiconductor nanostructures suspended on the semiconductor fin; a gate stack extending across the semiconductor fin, wherein the gate stack surrounds each of the semiconductor nanostructures; a first epitaxial structure and a second epitaxial structure sandwiching the semiconductor nanostructures, wherein each of the first epitaxial structure and the second epitaxial structure extends beyond the top surface of the semiconductor fin; and an isolation structure between the semiconductor fin and the gate stack, wherein the isolation structure further extends beyond the two sidewalls of the first epitaxial structure.

[0006] A semiconductor device structure includes: a plurality of channel structures suspended on a substrate; a gate stack surrounding the channel structures; a first epitaxial structure and a second epitaxial structure each connected to the channel structures, wherein each of the first epitaxial structure and the second epitaxial structure extends beyond the bottom surface of the gate stack; and an isolation structure between the channel structures and the substrate, wherein the entirety of the first epitaxial structure is located above the bottom surface of the isolation structure.

[0007] A method for forming a semiconductor device structure includes: forming a fin structure on a substrate, wherein the fin structure has a sacrificial base layer and a semiconductor stack on the sacrificial base layer, and the semiconductor stack has a plurality of sacrificial layers and a plurality of semiconductor layers laid alternately; forming a dummy gate stack to surround a part of the fin structure; partially removing the fin structure to form a first groove, exposing the side surfaces of the semiconductor layer and the sacrificial layer; at least partially removing the sacrificial base layer to form a second groove between the semiconductor stack and the substrate; forming an isolation structure to fill the second groove; forming an epitaxial structure in the first groove; removing the dummy gate stack and the sacrificial layers to release a plurality of semiconductor nanostructures, the semiconductor nanostructures being formed by the remaining parts of the semiconductor layer; and forming a metal gate stack to surround each of the semiconductor nanostructures. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The aspects of the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with standard practices in the industry, the various features are not drawn to scale. In fact, the dimensions of various components can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention.

[0009] Figure 1A and Figure 1B are top views of various stages of a process for forming a semiconductor device structure according to some embodiments.

[0010] Figures 2A to 2I are cross-sectional schematic views of various stages of a process for forming a semiconductor device structure according to some embodiments.

[0011] Figures 3A to 3K are cross-sectional schematic views of various stages of a process for forming a semiconductor device structure according to some embodiments.

[0012] Figures 4A to 4E are cross-sectional schematic views of various stages of a process for forming a semiconductor device structure according to some embodiments.

[0013] Figures 5A to 5C are cross-sectional schematic views of various stages of a process for forming a semiconductor device structure according to some embodiments.

[0014] Figures 6A to 6C are cross-sectional schematic views of various stages of a process for forming a semiconductor device structure according to some embodiments.

[0015] Figure 7 is a cross-sectional schematic view of a semiconductor device structure according to some embodiments.

[0016] Figure 8 is a cross-sectional schematic view of a semiconductor device structure according to some embodiments.

[0017] Figure 9 It is a schematic cross-sectional view of a semiconductor element structure according to some embodiments.

[0018] Figure 10 It is a schematic cross-sectional view of a semiconductor element structure according to some embodiments.

[0019] Figure 11 It is a schematic cross-sectional view of a semiconductor element structure according to some embodiments.

[0020] Figure 12 It is a schematic cross-sectional view of a semiconductor element structure according to some embodiments.

[0021] Description of reference numerals:

[0022] 10: First region

[0023] 20: Second region

[0024] 100: Semiconductor substrate

[0025] 101A1, 101A2, 101B1, 101B2: Semiconductor fins

[0026] 102a, 102b, 102c, 102d: Semiconductor layers

[0027] 102a’: Remaining structure

[0028] 104a, 104b, 104c, 104d: Semiconductor layers <{

[0029] 104a1: First part

[0030] 104a2: Second part

[0031] 104b’, 104c’, 104d’: Semiconductor nanostructures

[0032] 105b, 105c, 105d: Edge parts

[0033] 106A1, 106A2, 106B1, 106B2: Fin structures

[0034] 108: First mask layer

[0035] 110: Second mask layer

[0036] 112: Trench <{

[0037] 114: Isolation component

[0038] 116: dummy gate dielectric layer

[0039] 118: dummy gate electrode

[0040] 120A1, 120A2, 120B1, 120B2: dummy gate stack

[0041] 122, 124: mask layer

[0042] 126, 128: spacer layer

[0043] 126’, 128’: spacer component

[0044] 130: groove

[0045] 132: groove

[0046] 133: groove

[0047] 133’: groove

[0048] 134: spacer layer [[ID=XX]]

[0049] 136: inner spacer

[0050] 137A1, 137A2, 137B1, 137B1’, 137B2’: isolation structure

[0051] 138: epitaxial structure

[0052] 139: contact etch stop layer

[0053] 140: dielectric layer

[0054] 142A1, 142A2, 142B1, 142B2: trench

[0055] 144: groove

[0056] 150: gate dielectric layer

[0057] 152: work function layer

[0058] 154: conductive filler

[0059] 156A1, 156A2, 156B1, 156B2: metal gate stack

[0060] A - A: line segment

[0061] B - B: line segment

[0062] C - C: line segment

[0063] 2B - 2B, 2B’ - 2B’: line segment

[0064] 2D - 2D, 2D’ - 2D’: line segment

[0065] 3A - 3A, 3A’ - 3A’: line segment Note: There is an undefined "XX" in the original text, which is kept as it is in the translation. If this is an error, please check and correct the original text for a more accurate translation.

[0066] L LC : Channel width

[0067] L SC : Channel width

[0068] P LC : Pitch

[0069] P SC : Pitch

[0070] S: gap

[0071] S': gap

[0072] T1: thickness

[0073] T2: Thickness

[0074] T3: Thickness

[0075] T4: Thickness

[0076] T5: Thickness

[0077] T6: Thickness

[0078] V: Hollow DETAILED DESCRIPTION

[0079] The following disclosure provides many different embodiments or examples for implementing different components of the present disclosure. Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, the description mentions that a first component is formed on a second component, which may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which an additional component is formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference symbols and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity and does not itself dominate the relationship between the various embodiments and / or configurations discussed.

[0080] Furthermore, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and similar terms, may be used to facilitate describing the relationship of one component or feature to another component or feature in the drawings. Spatially relative terms are intended to encompass various orientations of the device in use or operation, as well as the orientations depicted in the drawings. When the device is rotated 90 degrees or in other orientations, the spatially relative adjectives used therein will also be interpreted based on the rotated orientation.

[0081] The term "substantially" in the description, such as in "substantially flat" or in "substantially coplanar", etc., will be understood by those skilled in the art. In some embodiments, the adjective "substantially" can be removed. Where applicable, the term "substantially" can also include embodiments with "completely", "fully", "entirely", etc. Where applicable, the term "substantially" can also be about 90% or higher, such as 95% or higher, especially 99% or higher, including 100%. Furthermore, terms such as "substantially parallel" or "substantially perpendicular" are construed not to exclude minor deviations from a particular configuration and can include, for example, deviations up to 10°. The term "substantially" does not exclude "completely", for example, a composition that is "substantially free of" Y can be "completely free of" Y.

[0082] The term "about" when combined with a particular distance or dimension is construed not to exclude minor deviations from the particular distance or dimension and can include, for example, deviations up to 10%. The term "about" with respect to a numerical value X can mean X ± 5% or 10%.

[0083] Embodiments of the present disclosure can relate to fin field-effect transistors (FinFETs) having fins. Any suitable method can be used to pattern the fins. For example, one or more lithography processes (including double-patterning or multi-patterning processes) can be used to pattern the fins. Generally, double-patterning or multi-patterning processes combine lithography and self-alignment processes, allowing the created pattern to have a smaller pitch than that obtained using a single or direct lithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. Then, the sacrificial layer is removed, and the remaining spacers can be used to pattern the fins. However, one or more suitable processes can be used to form the fins.

[0084] Embodiments of the present disclosure can relate to gate all-around (GAA) transistor structures. Any suitable method can be used to pattern the gate all-around structure. For example, one or more lithography processes (including double-patterning or multi-patterning processes) can be used to pattern the gate all-around structure. In one embodiment, double-patterning or multi-patterning processes combine lithography and self-alignment processes, allowing the created pattern to have a smaller pitch than that obtained using a single or direct lithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. Then, the sacrificial layer is removed, and the remaining spacers can be used to pattern the gate all-around structure.

[0085] Some embodiments of the present disclosure are described. Additional operations may be provided before, during, and / or after the steps described in these embodiments. Some of the steps described may be replaced or eliminated in different embodiments. Additional components may be added to the semiconductor device structure. Some of the components described below may be replaced or eliminated in different embodiments. Although some embodiments may discuss operations being performed in a specific order, these operations may be performed in another logical order.

[0086] Figures 2A to 2I is a cross-sectional schematic diagram of various stages of a process for forming a semiconductor device structure according to some embodiments. As Figure 2A shown, a semiconductor substrate 100 is received or provided. The semiconductor substrate 100 has a first region 10 and a second region 20. In some embodiments, one or more short-channel (SC) elements are formed on the first region 10. One or more long-channel (LC) elements are formed on the second region 20. In some embodiments, the semiconductor substrate 100 is a bulk semiconductor substrate, such as a semiconductor wafer. The semiconductor substrate 100 may include silicon or other elemental semiconductor materials, such as germanium. The semiconductor substrate 100 may be undoped or doped (e.g., P-type, N-type, or a combination thereof). In some embodiments, the semiconductor substrate 100 includes a semiconductor layer epitaxially grown on a dielectric layer. The epitaxially grown semiconductor layer may be formed of silicon germanium (SiGe), silicon, germanium, one or more other suitable materials, or a combination thereof.

[0087] In some other embodiments, the semiconductor substrate 100 includes a compound semiconductor. For example, the compound semiconductor includes one or more group III-V compound semiconductors having a composition defined by the chemical formula Al X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 where X1, X2, X3, Y1, Y2, Y3, and Y4 represent the relevant specific gravities. Each relevant specific gravity is greater than or equal to 0, and the sum of them is equal to 1. The compound semiconductor may include silicon carbide (SiC), gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors, or a combination thereof. Other suitable substrates may also be used, including group II-VI compound semiconductors.

[0088] In some other embodiments, the semiconductor substrate 100 is the active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor-on-insulator substrate can be fabricated using a separation by implantation of oxygen (SIMOX) process, a wafer bonding process, another suitable method, or a combination thereof. In some other embodiments, the semiconductor substrate 100 includes a multi-layer structure. For example, the semiconductor substrate 100 includes a silicon-germanium layer formed on a bulk silicon layer.

[0089] As Figure 2A shown, according to some embodiments, a semiconductor stack having a plurality of semiconductor layers is formed on the semiconductor substrate 100. The semiconductor stack covers a first region 10 and a second region 20 of the semiconductor substrate 100. In some embodiments, the semiconductor stack includes a plurality of semiconductor layers 102a, 102b, 102c, and 102d, and the semiconductor stack also includes a plurality of semiconductor layers 104a, 104b, 104c, and 104d. In some embodiments, the semiconductor layers 102a-102d and the semiconductor layers 104a-104d are laid in an interleaved manner, as Figure 2A shown.

[0090] In some embodiments, the semiconductor layer 102a is used as a sacrificial pedestal layer and will be partially or completely removed in subsequent processes. In some embodiments, the semiconductor layer 104a serves as a protective layer to prevent the semiconductor layer 102b thereon from being damaged during subsequent manufacturing processes. In some embodiments, the semiconductor layers 102b-102d serve as sacrificial layers, which will be removed in subsequent processes to release the semiconductor layers 104b-104d. The released semiconductor layers 104b-104d can serve as the channel structures of one or more transistors.

[0091] In some embodiments, the semiconductor layer 104a is thinner than the semiconductor layers 104b, 104c, and 104d. As Figure 2A shown, the semiconductor layer 104a has a thickness T1, while the semiconductor layer 104b has a thickness T2. In some embodiments, the thickness T2 is greater than the thickness T1. The thickness T1 can be in the range of about 2 nm to 6 nm. For example, the thickness T1 is about 4 nm. The ratio of the thickness T1 to the thickness T2 (T1 / T2) can be in the range of about 2 / 5 to 2 / 3. In some other embodiments, the ratio of the thickness T1 to the thickness T2 (T1 / T2) is in the range of about 3 / 5 to 3 / 4. The ratio (T1 / T2) will be discussed in detail later.

[0092] In some embodiments, each of the semiconductor layers 102b to 102d and each of the semiconductor layers 104b to 104d are approximately of the same thickness. In some embodiments, each of the semiconductor layers 104b to 104d is thicker than each of the semiconductor layers 102a to 102d. In some other embodiments, each of the semiconductor layers 102a to 102d is thicker than each of the semiconductor layers 104b to 104d.

[0093] In some embodiments, the semiconductor layer 102a (as a sacrificial base layer) is thicker than, or approximately equal to, the semiconductor layer 102b, 102c, or 102d (as a sacrificial layer). As Figure 2A shown, the semiconductor layer 102a has a thickness T3, and the semiconductor layer 102b has a thickness T4. In some embodiments, the thickness T3 is greater than the thickness T4. The thickness T3 can be in the range of about 4 nm to 10 nm. For example, the thickness T3 is about 5 nm. The ratio of the thickness T3 to the thickness T4 (T3 / T4) can be in the range of about 1 to 2. In some other embodiments, the ratio of the thickness T3 to the thickness T4 (T3 / T4) can be in the range of about 1.1 to 1.8. The ratio (T3 / T4) will be discussed in detail later.

[0094] In some embodiments, the semiconductor layers 102a to 102d and the semiconductor layers 104a to 104d are formed of different materials. In some embodiments, the semiconductor layers 102a to 102d are formed of silicon germanium or germanium, or include the above materials, and the semiconductor layers 104a to 104d are formed of silicon, or include silicon.

[0095] In some embodiments, the semiconductor layer 102a has a different germanium atom concentration from the semiconductor layer 102b, 102c, or 102d. In some embodiments, the semiconductor layer 102a has a higher germanium atom concentration than the semiconductor layer 102b, 102c, or 102d. The germanium atom concentration of the semiconductor layer 102a can be in the range of about 35% to 50%. The germanium atom concentration of the semiconductor layer 102b, 102c, or 102d can be in the range of about 15% to 25%. The higher germanium atom concentration of the semiconductor layer 102a results in an etch selectivity different from that of the semiconductor layer 102b, 102c, or 102d.

[0096] In some embodiments, the semiconductor layers 102a-102d and the semiconductor layers 104a-104d are formed using multiple epitaxial growth steps. The semiconductor layers 102a-102d and the semiconductor layers 104a-104d can be formed using a selective epitaxial growth (SEG) process, a chemical vapor deposition (CVD) process (such as a vapor-phase epitaxy (VPE) process, a low pressure chemical vapor deposition (LPCVD) process, and / or an ultra-high vacuum chemical vapor deposition (UHV-CVD) process), a molecular beam epitaxy process, one or more other suitable processes, or a combination thereof.

[0097] In some embodiments, the semiconductor layers 102a-102d and the semiconductor layers 104a-104d are grown in-situ in the same process chamber. In some embodiments, the growth of the semiconductor layers 102a-102d and the growth of the semiconductor layers 104a-104d are performed alternately and successively in the same process chamber to complete the formation of the semiconductor stack. In some embodiments, the vacuum of the process chamber is not interrupted before the epitaxial growth of the semiconductor stack is achieved.

[0098] After that, a hard mask component is formed on the semiconductor stack to assist in the subsequent patterning of the semiconductor stack. According to some embodiments, one or more etching processes are used to pattern the semiconductor stack into fin structures 106A1, 106A2, 106B1, and 106B2, as Figure 2B shown. The fin structures 106A1 and 106A2 are formed in the first region 10, and the fin structures 106B1 and 106B2 are formed in the second region 20. The semiconductor stack is partially removed to form a plurality of trenches 112, as Figure 2B shown. Each of the fin structures 106A1, 106A2, 106B1, and 106B2 can include partial semiconductor layers 102a-102d and 104a-104d, as well as semiconductor fins 101A1, 101A2, 101B1, and 101B2. The semiconductor substrate 100 can also be partially removed during the etching process for forming the fin structures 106A1, 106A2, 106B1, and 106B2. The protruding portions of the remaining semiconductor substrate 100 form the semiconductor fins 101A1, 101A2, 101B1, and 101B2.

[0099] Each hard mask component for patterning a semiconductor stack may include a first mask layer 108 and a second mask layer 110. The first mask layer 108 and the second mask layer 110 may be formed of different materials. In some embodiments, the material forming the first mask layer 108 has good adhesion to the semiconductor layer 104d. The first mask layer 108 may be formed of silicon oxide, germanium oxide, silicon germanium oxide, one or more other suitable materials, or a combination thereof. In some embodiments, the material forming the second mask layer 110 has a good etching selectivity ratio for the semiconductor layers 102a-102d and 104a-104d. The second mask layer 110 may be formed of silicon nitride, silicon oxynitride, silicon carbide, one or more other suitable materials, or a combination thereof.

[0100] Figure 1A and Figure 1B are top views of various stages of a process for forming a semiconductor device structure according to some embodiments. In some embodiments, the extending directions of the fin structures 106A1, 106A2, 106B1, and 106B2 are generally parallel to each other, as Figure 1A shown. In some embodiments, Figure 2B is a cross-sectional schematic view of the structure obtained along the line segments 2B-2B and 2B'-2B' in Figure 1A .

[0101] As Figure 2CAs shown, according to some embodiments, an isolation component 114 is formed to surround the lower portions of fin structures 106A1, 106A2, 106B1, and 106B2. In some embodiments, one or more dielectric layers are deposited on the fin structures 106A1, 106A2, 106B1, and 106B2 and the semiconductor substrate 100 to overfill the trenches 112. The dielectric layer can be formed of silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), low-k material, porous dielectric material, one or more other suitable materials, or a combination thereof. The dielectric layer can be deposited using a flowable chemical vapor deposition (FCVD) process, an atomic layer deposition (ALD) process, a chemical vapor deposition process, one or more other suitable processes, or a combination thereof.

[0102] After that, a planarization process is used to partially remove the dielectric layer. The hard mask component (including the first mask layer 108 and the second mask layer 110) can also function as a stop layer for the planarization process. The planarization process can include a chemical mechanical polish (CMP) process, a grinding process, a dry polishing process, an etching process, one or more other suitable processes, or a combination thereof. After that, one or more etch-back processes are used to partially remove the dielectric layer. In this way, the remaining portion of the dielectric layer forms the isolation component 114. The upper portions of the fin structures 106A1, 106A2, 106B1, and 106B2 protrude from the top surface of the isolation component 114, as Figure 2C shown. After that, the hard mask component (including the first mask layer 108 and the second mask layer 110) is removed. Alternatively, in some other embodiments, the hard mask component is removed or consumed during the planarization process and / or the etch-back process.

[0103] After that, according to some embodiments, dummy gate stacks 120A1, 120A2, 120B1, and 120B2 are formed to extend across the fin structures 106A1, 106A2, 106B1, and 106B2, as Figure 1B shown. In some embodiments, Figure 2D is a cross-sectional schematic view of the structure obtained along line segments 2D-2D and 2D'-2D' in Figure 1B . Figures 3A to 3Kis a cross-sectional schematic view of various stages of a process for forming a semiconductor device structure. In some embodiments, Figure 3A is a cross-sectional schematic view of the structure obtained along line segments 3A-3A and 3A'-3A' in Figure 1B .

[0104] As shown in Figure 1B , Figure 2D , and Figure 3A , according to some embodiments, dummy gate stacks 120A1, 120A2, 120B1, and 120B2 are formed to partially cover and extend across fin structures 106A1, 106A2, 106B1, and 106B2. In some embodiments, dummy gate stacks 120A1 and 120A2 surround fin structures 106A1 and 106A2. Dummy gate stacks 120B1 and 120B2 surround fin structures 106B1 and 106B2. As shown in , dummy gate stack 120A2 extends across and surrounds fin structures 106A1 and 106A2, and dummy gate stack 120B2 extends across and surrounds fin structures 106B1 and 106B2.

[0105] In some embodiments, elements formed on the second region 20 have a longer channel width than elements formed on the first region 10. As shown in Figure 2D , elements formed on the first region 10 have a channel width of L SC , while elements formed on the second region 20 have a channel width of L LC . Channel width L LC is longer than channel width L SC . Channel width L SC can be in the range of about 4 nm to 20 nm. Channel width L LC can be in the range of about 22 nm to 40 nm. As shown in Figure 1B , pitch P LC between dummy gate stacks 120B1 and 120B2 is longer than pitch P SC between dummy gate stacks 120A1 and 120A2. Pitch P SC can be in the range of about 15 nm to 60 nm. Pitch P LC is in the range of about 65 nm to 120 nm.

[0106] As shown in Figure 1B and Figure 2DAs shown, each dummy gate stack 120A1, 120A2, 120B1, and 120B2 includes a dummy gate dielectric layer 116 and a dummy gate electrode 118. The dummy gate dielectric layer 116 can be formed of silicon oxide or include the above materials. The dummy gate electrode 118 can be formed of polysilicon or include the above materials. In some embodiments, a dummy gate dielectric material layer and a dummy gate electrode layer are sequentially deposited on the isolation component 114 and the fin structures 106A1, 106A2, 106B1, and 106B2. The dummy gate dielectric material layer can be deposited using an atomic layer deposition process, a chemical vapor deposition process, one or more other suitable processes, or a combination thereof. The dummy gate electrode layer can be deposited using a chemical vapor deposition process. Thereafter, the dummy gate dielectric material layer and the dummy gate electrode layer are patterned to form the dummy gate stacks 120A1, 120A2, 120B1, and 120B2.

[0107] In some embodiments, a hard mask component including mask layers 122 and 124 is used to assist in the patterning process for forming the dummy gate stacks 120A1, 120A2, 120B1, and 120B2. Using the hard mask component as an etch mask, one or more etch processes are used to partially remove the dummy gate dielectric material layer and the dummy gate electrode layer. In this way, the remaining portions of the dummy gate dielectric material layer and the dummy gate electrode layer respectively form the dummy gate dielectric layer 116 and the dummy gate electrode 118 of the dummy gate stacks 120A1, 120A2, 120B1, and 120B2.

[0108] As Figure 3A shown, according to some embodiments, thereafter, spacer layers 126 and 128 are deposited on the structure shown in Figure 3B shown. The spacer layers 126 and 128 extend along the sidewalls of the dummy gate stacks 120A1, 120A2, 120B1, and 120B2. The spacer layers 126 and 128 are formed of different materials. The spacer layer 126 can be formed of a dielectric material having a low dielectric constant. The spacer layer 126 can be formed of silicon carbide, silicon oxycarbide, silicon oxide, one or more other suitable materials, or a combination thereof, or include the above materials. The spacer layer 128 can be formed of a dielectric material, which can provide more protection for the gate stack during subsequent processes. The spacer layer 128 can have a larger dielectric constant than the spacer layer 126. The spacer layer 128 can be formed of silicon nitride, silicon oxynitride, carbon-containing silicon nitride, carbon-containing silicon oxynitride, one or more other suitable materials, or a combination thereof. The spacer layers 126 and 128 can be sequentially deposited using a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition (PVD) process, one or more other suitable processes, or a combination thereof.

[0109] As shown Figure 3A in FIG. , according to some embodiments, the spacer layers 126 and 128 are partially removed. One or more anisotropic etching processes may be used to partially remove the spacer layers 126 and 128. In this way, the remaining portions of the spacer layers 126 and 128 respectively form spacer members 126' and 128'. The spacer members 126' and 128' extend along the sidewalls of the dummy gate stacks 120A1, 120A2, 120B1, and 120B2, as shown Figure 3C in FIG.

[0110] The fin structures 106A1, 106A2, 106B1, and 106B2 are partially removed to form grooves 130 for accommodating epitaxial structures (such as source / drain structures) formed later. The grooves 130 expose the sides of the semiconductor layers 102a-102d and 104a-104d.

[0111] One or more etching processes may be used to form the grooves 130. In some embodiments, a dry etching process is used to form the grooves 130. Alternatively, a wet etching process may be used to form the grooves 130. In some embodiments, each groove 130 passes through the fin structure 106A1 or 106B1. In some embodiments, the groove 130 further extends into the semiconductor fin (such as the semiconductor fin 101A1 or 101B1), as shown Figure 3C in FIG. The groove 130 extends downward beyond the top surface of the semiconductor fin 101A1 or 101B1. In some embodiments, the spacer members 126' and 128' and the grooves 130 are formed using the same etching process.

[0112] In some embodiments, each groove 130 has slanted sidewalls. The upper portion of the groove 130 is larger (or wider) than the lower portion of the groove 130. In these cases, due to the profile of the groove 130, the upper semiconductor layer (such as the semiconductor layer 104d) is shorter than the lower semiconductor layer (such as the semiconductor layer 104b).

[0113] However, embodiments of the present disclosure have many variations. In some other embodiments, the groove 130 has substantially vertical sidewalls. In these cases, due to the profile of the groove 130, the upper semiconductor layer (such as the semiconductor layer 104d) is substantially the same width as the lower semiconductor layer (such as the semiconductor layer 104b).

[0114] As shown Figure 3C in FIG. , according to some embodiments, the sides of the semiconductor layers 102b-102d exposed by the grooves 130 are etched laterally. In this way, the edges of the semiconductor layers 102b-102d retreat inward from the edges of the semiconductor layers 104a-104d. As shown Figure 3DAs shown, due to the lateral etching of the semiconductor layers 102b to 102d, the grooves 132 are formed. The grooves 132 can be used to accommodate inner spacers to be formed later. The semiconductor layers 102b to 102d are laterally etched using a wet etching process, a dry etching process, or a combination thereof.

[0115] In some embodiments, the semiconductor layer 102a (as a sacrificial pedestal layer) is completely or partially removed. In some embodiments, the semiconductor layer 102a is completely removed to form the groove 133, as Figure 3D and Figure 3D shown. Due to the support of the dummy gate stacks 120A1, 120A2, 120B1, and 120B2 (as Figure 2E shown), even if the semiconductor layer 102a is completely removed, the fin structures 106A1, 106A2, 106B1, and 106B2 can be prevented from collapsing. In some embodiments, during the lateral etching of the semiconductor layers 102b to 102d, the semiconductor layer 102a is etched simultaneously. In some embodiments, the semiconductor layers 102a to 102d are etched using the same etching process. During the removal of the semiconductor layer 102a, the semiconductor layer 104a serves as a protective layer to prevent the upper semiconductor layer 102b from being etched or damaged from the bottom surface of the semiconductor layer 102b.

[0116] As mentioned above, in some embodiments, the semiconductor layer 102a (as a sacrificial pedestal layer) is thicker than the semiconductor layers 102b, 102c, or 102d (as sacrificial layers). As mentioned above, in some embodiments, the semiconductor layer 102a has a higher germanium atom concentration than the semiconductor layers 102b, 102c, or 102d. Due to the semiconductor layer 102a being thicker and / or having a higher germanium atom concentration, the semiconductor layer 102a can be etched at an etching rate higher than that of the semiconductor layers 102b to 102d. Thus, according to some embodiments, after the etching process, the semiconductor layer 102a is completely removed to form the groove 133, while the semiconductor layers 102b to 102d are partially etched to form the grooves 132, as Figure 2E shown.

[0117] During the etching of the semiconductor layers 102a to 102d, the semiconductor layers 104a to 104d can also be slightly etched. Thus, the edge portions of the semiconductor layers 104b to 104d are partially etched and thus retracted to become the edge portions 105b to 105d, as Figure 3D shown. As Figure 3DAs shown, each edge portion 105b - 105d of the semiconductor layers 104b - 104d is thinner than the interior of the corresponding semiconductor layers 104b - 104d. In some embodiments, since the semiconductor layer 104a is thinner than each of the semiconductor layers 104b - 104d, no edge portion is formed beside the semiconductor layer 104a. As Figure 3D and Figure 3D shown, according to some embodiments, after the groove 133 is formed, the semiconductor layer 104a becomes thinner.

[0118] As Figure 2E shown, according to some embodiments, on the structure shown in Figure 3E a spacer layer 134 is deposited. The spacer layer 134 covers the dummy gate stacks 120A1, 120A2, 120B1, and 120B2, and fills the grooves 132 and 133. The spacer layer 134 can be formed of silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), one or more other suitable materials, or a combination thereof, or includes the above materials. The spacer layer 134 can be deposited using a chemical vapor deposition process, an atomic layer deposition process, one or more other suitable processes, or a combination thereof.

[0119] As Figure 3D shown, the portion of the spacer layer 134 on the first region 10 has a thickness T5 at the bottom of the groove 130, and the portion of the spacer layer 134 on the second region 20 has a thickness T6 at the bottom of the groove 130. In some embodiments, the thickness T5 is greater than the thickness T6. Since the pitch between the dummy gate stacks on the first region 10 is smaller, the groove 130 on the first region 10 is narrower than the groove 130 on the second region 20. Therefore, the deposition material for forming the spacer layer 134 can accumulate at the bottom of the groove 130 on the first region 10 at a higher deposition rate.

[0120] As Figure 3E shown, according to some embodiments, an etching process is used to partially remove the spacer layer 134. In some embodiments, the first remaining portion of the spacer layer 134 in the groove 132 forms an inner spacer 136, as Figure 3F shown. In some embodiments, the spacer layer 134 fills the groove 133 and the second remaining portion that fills some of the grooves 132 forms isolation structures 137A1, 137A2, 137B1, 137B1’, and 137B2’, as Figure 3F and Figure 3F shown. In some embodiments, the inner spacer 136 and the isolation structures 137A1, 137A2, 137B1, 137B1’, and 137B2’ are formed of the same material. The etching process for partially removing the spacer layer 134 can include a dry etching process, a wet etching process, or a combination thereof.

[0121] The inner spacer 136 and the isolation structures 137A1, 137B1, and 137B1' cover the edges of the semiconductor layers 102b to 102d, which were originally exposed by the grooves 132, as Figure 2F shown. The inner spacer 136 and the isolation structures 137A1, 137B1, and 137B1' can be used to prevent damage to the subsequently formed epitaxial structure (such as a source / drain structure) during the subsequent removal process of the semiconductor layers 102b to 102d. The inner spacer 136 and the isolation structures 137A1, 137B1, and 137B1' can also be used to reduce the parasitic capacitance between the subsequently formed source / drain structure and the gate stack. The isolation structures 137A1, 137A2, 137B1, 137B1', and 137B2' can help reduce or prevent the leakage current of the subsequently formed epitaxial structure. Therefore, the operating speed and reliability of the semiconductor device structure can be improved.

[0122] As shown in some embodiments of Figure 3F , the groove 130 extends downward beyond the top surface of the semiconductor fin 101A1 or 101B1, which ensures that the sides of the semiconductor layers 102b to 102d are exposed. Therefore, during the lateral etching shown in Figure 3C , each of the semiconductor layers 102b to 102d is laterally etched by a sufficient amount. All the grooves 132 are thus deep enough to accommodate the inner spacer 136 or a part of the isolation structures 137A1, 137B1, or 137B1'. Each inner spacer 136 or isolation structure 137A1, 137B1, or 137B1' is thus thick enough to provide sufficient protection for the subsequently formed epitaxial structure during the subsequent removal process of the semiconductor layers 102b to 102d.

[0123] In some embodiments, after the etching process for forming the inner spacer 136, the part of the semiconductor fin 101B1 that was originally covered by the spacer layer 134 is exposed through the groove 130, as Figure 3D shown. At the same time, according to some embodiments, the semiconductor fin 101A1 remains covered by the isolation structure 137A1 (which is the remaining part of the spacer layer 134), as Figure 3F shown.

[0124] As Figure 3F shown, according to some embodiments, an epitaxial structure 138 is formed beside the dummy gate stacks 120A1, 120A2, 120B1, and 120B2. In some embodiments, the epitaxial structure 138 fills the groove 130, as Figure 3GAs shown. In some other embodiments, the epitaxial structure 138 overfills the groove 130. In these cases, the top surface of the epitaxial structure 138 may be higher than the top surface of the dummy gate dielectric layer 116. In some other embodiments, the epitaxial structure 138 partially fills the groove 130. In some embodiments, the epitaxial structure 138 extends beyond or through the top surface of the semiconductor fin 101A1 or 101B1.

[0125] In some embodiments, the epitaxial structure 138 is connected to the semiconductor layers 104b - 104d. Each of the semiconductor layers 104b - 104d is sandwiched between two epitaxial structures 138. In some embodiments, the epitaxial structure 138 serves as a source / drain structure. In some embodiments, some of the epitaxial structures 138 directly contact the semiconductor fin 101B1, as Figure 3G shown. In some embodiments, some of the epitaxial structures 138 are separated from the semiconductor fin 101A1 by the isolation structure 137A1, as Figure 3G shown. In some embodiments, some of the epitaxial structures 138 directly contact the isolation structure 137A1.

[0126] In some embodiments, the epitaxial structure 138 is a P-type doped region. The epitaxial structure 138 may include epitaxially grown silicon germanium, epitaxially grown silicon, or another suitable epitaxially grown semiconductor material. In some other embodiments, the epitaxial structure 138 is an N-type doped region. The epitaxial structure 138 may include epitaxially grown silicon, epitaxially grown silicon carbide, epitaxially grown silicon phosphide (SiP), or another suitable epitaxially grown semiconductor material. In some embodiments, some of the epitaxial structures 138 are P-type doped regions, while other epitaxial structures 138 are N-type doped regions.

[0127] In some embodiments, the epitaxial structure 138 is formed using a selective epitaxial growth process, a chemical vapor deposition process (such as vapor phase epitaxy, low pressure chemical vapor deposition, and / or ultra-high vacuum chemical vapor deposition), a molecular beam epitaxy process, one or more other suitable processes, or a combination thereof.

[0128] In some embodiments, the epitaxial structure 138 is doped with one or more suitable dopants. For example, the epitaxial structure 138 is a silicon germanium source / drain component or a silicon source / drain component, which is doped with boron (B), gallium (Ga), indium (In), carbon (C), phosphorus (P), or another suitable dopant.

[0129] In some embodiments, the epitaxial structure 138 is doped in-situ during the epitaxial growth of the epitaxial structure 138. The initial reactant gas mixture used to form the epitaxial structure 138 includes dopants. In some other embodiments, the epitaxial structure 138 is not doped during the growth of the epitaxial structure 138. Instead, the epitaxial structure 138 is doped in a subsequent process after the epitaxial structure 138 is formed. In some embodiments, doping is achieved by using an ion implantation process, a plasma immersion ion implantation process, a gas and / or solid source diffusion process, one or more other suitable processes, or a combination thereof. In some embodiments, the epitaxial structure 138 is further exposed to one or more annealing processes to activate the dopants. For example, a rapid thermal annealing process is used.

[0130] As Figure 3G shown, according to some embodiments, a contact etch stop layer 139 and a dielectric layer 140 are formed to cover the epitaxial structure 138 and surround the dummy gate stacks 120A1, 120A2, 120B1, and 120B2. The contact etch stop layer 139 can be formed of silicon nitride, silicon oxynitride, silicon carbide, aluminum oxide, one or more other suitable materials, or a combination thereof, or include the above materials. The dielectric layer 140 can be formed of silicon oxide, silicon oxynitride, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, fluorosilicate glass, a low dielectric constant material, a porous dielectric material, one or more other suitable materials, or a combination thereof, or include the above materials.

[0131] In some embodiments, on the Figure 3H structure shown, an etch stop material layer and a dielectric material layer are sequentially deposited. The etch stop material layer can be deposited using a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, one or more other suitable processes, or a combination thereof. The dielectric material layer can be deposited using a flowable chemical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, one or more other suitable processes, or a combination thereof.

[0132] Thereafter, a planarization process is used to partially remove the etch stop material layer and the dielectric material layer. In this way, the remaining portions of the etch stop material layer and the dielectric material layer respectively form a contact etch stop layer 139 and a dielectric layer 140. The planarization process may include a chemical mechanical polishing process, a grinding process, an etching process, a dry polishing process, one or more other suitable processes, or a combination thereof. In some embodiments, the mask layers 122 and 124 are removed during the planarization process. In some embodiments, after the planarization process, the top surfaces of the contact etch stop layer 139, the dielectric layer 140, and the dummy gate electrode 118 are substantially coplanar.

[0133] As Figure 3G and Figure 2G shown, according to some embodiments, the dummy gate electrodes 118 of the dummy gate stacks 120A1, 120A2, 120B1, and 120B2 are removed to form trenches 142A1, 142A2, 142B1, and 142B2. The trenches 142A1, 142A2, 142B1, and 142B2 expose the dummy gate dielectric layer 116.

[0134] As Figure 3I and Figure 2H shown, according to some embodiments, the dummy gate dielectric layer 116 and the semiconductor layers 102b - 102d (as sacrificial layers) are removed to form grooves 144. In some embodiments, an etching process is used to remove the semiconductor layers 102b - 102d. Due to the high etch selectivity, the semiconductor layers 104b - 104d are only slightly (or substantially not) etched. The remaining portions of the semiconductor layers 104b - 104d form multiple semiconductor nanostructures 104b' - 104d' of the fin structures 106A1, 106A2, 106B1, and 106B2, as Figure 3J and Figure 2H shown. The semiconductor nanostructures 104b' - 104d' are constructed or formed by the remaining portions of the semiconductor layers 104b - 104d. The semiconductor nanostructures 104b' - 104d' suspended on the semiconductor fins 101A1, 101A2, 101B1, or 101B2 can serve as the channel structures of the transistors.

[0135] As mentioned above, in some embodiments, the etchant used to remove the semiconductor layers 102b - 102d also slightly removes the semiconductor layers 104b - 104d, which forms the semiconductor nanostructures 104b' - 104d'. In this way, after removing the semiconductor layers 102b - 102d, the obtained semiconductor nanostructures 104b' - 104d' become thinner. In some embodiments, each of the semiconductor nanostructures 104b' - 104d' is thinner than the edge portions 105b - 105d, as Figure 3JAs shown, by surrounding the edge portions 105b - 105d with other components, it is thus avoided being touched and etched by the etchant.

[0136] In some embodiments, the etchant used to remove the semiconductor layers 102b - 102d etches through the semiconductor layer 104a which is thinner than the semiconductor layers 104b, 104c, or 104d. In this way, the isolation structures 137A1, 137A2, 137B1, 137B1’, and 137B2’ are exposed.

[0137] As mentioned above, after removing the semiconductor layers 102b - 102d (as sacrificial layers), the grooves 144 are formed. The grooves 144 are connected to the trenches 142A1, 142A2, 142B1, and 142B2 and surround each semiconductor nanostructure 104b’ - 104d’. As Figure 3J shown, even when the grooves 144 are formed between the semiconductor nanostructures 104b’ - 104d’, the semiconductor nanostructures 104b’ - 104d’ are maintained supported by the epitaxial structure 138. Therefore, after removing the semiconductor layers 102b - 102d (as sacrificial layers), it is avoided that the released semiconductor nanostructures 104b’ - 104d’ collapse.

[0138] During the removal of the semiconductor layers 102b - 102d (as sacrificial layers), the inner spacers 136 and the isolation structures 137A1, 137B1, and 137B1’ protect the epitaxial structure 138 from being etched or damaged. The quality and reliability of the semiconductor device structure are ensured.

[0139] As mentioned above, in Figure 3J some embodiments shown, the ratio (T1 / T2) of the thickness T1 of the semiconductor layer 104a (which later serves as a protective layer for the semiconductor layer 102b during the process shown in Figure 2A and Figure 2E shown) and the thickness T2 of the semiconductor layer 104b (which later becomes the semiconductor nanostructure 104b’) can be in the range of about 2 / 5 to 2 / 3. In some cases, if the thickness ratio (T1 / T2) is lower than about 2 / 5, the semiconductor layer 104a with thickness T1 may be too thin. In this way, during the removal of the semiconductor layer 102a (as a sacrificial base layer), as Figure 3D and Figure 2E shown, the semiconductor layer 104a may be truncated or completely removed, exposing the upper semiconductor layer 102b to the etchant. The semiconductor layer 102b may be damaged or removed. In this way, the subsequently formed spacer layer 134 may occupy the space for accommodating the semiconductor layer 102b. It may become difficult to perform subsequent processes.

[0140] In some other cases, if the thickness ratio (T1 / T2) is greater than about 2 / 3, the semiconductor layer 104a with thickness T1 may be too thick. As such, for removing the semiconductor layer 104a, an additional or stronger etching process may be required in the Figure 3D and Figure 2H processes shown. The process time may become longer. The additional or stronger etching process may also damage other already formed components (such as the channel structure). There may be a risk of adverse effects on the performance and reliability of the semiconductor device structure.

[0141] As Figure 3J and Figure 2I shown, according to some embodiments, metal gate stacks 156A1, 156A2, 156B1, and 156B2 are formed to fill trenches 142A1, 142A2, 142B1, and 142B2. The metal gate stacks 156A1, 156A2, 156B1, and 156B2 extend into the recesses 144 to surround each semiconductor nanostructure 104b’-104d’. In some embodiments, each isolation structure 137A1, 137A2, 137B1, 137B1’, and 137B2’ directly contacts the corresponding semiconductor fin 101A1, 101A2, 101B1, and 101B2, the corresponding epitaxial structure 138, and / or the corresponding metal gate stack 156A1, 156A2, 156B1, and 156B2, as Figure 3K and Figure 2I shown.

[0142] Each metal gate stack 156A1, 156A2, 156B1, and 156B2 includes multiple metal gate stack layers. Each metal gate stack 156A1, 156A2, 156B1, and 156B2 may include a gate dielectric layer 150, a work function layer 152, and a conductive fill 154. In some embodiments, the formation of the metal gate stacks 156A1, 156A2, 156B1, and 156B2 involves depositing multiple metal gate stack layers on the dielectric layer 140 to fill the trenches 142A1, 142A2, 142B1, and 142B2 and the recesses 144. The metal gate stack layers extend into the recesses 144 to surround each semiconductor nanostructure 104b’-104d’.

[0143] In some embodiments, the gate dielectric layer 150 is made of a dielectric material having a high dielectric constant (high-k), or includes the above materials. The gate dielectric layer 150 is made of hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, one or more other suitable high-k materials, or a combination thereof. The gate dielectric layer 150 can be deposited using an atomic layer deposition process, a chemical vapor deposition process, one or more other suitable processes, or a combination thereof.

[0144] In some embodiments, an interfacial layer is formed on the surfaces of the semiconductor nanostructures 104b’ to 104d’ before forming the gate dielectric layer 150. The interfacial layer is very thin and is formed of, for example, silicon oxide or germanium oxide. In some embodiments, the interfacial layer is formed by coating an oxidizing agent on the surfaces of the semiconductor nanostructures 104b’ to 104d’. For example, a liquid containing hydrogen peroxide is coated or provided on the surfaces of the semiconductor nanostructures 104b’ to 104d’ to form the interfacial layer.

[0145] The work function layer 152 can be used to provide the desired work function for the transistor to improve device performance, including improved threshold voltage. In some embodiments, the work function layer 152 is used for forming an n-type metal-oxide semiconductor (NMOS) device. The work function layer 152 is an n-type work function layer. The n-type work function layer can provide a work function value suitable for its device, such as equal to or less than about 4.5 eV.

[0146] The n-type work function layer can include a metal, a metal carbide, a metal nitride, or a combination thereof. For example, the n-type work function layer includes titanium nitride, tantalum, tantalum nitride, one or more other suitable materials, or a combination thereof. In some embodiments, the n-type work function layer is an aluminum-containing layer. The aluminum-containing layer can be formed of titanium aluminum carbide (TiAlC), titanium aluminum oxide (TiAlO), titanium aluminum nitride (TiAlN), one or more other suitable materials, or a combination thereof, or includes the above materials.

[0147] In some other embodiments, a work function layer 152 is used for forming a p-type metal-oxide semiconductor (PMOS) device. The work function layer 152 is a p-type work function layer. The p-type work function layer can provide a work function value suitable for its device, such as equal to or greater than about 4.8 eV.

[0148] The p-type work function layer may include a metal, a metal carbide, a metal nitride, other suitable materials, or a combination thereof. For example, p-type metals include tantalum nitride, tungsten nitride, titanium, titanium nitride, one or more other suitable materials, or a combination thereof.

[0149] The work function layer 152 can also be formed of hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (such as hafnium carbide, zirconium carbide, titanium carbide, aluminum carbide), aluminides, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides, or a combination thereof, or include the above materials. The thickness and / or composition of the work function layer 152 can be fine-tuned to adjust the work function level.

[0150] The work function layer 152 can be deposited on the gate dielectric layer 150 using an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, one or more other suitable processes, or a combination thereof.

[0151] In some embodiments, a barrier layer is formed before the work function layer 152 to serve as an interface between the gate dielectric layer 150 and the subsequently formed work function layer 152. The barrier layer can also be used to prevent diffusion between the gate dielectric layer 150 and the subsequently formed work function layer 152. The barrier layer can be formed of a metal-containing material, or include the above materials. The metal-containing material can include titanium nitride, tantalum nitride, one or more other suitable materials, or a combination thereof. The barrier layer can be deposited using an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, one or more other suitable processes, or a combination thereof.

[0152] In some embodiments, the conductive filler 154 is formed of a metallic material or includes the above materials. The metallic material may include tungsten, aluminum, copper, cobalt, one or more other suitable materials, or a combination thereof. A conductive layer for forming the conductive filler 154 may be deposited on the work function layer 152 using a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, a spin coating process, one or more other suitable processes, or a combination thereof.

[0153] In some embodiments, a blocking layer is formed on the work function layer 152 before forming the conductive layer for forming the conductive filler 154. The blocking layer can be used to prevent the subsequently formed conductive layer from diffusing or penetrating into the work function layer 152. The blocking layer can be formed of tantalum nitride, titanium nitride, one or more other suitable materials, or a combination thereof, or includes the above materials. The blocking layer can be deposited using an atomic layer deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, one or more other suitable processes, or a combination thereof.

[0154] After that, according to some embodiments, a planarization process is performed to remove portions of the metal gate stack layer outside the trenches 142A1, 142A2, 142B1, and 142B2. In this way, the remaining portions of the metal gate stack layer form the metal gate stacks 156A1, 156A2, 156B1, and 156B2, as Figure 3K and Figure 2I shown.

[0155] In some embodiments, since the recess 144 is very small and has been filled with other components (such as the gate dielectric layer 150 and the work function layer 152), the conductive filler 154 does not extend into the recess 144. However, the embodiments of the present disclosure are not limited thereto. In some other embodiments, a portion of the conductive filler 154 extends into the recess 144, particularly the lower recess 144 with a larger space.

[0156] As Figure 3K shown, according to some embodiments, the isolation structure 137A1 extends beyond the two sidewalls of the (e.g., middle) epitaxial structure 138. In some embodiments, the isolation structure 137A1 further extends along the bottom of the epitaxial structure 138. In some embodiments, the entirety of the epitaxial structure 138 is above the bottom surface of the isolation structure 137A1. In some embodiments, the isolation structure 137A1 further extends between the semiconductor fin 101A1 and the metal gate stack 156A2. In some embodiments, the isolation structure 137A1 directly contacts the bottom of the epitaxial structure 138.

[0157] Due to the isolation structure 137A1, the leakage current of the epitaxial structure 138 can be blocked by the isolation structure 137A1. Thus, the leakage current between the epitaxial structures 138 passing through the semiconductor fin and / or the semiconductor substrate 100 is avoided. The isolation structure 137A1 can also help reduce the parasitic capacitance between the epitaxial structure 138 and the metal gate stack 156A1 or 156A2. Therefore, the operating speed and reliability of the semiconductor device structure can be improved.

[0158] As Figure 3K shown, according to some embodiments, each of the metal gate stacks 156B1 and 156B2 surrounds a plurality of semiconductor nanostructures 104b’ to 104d’. Each of the metal gate stacks 156B1 and 156B2 is wider than each of the metal gate stacks 156A1 or 156A2. In some embodiments, each of the semiconductor nanostructures 104b’ to 104d’ surrounded by the metal gate stack 156B1 or 156B2 is wider than each of the semiconductor nanostructures 104b’ to 104d’ surrounded by the metal gate stack 156A1 or 156A2, as Figure 3K shown.

[0159] The device formed on the second region 20 can be a long-channel device. In some embodiments, the isolation structures 137B1 and 137B1’ are separated from each other by one of the epitaxial structures 138, as Figure 3K shown. In some embodiments, the epitaxial structure 138 extends beyond the bottom surfaces of the isolation structures 137B1 and 137B1’, as Figure 3K shown. In some embodiments, the epitaxial structure 138 directly contacts the semiconductor fin 101B1. Since the epitaxial structures 138 on the second region 20 are separated from each other at a relatively long distance, the leakage current between the epitaxial structures 138 passing through the semiconductor fin 101B1 and / or the semiconductor substrate 100 may not occur.

[0160] As mentioned above, in some embodiments, the ratio (T3 / T4) of the thickness T3 of the semiconductor layer 102a to the thickness T4 of the semiconductor layer 102b is in the range of about 1 to 2. In some cases, if the thickness ratio (T3 / T4) is less than about 1, the semiconductor layer 102a may be too thin. In Figure 3K the process shown, the semiconductor layer 102a may not be etched at a sufficient etching rate, and it may be difficult to perform subsequent processes. In some other cases, if the thickness ratio (T3 / T4) is greater than about 2, the semiconductor layer 102a may be too thick. As a result, the groove 133 shown in Figure 3D or Figure 3D may be too large. The spacer layer 134 shown in Figure 2E may not be able to merge together. As a result, the resulting isolation structure may have too many voids and / or gaps, which can increase the risk of leakage current.

[0161] In some embodiments, the semiconductor layer 102a (as a sacrificial base layer) is completely removed during the formation of the groove 132 for accommodating the inner spacer 136, as Figure 3E shown. However, the embodiments of the present disclosure are not limited thereto. Many variations and / or modifications can be made to the embodiments of the present disclosure. In some other embodiments, during the formation of the groove 132, the semiconductor layer 102a is partially removed (instead of completely removed).

[0162] Figures 3C to 3F is a cross-sectional schematic diagram of various stages of a process for forming a semiconductor element structure according to some embodiments. As Figures 4A to 4E shown, a structure the same as or similar to that shown in Figure 4A is formed or received.

[0163] As Figure 3C shown, according to some embodiments, similar to the embodiments shown in Figure 4B the semiconductor layers 102b to 102d are laterally etched to form the groove 132. In some embodiments, similar to the embodiments shown in [[ID=e110]]Figure 3D the portion of the semiconductor layer 102a under the dummy gate stacks 120A1 and 120A2 is completely removed to form the groove 133. In some embodiments, the portion of the semiconductor layer 102a under the dummy gate stacks 120B1 and 120B2 is partially removed (instead of completely removed), as Figure 3D shown. The remaining portion of the semiconductor layer 102a forms a remaining structure 102a' surrounded by the groove 133', as Figure 4B shown.

[0164] As Figure 4B shown, the semiconductor layer 104a on the second region 20 has a first portion 104a1 and a second portion 104a2. The first portion 104a1 is directly above the remaining structure 102a', and thus is avoided from being etched during the formation of the groove 132. Therefore, in some embodiments, the first portion 104a1 is thicker than the second portion 104a2.

[0165] Figure 4B is a cross-sectional schematic diagram (or a plan view) of various stages of a process for forming a semiconductor element structure according to some embodiments. In some embodiments, Figures 5A to 5C is a cross-sectional schematic diagram (or a plan view) of the structure obtained along the line A-A in Figure 5A Figure 4B is a cross-sectional schematic diagram (or a plan view) of various stages of a process for forming a semiconductor element structure according to some embodiments. In some embodiments, Figures 6A to 6C is a cross-sectional schematic diagram (or a plan view) of the structure obtained along the line A-A in Figure 6ASchematic cross-sectional view (or plan view) of the structure obtained from the line segment A-A in

[0166] In some embodiments, the remaining structure 102a’ has substantially vertical edges, as Figure 4B shown. In some other embodiments, the remaining structure 102a’ has curved edges, as Figure 5A shown.

[0167] After that, according to some embodiments, the structure shown in Figure 6A is subjected to the same or similar process as that shown in Figure 4B Thus, the structure shown in Figures 3E to 3I is formed.

[0168] As Figure 4C shown, similar to the embodiment shown in Figure 4D according to some embodiments, the dummy gate dielectric layer 116 and the semiconductor layers 102b - 102d (as sacrificial layers) are removed to form the groove 144. The remaining structure 102a’ is also removed. Due to the removal of the remaining structure 102a’, the groove 144 penetrates through the isolation structures 137B1 and 137B1’ to expose the semiconductor fin 101B1.

[0169] In some embodiments, Figure 3J is a schematic cross-sectional view (or plan view) of the structure obtained from the line segment B-B in Figure 5B . In some embodiments, the isolation structure 137B1 has substantially vertical edges and surrounds the groove 144, as Figure 4D shown.

[0170] In some embodiments, Figure 5B is a schematic cross-sectional view (or plan view) of the structure obtained from the line segment B-B in Figure 6B . In some embodiments, the isolation structure 137B1 has curved edges and surrounds the groove 144, as Figure 4D shown.

[0171] As Figure 6B shown, according to some embodiments, similar to the embodiment shown in Figure 4E , the metal gate stacks 156A1, 156A2, 156B1, and 156B2 are formed. In some embodiments, each of the metal gate stacks 156B1 and 156B2 has a protruding portion that penetrates into the isolation structures 137B1 and 137B1’, as Figure 3KAs shown. In some embodiments, the protruding portions of the metal gate stacks 156B1 and 156B2 penetrate the isolation structures 137B1 and 137B1'. In some embodiments, the metal gate stacks 156B1 and 156B2 directly contact the semiconductor fin 101B1. For example, the gate dielectric layer 150 or an interface layer (not shown) below the gate dielectric layer 150 directly contacts the semiconductor fin 101B1.

[0172] In some embodiments, Figure 4E is a schematic cross-sectional view (or plan view) of the structure obtained along the line C-C in Figure 5C . In some embodiments, the isolation structure 137B1 has substantially vertical edges and surrounds the metal gate stack 156B1, as shown in Figure 4E . The interface between the protruding portion of the metal gate stack 156B1 and the isolation structure 137B1 can be substantially vertical.

[0173] In some embodiments, Figure 5C is a schematic cross-sectional view (or plan view) of the structure obtained along the line C-C in Figure 6C . In some embodiments, the isolation structure 137B1 has curved edges and surrounds the metal gate stack 156B1, as shown in Figure 4E . The interface between the protruding portion of the metal gate stack 156B1 and the isolation structure 137B1 can be curved. In some embodiments, the interface is convex and faces the inside of the protruding portion of the metal gate stack 156B1, as shown in Figure 6C .

[0174] In some embodiments, each of the metal gate stacks 156A1, 156A2, 156B1, and 156B2 includes a conductive filler 154, as shown in Figure 6C and Figure 3K . However, the embodiments of the present disclosure are not limited thereto. Many variations and / or modifications can be made to the embodiments of the present disclosure. In some other embodiments, some of the metal gate stacks are not large enough to accommodate the conductive filler 154.

[0175] Figure e4E is a schematic cross-sectional view of a semiconductor device structure according to some embodiments. As shown in Figure 7 , is formed with respect to Figure 7A similar structure as shown. In some embodiments, the trenches for accommodating the metal gate stacks 156A1 and 156A2 have a very narrow width. In this way, there may not be enough space to accommodate the conductive filler 154. During the formation of the metal gate stacks 156A1 and 156A2, the work function layer 152 can fill the remaining space of the trenches. In some embodiments, the trenches for accommodating the metal gate stacks 156B1 and 156B2 have enough space to accommodate the conductive filler 154. Therefore, similar to the Figure 3K metal gate stacks 156B1 and 156B2 shown, Figure 3K the metal gate stacks 156B1 and 156B2 shown still have the conductive filler 154.

[0176] Figure 7 is a cross-sectional schematic diagram of a semiconductor device structure according to some embodiments. As Figure 8 shown, a structure similar to that Figure 8 shown is formed. In some embodiments, the trenches for accommodating the metal gate stacks 156A1 and 156A2 have a very narrow width. In this way, there may not be enough space to accommodate the conductive filler 154. During the formation of the metal gate stacks 156A1 and 156A2, the work function layer 152 can fill the remaining space of the trenches. In some embodiments, the trenches for accommodating the metal gate stacks 156B1 and 156B2 have enough space to accommodate the conductive filler 154. Therefore, similar to the Figure 4E metal gate stacks 156B1 and 156B2 shown, Figure 4E the metal gate stacks 156B1 and 156B2 shown still have the conductive filler 154.

[0177] Many variations and / or modifications can be made to the embodiments of the present disclosure. Figure 8 is a cross-sectional schematic diagram of a semiconductor device structure according to some embodiments. In some embodiments, a structure similar to that Figure 9 shown is formed. In some embodiments, the epitaxial structure 138 is formed using an epitaxial growth process. In the epitaxial growth process under some conditions, the semiconductor material may tend to grow on the surface of the components formed of the semiconductor material, such as the surfaces of the edge portions 105b to 105d. The semiconductor material may not tend to grow on the surface of the isolation structure 137A1. In this way, according to some embodiments, a void V is formed between the epitaxial structure 138 and the isolation structure 137A1, as Figure 3K shown.

[0178] Figure 9 is a cross-sectional schematic diagram of a semiconductor device structure according to some embodiments. In some embodiments, a structure similar to that <00> Figure 10 shown is formed. In some embodiments, according to some embodiments, similar toFigure 4E Similar to the embodiment shown, a cavity V is formed between the epitaxial structure 138 and the isolation structure 137A1, as Figure 9 shown.

[0179] Many variations and / or modifications may be made to the embodiments of the present disclosure. Figure 10 is a cross-sectional schematic view of a semiconductor element structure according to some embodiments. A structure similar to that shown in Figure 11 is formed. In some embodiments, the spacer layer 134 may not completely fill the groove 133. In this way, according to some embodiments, one or more gaps S may be formed in the isolation structure 137B1 and / or 137B1', as Figure 3K shown.

[0180] Many variations and / or modifications may be made to the embodiments of the present disclosure. Figure 11 is a cross-sectional schematic view of a semiconductor element structure according to some embodiments. A structure similar to that shown in Figure 12 is formed. In some embodiments, similar to the embodiment shown in Figure 3K one or more gaps S' may be formed in the isolation structure 137A1, as Figure 11 Figure 12 shown. In some embodiments, the gap S in the isolation structure 137B1 or 137B1' is larger than the gap S' in the isolation structure 137A1.

[0181] Embodiments of the present disclosure form a semiconductor element structure having an isolation structure between a channel structure and a substrate. The channel structure is wrapped by a gate stack. For example, the semiconductor element structure includes a stack of multiple channel structures wrapped by a metal gate stack. An epitaxial structure is formed adjacent to the channel structure. The isolation structure further extends beyond the sidewalls on both sides of the epitaxial structure. Thus, the leakage current of the epitaxial structure is blocked by the isolation structure. The performance and reliability of the semiconductor element structure are significantly improved.

[0182] According to some embodiments, a semiconductor element structure is provided. The semiconductor element structure includes semiconductor fins on a substrate and multiple semiconductor nanostructures suspended on the semiconductor fins. The semiconductor element structure also includes a gate stack extending across the semiconductor fins, and the gate stack wraps each semiconductor nanostructure. The semiconductor element structure further includes a first epitaxial structure and a second epitaxial structure sandwiching the semiconductor nanostructures. Each of the first epitaxial structure and the second epitaxial structure extends beyond the top surface of the semiconductor fins. In addition, the semiconductor element structure includes an isolation structure between the semiconductor fins and the gate stack. The isolation structure further extends beyond the sidewalls on both sides of the first epitaxial structure.

[0183] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a plurality of channel structures suspended above a substrate. The semiconductor device structure also includes a gate stack surrounding the channel structures. The semiconductor device structure also includes a first epitaxial structure and a second epitaxial structure, each connected to the channel structure. Each of the first epitaxial structure and the second epitaxial structure extends beyond a bottom surface of the gate stack. In addition, the semiconductor device structure includes an isolation structure between the channel structure and the substrate. The entire first epitaxial structure is located above the bottom surface of the isolation structure.

[0184] According to some embodiments, a method for forming a semiconductor device structure is provided. The method for forming a semiconductor device structure includes forming a fin structure on a substrate. The fin structure has a sacrificial base layer and a semiconductor stack on the sacrificial base layer. The semiconductor stack has multiple sacrificial layers and multiple semiconductor layers arranged in an alternating manner. The method for forming a semiconductor device structure also includes forming a dummy gate stack to surround a portion of the fin structure. The method for forming a semiconductor device structure also includes partially removing the fin structure to form a first groove, exposing the side surfaces of the semiconductor layer and the sacrificial layer. In addition, the method for forming a semiconductor device structure includes partially or completely removing the sacrificial base layer to form a second groove between the semiconductor stack and the substrate. The method for forming a semiconductor device structure includes forming an isolation structure to fill the second groove and forming an epitaxial structure in the first groove. The method for forming a semiconductor device structure also includes removing the dummy gate stack and the sacrificial layer to release multiple semiconductor nanostructures, which are formed by the remaining portions of the semiconductor layer. The method for forming a semiconductor device structure also includes forming a metal gate stack to surround each semiconductor nanostructure.

[0185] The above summarizes the components of several embodiments so that those skilled in the art can better understand the concepts of the embodiments of the present disclosure. Those skilled in the art will understand that they can easily design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also understand that such equivalent structures do not depart from the concept and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions, and replacements without violating the concept and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor device structure comprising: a semiconductor fin on a substrate; a plurality of semiconductor nanostructures suspended on the semiconductor fin; a gate stack extending across the semiconductor fin, wherein the gate stack surrounds each of the plurality of semiconductor nanostructures; a first epitaxial structure and a second epitaxial structure sandwiching the plurality of semiconductor nanostructures, wherein each of the first epitaxial structure and the second epitaxial structure extends beyond a top surface of the semiconductor fin; as well as An isolation structure is provided between the semiconductor fin and the gate stack, wherein the isolation structure further extends beyond the sidewalls of the first epitaxial structure, wherein the isolation structure is a continuous structure to surround the sidewalls and bottom surface of a lower portion of the first epitaxial structure, wherein the isolation structure extends across the sidewalls of the first epitaxial structure. 2 . The semiconductor device structure as claimed in claim 1 , further comprising a plurality of inner spacers, wherein each of the plurality of inner spacers is interposed between the gate stack and the first epitaxial structure. 3 . The semiconductor device structure as claimed in claim 2 , wherein the plurality of inner spacers and the isolation structure are formed of the same material. 4 . The semiconductor device structure as claimed in claim 1 , further comprising at least one cavity between the isolation structure and the first epitaxial structure.

5. The semiconductor device structure according to claim 1 , further comprising: a plurality of second semiconductor nanostructures suspended on the semiconductor fin; as well as A second gate stack extends across the semiconductor fin, wherein the second gate stack surrounds each of the plurality of second semiconductor nanostructures, and the isolation structure further extends between the semiconductor fin and the second gate stack.

6. The semiconductor device structure according to claim 1 , further comprising: a second semiconductor fin on the substrate; a plurality of second semiconductor nanostructures suspended from the second semiconductor fin, wherein each of the plurality of second semiconductor nanostructures is wider than each of the plurality of semiconductor nanostructures; a second gate stack extending across the second semiconductor fin, wherein the second gate stack surrounds each of the plurality of second semiconductor nanostructures; a third epitaxial structure and a fourth epitaxial structure sandwiching the plurality of second semiconductor nanostructures, wherein each of the third epitaxial structure and the fourth epitaxial structure extends beyond a top surface of the second semiconductor fin; and A second isolation structure is between the second semiconductor fin and the second gate stack. The semiconductor device structure as claimed in claim 6 , wherein the third epitaxial structure directly contacts the second semiconductor fin. 8 . The semiconductor device structure as claimed in claim 6 , wherein the second gate stack has a protruding portion passing through the second isolation structure. 9 . The semiconductor device structure as claimed in claim 8 , wherein an interface between the protruding portion of the second gate stack and the second isolation structure is a convex surface facing an inner portion of the protruding portion of the second gate stack. 10 . The semiconductor device structure as claimed in claim 6 , further comprising at least one gap within the second isolation structure.

11. A semiconductor device structure comprising: A plurality of channel structures are suspended on a substrate; a gate stack surrounding the plurality of channel structures; a first epitaxial structure and a second epitaxial structure, each connecting the plurality of channel structures, wherein each of the first epitaxial structure and the second epitaxial structure extends beyond a bottom surface of the gate stack; as well as An isolation structure is provided between the plurality of channel structures and the substrate, wherein the entire first epitaxial structure is located above the bottom surface of the isolation structure, wherein the isolation structure is a continuous structure to surround the sidewalls and bottom surface of a lower portion of the first epitaxial structure, and wherein the isolation structure extends across both sidewalls of the first epitaxial structure.

12. The semiconductor device structure according to claim 11, further comprising: a plurality of second channel structures suspended on the substrate; a second gate stack surrounding each of the plurality of second channel structures, wherein the second gate stack is wider than the gate stack; a third epitaxial structure and a fourth epitaxial structure, each connected to the plurality of second channel structures, wherein each of the third epitaxial structure and the fourth epitaxial structure extends beyond a bottom surface of the second gate stack; as well as A second isolation structure is between the second channel structures and the substrate. 13 . The semiconductor device structure as claimed in claim 12 , wherein the third epitaxial structure extends beyond a bottom surface of the second isolation structure. 14 . The semiconductor device structure as claimed in claim 12 , wherein the second gate stack has a protruding portion penetrating into the second isolation structure. 15 . The semiconductor device structure as claimed in claim 12 , further comprising a cavity between the first epitaxial structure and the isolation structure.

16. A method for forming a semiconductor device structure, comprising: forming a fin structure on a substrate, wherein the fin structure comprises a sacrificial base layer and a semiconductor stack on the sacrificial base layer, and the semiconductor stack comprises a plurality of sacrificial layers and a plurality of semiconductor layers alternately arranged; forming a dummy gate stack to surround a portion of the fin structure; Partially removing the fin structure to form a first groove, exposing side surfaces of the plurality of semiconductor layers and the plurality of sacrificial layers; at least partially removing the sacrificial base layer to form a second recess between the semiconductor stack and the substrate; forming an isolation structure to fill the second groove; forming an epitaxial structure in the first recess, wherein the isolation structure is a continuous structure to surround the sidewalls and bottom surface of a lower portion of the epitaxial structure, and wherein the isolation structure extends across both sidewalls of the epitaxial structure; removing the dummy gate stack and the plurality of sacrificial layers to release a plurality of semiconductor nanostructures formed by the plurality of remaining portions of the plurality of semiconductor layers; as well as A metal gate stack is formed to surround each of the plurality of semiconductor nanostructures.

17. The method for forming a semiconductor device structure according to claim 16, further comprising: partially removing the plurality of sacrificial layers from sides of the plurality of sacrificial layers to form a plurality of third grooves after forming the first grooves; forming an inner spacer layer to fill the plurality of third grooves; as well as The inner spacer layer is partially removed so that remaining portions of the inner spacer layer in the third grooves form a plurality of inner spacers. 18 . The method for forming a semiconductor device structure according to claim 17 , wherein the inner spacer layer also fills the second groove, and after partially removing the inner spacer layer, a second remaining portion of the inner spacer layer filling the second groove forms the isolation structure.

19. The method for forming a semiconductor device structure as claimed in claim 16, wherein the sacrificial base layer is completely removed.

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