Filter Circuit for Pulse Width Modulation Signal

Abstract

Embodiments of the present disclosure relate to a filtering circuit for a pulse width modulation signal. A filtering circuit for filtering a pulse width modulation (PWM) signal includes: a D flip-flop having an input terminal configured to be coupled to a logic high signal and an output terminal coupled to an output terminal of the filtering circuit; and a circuit coupled between an input terminal of the filtering circuit and the D flip-flop, the circuit being configured to: for a first pulse of a PWM signal having a duty cycle within a predetermined range: generate a positive pulse at a clock terminal of the D flip-flop as a clock signal of the D flip-flop; and generate a negative pulse at a reset terminal of the D flip-flop as a reset signal of the D flip-flop, wherein a duration between a rising edge of the positive pulse and a falling edge of the negative pulse is equal to a duration of the first pulse of the PWM signal.

Description

Technical Field

[0001] The present invention generally relates to digital filter circuits, and in particular embodiments, to digital filter circuits for filtering pulse width modulation (PWM) signals. Background Art

[0002] Pulse width modulation (PWM) signals are commonly used in electrical and electronic systems. By varying (e.g., modulating) the duty cycle of a PWM signal (e.g., a periodic square wave sequence), information can be carried in the varying duty cycle of the waveform. PWM signals can be used to carry control signals or digital information (e.g., speed / audio information) in many types of systems such as control systems, power systems, audio systems, etc. The waveforms in PWM signals herein may also be referred to as square waves or pulses, and PWM signals are considered to include multiple pulses (or multiple square waves).

[0003] In some applications, such as in high-frequency class D amplifier applications, the PWM signals generated by a PWM modulator may have pulses with duty cycles outside a predetermined range, where the predetermined range may be, for example, between about 2% and about 98%. For example, some pulses may have too high (e.g., greater than about 98%) or too low (e.g., less than 2%) duty cycles. Pulses with duty cycles outside the predetermined range may cause problems for subsequent processing in the system. For example, pulses with too low a duty cycle may not be able to properly set or reset registers in a digital system, which may result in errors in the output level of the system. Thus, filtering the pulses of a PWM signal to remove pulses with duty cycles outside the predetermined range can be advantageous.

[0004] There are challenges in the design of filter circuits for PWM signals. For example, a simple RC filter may not be able to remove all pulses with duty cycles outside the predetermined range in a PWM signal. Additionally, an RC filter may introduce distortion into the filtered pulses, thereby distorting the shape of the pulses (e.g., changing the width of the pulses). For applications such as high-frequency class D amplifier applications, the distortion in the filtered pulses of a PWM signal may severely degrade system performance. Thus, there is a need in the art for filter circuits that can reliably remove the pulses of a PWM signal with duty cycles outside the predetermined range while introducing little or no distortion to the filtered pulses. Summary of the Invention

[0005] In some embodiments, a filter circuit for filtering a pulse width modulation (PWM) signal includes: a D flip-flop having an input terminal configured to be coupled to a logic high signal and an output terminal coupled to an output terminal of the filter circuit; and a circuit coupled between an input terminal of the filter circuit and the D flip-flop, the circuit being configured to: for a first pulse of the PWM signal having a duty cycle within a predetermined range, generate a positive pulse as a clock signal of the D flip-flop at a clock terminal of the D flip-flop; and generate a negative pulse as a reset signal of the D flip-flop at a reset terminal of the D flip-flop, wherein a duration between a rising edge of the positive pulse and a falling edge of the negative pulse is equal to a duration of the first pulse of the PWM signal.

[0006] In some embodiments, a filter circuit for filtering a pulse width modulation (PWM) signal, the filter circuit includes: a D flip-flop; a first circuit coupled between an input terminal of the filter circuit and an input clock terminal of the D flip-flop, wherein the first circuit includes: a first delay line; a first inverter; a first AND gate; and a second AND gate, wherein the first delay line is coupled between the input terminal of the filter circuit and the first inverter, the first inverter is coupled between the first delay line and a first input of the first AND gate, and a second input of the first AND gate is coupled to an output of the first delay line, wherein a first input of the second AND gate is coupled to the input terminal of the filter circuit, a second input of the second AND gate is coupled to an output of the first AND gate, and an output of the second AND gate is coupled to the input clock terminal of the D flip-flop. The filter circuit further includes a second circuit coupled between the input terminal of the filter circuit and a reset terminal of the D flip-flop, wherein the second circuit includes: a second delay line; a second inverter; a third inverter; a NAND gate; and an OR gate, wherein the second delay line is coupled between the input terminal of the filter circuit and the second inverter, the third inverter is coupled between the second inverter and a first input of the NAND gate, and a second input of the NAND gate is coupled to an output of the second inverter, wherein a first input of the OR gate is coupled to the input terminal of the filter circuit, a second input of the OR gate is coupled to an output of the NAND gate, and an output of the OR gate is coupled to the reset terminal of the D flip-flop.

[0007] In some embodiments, a method for filtering a pulse width modulation (PWM) signal, the method includes: applying a logic high signal to an input terminal of a D flip-flop; processing a first pulse of the PWM signal using a first circuit and a second circuit to respectively generate a clock signal and a reset signal, wherein the first pulse has a duty cycle within a predetermined range, wherein the clock signal is a positive pulse, and the reset signal is a negative pulse; and sending the clock signal and the reset signal to a clock terminal and a reset terminal of the D flip-flop, respectively. Description of the Drawings

[0008] Details of one or more embodiments of the present invention are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of the invention will be apparent from the specification, the drawings, and the claims. In the drawings, like reference numerals generally designate like parts throughout the various views, and for the sake of brevity, will not be described again. To understand the present invention more fully, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 Illustrates a schematic diagram of a filter circuit for filtering a PWM signal in one embodiment;

[0010] Figure 2 Illustrates in one embodiment the use of Figure 1 The functional block diagram of a power system of the filter circuit;

[0011] Figure 3 Is a timing diagram illustrating the filtering of a positive pulse by a filter circuit of Figure 1 In one embodiment;

[0012] Figure 4 Is a timing diagram illustrating the filtering of a negative pulse by a filter circuit of Figure 1 In one embodiment;

[0013] Figure 5 Illustrates various filtered PWM waveforms using the disclosed filter circuit and a reference filter circuit in one embodiment;

[0014] Figure 6 Illustrates the filtering of multiple negative pulses using the disclosed filter circuit in one embodiment;

[0015] Figure 7 Illustrates the filtering of multiple positive pulses using the disclosed filter circuit in one embodiment;

[0016] Figure 8 Illustrates the filtering of a pulse sequence having a time-varying duty cycle in one embodiment; and

[0017] Figure 9 Illustrates a flowchart of a method for filtering a PWM signal in some embodiments. Detailed Description

[0018] The fabrication and use of the presently preferred embodiments are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in a variety of specific environments. The specific embodiments discussed merely illustrate specific ways of fabricating and using the invention and do not limit the scope of the invention.

[0019] The present invention will be described with respect to exemplary embodiments in a particular context, namely, a filtering circuit for filtering a PWM signal to remove pulses of the PWM signal having a duty cycle outside a predetermined range.

[0020] Figure 1 FIG. shows a schematic diagram of a filtering circuit 100 (which may also be referred to as a PWM filter) for filtering a PWM signal in one embodiment. Figure 1 The filtering circuit 100 in includes a D flip-flop 101, a first circuit 108, and a second circuit 118. The input terminal D of the D flip-flop 101 is configured to be coupled to a logic high signal 106, e.g., a logic high level such as +3V or +5V. The first circuit 108 is coupled between the input terminal 110 of the filtering circuit 100 and the clock terminal (also referred to as the input clock terminal) of the D flip-flop 101, and this clock terminal is connected to a clock signal CLK. The second circuit 118 is coupled between the input terminal 110 and the reset terminal R of the D flip-flop 101. The output terminal Q of the D flip-flop 101 is the output terminal 104 of the filtering circuit 100. In Figure 1 the example of, the clock signal of the D flip-flop 101 has a valid rising edge, and the reset signal of the D flip-flop is a low-valid signal. In other words, the output at the output terminal Q of the D flip-flop 101 changes at the rising edge of the clock signal CLK, and when a logic low voltage level (e.g., 0V) is applied to the reset terminal R, the D flip-flop is reset (e.g., outputs a logic low value).

[0021] In Figure 1 the first circuit 108 processes (e.g., filters) the PWM signal at the input terminal 110 and generates the clock signal CLK at the output of the first circuit 108. The second circuit 118 processes (e.g., filters) the PWM signal at the input terminal 110 and generates a reset signal at the output of the second circuit 118 having an input terminal D coupled to a logic high signal, and at the clock signal CLK and the reset signal The D flip - flop 101 under the control of [[ID=]] generates a filtered PWM signal at the output terminal Q. The filtered PWM signal (also referred to as the output PWM signal) includes a plurality of pulses, and the plurality of pulses have a duty cycle within a predetermined range (e.g., between 2% and 98%), where each pulse in the plurality of pulses in the output PWM signal corresponds to a corresponding pulse in the PWM signal (also referred to as the input PWM signal) at the input terminal 110. In addition, pulses in the input PWM signal having a duty cycle outside the predetermined range are filtered out (e.g., removed), such that the output PWM signal does not have pulses with a duty cycle outside the predetermined range. In other words, the output PWM signal is otherwise similar to (e.g., substantially equal to) a delayed version of the input PWM signal, but pulses having a duty cycle outside the predetermined range are removed. Details regarding the filtering operation of the filter circuit 100 will be discussed below with reference to Figure 3 and Figure 4 .

[0022] Still referring to Figure 1 , the first circuit 108 includes a delay line X 102, an inverter 107, a first AND gate 105, and a second AND gate 103. The first circuit 108 may additionally include one or more buffers 109, which are coupled in series between the inverter 107 and the first AND gate 105. The delay line X 102 may be a digital delay line having a predetermined delay DelayX to generate a propagation delay between its input and output. The delay line X may be formed of digital components, e.g., an even number of inverters connected in series to provide a predetermined delay. The predetermined delay DelayX may be, for example, on the order of nanoseconds (ns), tens of nanoseconds, or even microseconds (μs), such as approximately 10 ns, although other values are also possible.

[0023] As shown in Figure 1 , the inverter 107 is coupled between the output of the delay line X 102 and the first input of the first AND gate 105. Figure 1 Also illustrated are a plurality of buffers 109, which are coupled in series between the output of the inverter 107 and the first input of the first AND gate 105. In some embodiments, the buffers 109 are used to adjust the width of the clock signal CLK (see the discussion below with reference to Figure 3 and 4 ). In the example of Figure 1 , six buffers 109 are illustrated as a non - limiting example. Other numbers of buffers 109 may be used, such as 0, 1, 2, 3, 4, 5, or greater than 6, without departing from the spirit of the present disclosure. The second input of the first AND gate 105 is coupled to the output of the delay line X 102.

[0024] The output of the first AND gate 105 is coupled to the first input of the second AND gate 103, and the second input of the second AND gate 103 is coupled to the input terminal 110. The output of the second AND gate 103 is the output of the first circuit 108 and is coupled to the clock terminal of the D flip-flop 101.

[0025] Still referring to Figure 1 , the second circuit 118 includes a delay line Y 112 having a predetermined delay DelayY, an inverter 113, an inverter 117, a NAND gate 119, and an OR gate 111. The second circuit 118 may additionally include one or more buffers 115 coupled in series between the inverter 113 and the inverter 117.

[0026] The delay line Y 112 may be similar to the delay line X 102. In some embodiments, the predetermined delays DelayX and DelayY are adjusted to determine a predetermined range for the duty cycle of the pulses, where pulses having a duty cycle within the predetermined range are allowed to pass through the filter circuit 100, and pulses having a duty cycle outside the predetermined range are filtered out (e.g., removed) from the output terminal 104 of the filter circuit 100. Details of the filter circuit 100 will be discussed below with reference to Figure 3 and Figure 4 to discuss the details of the filter circuit 100.

[0027] As Figure 1 shown, the delay line Y 112 is coupled between the input terminal 110 and the inverter 113. The inverter 117 is coupled between the output of the inverter 113 and the first input of the NAND gate 119. The second input of the NAND gate 119 is coupled to the output of the inverter 113. Figure 1 Also illustrated are a plurality of buffers 115 coupled in series between the inverter 113 and the inverter 117. In some embodiments, the buffers 115 are used to adjust the width of the reset signal (see the discussion below with reference to Figure 3 and Figure 4 ). In the Figure 1 example, six buffers 115 are illustrated as a non-limiting example. Other numbers of buffers 115 may be used, such as 0, 1, 2, 3, 4, 5, or greater than 6, without departing from the spirit of the present disclosure.

[0028] The output of the NAND gate 119 is coupled to the first input of the OR gate 111, and the second input of the OR gate is coupled to the input terminal 110 of the filter circuit 100. The output of the OR gate 111 is the output of the second circuit 118, which is coupled to the reset terminal of the D flip-flop 101.

[0029] Figure 2 Illustrated is the use in one embodiment Figure 1Block diagram of the power system 200 of the filter circuit 100. The power system 200 can be, for example, a class-D amplifier. Note that, for simplicity, Figure 2 not all features of the power system 200 are illustrated in Figure 2 . The power system 200 includes a PWM modulator 201, a filter circuit 100 (also referred to as a PWM filter), a PWM signal processor 203, and a PWM power stage 205.

[0030] The PWM modulator 201 generates a PWM signal. The PWM signal can be generated in different ways, such as in-phase, out-of-phase, closed-loop, or open-loop. Then, the PWM signal is filtered by the Figure 1 illustrated filter circuit 100. In some embodiments, the filter circuit 100 filters out (e.g., removes) pulses in the PWM signal that have a duty cycle outside a predetermined range. Then, the filtered PWM signal is sent to the PWM signal processor 203. In some embodiments, the PWM signal processor 203 is a mixed-signal circuit that adjusts the filtered PWM signal in preparation for outputting the filtered PWM signal through the PWM power stage 205. For example, the functions of the PWM signal processor 203 can include, for example, dead-time control, or adjustment according to the driving speed of the load 207. The output of the PWM signal processor 203 is sent to the PWM power stage 205. The PWM power stage 205 is a driver circuit that provides a power signal to the load 207 through, for example, an LC circuit, where the power signal at the output of the PWM power stage 205 corresponds to the output of the PWM signal processor 203, but has improved driving capabilities.

[0031] Figure 3 and Figure 4 illustrate details regarding filtering pulses in the PWM signal using the filter circuit 100, which helps to understand how the filter circuit 100 filters out pulses that have a duty cycle outside a predetermined range. In particular, Figure 3 is a timing diagram illustrating the filtering of positive pulses by the Figure 1 filter circuit 100, and Figure 4 is a timing diagram illustrating the filtering of negative pulses by the Figure 1 filter circuit 100. In some embodiments, the pulses in the input PWM signal are positive pulses. In some other embodiments, the pulses in the input PWM signal are negative pulses. Therefore, Figure 3 and Figure 4 cover different embodiments of the PWM signal.

[0032] In Figure 3 and Figure 4In this case, the x-axis represents time, and the y-axis represents the amplitude of various signals (e.g., logic high or logic low). The name of each illustrated signal is listed along the y-axis on the left side of the figure. Figure 3 and 4 the signals in Figure 1 correspond to the signals with the same name marked in Figure 1 . For example, in , the input PWM signal at the input terminal 110 is marked as signal N1. The two input signals to the second AND gate 103 are respectively marked as signal N1 and signal N2. The output of the first circuit 108 is marked as signal CLK, and the output of the second circuit 118 is marked as signal

[0033] and the output of the filter circuit 100 is marked as signal output PWM. Figure 3 Now referring to Figure 3 , which illustrates a positive pulse P1 having a pulse width W that arrives at time T1. The output of the delay line X 102 marked as signal N3 shows a delayed version of the positive pulse P1 at time T2 (e.g., delayed by the duration of DelayX). The signal N4 at the input of the first AND gate 105 is a delayed and inverted version of signal N3. Note that Figure 1 illustrates a delay of 7Δ between signal N3 and signal N4. For simplicity, it is assumed that each of the inverter 107 and the buffer 109 (e.g., a total of six buffers 109 are illustrated in Figure 3 and Figure 4 ) has a propagation delay of Δ. The delay Δ typically has a very small value, e.g., less than 100 picoseconds (ps) for complementary metal oxide semiconductor (CMOS) devices. However, the predetermined delays of the delay line X and the delay line Y (e.g., DelayX and DelayY) can have larger order-of-magnitude values, e.g., about 10 ns or even a few microseconds. Therefore, in order to illustrate all the delays (e.g., 7Δ, DelayX, and DelayY) in the drawings, Figure 3 and Figure 4 the delays (e.g., 7Δ, DelayX, and DelayY) may not be shown to scale. Additionally, for simplicity, in the timing diagrams of

[0034] the propagation delays through other logic gates or logic devices (e.g., 105, 103, 119, 111, and 101) are ignored. Figure 1 ) through a logical AND operation by the first AND gate 105, signal N3 and signal N4 are combined to generate signal N2. As shown in Figure 3As shown, signal N2 is a positive pulse with a pulse width of 7Δ that arrives at time T2. Note that the pulse width of 7Δ is caused by the total delay introduced by inverter 107 and buffer 109. By adjusting the number of buffers 109, the width of the positive pulse of signal N2 can be adjusted. Through the logical AND operation by the second AND gate 103, signal N2 and signal N1 are combined to generate signal CLK as shown in Figure 3 as shown.

[0035] Note that when the predetermined delay DelayX is less than the pulse width W of signal N1 (DelayX < W), the logical high portion of signal N2 aligns with that of signal N1, and thus, signal CLK is the same as signal N2. In other words, when DelayX < W, Figure 3 the signal CLK in

[0036] is generated as a valid clock signal (e.g., a positive pulse with a rising edge). Figure 3 On the other hand, if the predetermined delay DelayX is equal to or greater than the pulse width W of signal N1 (DelayX ≥ W), then signal N2 will align with the portion of signal N1 that has a logical low value, and thus, signal CLK will not be a positive pulse as shown in Figure 3 Instead,

[0037] the signal CLK in Figure 3 will only be a logical low signal (e.g., a flat line with a logical low value). Since D flip - flop 101 expects a rising - edge - sensitive clock signal, the signal CLK with a flat - line shape is not a valid clock signal. In other words, when DelayX ≥ W, the generated signal CLK will be an invalid clock signal (e.g., a flat line without a rising edge). Figure 3 and 4 For simplicity, in

[0038] as shown in Figure 3As shown, signal N8 is a delayed and inverted version of signal N7. The combination of signals N8 and N7 by NAND gate 119 generates signal N6, which is a negative pulse with a pulse width of 7Δ. Similar to the discussion above regarding signals N4 and N2, the number of buffers 115 can be adjusted to change the width of the negative pulse of signal N6. Then, signals N6 and N1 are combined by OR gate 111 to generate signal which is the same as signal N6 in the example at Figure 3 .

[0039] Since the input terminal D of D flip - flop 101 is coupled to a logic high signal, when the rising edge of signal CLK arrives at time T2, the output PWM signal at output terminal 104 turns high. When signal turns low at time T4, the output PWM signal turns low. As a result, the output PWM signal is a positive pulse and has the same pulse width W as the input PWM signal. As can be seen from Figure 3 , by selecting DelayY + Δ = DelayX (or simplified to DelayY = DelayX), the duration between the rising edge of signal CLK and the falling edge of signal is equal to the pulse width W, thus setting the pulse width of the output PWM signal to W.

[0040] Recall that if DelayX ≥ W, a valid clock signal CLK will not be generated. Therefore, the output PWM signal will stay at, for example, a logic low value, and the positive pulse of the output PWM signal as shown in Figure 3 will not be generated. Representing the period of the input PWM signal as T, the above relationship can be rewritten as Note that W / T is the duty cycle of the pulse of the input PWM signal. Therefore, the above relationship indicates that the pulses of an input PWM signal (e.g., P1) with a duty cycle less than or equal to DelayX / T will be filtered out (e.g., removed) by filter circuit 100.

[0041] Figure 3 The positive pulse P1' in signal N1 is also illustrated by a dashed line. The positive pulse P1' is the next positive pulse in the input PWM signal and is delayed by a duration T (pulse period) from positive pulse P1. Note that the reset signal is generated by combining signal N6 with signal N1 using OR gate 111 If the logic high part of positive pulse P1' overlaps with the logic low part of the negative pulse of signal N6, a valid reset signal (e.g., with a negative pulse) will not be generated. As a result, the positive pulse of the output PWM signal as shown in Figure 3 will not be produced. From Figure 3As can be seen, when W + DelayX + 7Δ ≥ T, the logical high portion of the next positive pulse P1' will overlap with the logical low portion of the negative pulse of signal N6. Rearranging the above inequality and dividing by T (the period of the PWM pulse), we can obtain Since Δ can be several orders of magnitude smaller than DelayX, the above inequality can be simplified to In other words, pulses with a duty cycle greater than 1 – DelayX / T will be filtered out (e.g., removed) by the filter circuit 100.

[0042] From the two inequalities discussed above, it can be concluded that for the input PWM signal, pulses with a duty cycle within a predetermined range (e.g., ) between DelayX / T and 1 – DelayX / T will pass through the filter circuit 100, and pulses with a duty cycle outside the predetermined range will be filtered out (e.g., removed) from the output PWM signal. Another observation is that the predetermined range (e.g., ) is centered relative to the entire range between zero percent and one hundred percent. As a result, the filtering (e.g., removal) of pulses outside the predetermined range is symmetric with respect to the center (e.g., 50%) of the entire range between zero percent and one hundred percent. For example, if DelayX / T is 2%, then pulses with a duty cycle at the highest 2% (e.g., between 98% and 100%) and at the lowest 2% (e.g., between 0% and 2%) will be filtered out. Thus, for a given period T, the predetermined delay DelayX (or DelayY, which is substantially the same as DelayX) of the delay line X 102 (or delay line Y 112) determines the predetermined range of the duty cycle. In some embodiments, the predetermined delay DelayX (or DelayY) is adjusted to change the predetermined range of the duty cycle of the pulses allowed to pass through the filter circuit 100.

[0043] Figure 4 is illustrated in one embodiment, by Figure 1 of the filter circuit 100 for filtering negative pulses. In Figure 4 , the input PWM signal at the input terminal 110 is the negative pulse P2 illustrated by signal N1. Figure 4 The logical operations used to generate various signals in Figure 3 are similar to those in Figure 3 and Figure 4 , so these details will not be elaborated further. Some differences between

[0044] are reviewed Figure 3 , before the reset signal is generated at time T4, the clock signal CLK is generated at time T2. In Figure 4In it, before the CLK signal CLK is generated at time T4, the reset signal is generated at time T2. Therefore, in , by resetting the D flip-flop 101 at time T2 and setting the output of the D flip-flop to logic high at time T4, the output negative pulse of the output PWM signal is generated. Figure 4 From the timing diagram of

[0045] it can be seen that when DelayY + Δ = DelayX (or approximately DelayY = Figure 4 ), the pulse of the output PWM signal has the same pulse width W as the pulse of the input PWM signal. Additionally, if DelayX ≥ W, no effective reset signal will be generated at time T2 DelayX . Moreover, similar to the discussion in , if W + DelayX + 7Δ ≥ T, no effective clock signal CLK will be generated at time T4, where T is the period of the pulse in the PWM signal, because the logic high part of the signal N2 will overlap with the logic low part of the next negative pulse in the PWM signal. Therefore, for negative pulses, we draw the same conclusion as in Figure 3 , that is, pulses of the input PWM signal (e.g., P2) having a duty cycle within a predetermined range between DelayX / T and 1 - DelayX / T (e.g., Figure 3 ) will pass through the filter circuit 100, while pulses having a duty cycle outside the predetermined range will be filtered out (e.g., removed) from the output PWM signal. Note that to achieve the above-mentioned predetermined range, it is assumed that the delay Δ is much smaller than DelayX (e.g., several orders of magnitude smaller).

[0046] Figure 5 FIG. shows the filtered PWM waveforms in an embodiment using the disclosed filter circuit 100 and a reference filter circuit. In particular, waveform 410 shows the pulse of the input PWM signal, which is filtered by the reference filter circuit and the filter circuit 100 for comparison. Waveform 420 shows the filtered pulse using a simple RC filter as the reference filter circuit, and waveform 430s shows the filtered pulse using the Figure 1 filter circuit 100. It can be seen that waveform 420 is distorted relative to the input waveform 410 (e.g., has a shorter pulse width). In contrast, waveform 430 shows little or no distortion and has the same pulse width as the input waveform 410.

[0047] Figure 6 FIG. shows the filtering of multiple negative pulses using the disclosed filter circuit 100 in an embodiment. Figure 6The x-axis in [figure] represents time, and the y-axis in both subfigures represents the amplitude of the pulses. In particular, the negative pulse 510 in the top subfigure is the pulse of the input PWM signal, and the negative pulse 520 in the bottom subfigure is the pulse of the output PWM signal. Due to Figure 6 the ratio, each of the pulses 510 and 520 appears as a line. Each pulse 520 has a one-to-one correspondence with the negative pulse 510 directly above it. In Figure 6 the example of, the duty cycle of the negative pulse 510 between times Ta and Tb is outside a predetermined range (e.g., ), and thus is filtered out and does not appear in the output PWM signal.

[0048] Figure 7 Illustrates, in one embodiment, the filtering of multiple positive pulses using the disclosed filter circuit 100. Figure 7 The x-axis in [figure] represents time, and the y-axis in the subfigure represents the amplitude of the pulses. In particular, the positive pulse 610 in the top subfigure is the pulse of the input PWM signal, and the positive pulse 620 in the bottom subfigure is the pulse of the output PWM signal. Each pulse 620 has a one-to-one correspondence with the positive pulse 610 directly above it. In Figure 7 the example of, the duty cycle of the positive pulse 610 between times Ta and Tb is outside a predetermined range (e.g., ), and thus is filtered out and does not appear in the output PWM signal.

[0049] Figure 8 Illustrates, in one embodiment, the filtering of a pulse sequence with a time-varying duty cycle. In Figure 8 [figure], the x-axis represents time, and the y-axis represents the amplitude of the pulses in the top three subfigures (e.g., for waveforms 710, 720, and 730), or represents the duty cycle of the filtered pulses in the bottom subfigure (e.g., for curves 810, 820, 830). In particular, waveform 710 illustrates a plurality of pulses having a duty cycle that gradually changes from approximately 100% at time T1 to approximately 0% at time T4. Waveform 720 illustrates the corresponding filtered pulses using Figure 1 the filter circuit 100. For comparison purposes, waveform 730 illustrates the corresponding filtered pulses using a simple RC filter. Curves 810, 820, and 830 in the bottom subfigure respectively illustrate the duty cycles of waveforms 710, 720, and 730 from time T1 to time T4.

[0050] From Figure 8Some observations can be made. Curve 810 linearly changes from an approximately 100% duty cycle at time T1 to an approximately 0% duty cycle at time T4. Waveform 720 does not have a filtered output pulse before time T2 or after time T3, indicating that the filter circuit 100 has the ability to remove pulses with a duty cycle outside a predetermined range. In Figure 8 the example of, the pulses in waveform 710 that occur before time T2 have a duty cycle greater than approximately 96.8%, and the pulses in waveform 710 that occur after time T3 have a duty cycle less than approximately 3.2%. Thus, in Figure 8 the example of, the filter circuit 100 allows pulses with a duty cycle within a predetermined range (e.g., between 3.2% and 96.8%) to pass through and removes pulses outside that predetermined range. Note the symmetry within the predetermined range. For example, the duty cycle at time T3 (e.g., 3.2%) and the duty cycle at time T2 (e.g., 96.8) add up to 100%. Due to the fact that the filter circuit 100 introduces little or no distortion into the filtered pulses, curve 810 overlaps curve 820 between time T2 and time T3. Note that, as discussed above, since no filtered pulses are generated outside the time period between time T2 and time T3, curve 810 is only plotted between time T2 and time T3.

[0051] Figure 8 The filtered pulses in waveform 730 using an RC filter are also illustrated. Although in this example, the RC filter also filters out pulses with a duty cycle outside a predetermined range, the filtering of the RC filter is not precisely controlled. For example, the RC filter also removes the pulses between time Tc and time T3. Additionally, as shown by curve 830, due to the distortion introduced by the RC filter, the duty cycle of the filtered pulses in waveform 730 using the RC filter is different from the duty cycle of the input pulses in waveform 710, as indicated by the gap between curve 810 and curve 830. In contrast, as indicated by the overlap of curve 810 and curve 820 between time T2 and time T3, the duty cycle of the filtered pulses in waveform 720 using the filter circuit 100 almost exactly matches the duty cycle of the input pulses in waveform 710.

[0052] Variations to the disclosed embodiments are possible and are fully intended to be included within the scope of this disclosure. For example, Figure 1 the number of buffers 109 and 115 in can be adjusted to change the pulse widths of the reset signal and the clock signal. As another example, Figure 1The D flip-flop 101 therein expects a clock signal that is active on the rising edge and a reset signal that is active low. This is only a non-limiting example. The D flip-flop 101 can expect other types of clock signals and reset signals, in which case simple logic gates (e.g., inverters) can be used to change the polarity or direction of the pulses to match the expectations of the D flip-flop 101. Additionally, although the D flip-flop 101 is used in the example of Figure 1 this is merely exemplary and not limiting. Those skilled in the art will understand that the D flip-flop 101 can be replaced by other suitable logic devices (such as registers) having the same or similar functionality.

[0053] Figure 9 FIG. illustrates a flowchart of a method for filtering a PWM signal in some embodiments. It should be understood that Figure 9 the illustrated embodiment method is merely one example of many possible embodiment methods. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. For example, as Figure 9 shown, the various steps can be added, removed, replaced, rearranged, and repeated.

[0054] Referring to Figure 9 , at step 1010, a logic high signal is applied to the input terminal of the D flip-flop. At step 1020, the first pulse of the PWM signal is processed using a first circuit and a second circuit to generate a clock signal and a reset signal respectively, where the first pulse has a duty cycle within a predetermined range, where the clock signal is a positive pulse, and the reset signal is a negative pulse. At step 1030, the clock signal and the reset signal are respectively sent to the clock terminal and the reset terminal of the D flip-flop.

[0055] Embodiments can achieve advantages. For example, the disclosed filter circuit 100 filters out (e.g., removes) pulses of the PWM signal having a duty cycle outside a predetermined range, thus removing pulses that may cause malfunctions in the set / reset register. The filter circuit 100 introduces little or no distortion into the filtered pulses, which is advantageous for applications that are sensitive to distortion of the pulse shape (e.g., high-frequency class D amplifiers, which have a PWM signal with a frequency of several megahertz (MHz), such as 2 MHz or higher). The predetermined range of the duty cycle can be easily adjusted by adjusting the predetermined delay (e.g., DelayX) of the delay line in the filter circuit 100. The filter circuit 100 can be implemented using all-digital units, which can minimize the spread of variations. The filter circuit 100 can be implemented without a high-speed clock. For example, the filter circuit 100 can include only logic gates and delay lines, which can be operated without using an external high-speed clock. Precise control of the filtering function of the filter circuit can be achieved, and good noise immunity is also achieved.

[0056] Example embodiments of the present invention are summarized herein. Other embodiments may be understood from the entire specification and claims submitted herein.

[0057] Example 1. A filter circuit for filtering a pulse width modulation (PWM) signal, the filter circuit comprising: a D flip-flop, an input terminal of the D flip-flop being configured to be coupled to a logic high signal, an output terminal of the D flip-flop being coupled to an output terminal of the filter circuit; and a circuit coupled between an input terminal of the filter circuit and the D flip-flop, the circuit being configured to: for a first pulse of a PWM signal having a duty cycle within a predetermined range: generate a positive pulse at a clock terminal of the D flip-flop as a clock signal of the D flip-flop; and generate a negative pulse at a reset terminal of the D flip-flop as a reset signal of the D flip-flop, wherein a duration between a rising edge of the positive pulse and a falling edge of the negative pulse is equal to a duration of the first pulse of the PWM signal.

[0058] Example 2. The filter circuit according to Example 1, wherein the D flip-flop is configured to: generate an output pulse at an output terminal of the D flip-flop using the clock signal and the reset signal, the output pulse corresponding to the first pulse of the PWM signal and having the same duration as the first pulse.

[0059] Example 3. The filter circuit according to Example 2, wherein the circuit is configured to, for a second pulse of a PWM signal having a duty cycle outside the predetermined range: stop generating the positive pulse or stop generating the negative pulse, thereby preventing the D flip-flop from generating an output pulse corresponding to the second pulse of the PWM signal.

[0060] Example 4. The filter circuit according to Example 1, wherein the predetermined range is substantially centered relative to the entire range between a zero percent duty cycle and a one hundred percent duty cycle.

[0061] Example 5. The filter circuit according to Example 1, wherein the clock signal of the D flip-flop is active on the rising edge, and the reset signal of the D flip-flop is active low.

[0062] Example 6. The filter circuit according to Example 1, wherein the PWM signal includes a first plurality of positive pulses having a duty cycle within the predetermined range, wherein for each positive pulse of the first plurality of positive pulses: the clock signal of the D flip-flop is generated by the circuit before the reset signal of the D flip-flop is generated by the circuit.

[0063] Example 7. The filter circuit according to Example 1, wherein the PWM signal includes a first plurality of negative pulses, wherein for each negative pulse of the first plurality of negative pulses: the clock signal of the D flip-flop is generated by the circuit after the reset signal of the D flip-flop is generated by the circuit.

[0064] Example 8. The filter circuit according to Example 1, wherein the circuit comprises: a first delay line having a first predetermined delay, the input of the first delay line being coupled to the input terminal of the filter circuit; a first inverter, the input of the first inverter being coupled to the output of the first delay line; a first AND gate, the first input of the first AND gate being coupled to the output of the first inverter, the second input of the first AND gate being coupled to the output of the first delay line; and a second AND gate, the first input of the second AND gate being coupled to the output of the first AND gate, the second input of the second AND gate being coupled to the input terminal of the filter circuit, and the output of the second AND gate being coupled to the clock terminal of the D flip-flop.

[0065] Example 9. The filter circuit according to Example 8, wherein the circuit further comprises one or more buffers coupled between the output of the first inverter and the first input of the first AND gate.

[0066] Example 10. The filter circuit according to Example 8, wherein the circuit further comprises: a second delay line having a second predetermined delay, the input of the second delay line being coupled to the input terminal of the filter circuit; a second inverter, the input of the second inverter being coupled to the output of the second delay line; a third inverter, the input of the third inverter being coupled to the output of the second inverter; a NAND gate, the first input of the NAND gate being coupled to the output of the second inverter, the second input of the NAND gate being coupled to the output of the third inverter; an OR gate, the first input of the OR gate being coupled to the output of the NAND gate, the second input of the OR gate being coupled to the input terminal of the filter circuit, and the output of the OR gate being coupled to the reset terminal of the D flip-flop.

[0067] Example 11. The filter circuit according to Example 10, wherein the circuit further comprises one or more buffers coupled between the output of the second inverter and the input of the third inverter.

[0068] Example 12. A filter circuit for filtering a pulse width modulation (PWM) signal, the filter circuit comprising: a D flip-flop and a first circuit, the first circuit being coupled between an input terminal of the filter circuit and an input clock terminal of the D flip-flop, wherein the first circuit comprises: a first delay line; a first inverter; a first AND gate; and a second AND gate, wherein the first delay line is coupled between the input terminal of the filter circuit and the first inverter, the first inverter is coupled between the first delay line and a first input terminal of the first AND gate, and a second input of the first AND gate is coupled to an output of the first delay line, wherein a first input of the second AND gate is coupled to the input terminal of the filter circuit, a second input of the second AND gate is coupled to an output of the first AND gate, and an output of the second AND gate is coupled to the input clock terminal of the D flip-flop. The filter circuit further comprises a second circuit, the second circuit being coupled between the input terminal of the filter circuit and a reset terminal of the D flip-flop, wherein the second circuit comprises: a second delay line; a second inverter; a third inverter; a NAND gate; and an OR gate, wherein the second delay line is coupled between the input terminal of the filter circuit and the second inverter, the third inverter is coupled between the second inverter and a first input of the NAND gate, and a second input of the NAND gate is coupled to an output of the second inverter, wherein a first input of the OR gate is coupled to the input terminal of the filter circuit, a second input of the OR gate is coupled to an output of the NAND gate, and an output of the OR gate is coupled to the reset terminal of the D flip-flop.

[0069] Example 13. The filter circuit according to Example 12, wherein an input terminal of the D flip-flop is configured to be coupled to a logic high signal.

[0070] Example 14. The filter circuit according to Example 13, wherein an input clock terminal of the D flip-flop is configured to receive a clock signal having a valid rising edge, and a reset terminal of the D flip-flop is configured to receive a reset signal having a valid low voltage level.

[0071] Example 15. The filter circuit according to Example 13, wherein the first circuit further comprises one or more buffers, wherein the one or more buffers are coupled in series between the first inverter and the first input of the first AND gate.

[0072] Example 16. The filter circuit according to Example 13, wherein the second circuit further comprises one or more buffers, wherein the one or more buffers are coupled in series between the second inverter and the third inverter.

[0073] Example 17. A method for filtering a pulse width modulation (PWM) signal, the method comprising: applying a logic high signal to an input terminal of a D flip-flop; processing a first pulse of the PWM signal using a first circuit and a second circuit to generate a clock signal and a reset signal respectively, wherein the duty cycle of the first pulse is within a predetermined range, wherein the clock signal is a positive pulse and the reset signal is a negative pulse; and sending the clock signal and the reset signal to a clock terminal and a reset terminal of the D flip-flop respectively.

[0074] Example 18. The method according to Example 17, further comprising: generating an output signal at an output terminal of the D flip-flop by the D flip-flop, the output signal having the same pulse width as the first pulse of the PWM signal.

[0075] Example 19. The method according to Example 18, further comprising: processing a second pulse of the PWM signal using the first circuit and the second circuit to generate a first signal and a second signal respectively, wherein the second pulse has a duty cycle outside the predetermined range, wherein the first circuit is configured to stop generating the clock signal when the second pulse is a positive pulse, and the second circuit is configured to stop generating the reset signal when the second pulse is a negative pulse; and sending the first signal and the second signal to the clock terminal and the reset terminal of the D flip-flop respectively.

[0076] Example 20. The method according to Example 19, wherein the D flip-flop is configured to not generate a pulse at the output terminal of the D flip-flop in response to the first signal and the second signal.

[0077] Although the present invention has been described with reference to illustrative embodiments, the description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be apparent to those skilled in the art based on a review of the specification. Accordingly, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A filtering circuit for filtering a pulse width modulation (PWM) signal, the filtering circuit comprising: A D flip-flop, an input terminal of the D flip-flop being configured to be coupled to a logic high signal, and an output terminal of the D flip-flop being coupled to an output terminal of the filtering circuit; And A circuit coupled between an input terminal of the filtering circuit and the D flip-flop, the circuit being configured to: for a first pulse of the PWM signal having a duty cycle within a predetermined range: Generate a positive pulse at a clock terminal of the D flip-flop as a clock signal of the D flip-flop; And Generate a negative pulse at a reset terminal of the D flip-flop as a reset signal of the D flip-flop, wherein a duration between a rising edge of the positive pulse and a falling edge of the negative pulse is equal to a duration of the first pulse of the PWM signal.

2. The filtering circuit according to claim 1, wherein the D flip-flop is configured to generate an output pulse at the output terminal of the D flip-flop using the clock signal and the reset signal, the output pulse corresponding to the first pulse of the PWM signal and having the same duration as the first pulse.

3. The filtering circuit according to claim 2, wherein the circuit is configured to: for a second pulse of the PWM signal having a duty cycle outside the predetermined range: Stop generating the positive pulse or stop generating the negative pulse, thereby preventing the D flip-flop from generating an output pulse corresponding to the second pulse of the PWM signal.

4. The filtering circuit according to claim 1, wherein the predetermined range is substantially centered relative to an entire range between a zero percent duty cycle and a one hundred percent duty cycle.

5. The filtering circuit according to claim 1, wherein the clock signal of the D flip-flop is rising-edge effective, and the reset signal of the D flip-flop is low-effective.

6. The filtering circuit according to claim 1, wherein the PWM signal includes a first plurality of positive pulses having a duty cycle within the predetermined range, and for each positive pulse of the first plurality of positive pulses: Before the reset signal of the D flip-flop is generated by the circuit, the clock signal of the D flip-flop is generated by the circuit.

7. The filtering circuit according to claim 1, wherein the PWM signal includes a first plurality of negative pulses, and for each negative pulse of the first plurality of negative pulses: After the reset signal of the D flip-flop is generated by the circuit, the clock signal of the D flip-flop is generated by the circuit.

8. The filtering circuit according to claim 1, wherein the circuit includes: A first delay line having a first predetermined delay, an input of the first delay line being coupled to the input terminal of the filtering circuit; A first inverter, an input of the first inverter being coupled to an output of the first delay line; A first AND gate, a first input of the first AND gate being coupled to the output of the first inverter, and a second input of the first AND gate being coupled to the output of the first delay line; and a second AND gate, a first input of the second AND gate being coupled to an output of the first AND gate, a second input of the second AND gate being coupled to the input terminal of the filter circuit, and an output of the second AND gate being coupled to the clock terminal of the D flip-flop.

9. The filter circuit according to claim 8, wherein the circuit further comprises one or more buffers coupled between the output of the first inverter and the first input of the first AND gate.

10. The filter circuit according to claim 8, wherein the circuit further comprises: a second delay line having a second predetermined delay, an input of the second delay line being coupled to the input terminal of the filter circuit; a second inverter, an input of the second inverter being coupled to an output of the second delay line; a third inverter, an input of the third inverter being coupled to an output of the second inverter; a NAND gate, a first input of the NAND gate being coupled to the output of the second inverter, a second input of the NAND gate being coupled to the output of the third inverter; and an OR gate, a first input of the OR gate being coupled to the output of the NAND gate, a second input of the OR gate being coupled to the input terminal of the filter circuit, and an output of the OR gate being coupled to the reset terminal of the D flip-flop.

11. The filter circuit according to claim 10, wherein the circuit further comprises one or more buffers coupled between the output of the second inverter and the input of the third inverter.

12. A filter circuit for filtering a pulse width modulation (PWM) signal, the filter circuit comprising: a D flip-flop; a first circuit coupled between an input terminal of the filter circuit and an input clock terminal of the D flip-flop, wherein the first circuit comprises: a first delay line; a first inverter; a first AND gate; and a second AND gate, wherein the first delay line is coupled between the input terminal of the filter circuit and the first inverter, the first inverter is coupled between the first delay line and a first input of the first AND gate, and a second input of the first AND gate is coupled to an output of the first delay line, wherein a first input of the second AND gate is coupled to the input terminal of the filter circuit, a second input of the second AND gate is coupled to an output of the first AND gate, and an output of the second AND gate is coupled to the input clock terminal of the D flip-flop; and a second circuit coupled between the input terminal of the filter circuit and a reset terminal of the D flip-flop, wherein the second circuit comprises: a second delay line; a second inverter; a third inverter; a NAND gate; and An OR gate, wherein the second delay line is coupled between the input terminal of the filtering circuit and the second inverter, the third inverter is coupled between the second inverter and the first input of the NAND gate, and the second input of the NAND gate is coupled to the output of the second inverter, wherein the first input of the OR gate is coupled to the input terminal of the filtering circuit, the second input of the OR gate is coupled to the output of the NAND gate, and the output of the OR gate is coupled to the reset terminal of the D flip-flop.

13. The filtering circuit according to claim 12, wherein the input terminal of the D flip-flop is configured to be coupled to a logic high signal.

14. The filtering circuit according to claim 13, wherein the input clock terminal of the D flip-flop is configured to receive a clock signal having a valid rising edge, and the reset terminal of the D flip-flop is configured to receive a reset signal having a valid low voltage level.

15. The filtering circuit according to claim 13, wherein the first circuit further comprises one or more buffers, wherein the one or more buffers are coupled in series between the first inverter and the first input of the first AND gate.

16. The filtering circuit according to claim 13, wherein the second circuit further comprises one or more buffers, wherein the one or more buffers are coupled in series between the second inverter and the third inverter.

17. A method for filtering a pulse width modulation (PWM) signal, the method comprising: Applying a logic high signal to the input terminal of a D flip-flop; Processing a first pulse of the PWM signal using a first circuit and a second circuit to respectively generate a clock signal and a reset signal, wherein the first pulse has a duty cycle within a predetermined range, wherein the clock signal is a positive pulse, and the reset signal is a negative pulse; And Sending the clock signal and the reset signal to the clock terminal and the reset terminal of the D flip-flop respectively.

18. The method according to claim 17, further comprising: Generating, by the D flip-flop, an output signal at the output terminal of the D flip-flop, the output signal having the same pulse width as the first pulse of the PWM signal.

19. The method according to claim 18, further comprising: Processing a second pulse of the PWM signal using the first circuit and the second circuit to respectively generate a first signal and a second signal, wherein the second pulse has a duty cycle outside the predetermined range, wherein the first circuit is configured to: stop generating the clock signal when the second pulse is a positive pulse, and the second circuit is configured to: stop generating the reset signal when the second pulse is a negative pulse; And Sending the first signal and the second signal to the clock terminal and the reset terminal of the D flip-flop respectively.

20. The method according to claim 19, wherein the D flip-flop is configured to not generate a pulse at the output terminal of the D flip-flop in response to the first signal and the second signal.

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