Integrated device of reference voltage source with base current compensation

Abstract

The present disclosure provides a reference voltage source integrated device with base current compensation, comprising: a reference voltage generating module, the base of the reference voltage generating module is used to output a reference voltage; a base current compensation module, the base current compensation module generates a base compensation current and outputs it to the base of the reference voltage generating module to offset the base current of the base of the reference voltage source generating module, so that the reference voltage generating module outputs a compensated reference voltage; and a reference voltage output module, the reference voltage output module includes a voltage adjustment submodule, and the voltage adjustment submodule can increase the compensated reference voltage to a predetermined voltage.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of reference voltage sources, and in particular relates to a reference voltage source integrated device with base current compensation. Background Art

[0002] Reference voltage sources are widely used in integrated devices (eg, integrated circuit chips) because they can generate accurate and stable reference voltages.

[0003] However, the reference voltage source in the prior art still has the problem of low accuracy, for example, being affected by external factors of the voltage source or circuit structure. Summary of the invention

[0004] In order to solve at least one of the above technical problems, the present disclosure provides a reference voltage source integrated device with base current compensation.

[0005] The reference voltage source integrated device with base current compensation disclosed in the present invention is implemented through the following technical solution.

[0006] The integrated device of reference voltage source with base current compensation includes:

[0007] A reference voltage generating module, the base of which is used to output a reference voltage; a base current compensation module, which generates a base compensation current and outputs it to the base of the reference voltage generating module to offset the base current of the base of the reference voltage source generating module, so that the reference voltage generating module outputs a compensated reference voltage; and a reference voltage output module, which includes a voltage adjustment submodule, which is capable of raising the compensated reference voltage to a predetermined voltage.

[0008] According to at least one embodiment of the reference voltage source integrated device with base current compensation disclosed herein, the reference voltage output module includes a third resistor, a fourth resistor and a first buffer, the first end of the third resistor is grounded, the second end of the third resistor is connected to the first end of the fourth resistor, the second end of the fourth resistor is connected to the first end of the first buffer, the second end of the first buffer is connected to the device voltage end of the reference voltage source integrated device, the second end of the third resistor is connected to the base of the reference voltage generating module, and the second end of the fourth resistor outputs the predetermined voltage.

[0009] According to the reference voltage source integrated device with base current compensation of at least one embodiment of the present disclosure, the predetermined voltage can be adjusted by a ratio of the third resistor to the fourth resistor.

[0010] According to at least one embodiment of the reference voltage source integrated device with base current compensation disclosed herein, the base current compensation module includes a first current mirror module, a second current mirror module and a first compensation transistor. The first current mirror module mirrors the bias current of the reference voltage integrated device to M times, that is, M*IPTAT, where M is a natural number greater than or equal to 1, so that the emitter current of the first compensation transistor is M times the bias current and the base current of the first compensation transistor is M*IPTAT / Beta, wherein Beta is the current amplification factor of the first compensation transistor. The second current mirror module mirrors the base current of the first compensation transistor to M*IPTAT / Beta, and outputs it to the base of the reference voltage generating module as the base compensation current.

[0011] According to at least one embodiment of the reference voltage source integrated device with base current compensation of the present disclosure, the base current compensation module includes a first current mirror module, a second current mirror module and a first compensation transistor. The first current mirror module mirrors the bias current IPTAT of the reference voltage integrated device to twice, i.e., 2*IPTAT, so that the emitter current of the first compensation transistor is twice the bias current and the base current of the first compensation transistor is 2*IPTAT / Beta, wherein Beta is the current amplification factor of the first compensation transistor. The second current mirror module mirrors the base current of the first compensation transistor to 2*IPTAT / Beta, which is output as the base compensation current to the base of the reference voltage generating module.

[0012] According to at least one embodiment of the reference voltage source integrated device with base current compensation disclosed herein, the first current mirror module includes a third N-type field effect transistor and a fourth N-type field effect transistor, the first end of the third N-type field effect transistor is grounded, the first end of the fourth N-type field effect transistor is grounded, the control end of the third N-type field effect transistor is connected to the control end of the fourth N-type field effect transistor, the second end of the third N-type field effect transistor is connected to the control end of the third N-type field effect transistor, the second end of the third N-type field effect transistor is input with a bias current, and the second end of the fourth N-type field effect transistor is connected to the emitter of the first compensation transistor.

[0013] According to the reference voltage source integrated device with base current compensation of at least one embodiment of the present disclosure, the second current mirror module includes a seventh P-type field effect transistor, an eighth P-type field effect transistor, a ninth P-type field effect transistor and a tenth P-type field effect transistor, the first end of the eighth P-type field effect transistor is connected to the base of the first compensation transistor, the second end of the eighth P-type field effect transistor is connected to the first end of the tenth P-type field effect transistor, the second end of the tenth P-type field effect transistor is connected to the device voltage end of the reference voltage source integrated device, the second end of the ninth P-type field effect transistor is connected to the device voltage end of the reference voltage source integrated device, the first end of the ninth P-type field effect transistor is connected to the second end of the seventh P-type field effect transistor, and the first end of the seventh P-type field effect transistor is connected to the base of the reference voltage generation module;

[0014] The control end of the seventh P-type field effect transistor is connected to the control end of the eighth P-type field effect transistor, and the control end of the ninth P-type field effect transistor is connected to the control end of the tenth P-type field effect transistor;

[0015] The first end of the eighth P-type field effect transistor is connected to the control end of the tenth P-type field effect transistor.

[0016] According to at least one embodiment of the reference voltage source integrated device with base current compensation of the present disclosure, the ratio of the channel width-to-length ratio of the third N-type field effect transistor to the channel width-to-length ratio of the fourth N-type field effect transistor is 1:2.

[0017] According to at least one embodiment of the reference voltage source integrated device with base current compensation disclosed herein, the channel area width-to-length ratio of the seventh P-type field effect transistor is the same as the channel width-to-length ratio of the eighth P-type field effect transistor, and the channel width-to-length ratio of the ninth P-type field effect transistor is the same as the channel width-to-length ratio of the tenth P-type field effect transistor.

[0018] According to the reference voltage source integrated device with base current compensation of at least one embodiment of the present disclosure, the base current compensation module also includes a second buffer, a first end of the second buffer is connected to the collector of the first compensation transistor, a second end of the second buffer is connected to the device voltage end of the reference voltage source integrated device, and a control end of the second buffer is connected to the control end of the first buffer.

[0019] According to the reference voltage source integrated device with base current compensation of at least one embodiment of the present disclosure, the base current compensation module also includes a third current mirror module, which mirrors the bias current of the reference voltage generating module to input the bias current to the first current mirror module, so that the first current mirror module mirrors the bias current of the reference voltage integrated device to twice.

[0020] According to at least one embodiment of the reference voltage source integrated device with base current compensation of the present disclosure, the reference voltage generation module includes a first P-type field effect transistor, a second P-type field effect transistor, a fourth P-type field effect transistor, a fifth P-type field effect transistor, a bias resistor, a first N-type field effect transistor, a second N-type field effect transistor, a first transistor, a second transistor, a first resistor and a second resistor;

[0021] The second end of the fourth P-type field effect transistor is connected to the device voltage end of the reference voltage source integrated device, the first end of the fourth P-type field effect transistor is connected to the second end of the first P-type field effect transistor, the first end of the first P-type field effect transistor is connected to the second end of the bias resistor, the first end of the bias resistor is connected to the second end of the first N-type field effect transistor, the first end of the first N-type field effect transistor is connected to the collector of the first triode, the emitter of the first triode is connected to the second end of the first resistor, the first end of the first resistor is connected to the second end of the second resistor, and the first end of the second resistor is grounded;

[0022] The second end of the fifth P-type field effect transistor is connected to the device voltage end of the reference voltage source integrated device, the first end of the fifth P-type field effect transistor is connected to the second end of the second P-type field effect transistor, the first end of the second P-type field effect transistor is connected to the second end of the second N-type field effect transistor, the first end of the second N-type field effect transistor is connected to the collector of the second transistor, and the emitter of the second transistor is connected to the second end of the second resistor;

[0023] The control end of the fourth P-type field effect transistor is connected to the control end of the fifth P-type field effect transistor;

[0024] The control end of the fourth P-type field effect transistor is connected to the first end of the first P-type field effect transistor;

[0025] The control end of the first P-type field effect transistor is connected to the control end of the second P-type field effect transistor;

[0026] The control end of the first P-type field effect transistor is connected to the second end of the first N-type field effect transistor;

[0027] The second end of the second N-type field effect transistor is connected to the control end of the second N-type field effect transistor;

[0028] The base of the first transistor is connected to the base of the second transistor.

[0029] According to at least one embodiment of the reference voltage source integrated device with base current compensation disclosed herein, the third current mirror module includes a third P-type field effect transistor and a sixth P-type field effect transistor, the second end of the sixth P-type field effect transistor is connected to the device voltage end of the reference voltage source integrated device, the first end of the sixth P-type field effect transistor is connected to the second end of the third P-type field effect transistor, and the first end of the third P-type field effect transistor is connected to the second end of the third N-type field effect transistor of the first current mirror module.

[0030] According to the reference voltage source integrated device with base current compensation of at least one embodiment of the present disclosure, the fourth P-type field effect transistor, the fifth P-type field effect transistor and the sixth P-type field effect transistor have the same channel width-to-length ratio.

[0031] According to the reference voltage source integrated device with base current compensation of at least one embodiment of the present disclosure, the channel width-to-length ratios of the first P-type field effect transistor, the second P-type field effect transistor, and the third P-type field effect transistor are the same.

[0032] According to the reference voltage source integrated device with base current compensation of at least one embodiment of the present disclosure, the channel width-to-length ratio of the first N-type field effect transistor is the same as the channel width-to-length ratio of the second N-type field effect transistor.

[0033] According to the reference voltage source integrated device with base current compensation of at least one embodiment of the present disclosure, the emitter area ratio of the first transistor to the second transistor is N:1, where N is a natural number.

[0034] According to the reference voltage source integrated device with base current compensation of at least one embodiment of the present disclosure, the first current mirror module includes a third N-type field effect transistor, a fourth N-type field effect transistor, a fifth N-type field effect transistor, a sixth N-type field effect transistor and a fifth resistor;

[0035] The first end of the third N-type field effect transistor is grounded, the first end of the fourth N-type field effect transistor is grounded, and the control end of the third N-type field effect transistor is connected to the control end of the fourth N-type field effect transistor;

[0036] The second end of the third N-type field effect transistor is connected to the first end of the fifth N-type field effect transistor, the second end of the fourth N-type field effect transistor is connected to the first end of the sixth N-type field effect transistor; the control end of the fifth N-type field effect transistor is connected to the control end of the sixth N-type field effect transistor;

[0037] The control end of the third N-type field effect transistor is connected to the second end of the fifth N-type field effect transistor;

[0038] The first end of the fifth resistor is connected to the second end of the fifth N-type field effect transistor;

[0039] The second end of the fifth resistor is connected to the control end of the fifth N-type field effect transistor;

[0040] The bias current is input to the second end of the fifth resistor, and the second end of the sixth N-type field effect transistor is connected to the emitter of the first compensation transistor.

[0041] According to the reference voltage source integrated device with base current compensation of at least one embodiment of the present disclosure, the second current mirror module includes a seventh P-type field effect transistor, an eighth P-type field effect transistor, a ninth P-type field effect transistor and a tenth P-type field effect transistor;

[0042] The second current mirror module also includes a third buffer and an operational amplifier, wherein the second end of the third buffer is connected to the first end of the eighth P-type field effect transistor, the first end of the third buffer is connected to the base of the first compensation transistor, the output end of the operational amplifier OP is connected to the control end of the third buffer, the non-inverting input end of the operational amplifier OP is connected to the first end of the seventh P-type field effect transistor, and the inverting input end of the operational amplifier OP is connected to the first end of the third buffer;

[0043] The first end of the eighth P-type field effect transistor is connected to the second end of the third buffer, the second end of the eighth P-type field effect transistor is connected to the first end of the tenth P-type field effect transistor, the second end of the tenth P-type field effect transistor is connected to the device voltage end of the reference voltage source integrated device, the second end of the ninth P-type field effect transistor is connected to the device voltage end of the reference voltage source integrated device, the first end of the ninth P-type field effect transistor is connected to the second end of the seventh P-type field effect transistor, and the first end of the seventh P-type field effect transistor is connected to the base of the reference voltage generation module;

[0044] The control end of the seventh P-type field effect transistor is connected to the control end of the eighth P-type field effect transistor, and the control end of the ninth P-type field effect transistor is connected to the control end of the tenth P-type field effect transistor;

[0045] The first end of the eighth P-type field effect transistor is connected to the control end of the tenth P-type field effect transistor.

[0046] According to at least one embodiment of the reference voltage source integrated device with base current compensation of the present disclosure, the ratio of the channel width-to-length ratio of the third N-type field effect transistor to the channel width-to-length ratio of the fourth N-type field effect transistor is 1:2.

[0047] According to at least one embodiment of the reference voltage source integrated device with base current compensation disclosed herein, the channel area width-to-length ratio of the seventh P-type field effect transistor is the same as the channel width-to-length ratio of the eighth P-type field effect transistor, and the channel width-to-length ratio of the ninth P-type field effect transistor is the same as the channel width-to-length ratio of the tenth P-type field effect transistor.

[0048] According to the reference voltage source integrated device with base current compensation of at least one embodiment of the present disclosure, the third current mirror module includes a third P-type field effect transistor and a sixth P-type field effect transistor, the second end of the sixth P-type field effect transistor is connected to the device voltage end of the reference voltage source integrated device, the first end of the sixth P-type field effect transistor is connected to the second end of the third P-type field effect transistor, and the first end of the third P-type field effect transistor is connected to the second end of the fifth resistor of the first current mirror module. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The accompanying drawings illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

[0050] Figure 1 A schematic diagram of the circuit structure of a reference voltage source integrated device with base current compensation according to an embodiment of the present disclosure.

[0051] Figure 2 A schematic diagram of the circuit structure of a reference voltage source integrated device with base current compensation according to yet another embodiment of the present disclosure. DETAILED DESCRIPTION

[0052] The present disclosure is further described in detail below in conjunction with the accompanying drawings and implementations. It is understood that the specific implementations described herein are only used to explain the relevant content, rather than to limit the present disclosure. It should also be noted that, for ease of description, only the parts related to the present disclosure are shown in the accompanying drawings.

[0053] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in the present disclosure can be combined with each other. The technical solution of the present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0054] Unless otherwise specified, the exemplary embodiments / embodiments shown will be understood as providing exemplary features of various details of some ways in which the technical concept of the present disclosure can be implemented in practice. Therefore, unless otherwise specified, the features of the various embodiments / embodiments can be combined, separated, interchanged and / or rearranged without departing from the technical concept of the present disclosure.

[0055] The use of cross-hatching and / or shading in the accompanying drawings is generally used to make the boundaries between adjacent components clear. As such, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for the specific materials, material properties, dimensions, proportions, commonalities between the components shown, and / or any other characteristics, attributes, properties, etc. of the components. In addition, in the accompanying drawings, the sizes and relative sizes of the components may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed in a different order than described. For example, two successively described processes can be performed substantially simultaneously or in an order opposite to the described order. In addition, the same figure numbers represent the same components.

[0056] When a component is referred to as being "on" or "over," "connected to," or "coupled to" another component, the component may be directly on, directly connected to, or directly coupled to the other component, or intervening components may be present. However, when a component is referred to as being "directly on," "directly connected to," or "directly coupled to" another component, there are no intervening components. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, etc., with or without intervening components.

[0057] For descriptive purposes, the present disclosure may use spatially relative terms such as "under," "beneath," "under," "down," "over," "upper," "above," "higher," and "side (e.g., as in "sidewall")," to describe the relationship of one component to another (other) component as shown in the accompanying drawings. The spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, components described as "under" or "beneath" other components or features would subsequently be positioned "over" the other components or features. Thus, the exemplary term "under" can encompass both the "above" and "below" orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0058] The terms used here are for the purpose of describing specific embodiments, and are not intended to be restrictive. As used here, unless the context clearly indicates otherwise, the singular forms "one (kind, person)" and "said (the)" are also intended to include plural forms. In addition, when the terms "comprise" and / or "include" and their variations are used in this specification, it is explained that there are stated features, integral bodies, steps, operations, parts, assemblies and / or their groups, but it is not excluded that there are or add one or more other features, integral bodies, steps, operations, parts, assemblies and / or their groups. It should also be noted that, as used here, the terms "substantially", "approximately" and other similar terms are used as approximate terms and not as degree terms, so that they are used to explain the inherent deviations of the measured values, calculated values ​​and / or the values ​​provided that will be recognized by those of ordinary skill in the art.

[0059] According to an embodiment of the present disclosure, a reference voltage source integrated device 10 with base current compensation includes: a reference voltage generating module 100, wherein the base B of the reference voltage generating module 100 is used to output a reference voltage; a base current compensation module 200, wherein the base current compensation module 200 generates a base compensation current and outputs it to the base B of the reference voltage generating module 100 to offset the base current of the base B of the reference voltage source generating module 100, so that the reference voltage generating module 100 outputs a compensated reference voltage VREF1 (for example, 1.24V); and a reference voltage output module 300, wherein the reference voltage output module 300 includes a voltage adjustment submodule (including MNbuf1, R3, and R4), and the voltage adjustment submodule is capable of raising the compensated reference voltage to a predetermined voltage VREF.

[0060] The reference voltage generation module 100 may adopt a reference source core module in the prior art.

[0061] Those skilled in the art should understand that the reference voltage source integrated device with base current compensation 10 may be an independent integrated device (eg, an integrated circuit chip) or a part of other integrated devices (eg, an integrated circuit chip).

[0062] In the reference voltage source integrated device 10 of the above embodiment, the base current compensation module 200 generates a base compensation current to offset the base current of the base B of the reference voltage source generating module 100, so that the error caused by the base current is eliminated.

[0063] The reference voltage source integrated device 10 of the above embodiment realizes the output of any voltage through the reference voltage output module 300 including the voltage adjustment submodule (including MNbuf1, R3, R4).

[0064] Figure 1It is a schematic diagram of the circuit structure of a reference voltage source integrated device 10 with base current compensation according to a preferred embodiment of the present disclosure.

[0065] like Figure 1 As shown, preferably, the reference voltage output module 300 includes a third resistor R3, a fourth resistor R4 and a first buffer MNbuf1, the first end of the third resistor R3 is grounded Vss, the second end of the third resistor R3 is connected to the first end of the fourth resistor R4, the second end of the fourth resistor R4 is connected to the first end of the first buffer MNbuf1, the second end of the first buffer is connected to the device voltage terminal VDD of the reference voltage source integrated device 10, the second end of the third resistor R3 is connected to the base B of the reference voltage generating module 100, and the second end of the fourth resistor R4 outputs a predetermined voltage.

[0066] The first buffer MNbuf1 is an N-type field effect transistor.

[0067] For the reference voltage source integrated device 10 of the above embodiment, the predetermined voltage can be adjusted by the ratio of the third resistor R3 to the fourth resistor R4.

[0068] The third resistor and the fourth resistor may both be adjustable resistance resistors.

[0069] In the above embodiment, preferably, the base current compensation module 200 of the reference voltage source integrated device 10 includes a first current mirror module, a second current mirror module and a first compensation transistor Qcomp. The first current mirror module mirrors the bias current IPTAT of the reference voltage integrated device 10 to M times, that is, M*IPTAT, M is a natural number greater than or equal to 1, so that the emitter current of the first compensation transistor Qcomp is M times the bias current and the base current of the first compensation transistor Qcomp is M*IPTAT / Beta, wherein Beta is the current amplification factor of the first compensation transistor Qcomp. The second current mirror module mirrors the base current of the first compensation transistor Qcomp to M*IPTAT / Beta, and outputs it to the base B of the reference voltage generation module 100 as the base compensation current.

[0070] In the above embodiment, more preferably, the base current compensation module 200 includes a first current mirror module, a second current mirror module and a first compensation transistor Qcomp. The first current mirror module mirrors the bias current IPTAT of the reference voltage integrated device to twice, that is, 2*IPTAT, so that the emitter current of the first compensation transistor Qcomp is twice the bias current and the base current of the first compensation transistor Qcomp is 2*IPTAT / Beta, wherein Beta is the current amplification factor of the first compensation transistor Qcomp. The second current mirror module mirrors the base current of the first compensation transistor Qcomp to 2*IPTAT / Beta, and outputs it to the base B of the reference voltage generation module 100 as the base compensation current.

[0071] Preferably, the first current mirror module of the reference voltage source integrated device 10 includes a third N-type field effect transistor MN3 and a fourth N-type field effect transistor MN4, the first end of the third N-type field effect transistor MN3 is grounded, the first end of the fourth N-type field effect transistor MN4 is grounded, the control end of the third N-type field effect transistor MN3 is connected to the control end of the fourth N-type field effect transistor MN4, the second end of the third N-type field effect transistor MN3 is connected to the control end of the third N-type field effect transistor MN3, the second end of the third N-type field effect transistor MN3 is input with a bias current IPTAT, and the second end of the fourth N-type field effect transistor MN4 is connected to the emitter of the first compensation transistor Qcomp.

[0072] Preferably, the second current mirror module of the reference voltage source integrated device 10 includes a seventh P-type field effect transistor MP7, an eighth P-type field effect transistor MP8, a ninth P-type field effect transistor MP9 and a tenth P-type field effect transistor MP10, the first end of the eighth P-type field effect transistor MP8 is connected to the base of the first compensation transistor Qcomp, the second end of the eighth P-type field effect transistor MP8 is connected to the first end of the tenth P-type field effect transistor MP10, the second end of the tenth P-type field effect transistor MP10 is connected to the device voltage terminal VDD of the reference voltage source integrated device 10, the second end of the ninth P-type field effect transistor MP9 is connected to the device voltage terminal VDD of the reference voltage source integrated device 10, the first end of the ninth P-type field effect transistor MP9 is connected to the second end of the seventh P-type field effect transistor MP7, and the first end of the seventh P-type field effect transistor MP7 is connected to the base B of the reference voltage generation module 100;

[0073] The control end of the seventh P-type field effect transistor MP7 is connected to the control end of the eighth P-type field effect transistor MP8, and the control end of the ninth P-type field effect transistor MP9 is connected to the control end of the tenth P-type field effect transistor MP10;

[0074] The first end of the eighth P-type field effect transistor MP8 is connected to the control end of the tenth P-type field effect transistor MP10 .

[0075] According to a preferred embodiment of the present disclosure, the ratio of the channel width-to-length ratio of the third N-type field effect transistor MN3 to the channel width-to-length ratio of the fourth N-type field effect transistor MN4 of the reference voltage source integrated device with base current compensation 10 is 1:2.

[0076] Preferably, the channel area width-to-length ratio of the seventh P-type field effect transistor MP7 is the same as the channel area width-to-length ratio of the eighth P-type field effect transistor MP8, and the channel area width-to-length ratio of the ninth P-type field effect transistor MP9 is the same as the channel area width-to-length ratio of the tenth P-type field effect transistor MP10.

[0077] In the above embodiment, preferably, the base current compensation module 200 of the reference voltage source integrated device 10 also includes a second buffer MNbuf2, a first end of the second buffer MNbuf2 is connected to the collector of the first compensation transistor Qcomp, a second end of the second buffer MNbuf2 is connected to the device voltage terminal VDD of the reference voltage source integrated device 10, and a control end of the second buffer MNbuf2 is connected to the control end of the first buffer MNbuf1.

[0078] Wherein, the second buffer is an N-type field effect transistor.

[0079] For the reference voltage source integrated device 10 with base current compensation of the above-mentioned embodiment, the base current compensation module 200 also includes a third current mirror module, which mirrors the bias current IPTAT of the reference voltage generating module 100 to input the bias current IPTAT to the first current mirror module, so that the first current mirror module mirrors the bias current IPTAT of the reference voltage integrated device to twice.

[0080] For the reference voltage source integrated device 10 with base current compensation of the above embodiment, the reference voltage generation module 100 includes a first P-type field effect transistor MP1, a second P-type field effect transistor MP2, a fourth P-type field effect transistor MP4, a fifth P-type field effect transistor MP5, a bias resistor Rb, a first N-type field effect transistor MN1, a second N-type field effect transistor MN2, a first transistor Q1, a second transistor Q2, a first resistor R1 and a second resistor R2;

[0081] The second end of the fourth P-type field effect transistor MP4 is connected to the device voltage terminal VDD of the reference voltage source integrated device 10, the first end of the fourth P-type field effect transistor MP4 is connected to the second end of the first P-type field effect transistor MP1, the first end of the first P-type field effect transistor MP1 is connected to the second end of the bias resistor Rb, the first end of the bias resistor Rb is connected to the second end of the first N-type field effect transistor MN1, the first end of the first N-type field effect transistor MN1 is connected to the collector C of the first transistor Q1, the emitter of the first transistor Q1 is connected to the second end of the first resistor R1, the first end of the first resistor R1 is connected to the second end of the second resistor R2, and the first end of the second resistor R2 is grounded to Vss;

[0082] The second end of the fifth P-type field effect transistor MP5 is connected to the device voltage terminal VDD of the reference voltage source integrated device 10, the first end of the fifth P-type field effect transistor MP5 is connected to the second end of the second P-type field effect transistor MP2, the first end of the second P-type field effect transistor MP2 is connected to the second end of the second N-type field effect transistor MN2, the first end of the second N-type field effect transistor MN2 is connected to the collector C of the second triode Q2, and the emitter E of the second triode Q2 is connected to the second end of the second resistor R2;

[0083] The control end of the fourth P-type field effect transistor MP4 is connected to the control end of the fifth P-type field effect transistor MP5;

[0084] The control end of the fourth P-type field effect transistor MP4 is connected to the first end of the first P-type field effect transistor MP1;

[0085] The control end of the first P-type field effect transistor MP1 is connected to the control end of the second P-type field effect transistor MP2;

[0086] The control end of the first P-type field effect transistor MP1 is connected to the second end of the first N-type field effect transistor MN1;

[0087] The second end of the second N-type field effect transistor MN2 is connected to the control end of the second N-type field effect transistor MN2;

[0088] The base of the first transistor Q1 is connected to the base of the second transistor Q2.

[0089] Preferably, the third current mirror module includes a third P-type field effect transistor MP3 and a sixth P-type field effect transistor MP6, the second end of the sixth P-type field effect transistor MP6 is connected to the device voltage terminal VDD of the reference voltage source integrated device 10, the first end of the sixth P-type field effect transistor MP6 is connected to the second end of the third P-type field effect transistor MP3, and the first end of the third P-type field effect transistor MP3 is connected to the second end of the third N-type field effect transistor MN3 of the first current mirror module.

[0090] For the reference voltage source integrated device with base current compensation 10 of the above embodiment, the fourth P-type field effect transistor MP4 , the fifth P-type field effect transistor MP5 , and the sixth P-type field effect transistor MP6 have the same channel width-to-length ratio.

[0091] Preferably, the first P-type field effect transistor MP1 , the second P-type field effect transistor MP2 , and the third P-type field effect transistor MP3 have the same channel width-to-length ratio.

[0092] Preferably, the channel width-to-length ratio of the first N-type field effect transistor MN1 is the same as the channel width-to-length ratio of the second N-type field effect transistor MN2.

[0093] Preferably, the emitter area ratio of the first transistor Q1 to the second transistor Q2 is N:1, where N is a natural number.

[0094] Figure 2 It is a circuit structure diagram of a reference voltage source integrated device 10 with base current compensation according to another preferred embodiment of the present disclosure.

[0095] The following article focuses on Figure 2 The circuit structure and Figure 1 The differences between the circuit structures shown are described below.

[0096] like Figure 2 As shown, the first current mirror module of the reference voltage source integrated device with base current compensation 10 includes a third N-type field effect transistor MN3, a fourth N-type field effect transistor MN4, a fifth N-type field effect transistor MN5, a sixth N-type field effect transistor MN4 and a fifth resistor R5;

[0097] A first end of the third N-type field effect transistor MN3 is grounded, a first end of the fourth N-type field effect transistor MN4 is grounded, and a control end of the third N-type field effect transistor MN3 is connected to a control end of the fourth N-type field effect transistor MN4;

[0098] The second end of the third N-type field effect transistor MN3 is connected to the first end of the fifth N-type field effect transistor MN5, the second end of the fourth N-type field effect transistor MN4 is connected to the first end of the sixth N-type field effect transistor MN6; the control end of the fifth N-type field effect transistor MN3 is connected to the control end of the sixth N-type field effect transistor MN6;

[0099] The control end of the third N-type field effect transistor MN3 is connected to the second end of the fifth N-type field effect transistor MN5;

[0100] A first end of the fifth resistor R5 is connected to a second end of the fifth N-type field effect transistor MN5;

[0101] The second end of the fifth resistor R5 is connected to the control end of the fifth N-type field effect transistor MN5;

[0102] The bias current IPTAT is input to the second end of the fifth resistor R5 , and the second end of the sixth N-type field effect transistor MN6 is connected to the emitter of the first compensation transistor Qcomp.

[0103] Relative to Figure 1 The first current mirror module in Figure 2 The first current mirror module in the embodiment has higher current replication accuracy.

[0104] like Figure 2 As shown, preferably, the second current mirror module of the reference voltage source integrated device 10 includes a seventh P-type field effect transistor MP7, an eighth P-type field effect transistor MP8, a ninth P-type field effect transistor MP9 and a tenth P-type field effect transistor MP10;

[0105] The second current mirror module also includes a third buffer MNbuf3 and an operational amplifier OP, the second end of the third buffer MNbuf3 is connected to the first end of the eighth P-type field effect transistor MP8, the first end of the third buffer MNbuf3 is connected to the base of the first compensation transistor Qcomp, the output end of the operational amplifier OP is connected to the control end of the third buffer MNbuf3, the non-inverting input end of the operational amplifier OP is connected to the first end of the seventh P-type field effect transistor MP7, and the inverting input end of the operational amplifier OP is connected to the first end of the third buffer MNbuf3;

[0106] The first end of the eighth P-type field effect transistor MP8 is connected to the second end of the third buffer MNbuf3, the second end of the eighth P-type field effect transistor MP8 is connected to the first end of the tenth P-type field effect transistor MP10, the second end of the tenth P-type field effect transistor MP10 is connected to the device voltage terminal VDD of the reference voltage source integrated device 10, the second end of the ninth P-type field effect transistor MP9 is connected to the device voltage terminal VDD of the reference voltage source integrated device 10, the first end of the ninth P-type field effect transistor MP9 is connected to the second end of the seventh P-type field effect transistor MP7, and the first end of the seventh P-type field effect transistor MP7 is connected to the base B of the reference voltage generation module 100;

[0107] The control end of the seventh P-type field effect transistor MP7 is connected to the control end of the eighth P-type field effect transistor MP8, and the control end of the ninth P-type field effect transistor MP9 is connected to the control end of the tenth P-type field effect transistor MP10;

[0108] The first end of the eighth P-type field effect transistor MP8 is connected to the control end of the tenth P-type field effect transistor MP10 .

[0109] In the above embodiment, preferably, the ratio of the channel width-to-length ratio of the third N-type field effect transistor MN3 to the channel width-to-length ratio of the fourth N-type field effect transistor MN4 is 1:2.

[0110] In the above embodiment, preferably, the channel area width-to-length ratio of the seventh P-type field effect transistor MP7 is the same as the channel area width-to-length ratio of the eighth P-type field effect transistor MP8, and the channel area width-to-length ratio of the ninth P-type field effect transistor MP9 is the same as the channel area width-to-length ratio of the tenth P-type field effect transistor MP10.

[0111] In the above embodiment, preferably, the third current mirror module includes a third P-type field effect transistor MP3 and a sixth P-type field effect transistor MP6, the second end of the sixth P-type field effect transistor MP6 is connected to the device voltage terminal VDD of the reference voltage source integrated device 10, the first end of the sixth P-type field effect transistor MP6 is connected to the second end of the third P-type field effect transistor MP3, and the first end of the third P-type field effect transistor MP3 is connected to the second end of the fifth resistor R5 of the first current mirror module.

[0112] In the above implementation, preferably, the channel width-to-length ratio of the second buffer MNbuf2 and the channel width-to-length ratio of the second N-type field effect transistor MN2 are 2:1.

[0113] In the above implementation, preferably, the ratio of the fourth resistor R4 to the fifth resistor R5 is 2:1.

[0114] In the embodiment of the present invention, the emitter area of ​​the second transistor Q2 is the same as that of the first compensation transistor Qcomp.

[0115] The reference voltage source integrated device 10 disclosed in the present invention can achieve arbitrary voltage output without being based on an operational amplifier, has low offset performance, has a low temperature coefficient (no additional temperature coefficient caused by the operational amplifier offset voltage), can output high-precision voltage (the error caused by the base current is compensated), does not require a high Beta process, and therefore does not have an additional high-order temperature coefficient introduced by high Beta.

[0116] In the description of this specification, the description with reference to the terms "one embodiment / method", "some embodiments / methods", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment / method or example are included in at least one embodiment / method or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment / method or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments / methods or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments / methods or examples described in this specification and the features of the different embodiments / methods or examples, unless they are contradictory.

[0117] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0118] Those skilled in the art should understand that the above embodiments are only for the purpose of clearly illustrating the present disclosure, and are not intended to limit the scope of the present disclosure. For those skilled in the art, other changes or modifications may be made based on the above disclosure, and these changes or modifications are still within the scope of the present disclosure.

Claims

1. A reference voltage source integrated device with base current compensation, characterized in that: include: A reference voltage generating module, whose base is used to output a reference voltage; A base current compensation module, which generates a base compensation current and outputs it to the base of the reference voltage generation module to offset the base current of the base of the reference voltage generation module, so that the reference voltage generation module outputs a compensated reference voltage; as well as A reference voltage output module, comprising a voltage adjustment submodule, the voltage adjustment submodule being capable of raising the compensated reference voltage to a predetermined voltage; The base current compensation module includes a first current mirror module, a second current mirror module, a third current mirror module and a first compensation transistor. The third current mirror module mirrors the bias current IPTAT of the reference voltage integrated device to input the bias current to the first current mirror module. The first current mirror module mirrors the bias current to twice, i.e., 2*IPTAT, so that the emitter current of the first compensation transistor is twice the bias current and the base current of the first compensation transistor is 2*IPTAT / Beta, Beta is the current amplification factor of the first compensation transistor. The second current mirror module mirrors the base current of the first compensation transistor to 2*IPTAT / Beta, which is output as the base compensation current to the base of the reference voltage generation module. The base current compensation module also includes a second buffer, a first end of the second buffer is connected to the collector of the first compensation transistor, a second end of the second buffer is connected to the device voltage end of the reference voltage source integrated device, and a control end of the second buffer is connected to the control end of the first buffer; The third current mirror module includes: A third P-type field effect transistor, a first end of which is connected to the first current mirror module; and The sixth P-type field effect transistor has a second end connected to the device voltage end of the reference voltage source integrated device, and a first end connected to the second end of the third P-type field effect transistor.

2. The reference voltage source integrated device with base current compensation according to claim 1, characterized in that: The reference voltage output module includes a third resistor, a fourth resistor and a first buffer, the first end of the third resistor is grounded, the second end of the third resistor is connected to the first end of the fourth resistor, the second end of the fourth resistor is connected to the first end of the first buffer, the second end of the first buffer is connected to the device voltage end of the reference voltage source integrated device, the second end of the third resistor is connected to the base of the reference voltage generation module, and the second end of the fourth resistor outputs the predetermined voltage.

3. The reference voltage source integrated device with base current compensation according to claim 2, characterized in that: The predetermined voltage can be adjusted by a ratio of the third resistor to the fourth resistor.

4. The reference voltage source integrated device with base current compensation according to claim 1, characterized in that: The first current mirror module mirrors the bias current IPTAT of the reference voltage integrated device to M times, that is, M*IPTAT, where M is a natural number greater than or equal to 1, so that the emitter current of the first compensation transistor is M times the bias current and the base current of the first compensation transistor is M*IPTAT / Beta, where Beta is the current amplification factor of the first compensation transistor. The second current mirror module mirrors the base current of the first compensation transistor to M*IPTAT / Beta, and outputs it as the base compensation current to the base of the reference voltage generating module.

5. The reference voltage source integrated device with base current compensation according to claim 1, characterized in that: The first current mirror module includes a third N-type field effect transistor and a fourth N-type field effect transistor, the first end of the third N-type field effect transistor is grounded, the first end of the fourth N-type field effect transistor is grounded, the control end of the third N-type field effect transistor is connected to the control end of the fourth N-type field effect transistor, the second end of the third N-type field effect transistor is connected to the control end of the third N-type field effect transistor, the second end of the third N-type field effect transistor is connected to the first end of the third P-type field effect transistor, and a bias current is input, and the second end of the fourth N-type field effect transistor is connected to the emitter of the first compensation transistor.

6. The reference voltage source integrated device with base current compensation according to claim 1, characterized in that: The second current mirror module includes a seventh P-type field effect transistor, an eighth P-type field effect transistor, a ninth P-type field effect transistor and a tenth P-type field effect transistor, the first end of the eighth P-type field effect transistor is connected to the base of the first compensation transistor, the second end of the eighth P-type field effect transistor is connected to the first end of the tenth P-type field effect transistor, the second end of the tenth P-type field effect transistor is connected to the device voltage end of the reference voltage source integrated device, the second end of the ninth P-type field effect transistor is connected to the device voltage end of the reference voltage source integrated device, the first end of the ninth P-type field effect transistor is connected to the second end of the seventh P-type field effect transistor, and the first end of the seventh P-type field effect transistor is connected to the base of the reference voltage generation module; The control end of the seventh P-type field effect transistor is connected to the control end of the eighth P-type field effect transistor, and the control end of the ninth P-type field effect transistor is connected to the control end of the tenth P-type field effect transistor; The first end of the eighth P-type field effect transistor is connected to the control end of the tenth P-type field effect transistor.

7. The reference voltage source integrated device with base current compensation according to claim 5, characterized in that: The ratio of the channel width-to-length ratio of the third N-type field effect transistor to the channel width-to-length ratio of the fourth N-type field effect transistor is 1:

2.

8. The reference voltage source integrated device with base current compensation according to claim 6, characterized in that: The channel area width-to-length ratio of the seventh P-type field effect transistor is the same as that of the eighth P-type field effect transistor, and the channel area width-to-length ratio of the ninth P-type field effect transistor is the same as that of the tenth P-type field effect transistor.

9. The reference voltage source integrated device with base current compensation according to claim 1, characterized in that: The reference voltage generation module includes a first P-type field effect transistor, a second P-type field effect transistor, a fourth P-type field effect transistor, a fifth P-type field effect transistor, a bias resistor, a first N-type field effect transistor, a second N-type field effect transistor, a first transistor, a second transistor, a first resistor and a second resistor; The second end of the fourth P-type field effect transistor is connected to the device voltage end of the reference voltage source integrated device, the first end of the fourth P-type field effect transistor is connected to the second end of the first P-type field effect transistor, the first end of the first P-type field effect transistor is connected to the second end of the bias resistor, the first end of the bias resistor is connected to the second end of the first N-type field effect transistor, the first end of the first N-type field effect transistor is connected to the collector of the first triode, the emitter of the first triode is connected to the second end of the first resistor, the first end of the first resistor is connected to the second end of the second resistor, and the first end of the second resistor is grounded; The second end of the fifth P-type field effect transistor is connected to the device voltage end of the reference voltage source integrated device, the first end of the fifth P-type field effect transistor is connected to the second end of the second P-type field effect transistor, the first end of the second P-type field effect transistor is connected to the second end of the second N-type field effect transistor, the first end of the second N-type field effect transistor is connected to the collector of the second transistor, and the emitter of the second transistor is connected to the second end of the second resistor; The control end of the fourth P-type field effect transistor is connected to the control end of the fifth P-type field effect transistor; The control end of the fourth P-type field effect transistor is connected to the first end of the first P-type field effect transistor; The control end of the first P-type field effect transistor is connected to the control end of the second P-type field effect transistor; The control end of the first P-type field effect transistor is connected to the second end of the first N-type field effect transistor; The second end of the second N-type field effect transistor is connected to the control end of the second N-type field effect transistor; The control end of the second N-type field effect transistor is connected to the control end of the first N-type field effect transistor; The base of the first transistor is connected to the base of the second transistor.

10. The reference voltage source integrated device with base current compensation according to claim 9, characterized in that: The fourth P-type field effect transistor, the fifth P-type field effect transistor and the sixth P-type field effect transistor have the same channel width-to-length ratio.

11. The reference voltage source integrated device with base current compensation according to claim 9, characterized in that: The first P-type field effect transistor, the second P-type field effect transistor and the third P-type field effect transistor have the same channel width-to-length ratio.

12. The reference voltage source integrated device with base current compensation according to claim 9, characterized in that: The channel width-to-length ratio of the first N-type field effect transistor is the same as the channel width-to-length ratio of the second N-type field effect transistor.

13. The reference voltage source integrated device with base current compensation according to claim 9, characterized in that: The emitter area ratio of the first transistor and the second transistor is N:1, where N is a natural number.

14. The reference voltage source integrated device with base current compensation according to claim 1, characterized in that: The first current mirror module includes a third N-type field effect transistor, a fourth N-type field effect transistor, a fifth N-type field effect transistor, a sixth N-type field effect transistor and a fifth resistor; The first end of the third N-type field effect transistor is grounded, the first end of the fourth N-type field effect transistor is grounded, and the control end of the third N-type field effect transistor is connected to the control end of the fourth N-type field effect transistor; The second end of the third N-type field effect transistor is connected to the first end of the fifth N-type field effect transistor, the second end of the fourth N-type field effect transistor is connected to the first end of the sixth N-type field effect transistor; the control end of the fifth N-type field effect transistor is connected to the control end of the sixth N-type field effect transistor; The control end of the third N-type field effect transistor is connected to the second end of the fifth N-type field effect transistor; The first end of the fifth resistor is connected to the second end of the fifth N-type field effect transistor; The second end of the fifth resistor is connected to the control end of the fifth N-type field effect transistor; The second end of the fifth resistor is connected to the first end of the third P-type field effect transistor to input a bias current, and the second end of the sixth N-type field effect transistor is connected to the emitter of the first compensation transistor.

15. The reference voltage source integrated device with base current compensation according to claim 1, characterized in that: The second current mirror module includes a seventh P-type field effect transistor, an eighth P-type field effect transistor, a ninth P-type field effect transistor and a tenth P-type field effect transistor; The second current mirror module further includes a third buffer and an operational amplifier, wherein the second end of the third buffer is connected to the first end of the eighth P-type field effect transistor, the first end of the third buffer is connected to the base of the first compensation transistor, the output end of the operational amplifier is connected to the control end of the third buffer, the non-inverting input end of the operational amplifier is connected to the first end of the seventh P-type field effect transistor, and the inverting input end of the operational amplifier is connected to the first end of the third buffer; The first end of the eighth P-type field effect transistor is connected to the second end of the third buffer, the second end of the eighth P-type field effect transistor is connected to the first end of the tenth P-type field effect transistor, the second end of the tenth P-type field effect transistor is connected to the device voltage end of the reference voltage source integrated device, the second end of the ninth P-type field effect transistor is connected to the device voltage end of the reference voltage source integrated device, the first end of the ninth P-type field effect transistor is connected to the second end of the seventh P-type field effect transistor, and the first end of the seventh P-type field effect transistor is connected to the base of the reference voltage generation module; The control end of the seventh P-type field effect transistor is connected to the control end of the eighth P-type field effect transistor, and the control end of the ninth P-type field effect transistor is connected to the control end of the tenth P-type field effect transistor; The first end of the eighth P-type field effect transistor is connected to the control end of the tenth P-type field effect transistor.

16. The reference voltage source integrated device with base current compensation according to claim 14, characterized in that: The ratio of the channel width-to-length ratio of the third N-type field effect transistor to the channel width-to-length ratio of the fourth N-type field effect transistor is 1:

2.

17. The reference voltage source integrated device with base current compensation according to claim 15, characterized in that: The channel area width-to-length ratio of the seventh P-type field effect transistor is the same as that of the eighth P-type field effect transistor, and the channel area width-to-length ratio of the ninth P-type field effect transistor is the same as that of the tenth P-type field effect transistor.

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