Electronic device and method for manufacturing the same

Abstract

The electronic device disclosed in the present invention includes: a semiconductor memory, which includes: a column line; a row line that intersects the column line; a memory cell located at the intersection between the column line and the row line; a dummy insulating pattern that is located adjacent to the memory cell; a pad layer formed on the side wall of the memory cell; and a dummy pad layer formed on the side wall of the dummy insulating pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2019-0130959, filed on October 21, 2019, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate generally to an electronic device, and more particularly, to an electronic device including a semiconductor memory and a method of manufacturing the electronic device. Background Art

[0004] Recently, with the requirements of miniaturization, low power consumption, high performance and diversification of electronic devices, semiconductor devices for storing information need to be configured in various types of electronic devices such as computers and portable communication devices. Therefore, semiconductor devices configured to store data using the characteristic of switching between different resistance states according to applied voltage or current have been studied. Examples of such semiconductor devices may include resistive random access memory (RRAM), phase change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), E-fuse, and the like. Summary of the invention

[0005] Various embodiments are directed to an electronic device and a method of manufacturing the same capable of improving operating characteristics and reliability.

[0006] According to an embodiment, an electronic device may include a semiconductor memory, which includes: a column line; a row line that intersects the column line; a memory cell located at the intersection between the column line and the row line; a dummy insulating pattern located adjacent to the memory cell; a liner layer formed on the side wall of the memory cell; and a dummy liner layer formed on the side wall of the dummy insulating pattern.

[0007] A method for manufacturing an electronic device including a semiconductor memory, the method may include: forming a cell stack in a cell region of a substrate; forming a first insulating layer in a peripheral region of the substrate; forming a cell pattern by patterning the cell stack; forming a first dummy insulating pattern by patterning the first insulating layer; forming a liner layer on a sidewall of the cell pattern; and forming a dummy liner layer on the sidewall of the first dummy insulating pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a diagram showing a structure of an electronic device according to an embodiment of the present invention.

[0009] Figure 2A and Figure 2B is a diagram showing a structure of an electronic device according to an embodiment of the present disclosure.

[0010] Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B and Fig.13 is a diagram illustrating a method of manufacturing an electronic device according to an embodiment of the present disclosure.

[0011] Fig.14 is a diagram showing a configuration of a microprocessor implementing a memory device according to an embodiment of the present disclosure.

[0012] Fig.15 is a diagram showing a configuration of a processor implementing a memory device according to an embodiment of the present disclosure.

[0013] Fig.16 is a diagram showing a configuration of a system implementing a memory device according to an embodiment of the present disclosure.

[0014] Fig.17 is a diagram showing a configuration of a data storage system implementing a memory device according to an embodiment of the present disclosure.

[0015] Fig.18 is a diagram showing a configuration of a memory system implementing a memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] In order to describe an example of an embodiment of the concept disclosed in this specification, only the specific structure or functional description of the example of the embodiment of the concept is shown, and the example of the embodiment of the concept can be implemented in various forms, and the description is not limited to the example of the embodiment described in this specification.

[0017] Figure 1 The structure of an electronic device according to an embodiment of the present disclosure is shown.

[0018] refer to Figure 1The electronic device may include a semiconductor memory. The semiconductor memory may be a nonvolatile memory device or a variable resistance memory device.

[0019] The semiconductor memory may include row lines RL and column lines CL intersecting the row lines RL. The row lines RL may extend in parallel in a second direction II. The column lines CL may extend in a first direction I intersecting the second direction II. The row lines RL may be word lines, and the column lines CL may be bit lines. However, in other embodiments, the word lines and the bit lines may be used for different purposes. For example, the row lines RL may be bit lines, and the column lines CL may be word lines.

[0020] The cell array 100 may include memory cells MC arranged between column lines CL and row lines RL. The memory cells MC may be arranged at the intersections between the column lines CL and the row lines RL. Each memory cell MC may include a selection element or a storage element. The storage element may be a storage node for storing data and may include a variable resistance material. The selection element may be used to select the memory cell MC and may include a switching material. Various modifications may be made to the shape and configuration of each memory cell MC. For example, in some embodiments, the selection element or the storage element may be omitted.

[0021] The electronic device may further include a dummy insulating pattern. The dummy insulating pattern may be located at an outer edge of the cell array 100, or at a peripheral region where a peripheral circuit is located. The dummy insulating pattern may include at least one first dummy insulating pattern DP1, at least one second dummy insulating pattern DP2, or both the first dummy insulating pattern DP1 and the second dummy insulating pattern DP2.

[0022] The first dummy insulation pattern DP1 may be disposed adjacent to the memory cell MC, the row line RL, and the column line CL in the first direction I. In a plan view, the first dummy insulation pattern DP1 may have a linear shape or an island shape. When the first dummy insulation pattern DP1 has a linear shape, the first dummy insulation pattern DP1 may extend in parallel with the row line RL and may extend in the second direction II. When the first dummy insulation pattern DP1 has an island-shaped plane, the first dummy insulation pattern DP1 may be arranged adjacent to each other in the first direction I and / or the second direction II.

[0023] Each first dummy insulation pattern DP1 may have a length in the second direction II and a width in the first direction I. The first dummy insulation pattern DP1 may have a greater width than the row line RL. When the row line RL has different widths, the width of the first dummy insulation pattern DP1 may be greater than the maximum width of the row line RL. The first dummy insulation patterns DP1 may have substantially the same depth or different depths. In addition, the first dummy insulation patterns DP1 may have substantially the same width or different widths. Substantially the same may mean that the deviation from the nominal is typical in a manufacturing environment.

[0024] The second dummy insulation pattern DP2 may be disposed adjacent to the memory cell MC, the row line RL, and the column line CL in the second direction II. In a plan view, the second dummy insulation pattern DP2 may have a linear shape or an island shape. When the second dummy insulation pattern DP2 has a linear plane, the second dummy insulation pattern DP2 may extend in parallel with the column line CL and may extend in the first direction I. When the second dummy insulation pattern DP2 has an island shape, the second dummy insulation pattern DP2 may be arranged adjacent to each other in the first direction I and / or the second direction II.

[0025] Each second dummy insulation pattern DP2 may have a length in the first direction I and a width in the second direction II. The second dummy insulation pattern DP2 may have a greater width than the column line CL. When the column lines CL have different widths, the width of the second dummy insulation pattern DP2 may be greater than the maximum width of the column lines CL. The second dummy insulation patterns DP2 may have substantially the same depth or different depths. In addition, the second dummy insulation patterns DP2 may have substantially the same width or different widths.

[0026] Figure 2A and Figure 2B is a diagram showing a structure of an electronic device according to an embodiment of the present disclosure. Figure 2A yes Figure 1 A cross-sectional view of the unit array 100 in the first direction I. Figure 2B yes Figure 1 A cross-sectional view of the unit array 100 in the second direction II.

[0027] refer to Figure 2A and Figure 2B According to an embodiment of the present disclosure, the electronic device may include a row line RL, a memory cell MC, a column line CL, a first dummy insulating pattern DP1 and a second dummy insulating pattern DP2, a first pad layer 16, a second pad layer 18, a first dummy pad layer 17 and a second dummy pad layer 19. The electronic device may further include a substrate 10 and insulating layers 20 and 21. The substrate 10 may be a semiconductor substrate.

[0028] The substrate 10 may include a cell region CR and a peripheral region PR. The cell array may be located in the cell region CR. A peripheral circuit for driving the cell array may be located in the peripheral region PR. Row lines RL, memory cells MC, column lines CL, a first pad layer 16, and a second pad layer 18 may be located in the cell region CR. In addition, a first dummy insulating pattern DP1, a second dummy insulating pattern DP2, a first dummy pad layer 17, and a second dummy pad layer 19 may be located in the peripheral region PR.

[0029] Each memory cell MC may include a first electrode 11, a switch layer 12, a second electrode 13, a variable resistance layer 14, and a third electrode 15. In some embodiments, the positions of the switch layer 12 and the variable resistance layer 14 may be reversed. For example, the positions of the switch layer 12 and the variable resistance layer 14 may be opposite to each other. Figure 2A and Figure 2B The configuration shown is reversed.

[0030] The variable resistance layer 14 can reversibly change between different resistance states according to the applied voltage or current. Therefore, when the variable resistance layer 14 has a low resistance state, data "1" can be stored. On the other hand, when the variable resistance layer 14 has a high resistance state, data "0" can be stored.

[0031] When the variable resistance layer 14 includes a resistance material, the variable resistance layer 14 may include a transition metal oxide, or a metal oxide such as a perovskite-based material. Therefore, when an electron path is generated or removed in the variable resistance layer 14, data may be stored.

[0032] When the variable resistance layer 14 has a magnetic tunnel junction (MTJ) structure, the variable resistance layer 14 may include a magnetization fixed layer, a magnetization free layer, and a tunnel barrier layer therebetween. For example, the magnetization fixed layer and the magnetization free layer may include a magnetic material, and the tunnel barrier layer may include an oxide such as magnesium (Mg), aluminum (Al), zinc (Zn), or titanium (Ti). The magnetization direction of the magnetization free layer may be changed by the spin torque of electrons in the applied current. Therefore, data may be stored according to the change in the magnetization direction of the magnetization free layer relative to the magnetization direction of the magnetization fixed layer.

[0033] When the variable resistance layer 14 includes a phase change material, the variable resistance layer 14 may include a chalcogenide-based material. The variable resistance layer 14 may include silicon (Si), germanium (Ge), antimony (b), tellurium (Te), bismuth (Bi), indium (In), tin (Sn), selenium (Se) or a combination thereof as a chalcogenide-based material. For example, the variable resistance layer 14 may be a Ge-Sb-Te (GST) material, such as Ge2Sb2Te5, Ge2Sb2Te7, Ge1Sb2Te4 or Ge1Sb4Te7. The chemical composition ratio of the variable resistance layer 14 may be determined according to the characteristics of the melting point and the crystallization temperature. The variable resistance layer 14 may also include carbon (C) or nitrogen (N) impurities. The phase change material may have a low resistance characteristic when in a crystalline state and a high resistance characteristic when in an amorphous state. Therefore, data may be stored according to a setting operation of switching a high resistance amorphous state to a low resistance crystalline state and a reset operation of switching a low resistance crystalline state to a high resistance amorphous state.

[0034] The switch layer 12 may be a selective element that controls the flow of current according to the amount of applied voltage or current. When the magnitude of the applied voltage or current is less than a threshold, a small amount of current may flow through the switch layer 12, and when the applied voltage or current exceeds the threshold, a large amount of current may flow.

[0035] When the switch layer 12 is a metal insulator transition (MIT) device, the switch layer 12 may include VO2, NbO2, TiO2, WO2, TiO2, etc. When the switch layer 12 is a mixed ion-electron conduction (MIEC) device, the switch layer 12 may include ZrO2 (Y2O3), Bi2O3-BaO, (La2O3) x (CeO2) 1-x Etc. In addition, when the switch layer 12 is an omni-directional threshold switch (OTS) device, the switch layer 12 may include Te, Se, Ge, Si, As, Ti, S, Sb, etc. For example, the switch layer 12 may include a chalcogenide-based material such as AsTe, AsSe, AsTeSe, AsTeGe, AsSeGe, and AsTeGeSe.

[0036] The first electrode 11 may be electrically coupled to the row line RL, the second electrode 13 may be interposed between the switch layer 12 and the variable resistance layer 14, and the third electrode 15 may be electrically coupled to the column line CL. The first electrode 11, the second electrode 13, and the third electrode 15 may include a conductive material such as a metal or a metal nitride. For example, each of the first electrode 11, the second electrode 13, and the third electrode 15 may include tungsten (W), tungsten nitride (WN), tungsten silicide (WSi), titanium (Ti), titanium nitride (TiNx), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbonitride (SiCN), copper (Cu), zinc (Zn), cobalt (Co), lead (Pd), platinum (Pt), or a combination thereof.

[0037] The first liner layer 16 and the second liner layer 18 may be provided as a stacked layer to protect the memory cell MC during the manufacturing process. The first liner layer 16 may be formed to cover the side walls of the memory cell MC facing each other in the first direction I. The first liner layer 16 may extend in the second direction II. The second liner layer 18 may be formed to surround the side walls of the memory cell MC facing each other in the second direction II, and may extend in the first direction I. The first liner layer 16 and the second liner layer 18 may be formed on all or part of the side walls of the memory cell MC. The first liner layer 16 may extend to the side walls of the row line RL, and the second liner layer 18 may extend to the side walls of the column line CL.

[0038] The first liner layer 16 and the second liner layer 18 may include a non-conductive material, and may include nitride, oxide, etc. For example, the first liner layer 16 and the second liner layer 18 may include silicon oxide (SiO x ), silicon nitride (Si3N4), polysilicon, titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof. In addition, each of the first liner layer 16 and the second liner layer 18 can be a single material layer or a multi-layer film.

[0039] The first dummy insulating pattern DP1 may be arranged adjacent to the memory cell MC, the row line RL, and the column line CL in the first direction I. The upper surface of the first dummy insulating pattern DP1 may be located at substantially the same level L1 as the upper surface of the memory cell MC. For example, the upper surface of the third electrode 15 and the upper surface of the first dummy insulating pattern DP1 may be located at substantially the same level L1. Alternatively, the upper surface of the first dummy insulating pattern DP1 may be located at a lower level than the upper surface of the third electrode 15.

[0040] The second dummy insulating pattern DP2 may be disposed adjacent to the memory cell MC, the row line RL, and the column line CL in the second direction II. The upper surface of the second dummy insulating pattern DP2 may be located at a level L2 substantially the same as the upper surface of the column line CL. In addition, the second dummy insulating pattern DP2 may have a different depth from the first dummy insulating pattern DP1. Therefore, the upper surface of the second dummy insulating pattern DP2 may be located at a higher level (L2>L1) than the upper surface of the first dummy insulating pattern DP1.

[0041] Each of the first dummy insulation pattern DP1 and the second dummy insulation pattern DP2 may have a single material layer. In addition, each of the first dummy insulation pattern DP1 and the second dummy insulation pattern DP2 may include a single material. For example, each of the first dummy insulation pattern DP1 and the second dummy insulation pattern DP2 may be an oxide material layer or a nitride material layer.

[0042] A first dummy liner layer 17 may be formed on the sidewalls of the first dummy insulation pattern DP1. In addition, the first dummy liner layer 17 may cover two sidewalls of the first dummy insulation pattern DP1 facing each other in the first direction I. The first dummy liner layer 17 may extend in the second direction II. The second dummy liner layer 19 may cover two sidewalls of the second dummy insulation pattern DP2 facing each other in the second direction II. The second dummy liner layer 19 may extend in the first direction I. The first dummy liner layer 17 may be formed on all or part of the sidewalls of the first dummy insulation pattern DP1. The second dummy liner layer 19 may be formed on all or part of the sidewalls of the second dummy insulation pattern DP2.

[0043] The first dummy liner layer 17 and the second dummy liner layer 19 may include a non-conductive material, and may include nitride, oxide, etc. For example, the first dummy liner layer 17 and the second dummy liner layer 19 may include silicon oxide (SiOx), silicon nitride (Si3N4), polysilicon, titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof. In addition, each of the first dummy liner layer 17 and the second dummy liner layer 19 may be a single material layer or a multilayer film.

[0044] The first dummy liner layer 17 may be formed when the first liner layer 16 is formed. Therefore, the structure and material of the first dummy liner layer 17 may correspond to the structure and material of the first liner layer 16. The second dummy liner layer 19 may be formed when the second liner layer 18 is formed. Therefore, the structure and material of the second dummy liner layer 19 may correspond to the structure and material of the second liner layer 18.

[0045] The first insulating layer 20 and the second insulating layer 21 may be formed to fill the space between adjacent memory cells MC. The first insulating layer 20 may fill the space between adjacent memory cells MC in the first direction I and the space between adjacent row lines RL in the first direction I. The second insulating layer 21 may fill the space between adjacent memory cells MC in the second direction II and the space between adjacent column lines CL in the second direction II. The first insulating layer 20 and the second insulating layer 21 may include a flowable oxide layer such as a spin on coating (SOC) layer or a spin on dielectric (SOD) layer, an oxide such as silicon oxide (SiO2), or a combination thereof.

[0046] FIG. 3A to FIG. 12A and FIG. 3B to FIG. 12B is a diagram illustrating a method of manufacturing an electronic device according to an embodiment of the present disclosure. FIG. 3A to FIG. 12A is a plan view, and FIG. 3B to FIG. 12B It is a cross-sectional view.

[0047] refer to Figure 3A and Figure 3B , a first conductive material 31 may be formed on a substrate 30. The substrate 30 may include a semiconductor substrate. The substrate 30 may include a cell region CR and a peripheral region PR. The first conductive material 31 may be provided to form a row line and include a metal, such as tungsten.

[0048] The stacked structure ST may be formed on the first conductive material 31. The stacked structure ST may be formed on the cell region CR of the substrate 30, or may be formed on both the cell region CR and the peripheral region PR of the substrate 30. The stacked structure ST may include a plurality of layers stacked in the third direction III. The stacked structure ST may include at least one of a first electrode material 32, a switching material 33, a second electrode material 34, a variable resistance material 35, and a third electrode material 36. The third direction III may intersect the first direction I and the second direction II. For example, the third direction III may be orthogonal to the plane defined by the first direction I and the second direction II, and may be a depth direction of the device.

[0049] refer to Figure 4A and Figure 4B , a cell stack CS may be formed. The cell stack CS may be formed by etching a portion of the stack structure ST corresponding to the peripheral region PR. Subsequently, a portion of the first conductive material 31 corresponding to the peripheral region PR may be etched to expose the substrate 30 .

[0050] An insulating layer 37 may be formed on the peripheral region PR of the substrate 30. In one embodiment, after forming an insulating material on the cell stack CS and the substrate 30, the insulating material may be etched until an upper surface of the cell stack CS is exposed, thereby forming the insulating layer 37. The insulating layer 37 may include an oxide layer.

[0051] refer to Figure 5A , Figure 5B , Fig. 6A and Figure 6B , a first mask pattern 38A and a second mask pattern 38B may be formed on the cell stack CS and the insulating layer 37. The first mask pattern 38A may be formed on the cell stack CS, and the second mask pattern 38B may be formed on the insulating layer 37. In one embodiment, the second mask pattern 38B may be formed after forming the first mask pattern 38A. However, in another embodiment, the first mask pattern 38A may be formed after forming the second mask pattern 38B. The following disclosure describes an embodiment of a method of forming the second mask pattern 38B after forming the first mask pattern 38A.

[0052] refer to Figure 5A and Figure 5B , a first mask pattern 38A may be formed using a spacer patterning technology (SPT). First, a hard mask layer 38 may be formed on the cell stack CS, and a sacrificial pattern (not shown) may be formed on the hard mask layer 38. A spacer having a ring shape may then be formed on the sidewall of the sacrificial pattern. Next, the sacrificial pattern may be removed. Subsequently, the hard mask layer 38 may be etched using the spacer as an etch barrier to form a first mask pattern 38A. As a result, a first mask pattern 38A having a pitch narrower than the resolution of an exposure device may be formed.

[0053] The first mask pattern 38A may include a pattern having a ring shape. Figure 5A As shown, the annular shape may be an elongated and closed annular shape having a major axis oriented in the second direction II. The pattern may have a constant or varying width. Some patterns may have a greater width than other patterns, or a portion of a pattern may have a greater width than the rest of the pattern. For example, a portion 38A1 of the first mask pattern 38A located at the edge of the cell region CR may have a greater width than a portion 38A2 located at the center of the cell region CR.

[0054] refer to Fig. 6A and Figure 6B, a portion of the hard mask layer 38 in the peripheral region PR may be patterned to form a second mask pattern 38B. First, after a photoresist pattern is formed on the hard mask layer 38, the hard mask layer 38 may be etched using the photoresist pattern as an etch barrier to form a second mask pattern 38B. The second mask pattern 38B may be formed by a general patterning process instead of using SPT. In addition, when forming the second mask pattern 38B, a cell closed mask may be used so as not to expose the cell region CR in which the first mask pattern 38A is pre-formed. The second mask pattern 38B may have a greater width (W2>W1) than the first mask pattern 38A.

[0055] The second mask pattern 38B may have linear patterns. Each pattern may extend in the second direction II and may have a length in the second direction II and a width in the first direction I. The patterns may have the same or different lengths from each other.

[0056] refer to Fig. 7A and Figure 7B , a cell pattern CP, a row line 31A, and a first dummy insulating pattern 37A may be formed. The cell stack CS may be etched using the first mask pattern 38A as an etch barrier to form the cell pattern CP. Subsequently, the row line 31A may be formed by etching the first conductive material 31.

[0057] In addition, by etching the insulating layer 37 using the second mask pattern 38B as an etch barrier, a first dummy insulating pattern 37A may be formed. The first dummy insulating pattern 37A may be formed when forming the cell pattern CP and the row line 31A. The upper surface of the cell pattern CP and the upper surface of the first dummy insulating pattern 37A may be located at substantially the same level.

[0058] The shape of the cell pattern CP may correspond to the shape of the first mask pattern 38A. Each cell pattern CP may have a ring shape. The cell pattern CP located at the edge of the cell region CR may have a greater width than the cell pattern CP located at the center of the cell region CR. The shape of the row line 31A may correspond to the shape of the cell pattern CP. Each row line 31A may have a ring shape, and the row line located at the edge of the cell region CR may have a greater width than the row line located at the center of the cell region CR.

[0059] The shape of the first dummy insulating pattern 37A may correspond to the shape of the second mask pattern 38B. The first dummy insulating pattern 37A may extend parallel to the row lines 31A and extend in the second direction II.

[0060] refer to Fig. 8A and Figure 8B, taking into account the formation process of the insulating material 43, the length, width, distance, shape, number and pattern density of the first dummy insulating pattern 37A can be determined. For example, when the insulating material 43 is coated using a spin coating process, the shape of the insulating material coating can vary according to the centrifugal force generated during coating and the surface tension of the insulating material. In addition, the pattern density of the first dummy insulating pattern 37A can affect the interaction mode between the insulating material 43 and the pattern based on the surface tension of the insulating material 43. When the spacing between the first dummy insulating patterns 37A is greater than or equal to the threshold value, the effect of the surface tension can be reduced, and the effect of the centrifugal force can become greater than the effect of the surface tension. As a result, the insulating material may not be coated uniformly. Therefore, the pattern density of the first dummy insulating pattern 37A can be controlled to provide a balance between the centrifugal force and the surface tension, thereby obtaining a uniform coating.

[0061] refer to Fig. 8A and Figure 8B , a first pad layer 41 and a first dummy pad layer 42 may be formed. The first pad layer 41 may be formed on the sidewalls of the cell pattern CP. The first pad layer 41 may be formed on all or part of the sidewalls of the cell pattern CP. The first pad layer 41 may extend to the sidewalls of the row line 31A. The first dummy pad layer 42 may be formed on the sidewalls of the first dummy insulating pattern 37A. The first dummy pad layer 42 may be formed on all or part of the sidewalls of the first dummy insulating pattern 37A.

[0062] The first dummy liner layer 42 may be formed when the first liner layer 41 is formed. Therefore, the structure and material of the first dummy liner layer 42 may be substantially the same as the structure and material of the first liner layer 41. The first liner layer 41 and the first dummy liner layer 42 may be formed using a deposition process and may be formed on the cell pattern CP and the first dummy insulating pattern 37A so that the coating conforms to the contours of the cell pattern CP and the first dummy insulating pattern 37A. The first liner layer 41 and the first dummy liner layer 42 may include a non-conductive material and may include nitride, oxide, etc. In one embodiment, a portion of the first liner layer 41 disposed above the top surface of the cell pattern CP may be removed using a grinding or etching process.

[0063] Subsequently, an insulating material 43 may be formed. The insulating material 43 may be formed to fill the space between the cell patterns CP, the space between the row lines 31A, and the space between the first dummy insulating patterns 37A. The insulating material 43 may include a low-k material. The insulating material 43 may be formed using a deposition process, or may be coated using a spin coating process.

[0064] When the first dummy insulating pattern 37A is not present, the peripheral region PR may not be able to receive a sufficiently thick coating of the insulating material 43. When the first dummy insulating pattern 37A is not present in the peripheral region PR, the height of the insulating material 43 in the peripheral region PR may be substantially lower than the height of the insulating material 43 in the cell pattern CP (eg, Figure 8B ). On the other hand, when a first dummy insulating pattern 37A having a height substantially the same as or close to that of the cell pattern CP is formed in the peripheral region PR, the level difference between the cell region CR and the peripheral region PR can be reduced. The space between the first dummy insulating patterns 37A can be filled with an insulating material 43. In addition, the volume occupied by the dummy insulating pattern 37A can replace the insulating material so that the insulating material 43 has a uniform thickness between the cell region CR and the peripheral region PR. Therefore, embodiments of the present disclosure can provide an insulating material 43 with minimal height variation between the cell region CR and the peripheral region PR.

[0065] refer to Fig.9A and Fig. 9B , an insulating layer 43A may be formed. The insulating material 43 may be planarized to form the insulating layer 43A. The planarization process may be performed using a chemical mechanical polishing (CMP) method or an etch-back method. The insulating material 43 may be etched until the upper surface of the cell pattern and the upper surface of the first dummy insulating pattern 37A are exposed, thereby forming the insulating layer 43A.

[0066] When the first dummy insulating pattern 37A is not formed, the peripheral region PR may not be coated with a sufficient amount of the insulating material 43. As a result, during the process of planarizing the insulating material 43, the cell pattern CP adjacent to the peripheral region PR may be exposed. In addition, the exposed cell pattern CP may be damaged. On the other hand, when the first dummy insulating pattern 37A is provided, the peripheral region PR may be coated with a sufficient amount of the insulating material 43. As a result, when the insulating layer 43A is formed, the cell pattern CP may not be exposed. Therefore, damage to the cell pattern CP can be prevented.

[0067] exist FIG. 3A to FIG. 9B A perspective view is shown, which includes a plane view with an X-axis in the I direction and a Y-axis in the II direction and a cross-sectional view in the plane in the I direction and the III direction, FIG. 10A to FIG. 12B A plan view with the X axis in the II direction and the Y axis in the I direction and a cross-sectional view in the planes in the II direction and the III direction are shown. FIG. 3A to FIG. 9B and Figure 1 and shows the perspective view of Figure 1 While the area occupied by the dummy pattern DP1 in FIG. 10A to FIG. 12B is converted to show the area occupied by the dummy pattern DP2.

[0068] refer to Fig. 10A and Fig. 10B , a second conductive material 39 may be formed on the cell stack CS. After forming the second conductive material 39 in the cell region CR and the peripheral region PR, a portion of the second conductive material 39 formed in the peripheral region PR may be etched. The second conductive material 39 may form a column line and may include a metal such as tungsten.

[0069] Subsequently, an insulating layer 47 may be formed in the peripheral region PR. The insulating layer 47 may include an oxide layer. The insulating layer 47 may be a single-layer or multi-layer film. The lower portion of the insulating layer 47 may be formed when the insulating material 43 is formed, so the step of forming the insulating layer 47 may include depositing the insulating material on the insulating material 43. The upper surface of the insulating layer 47 may be located at a level substantially the same as or close to the upper surface of the second conductive material 39.

[0070] Subsequently, a third mask pattern 48A and a fourth mask pattern 48B may be formed. The third mask pattern 48A may be formed on the cell stack CS, and the fourth mask pattern 48B may be formed on the insulating layer 47. The fourth mask pattern 48B may be formed after the third mask pattern 48A is formed. However, in another embodiment, the third mask pattern 48A may be formed after the fourth mask pattern 48B is formed.

[0071] The third mask pattern 48A may intersect the unit pattern CP and have a ring shape having a major axis extending in the first direction I. A portion 48A1 of the third mask pattern 48A may have a greater width than a remaining portion 48A2 of the pattern. The third mask pattern 48A may be formed in a manner similar to the first mask pattern 38A described above.

[0072] The fourth mask pattern 48B may extend in parallel with the third mask pattern 48A and may have a greater width than the third mask pattern 48A. The length of a portion 48B2 of the fourth mask pattern 48B located at the edge of the peripheral region PR may be greater than the length of a portion 48B1 located inside the edge of the peripheral region PR. The fourth mask pattern 48B may be formed in a manner similar to the second mask pattern 38B described above.

[0073] refer to Fig.11A and Fig. 11B, a column line 39A, a memory cell MC, and a second dummy insulating pattern 47A may be formed. By etching the second conductive material 39 using the third mask pattern 48A as an etching barrier, a column line 39A may be formed. Each column line 39A may have a ring shape. Subsequently, a memory cell MC may be formed by etching the cell pattern CP. The memory cell MC may be located at an intersection between the column line 39A and the row line 31A. Each memory cell MC may include at least one of a first electrode 32A, a switch layer 33A, a second electrode 34A, a variable resistance layer 35A, and a third electrode 36A.

[0074] In addition, refer to Fig.11A and Fig. 11B By etching the insulating layer 47 using the fourth mask pattern 48B as an etch barrier, a second dummy insulating pattern 47A may be formed. The second dummy insulating pattern 47A may be formed when forming the memory cell MC and the column line 39A. The upper surface of the column line 39A and the upper surface of the second dummy insulating pattern 47A may be located at approximately the same level.

[0075] Subsequently, a second liner layer 51 and a second dummy liner layer 52 may be formed. The second liner layer 51 may be formed on the sidewalls of the memory cells MC. The second liner layer 51 may be formed on all or part of the sidewalls of the memory cells MC and the column lines 39A. The second dummy liner layer 52 may be formed on the sidewalls of the second dummy insulating pattern 47A. The second dummy liner layer 52 may be formed on all or part of the sidewalls of the second dummy insulating pattern 47A.

[0076] The second dummy liner layer 52 may be formed when the second liner layer 51 is formed. Therefore, the structure and material of the second dummy liner layer 52 may be substantially the same as those of the second liner layer 51. The second liner layer 51 and the second dummy liner layer 52 may be formed using a deposition process so that the liner layer material conforms to the contours of the memory cells MC and the second dummy insulating patterns 47A. The second liner layer 51 and the second dummy liner layer 52 may include a non-conductive material such as an oxide or nitride material.

[0077] refer to Fig. 12A and Fig. 12B , an insulating layer 53 may be formed. The insulating layer 53 may fill the space between the memory cells MC, the space between the column lines 39A, and the space between the second dummy insulating patterns 47A.

[0078] The insulating layer 53 may be formed in a manner similar to the insulating layer 43A described above. First, an insulating material may be formed to fill the spaces between the memory cells MC, the spaces between the column lines 39A, and the spaces between the second dummy insulating patterns 47A. Subsequently, the insulating material may be planarized to form the insulating layer 53. The second dummy insulating pattern 47A in the peripheral region PR may reduce or eliminate the level difference between the cell region CR and the peripheral region PR, and may provide a sufficient amount of insulating material in the peripheral region PR. Therefore, damage to the column lines 39A and the memory cells MC may be prevented.

[0079] refer to Fig.13 , the ends of the row lines 31A and the column lines 39A may be etched. As a result, the row lines 31B extending in the second direction II and the column lines 39B extending in the first direction I may be formed.

[0080] In addition, at least one of the first dummy insulating pattern 37A, the first dummy liner layer 42, the second dummy insulating pattern 47A, and the second dummy liner layer 52 may be removed. For example, the process of etching the ends of the column lines 39A and the row lines 31A may remove the first dummy insulating pattern 37A. However, in another embodiment, the dummy insulating pattern may be removed using a separate process.

[0081] According to the above-described manufacturing method, the first dummy insulating pattern 37A, the second dummy insulating pattern 47A, or a combination of the first dummy insulating pattern 37A and the second dummy insulating pattern 47A may be formed in the peripheral region PR. The insulating layer 37 and the insulating layer 47 may be formed in the peripheral region PR with a predetermined thickness, and may prevent exposure or damage of the cell pattern CP or exposure or damage of the memory cell MC when the memory cell MC is formed.

[0082] Fig.14 is a diagram showing a configuration of a microprocessor 1000 implementing a memory device according to an embodiment of the present disclosure.

[0083] refer to Fig.14 , the microprocessor 1000 can control and adjust the following series of processes: receiving data from various types of external devices, processing data, and sending the results to the external devices. The microprocessor 1000 may include a memory 1010, an operation unit 1020, and a control unit 1030. The microprocessor 1000 may be various data processing units, such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), and an application processor (AP).

[0084] The memory 1010 may be a processor register or registers and may store data in the microprocessor 1000. The memory 1010 may include various types of registers, including data registers, address registers, and floating point registers. The memory 1010 may be used to temporarily store such addresses, where data of an operation to be performed, data corresponding to a result of the operation, and data for performing the operation are stored.

[0085] The memory 1010 may include at least one of the embodiments of the semiconductor device described above. For example, the memory 1010 may include: a column line; a row line intersecting the column line; a memory cell located at the intersection between the column line and the row line; a dummy insulating pattern located adjacent to the memory cell; a liner layer formed on the sidewall of the memory cell; and a dummy liner layer formed on the sidewall of the dummy insulating pattern. Therefore, the read operation characteristics of the memory 1010 may be improved. As a result, the read operation characteristics of the microprocessor 1000 may be improved.

[0086] The operation unit 1020 may perform various arithmetic operations or logic operations according to a result obtained by decoding the instruction by the control unit 1030. The operation unit 1020 may include at least one arithmetic logic unit (ALU).

[0087] The control unit 1030 may receive signals from the memory 1010 of the microprocessor 1000 , the operation unit 1020 , and external devices, extract or decode commands, control signal input and output of the microprocessor 1000 , and execute processing represented by a program.

[0088] According to the present disclosure, the microprocessor 1000 may further include a cache memory 1040, which may also temporarily store data input from an external device other than the memory 1010 or data to be output to an external device. The cache memory 1040 may exchange data with the memory 1010, the operation unit 1020, and the control unit 1030 through the bus interface 1050.

[0089] Fig.15 is a diagram showing a configuration of a processor 1100 implementing a memory device according to an embodiment of the present disclosure.

[0090] refer to Fig.15, the processor 1100 can improve performance and perform various functions in addition to the function of the microprocessor, the function of which is to control and adjust the following series of processes: receiving and processing data from various external devices and sending the results thereof to the external devices. The processor 1100 may include: a core 1110 used as a microprocessor, a cache memory 1120 for temporarily storing data, and a bus interface 1130 for transmitting data between internal and external devices. The processor 1100 may include various types of systems on chip (SoCs), such as a multi-core processor, a graphics processing unit (GPU), and an application processor (AP).

[0091] According to an embodiment of the present disclosure, the core 1110 may perform arithmetic and logic operations on data input from an external device, and may include a memory 1111 , an operation unit 1112 , and a control unit 1113 .

[0092] The memory 1111 may be a processor register or register, and may store data in the microprocessor 1100. The memory 1111 may include various types of registers, including data registers, address registers, and floating-point registers. The memory 1111 may be used to temporarily store such addresses, i.e., data in which the operation is performed, data corresponding to the result of the operation, and data for performing the operation are stored. The operation unit 1112 may perform operations in the processor 1100. More specifically, the operation unit 1112 may perform various basic arithmetic operations or logic operations according to the result of decoding the instruction. The operation unit 1112 may include at least one arithmetic logic unit (ALU). The control unit 1113 may receive signals from the memory 1111, the operation unit 1112, and an external device of the processor 1100, extract or decode commands, control the signal input and output of the processor 1100, and perform processing represented by the program.

[0093] The cache memory 1120 can temporarily store data in order to compensate for the difference in data processing speed between the core 1110 operating at a high speed and the external device operating at a low speed. The cache memory 1120 may include a primary storage part 1121, a secondary storage part 1122, and a tertiary storage part 1123. Generally, the cache memory 1120 may include a primary storage part 1121 and a secondary storage part 1122. When high capacity is required, the cache memory 1120 may also include a tertiary storage part 1123. If necessary, the cache memory 1120 may include more storage parts. In other words, the number of storage parts included in the cache memory 1120 may vary according to the design. The primary storage part 1121, the secondary storage part 1122, and the tertiary storage part 1123 may have the same or different processing speeds to store and determine data. When the respective storage parts have different processing speeds, among the primary storage part 1121, the secondary storage part 1122, and the tertiary storage part 1123, the primary storage part 1121 may have the highest processing speed. At least one of the primary storage portion 1121, the secondary storage portion 1122, and the tertiary storage portion 1123 may include at least one of the embodiments of the semiconductor device described above. For example, the cache memory 1120 may include: a column line; a row line that intersects the column line; a memory cell located at the intersection between the column line and the row line; a dummy insulating pattern located adjacent to the memory cell; a pad layer formed on the sidewall of the memory cell; and a dummy pad layer formed on the sidewall of the dummy insulating pattern. Therefore, the read operation characteristics of the cache memory 1120 may be improved. As a result, the read operation characteristics of the processor 1100 may be improved.

[0094] like Fig.15 As shown, the primary storage part 1121, the secondary storage part 1122, and the tertiary storage part 1123 may all be included in the cache memory 1120. However, the primary storage part 1121, the secondary storage part 1122, and the tertiary storage part 1123 of the cache memory 1120 may be arranged outside the core 1110 to compensate for the difference in processing speed between the core 1110 and the external device. Alternatively, the primary storage part 1121 of the cache memory 1120 may be located in the core 1110, and the secondary storage part 1122 and the tertiary storage part 1123 may be arranged outside the core 1110 to enhance the function of supplementing the difference in data processing speed. However, the primary storage part 1121 and the secondary storage part 1122 may be located in the core 1110, and the tertiary storage part 1123 may be located outside the core 1110.

[0095] The bus interface 1130 may connect the core 1110 , the cache memory 1120 , and external devices so that data may be efficiently transferred.

[0096] According to an embodiment of the present disclosure, the processor 1100 may include a plurality of cores 1110 that may share a cache memory 1120. The plurality of cores 1110 and the cache memory 1120 may be directly coupled to each other or may be coupled through a bus interface 1130. Each of the plurality of cores 1110 may have the same configuration as the above-mentioned core. When the processor 1100 includes a plurality of cores 1110, the number of primary storage parts 1121 of the cache memory 1120 may correspond to the number of core units 1110. Each primary storage part 1121 of the cache memory 1120 may be included in each core 1110. In addition, the secondary storage part 1121 and the tertiary storage part 1123 may be provided outside the plurality of core units 1110 and shared through the bus interface 1130. The primary storage part 1121 may have a faster processing speed than the secondary storage part 1122 and the tertiary storage part 1123. In another embodiment, the number of the primary storage parts 1121 and the number of the secondary storage parts 1122 may correspond to the number of the cores 1110. Each primary storage part 1121 and each secondary storage part 1122 may be included in each core 1110. The tertiary storage part 1123 may be provided outside the plurality of cores 1110 and shared by the plurality of cores 1110 through the bus interface 1130.

[0097] According to an embodiment of the present disclosure, the processor 1100 may include: an embedded memory 1140 that stores data; a communication module unit 1150 that sends data to an external device or receives data from an external device in a wired or wireless manner; a memory control unit 1160 that drives an external storage device; and a media processing unit 1170 that processes data processed by the processor 1100 or input from an external input device or outputs it to an external interface device. The processor 1100 may also include various modules and devices. The added modules may exchange data with each other and with the core 1110 and the cache memory 1120 through the bus interface 1130.

[0098] The embedded memory 1140 may include a non-volatile memory and a volatile memory. The volatile memory may include a dynamic random access memory (DRAM), a mobile DRAM, a static random access memory (SRAM), and a memory having similar functions. The non-volatile memory may include a read-only memory (ROM), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), and a memory having similar functions.

[0099] The communication module unit 1150 may include a module connected to a wired network, a module connected to a wireless network, or may include both. The wired network module may include a local area network (LAN), a universal serial bus (USB), Ethernet, a power line communication (PLC), etc., and the module sends and receives data through a transmission line. The wireless network module may include an infrared data association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), wireless LAN, Zigbee, ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), broadband CDMA (WCDMA), ultra-wideband (UWB), etc., and the module does not need to send and receive data through a transmission line.

[0100] The memory control unit 1160 may include various controllers for processing and managing data transmitted between the processor 1100 and an external storage device operating according to a communication standard different from that of the processor 1100. For example, the memory control unit 1160 may include such controllers that control an integrated device electronics (IDE), a serial advanced technology attachment (SATA), a small computer system interface (SCSI), a redundant array of independent disks (RAID), a solid state disk (SSD), an external SATA (eSATA), a personal computer memory card international association (PCMCIA), a USB, a secure digital (SD) card, a mini secure digital (mSD) card, a micro SD card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media card (SM), a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, etc.

[0101] The media processing unit 1170 may process data processed by the processor 1100 or data input from an external input device in the form of video or audio or other forms, and may output the processed data to an external interface device. The media processing unit 1170 may include a graphics processing unit (GPU), a digital signal processor (DSP), a high-definition audio (HD audio), a high-definition multimedia interface (HDMI) controller, etc.

[0102] Fig.16 is a diagram showing a configuration of a system 1200 implementing a memory device according to an embodiment of the present disclosure.

[0103] refer to Fig.16, the system 1200 may refer to a device configured to process data. In order to perform a series of operation processes for data, the system 1200 may perform input, processing, output, communication, storage, etc. to perform a series of operations on the data. The system 1200 may include a processor 1210, a main memory device 1220, an auxiliary memory device 1230, and an interface device 1240. According to an embodiment of the present disclosure, the system 1200 may be a computer, a server, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, a digital music player, a portable multimedia player (PMP), a camera, a global positioning system (GPS), a video camera, a recorder, telematics, an audio-visual (AV) system, or a smart TV.

[0104] The processor 1210 may control decoding of input commands and processing of data stored in the system 1200, such as data operations and comparisons. The processor 1210 may include one or more of the following: a microprocessor unit (MPU), a central processing unit (CPU), a single / multi-core processor, a graphics processing unit (GPU), an application processor (AP), and a digital signal processor (DSP).

[0105] The main memory device 1220 may refer to a storage device in which, when executing a program, a program code or data is called from the auxiliary memory device 1230 and stored and executed. The stored data may be retained even in the absence of power. The main memory device 1220 may include at least one of the embodiments of the semiconductor device described above. For example, the main memory device 1220 may include: a column line; a row line intersecting the column line; a memory cell located at the intersection between the column line and the row line; a dummy insulating pattern located adjacent to the memory cell; a liner layer formed on the sidewall of the memory cell; and a dummy liner layer formed on the sidewall of the dummy insulating pattern. Therefore, the read operation characteristics of the main memory device 1220 may be improved. As a result, the read operation characteristics of the system 1200 may be improved.

[0106] In addition, the main memory device 1220 may also include a nonvolatile static random access memory (SRAM) or a nonvolatile dynamic random access memory (DRAM) that maintains all data when the power is blocked. In another example, the main memory device 1220 may not include the semiconductor device according to the above-mentioned embodiment, and may include a volatile static random access memory (SRAM) or a volatile dynamic random access memory (DRAM) that loses all data when the power is blocked.

[0107] The auxiliary memory device 1230 may refer to a memory device designed to store program code or data. Although the auxiliary memory device 1230 is slower than the main memory device 1220, the auxiliary memory device 1230 can store more data than the main memory device 1220. The auxiliary memory device 1230 may include at least one of the embodiments of the semiconductor device described above. For example, the auxiliary memory device 1230 may include: a column line; a row line that intersects the column line; a memory cell located at the intersection between the column line and the row line; a dummy insulating pattern located adjacent to the memory cell; a liner layer formed on the sidewall of the memory cell; and a dummy liner layer formed on the sidewall of the dummy insulating pattern. Therefore, the read operation characteristics of the auxiliary memory device 1230 can be improved. As a result, the read operation characteristics of the system 1200 can be improved.

[0108] In addition, the auxiliary storage device 1230 may also include Fig.17 The data storage system 1300 shown in the figure may include a magnetic tape, a magnetic disk, an optical disk, a magneto-optical disk using both magnetic and optical properties, a solid state disk (SSD), a universal serial bus (USB) memory, a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, etc. However, in contrast to this, the auxiliary storage device 1230 may not include the semiconductor device according to the above-mentioned embodiments, and may further include a semiconductor device such as Fig.17 The data storage system 1300 shown, such as a magnetic tape, a magnetic disk, an optical disc, a magneto-optical disc using both magnetic and optical properties, a solid-state drive (SSD), a universal serial bus (USB) memory, a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (SD) card, a secure digital high-capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, etc.

[0109] The interface device 1240 can be used to perform the exchange of commands and data between the system 1200 of this embodiment and external devices. The interface device 1240 can be a keypad, a keyboard, a mouse, a speaker, a microphone, a display, various human-computer interaction devices (HID), a communication device, etc. The communication device can include any one of a module connected to a wired network and a module connected to a wireless network or both. The wired network module can include a local area network (LAN), a universal serial bus (USB), an Ethernet, a power line communication (PLC) in the same manner as in various devices that send and receive data through a transmission line. The wireless network module can include infrared data association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), wireless LAN, Zigbee, ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), wideband CDMA (WCDMA) and ultra wideband (UWB), etc. in the same way as in various devices that send and receive data without a transmission line.

[0110] Fig.17 is a diagram showing a configuration of a data storage system 1300 implementing a storage device according to an embodiment of the present disclosure.

[0111] refer to Fig.17 , the data storage system 1300 may include: a storage device 1310, which is a component for storing data and has a non-volatile characteristic; a controller 1320 for controlling the storage device 1310; an interface 1330 for connecting with an external device; and a temporary storage device 1340 for temporarily storing data. The data storage system 1300 may be a disk type such as a hard disk drive (HDD), a compact disc read only memory (CDROM), a digital versatile disk (DVD), and a solid state disk (SSD), and may be a card type such as a universal serial bus (USB) memory, a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), and a compact flash (CF) card.

[0112] The storage device 1310 may include a nonvolatile memory that semi-permanently stores data. The nonvolatile memory may include a read-only memory (ROM), a NOR flash memory, a NAND flash memory, a phase-change random access memory (PRAM), a resistive random access memory (RRAM), and a magnetic random access memory (MRAM).

[0113] The controller 1320 may control data exchange between the storage device 1310 and the interface 1330. The controller 1320 may include a processor 1321 for performing the following operations: processing a command input from an external device of the data storage system 1300 through the interface 1330.

[0114] Interface 1330 can be set to exchange commands and data between external devices. In the case where data storage system 1300 is a card type device, interface 1330 can be compatible with the interface used in the following devices, such as universal serial bus (USB) memory, secure digital (SD) card, mini secure digital (mSD) card, micro secure digital (SD) card, secure digital high capacity (SDHC) card, memory stick card, smart media (SM) card, multimedia card (MMC), embedded MMC (eMMC) and compact flash (CF) card, or can be compatible with the interface used in devices similar to the above devices. In the case where data storage system 1300 is a disk type device, interface 1330 can be compatible with interfaces such as IDE (integrated device circuit), SATA (serial advanced technology attachment), SCSI (small computer system interface), eSATA (external SATA), PCMCIA (personal computer memory card international association) and USB (universal serial bus) etc. Interface 1300 can be compatible with interfaces similar to these interfaces. Interface 1330 can be compatible with one or more interfaces with different types.

[0115] The temporary storage device 1340 can temporarily store data according to the diversity and high performance of the interface with the external device, the controller, and the system to effectively transmit data between the interface 1330 and the storage device 1310. The temporary storage device 1340 may include at least one of the embodiments of the above-mentioned semiconductor device. For example, the temporary storage device 1340 may include: a column line; a row line that intersects the column line; a storage cell located at the intersection between the column line and the row line; a dummy insulating pattern located adjacent to the storage cell; a liner layer formed on the side wall of the storage cell; and a dummy liner layer formed on the side wall of the dummy insulating pattern. Therefore, the read operation characteristics of the temporary storage device 1340 can be improved. As a result, the read operation characteristics of the data storage system 1300 can be improved.

[0116] Fig.18 is a diagram showing a configuration of a memory system 1400 implementing a memory device according to an embodiment of the present disclosure.

[0117] refer to Fig.18, the storage system 1400 may include: a memory 1410, which is a component for storing data and has a non-volatile characteristic; a memory controller 1420, which controls the memory 1410; and an interface 1430, which is used to connect with an external device. The storage system 1400 may be a card-type device such as a solid state disk (SSD), a universal serial bus (USB) memory, a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, etc.

[0118] The memory 1410 storing data may include at least one of the embodiments of the semiconductor device described above. For example, the memory 1410 may include: a column line; a row line intersecting the column line; a memory cell located at the intersection between the column line and the row line; a dummy insulating pattern located adjacent to the memory cell; a liner layer formed on the sidewall of the memory cell; and a dummy liner layer formed on the sidewall of the dummy insulating pattern. Therefore, the read operation characteristics of the memory 1410 may be improved. As a result, the read operation characteristics of the memory system 1400 may be improved.

[0119] The memory according to the embodiment may include a read only memory (ROM), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), and a magnetic random access memory (MRAM).

[0120] The memory controller 1420 may control data exchange between the memory 1410 and the interface 1430. The memory controller 1420 may include a processor 1421 to perform operations of processing a command input from an external device of the memory system 1400 through the interface 1430.

[0121] The interface 1430 may be configured to exchange commands and data between the storage system 1400 and an external device. The interface 1430 may be compatible with interfaces used in devices such as a universal serial bus (USB) memory, a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), and a compact flash (CF) card, or may be compatible with interfaces used in devices similar to the above devices. The interface 1430 may be compatible with one or more interfaces having different types.

[0122] According to the embodiment, the memory system 1400 may further include a buffer memory 1440 for efficiently transmitting data input and output between the interface 1430 and the memory 1410 according to the diversity and high performance of the interface with the external device, the memory controller, and the memory system. The buffer memory 1440 for temporarily storing data may include at least one of the embodiments of the semiconductor device described above. For example, the buffer memory 1440 may include: a column line; a row line intersecting the column line; a memory cell located at the intersection between the column line and the row line; a dummy insulating pattern located adjacent to the memory cell; a liner layer formed on the sidewall of the memory cell; and a dummy liner layer formed on the sidewall of the dummy insulating pattern. As a result, the read operation characteristics of the memory system 1400 may be improved.

[0123] In addition, according to the present embodiment, the buffer memory 1440 may further include a static random access memory (SRAM) or a dynamic random access memory (DRAM) having a volatile characteristic, and a read-only memory (ROM), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), or a magnetic random access memory (MRAM) having a non-volatile characteristic. However, in contrast, the buffer memory 1440 may not include the semiconductor device according to the above-mentioned embodiment, and may further include a static random access memory (SRAM) or a dynamic random access memory (DRAM) having a volatile characteristic, and a read-only memory (ROM), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), or a magnetic random access memory (MRAM) having a non-volatile characteristic.

[0124] The operating characteristics and reliability of electronic equipment can be improved.

[0125] Although exemplary embodiments of the present disclosure have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible. Therefore, the present invention is intended to cover all such modifications as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. An electronic device comprising a semiconductor memory, The semiconductor memory comprises: Column line; row lines that intersect the column lines; a memory cell located at an intersection between the column line and the row line; a dummy insulating pattern located adjacent to the storage unit; a liner layer formed on a sidewall of the memory cell; and a dummy liner layer formed on a sidewall of the dummy insulating pattern, Each dummy insulating pattern includes an insulating material extending continuously from a first level to a second level, wherein a bottom surface of each row line is located at the first level, and a top surface of each memory cell is located at the second level.

2. The electronic device according to claim 1, wherein: The dummy insulating pattern comprises: a first dummy insulating pattern extending parallel to the row line; and A second dummy insulating pattern extends parallel to the column line.

3. The electronic device according to claim 1, wherein: The column lines extend in a first direction, the row lines extend in a second direction crossing the first direction, and the dummy insulation patterns extend in the second direction.

4. The electronic device according to claim 3, wherein: The dummy insulation pattern is adjacent to the row line in the first direction.

5. The electronic device according to claim 3, wherein: An upper surface of the dummy insulating pattern is located at the same level as an upper surface of the memory cell.

6. The electronic device according to claim 1, wherein: The column lines extend in a first direction, the row lines extend in a second direction crossing the first direction, and the dummy insulation patterns extend in the first direction.

7. The electronic device according to claim 6, wherein: The dummy insulation pattern is adjacent to the column line in the second direction.

8. The electronic device according to claim 6, wherein: An upper surface of the dummy insulation pattern is located at the same level as an upper surface of the column line.

9. The electronic device according to claim 1, wherein: The width of the dummy insulating pattern is greater than the width of the row line or the column line.

10. The electronic device according to claim 1, wherein Each of the dummy insulating patterns is a single layer.

11. A method for manufacturing an electronic device including a semiconductor memory, the method comprising: forming a first conductive material on a substrate; forming a cell stack on the first conductive material in a cell region of the substrate; forming a first insulating layer in a peripheral region of the substrate; forming a unit pattern by patterning the unit stack; Forming row lines in a cell region of the substrate by etching the first conductive material; forming a first dummy insulating pattern by patterning the first insulating layer, Each of the first dummy insulating patterns includes the first insulating layer extending continuously from a first level to a second level, wherein a bottom surface of each of the row lines is located at the first level, and a top surface of each of the unit patterns is located at the second level; forming a liner layer on a sidewall of the unit pattern; and A dummy liner layer is formed on sidewalls of the first dummy insulation pattern.

12. The method according to claim 11, wherein: When forming the unit pattern, the first dummy insulating pattern is formed.

13. The method according to claim 11, wherein: When forming the liner layer, the dummy liner layer is formed.

14. The method according to claim 11, wherein: The step of forming the unit pattern comprises: forming a hard mask layer on the cell stack and the first insulating layer; forming a first mask pattern on the cell stack by etching the hard mask layer; and The cell stack is etched using the first mask pattern as an etch barrier.

15. The method according to claim 14, wherein: The step of forming the first dummy insulating pattern comprises: forming a second mask pattern on the first insulating layer by etching the hard mask layer; and The first insulating layer is etched using the second mask pattern as an etch barrier.

16. The method according to claim 11, further comprising: forming an insulating material to fill spaces between the unit patterns and spaces between the first dummy insulating patterns; as well as The insulating material is planarized.

17. The method according to claim 16, wherein: The step of forming the insulating material includes coating a low-k material using a spin coating process.

18. The method according to claim 16, wherein: The step of planarizing the insulating material includes planarizing the insulating material until upper surfaces of the cell pattern and the first dummy insulating pattern are exposed.

19. The method according to claim 11, wherein: The steps of forming the unit stack include: forming a stacked structure including an electrode material and a variable resistance material on a substrate including the cell region and the peripheral region; and A portion of the stack structure at a position corresponding to the peripheral region is etched.

20. The method according to claim 11, in, The row lines are formed after the unit patterns are formed.

21. The method according to claim 20, further comprising: forming a second conductive material on the unit pattern; forming column lines by etching the second conductive material; as well as Memory cells are formed by etching the cell patterns.

22. The method according to claim 21, further comprising: forming a second insulating layer in the peripheral region of the substrate; and When forming the column lines and the memory cells, a second dummy insulating pattern is formed by etching the second insulating layer.

23. The method according to claim 22, further comprising: forming an insulating material to fill the spaces between the memory cells and the spaces between the second dummy insulating patterns; as well as The insulating material is planarized.

24. The method according to claim 23, wherein: The step of forming the insulating material includes coating a low-k material using a spin coating process.

25. The method according to claim 24, wherein: The step of planarizing the insulating material includes planarizing the insulating material until upper surfaces of the column lines and the second dummy insulating patterns are exposed.

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