Driver integrated circuit and display device including the same

Abstract

A driver integrated circuit and a display device including the driver integrated circuit. The driver integrated circuit IC according to an embodiment of the present disclosure includes: a first IC; a second IC combined with the first IC; a first circuit configured to receive first image data and generate second image data by correcting the first image data; a second circuit configured to sample the second image data; and a third circuit configured to convert the sampled second image data into a source signal, wherein the first circuit is mounted on the first IC, the second circuit is mounted on one of the first IC and the second IC, and the third circuit is mounted on the second IC.

Description

Technical Field

[0001] The present disclosure relates to a driver integrated circuit (IC) and a display device including the driver integrated circuit. Background Art

[0002] As the development into an information society progresses, various demands for display devices for displaying images are increasing. Therefore, recently, various types of display devices such as liquid crystal display (LCD) devices or organic light emitting display devices are being used.

[0003] A display device includes a display panel and a driver integrated circuit (IC). The display panel is composed of a plurality of pixels arranged in a matrix form, and each pixel is composed of sub-pixels such as red (R), green (G), and blue (B). In addition, each pixel or each sub-pixel emits light in grayscale according to an image, thereby displaying an image on the entire display panel.

[0004] A driver IC is used to send display data indicating the grayscale value of each pixel or each sub-pixel to the display panel. Summary of the Invention

[0005] The present disclosure aims to provide a driver integrated circuit (IC) that can be miniaturized and a display device including the driver integrated circuit.

[0006] The present disclosure also aims to provide a driver IC that can minimize the loss of image data and a display device including the driver IC.

[0007] The present disclosure also aims to provide a driver IC that can minimize the wiring for image data and a display device including the driver IC.

[0008] The present disclosure also aims to provide a driver IC manufactured by a wafer-on-wafer process and a display device including the driver IC.

[0009] According to an aspect of the present disclosure, there is provided a driver IC including: a first IC; a second IC combined with the first IC; a first circuit configured to receive first image data and generate second image data by correcting the first image data; a second circuit configured to sample the second image data; and a third circuit configured to convert the sampled second image data into a source signal, wherein the first circuit is mounted on the first IC, the second circuit is mounted on one of the first IC and the second IC, and the third circuit is mounted on the second IC. Brief Description of the Drawings

[0010] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of this application. The accompanying drawings illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure. In the accompanying drawings:

[0011] Figure 1 is a diagram of a display device including a driver integrated circuit (IC) to which an embodiment of the present disclosure is applied;

[0012] Figure 2 is a schematic block diagram of a driver IC according to an embodiment of the present disclosure;

[0013] Figure 3 is a diagram illustrating the structure of a data driving unit of a driver IC according to an embodiment of the present disclosure;

[0014] Figure 4 is a diagram illustrating signal waveforms inside a driver IC according to an embodiment of the present disclosure;

[0015] Figure 5 is a diagram illustrating signal waveforms inside a driver IC according to another embodiment of the present disclosure;

[0016] Figure 6 is a schematic block diagram of a driver IC according to another embodiment of the present disclosure; and

[0017] Figure 7 is a diagram illustrating the structure of a data driving unit of a driver IC according to another embodiment of the present disclosure. Detailed Embodiments

[0018] In the description, it should be noted that, whenever possible, like reference numerals have been used for like elements that are represented in other figures. In the following description, when functions and configurations known to those skilled in the art are not relevant to the basic configuration of the present disclosure, their detailed descriptions will be omitted. The terms described in this specification should be understood as follows.

[0019] The advantages and features of the present disclosure and methods for implementing the same will be clarified by the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different ways and should not be construed as limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Additionally, the present disclosure is only defined by the scope of the claims.

[0020] The shapes, sizes, ratios, angles, and quantities disclosed in the drawings for describing the embodiments of the present disclosure are merely examples. Therefore, the present disclosure is not limited to the illustrated details. Similar reference numerals always refer to similar elements. In the following description, when it is determined that the detailed description of related known functions or configurations unnecessarily obscures the gist of the present disclosure, the detailed description will be omitted.

[0021] In the case of using "comprising", "having", and "including" described in this specification, unless "only" " is used, another part may be added. Terms in the singular form may include the plural form unless stated otherwise.

[0022] When interpreting an element, the element is interpreted as including an error range even though not explicitly described.

[0023] When describing a positional relationship, for example, when the positional relationship between two parts is described as "on ", "above ", "under ", and "adjacent to ", one or more other parts may be provided between the two parts unless "exactly" or "precisely" is used.

[0024] When describing a temporal relationship, for example, when the chronological order is described as "after ", "subsequently ", "immediately ", and "before ", discontinuous cases may be included unless "exactly" or "precisely" is used.

[0025] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0026] The X-axis direction, Y-axis direction, and Z-axis direction should not be interpreted only as a perpendicular geometric relationship between them, but may represent a broader directivity within the range where the elements of the present disclosure operate functionally.

[0027] The term "at least one" should be understood to include any combination and all combinations of one or more of the associated listed items. For example, the meaning of "at least one of the first item, the second item, and the third item" represents all combinations of two or more items selected from the first item, the second item, and the third item, as well as the first item, the second item, or the third item.

[0028] As can be fully understood by those skilled in the art, the features of the various embodiments of the present disclosure can be partially or fully coupled or combined with each other, and can interoperate with each other in various ways and be technically driven. The embodiments of the present disclosure can be implemented independently of each other, or can be implemented together in a mutually dependent relationship.

[0029] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0030] Figure 1 FIG. is an illustration of a display device to which a driver integrated circuit (IC) according to an embodiment of the present disclosure is applied. The display device 1000 according to the present disclosure includes an external system 100, a main board 200, a display panel 300, and a driver IC 400.

[0031] The display device 1000 may be a large terminal such as a television (TV) or a personal computer (PC), and may be a mobile terminal such as a smart phone or a cellular phone, or a tablet PC, etc.

[0032] The external system 100 may send display data to be displayed (e.g., image data, video data, or still image data) to the driver IC 400. The display data may be divided into row data units corresponding to the horizontal lines of the display panel 300.

[0033] When the display device 1000 according to the present disclosure is a smart phone, the external system 100 may be an application processor (AP) that wirelessly communicates with an external communication network to receive audio or data.

[0034] A power supply 210 and various circuit components may be mounted on the main board 200.

[0035] The power supply 210 provides a voltage for driving the display panel 300 and the driver IC 400. Specifically, the power supply 210 generates a voltage according to the driving voltage of each circuit included in the driver IC 400, supplies the voltage to each circuit, and provides power for driving the display panel 300.

[0036] The display panel 300 may be an organic light-emitting panel in which organic light-emitting diodes are formed, or may be a liquid crystal panel in which liquid crystals are formed. That is, all types of panels currently in use may be applied as the display panel 300 to which the present disclosure is applied. Therefore, the display device according to the present disclosure may also include an organic light-emitting display device, a liquid crystal display device, and various other types of display devices. However, for the sake of convenience in description, hereinafter, as an example of the present disclosure, the display device is described as a liquid crystal display device. Therefore, in the following description, the case where the display panel 300 is a liquid crystal panel is described as an example of the present disclosure.

[0037] In the case where the display panel 300 is a liquid crystal panel, a plurality of data lines DLl to DLd, a plurality of gate lines GLl to GLg intersecting the data lines, a plurality of thin film transistors (TFTs) formed at the intersections of the data lines and the gate lines, a plurality of pixel electrodes for charging data voltages into pixels, and a common electrode for driving the liquid crystals filled in the liquid crystal layer together with the pixel electrodes are formed on the lower glass substrate of the display panel 300, and due to the intersecting structure of the data lines and the gate lines, the pixels are arranged in a matrix form.

[0038] A black matrix BM and a color filter are formed on the upper glass substrate of the display panel 300. Liquid crystals are filled between the lower glass substrate and the upper glass substrate.

[0039] As the liquid crystal mode applied to the display panel 300 of the present disclosure, not only twisted nematic (TN) mode, vertical alignment (VA) mode, in-plane switching (IPS) mode, and fringe field switching (FFS) mode can be used, but also any kind of liquid crystal mode can be used. In addition, the display device 1000 according to the present disclosure can be implemented in any form, such as a transmissive liquid crystal display device, a transflective liquid crystal display device, or a reflective liquid crystal display device, etc.

[0040] The display panel 300 displays an image in response to a gate signal and a source signal output from the driver IC 400.

[0041] The driver IC 400 may be composed of a timing control unit 410, a gate driving unit 420, and a data driving unit 430. The timing control unit 410 is configured to control the gate driving unit 420 and the data driving unit 430 formed on the display panel 300. The gate driving unit 420 is configured to control the signals input through the gate lines. The data driving unit 430 is configured to control the signals input through the data lines formed on the display panel 300.

[0042] As Figure 1As shown, the driver IC 400 may be mounted on the display panel 300, but the present disclosure is not limited thereto, and the driver IC 400 may be mounted on a separate board separate from the display panel 300.

[0043] In addition, the timing control unit 410, the gate driving unit 420, and the data driving unit 430 may be formed separately, as Figure 1 shown, or formed in a single chip package.

[0044] Hereinafter, each component of the driver IC 400 will be described in more detail with reference to Figure 2 and Figure 3 FIGs.

[0045] Figure 2 is a schematic block diagram of a driver IC according to an embodiment of the present disclosure, and Figure 3 is a diagram illustrating the structure of a data driving unit of a driver IC according to an embodiment of the present disclosure.

[0046] As Figure 2 shown, the driver IC 400 includes a timing control unit 410, a gate driving unit 420, and a data driving unit 430.

[0047] The timing control unit 410 receives the first image data DATA1 and the timing signal TS from the external system 100, and generates a gate control signal GCS for controlling the gate driving unit 420 and a data control signal DCS for controlling the data driving unit 430 according to the timing signal TS. Here, the gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, etc., and the data control signal DCS includes a source start pulse SSP, a source sampling clock SSC, a source output enable signal SOE, etc.

[0048] The timing control unit 410 sends the gate control signal GCS to the gate driving unit 420, and sends the data control signal DCS to the data driving unit 430.

[0049] The timing control unit 410 arranges the first image data DATA1 received from the external system 100. Specifically, the timing control unit 410 arranges the first image data DATA1 to match the structure and characteristics of the display panel 300. The timing control unit 410 sends the arranged first image data DATA1 to the data driving unit 430.

[0050] The gate driving unit 420 outputs a gate signal synchronized with a source signal generated by the data driving unit 430 to a gate line in response to a gate control signal GCS generated by the timing control unit 410. Specifically, the gate driving unit 420 outputs a gate signal synchronized with the source signal to the gate line according to a gate start pulse, a gate shift clock, and a gate output enable signal generated by the timing control unit 410.

[0051] The gate driving unit 420 includes a gate shift register, a gate level shifter, and the like. Here, the gate shift register can be directly formed on the TFT array substrate of the display panel 300 through an in-panel gate (GIP) process. In this case, the gate driving unit 420 supplies a gate start pulse and a gate shift clock to the gate shift register formed on the TFT array substrate through the GIP process.

[0052] The data driving unit 430 converts first image data DATA1 into a source signal according to a data control signal DCS generated by the timing control unit 410. Specifically, the data driving unit 430 converts the first image data DATA1 into a source signal according to a source start pulse, a source sampling clock, and a source output enable signal. The data driving unit 430 outputs a source signal corresponding to one horizontal line to a data line during each horizontal period when the gate signal is supplied to the gate line.

[0053] Here, the data driving unit 430 receives a gamma voltage from a gamma voltage generator (not shown) and uses the gamma voltage to convert the first image data into a source signal.

[0054] According to an embodiment of the present disclosure, as Figure 2 shown, the data driving unit 430 includes a first circuit 450, a second circuit 460, and a third circuit 470.

[0055] According to an embodiment of the present disclosure, as Figure 2 and Figure 3 shown, the data driving unit 430 includes a first circuit 450 located in the first IC 10, a second circuit 460 located in the first IC 10, and a third circuit 470 located in the second IC 20.

[0056] The driver IC 400 according to the present disclosure can be manufactured by a wafer-on-wafer process. Compared with the case where the driver IC 400 is manufactured using a single wafer, in the present disclosure, the circuit of the driver IC 400 is divided and formed in a first wafer and a second wafer, and the two wafers are combined to manufacture the driver IC 400, so that the number of required masks is reduced, thereby reducing costs. As described above, since the driver IC according to the present disclosure is manufactured by a wafer-on-wafer process, the circuit is divided and formed in two ICs.

[0057] In addition, according to an embodiment of the present disclosure, as Figure 3 shown, the first IC 10 and the second IC 20 can be combined with each other. Specifically, the first IC 10 and the second IC 20 can be combined by methods such as wire bonding using wires, flip-chip bonding by connecting through bumps, and through-silicon via (TSV) bonding. Therefore, since the circuit constituting the driver IC 400 is formed in the two ICs 10 and 20, and the first IC 10 and the second IC 20 are combined, the driver IC can be miniaturized.

[0058] According to an embodiment of the present disclosure, the data driving unit 430 includes: a first circuit 450 configured to receive and process first image data DATA1 to generate second image data DATA2; a second circuit 460 configured to sample the second image data DATA2 using a data control signal DCS; and a third circuit 470 configured to convert the sampled second image data DATA2 into a source signal.

[0059] The first circuit 450 receives and processes the first image data DATA1 to generate the second image data DATA2, and sends the generated second image data DATA2 to the second circuit 460.

[0060] According to an embodiment of the present disclosure, the first circuit 450 includes an interface part 451 and a data processing part 452.

[0061] The interface part 451 can perform docking on signals and / or data transmitted and received between the timing control unit 410 and the data processing part 452. Specifically, the interface part 451 performs docking after receiving the first image data DATA1 transmitted from the timing control unit 410, and sends the docked first image data DATA1 to the data processing part 452. Here, the first image data DATA1 can be R, G, and B data.

[0062] The interface portion 451 may be an interface suitable for a serial interface, such as a Mobile Industry Processor Interface Mobile Display Digital Interface (MDDI), DisplayPort, or Embedded DisplayPort (eDP).

[0063] The data processing portion 452 generates second image data DATA2 by correcting first image data DATA1 transmitted from the interface portion 451. In this case, the generated second image data DATA2 may be image data that enables the image quality of the display panel to be improved compared to the first image data DATA1. The data processing portion 452 transmits the generated second image data DATA2 to the shift register portion 461 of the second circuit 460.

[0064] According to an embodiment of the present disclosure, the data processing portion 452 calculates checksum data CHKSUM for the second image data DATA2 and transmits the checksum data to the second circuit 460. The checksum data CHKSUM will be described in detail below with reference to Figure 4 The checksum data CHKSUM can minimize the loss of image data by correcting errors that occur during the transmission of the image data using the checksum data CHKSUM according to an embodiment of the present disclosure.

[0065] The second circuit 460 receives the second image data DATA2 and the data control signal DCS and outputs a sampling signal.

[0066] According to an embodiment of the present disclosure, the second circuit 460 includes a shift register portion 461 and a first level shifter 462.

[0067] The shift register portion 461 controls the timing at which the second image data DATA2 is sequentially stored in the latch portion 471 of the third circuit 470. Specifically, the shift register portion 461 uses the data control signal DCS to output a sampling signal. The shift register portion 461 outputs a sampling signal by sequentially shifting a source start pulse according to a source sampling clock.

[0068] The first level shifter 462 changes the voltage level of the second image data DATA2. Specifically, the first level shifter 462 amplifies the voltage level of the second image data DATA2 to a voltage level that the second circuit 460 can drive. According to an embodiment of the present disclosure, the first level shifter 462 transmits the second image data DATA2 having the amplified voltage level to the latch portion 471 of the third circuit 470 mounted on the second IC 20.

[0069] A third circuit 470 converts the sampled second image data DATA2 into a source signal and outputs the source signal to the data lines DL of the display panel.

[0070] According to an embodiment of the present disclosure, the third circuit 470 includes a latch part 471, a second level shifter 472, a digital-to-analog converter 473, and a buffer part 474.

[0071] The latch part 471 sequentially samples and latches the second image data DATA2 amplified by the first level shifter 462 of the second circuit 460 in a predetermined unit according to a sampling signal. Specifically, the latch part 471 stores the second image data DATA2 having an amplified voltage level and received from the first level shifter 462 of the second circuit 460 in response to the sampling signal generated by the shift register part 461 of the second circuit 460. In this case, the second image data DATA2 may be R, G, and B data. The latch part 471 transfers the stored second image data DATA2 to the second level shifter 472.

[0072] The second level shifter 472 changes the voltage level of the latched second image data DATA2. Specifically, the second level shifter 472 amplifies the voltage level of the second image data DATA2 to a voltage level that the digital-to-analog converter 473 can drive. The second level shifter 472 transfers the second image data DATA2 having the amplified voltage level to the digital-to-analog converter 473.

[0073] The digital-to-analog converter 473 converts the second image data DATA2 having the amplified voltage level into a source signal as an analog signal. The digital-to-analog converter 473 transfers the source signal converted into an analog signal to the buffer part 474.

[0074] The buffer part 474 outputs the source signal to the data lines. Specifically, the buffer part 474 buffers the source signal according to the source output enable signal generated by the timing control unit 410 and outputs the buffered source signal to the data lines.

[0075] According to an embodiment of the present disclosure, the number of wires between the second circuit 460 including the shift register part 461 and the first level shifter 462 and mounted on the first IC 10 and the third circuit 470 including the latch part 471 and mounted on the second IC 20 can be minimized. Since the number of wires connected between the first level shifter 462 of the first IC 10 and the latch part 471 of the second IC 20 can be reduced, the number of wires between the first IC 10 and the second IC 20 can be minimized.

[0076] Hereinafter, reference will be made to Figure 4and Figure 5 The checksum data according to an embodiment of the present disclosure is described in detail.

[0077] Figure 4 is a diagram illustrating signal waveforms inside a driver IC according to an embodiment of the present disclosure, and Figure 5 is a diagram illustrating signal waveforms inside a driver IC according to another embodiment of the present disclosure.

[0078] As described above, a driver IC according to an embodiment of the present disclosure generates checksum data CHKSUM for second image data DATA2. The second image data DATA2 is composed of multiple horizontal line data, and one horizontal line data is composed of first channel data CH1 to eighth channel data CH8.

[0079] The shift register section 461 of the second circuit 460 is enabled according to the control signal of the timing control unit 410, and the channel data CH1 to CH8 are sequentially stored in the registers of the shift register section 461, respectively. Specifically, as Figure 4 and Figure 5 shown, after the first channel data CH1 to the eighth channel data CH8 of one horizontal line data are sequentially stored in the registers respectively, the checksum data CHKSUM for the corresponding horizontal line data is stored in the register.

[0080] The latch section 471 of the third circuit 470 is enabled in response to the control signal of the timing control unit 410, and the channel data CH1 to CH8 are stored in the latches of the latch section 471, respectively. Specifically, as Figure 4 and Figure 5 shown, after the first channel data CH1 to the eighth channel data CH8 of one horizontal line data are stored in the latches respectively, the checksum data CHKSUM for the corresponding horizontal line data is stored in the latch.

[0081] Here, as Figure 4 shown, the latch section 471 of the third circuit 470 can be enabled while the register among the registers of the shift register section 461 of the second circuit 460 in which the eighth channel data CH8 is stored is enabled. Therefore, when the register among the registers of the shift register section 461 of the second circuit 460 in which the eighth channel data CH8 is stored is enabled and thus the eighth channel data CH8 is stored, the first channel data CH1 to the eighth channel data CH8 of one horizontal line data can be stored in the latches respectively.

[0082] Alternatively, as Figure 5As shown, the latch part 471 of the third circuit 470 can be enabled while the register storing the checksum data CHKSUM among the registers of the shift register part 461 of the second circuit 460 is enabled. Accordingly, when the register storing the checksum data CHKSUM among the registers of the shift register part 461 of the second circuit 460 is enabled and thus the checksum data CHKSUM is stored in the register, the first channel data CH1 to the eighth channel data CH8 of a horizontal line of data can be respectively stored in the latches.

[0083] Figure 6 is a schematic block diagram of a driver IC according to another embodiment of the present disclosure, and Figure 7 is a diagram illustrating the structure of a data driving unit of a driver IC according to another embodiment of the present disclosure. Hereinafter, reference will be made to Figure 6 and Figure 7 to describe in detail a driver IC according to another embodiment of the present disclosure. Hereinafter, detailed descriptions of the same content as the above will be omitted.

[0084] According to another embodiment of the present disclosure, as Figure 6 shown, the data driving unit 430 includes a first circuit 460, a second circuit 470, and a third circuit 480.

[0085] According to another embodiment of the present disclosure, as Figure 6 and Figure 7 shown, the data driving unit 430 includes a first circuit 460 located in the first IC 10, a second circuit 470 located in the second IC 20, and a third circuit 480 located in the second IC 20.

[0086] According to another embodiment of the present disclosure, as Figure 7 shown, the first IC 10 and the second IC 20 can be combined with each other. Specifically, the first IC 10 and the second IC 20 can be combined by methods such as wire bonding using a wire, flip chip bonding by connecting with bumps, and through-silicon via (TSV) bonding.

[0087] According to another embodiment of the present disclosure, the data driving unit 430 includes: a first circuit 460 configured to receive and process first image data DATA1 to generate second image data DATA2; a second circuit 470 configured to generate sampled second image data DATA2 using the second image data DATA2 and a data control signal DCS; and a third circuit 480 configured to convert the sampled second image data DATA2 into a source signal and transmit the source signal to a data line DL of a display panel.

[0088] The first circuit 460 receives and processes the first image data DATA1 to generate the second image data DATA2, and transmits the generated second image data DATA2 to the second circuit 470.

[0089] According to another embodiment of the present disclosure, the first circuit 460 includes an interface portion 461 and a data processing portion 462.

[0090] The interface portion 461 may perform docking on signals and / or data transmitted and received between the timing control unit 410 and the data processing portion 462. Specifically, the interface portion 461 performs docking after receiving the first image data DATA1 transmitted from the timing control unit 410, and transmits the docked first image data DATA1 to the data processing portion 462. Here, the first image data DATA1 may be R, G, and B data.

[0091] The interface portion 461 may be an interface suitable for a serial interface, such as a Mobile Industry Processor Interface Mobile Display Digital Interface (MDDI), DisplayPort, or Embedded DisplayPort (eDP).

[0092] The data processing portion 462 generates the second image data DATA2 by correcting the first image data DATA1 transmitted from the interface portion 461. In this case, compared with the first image data DATA1, the generated second image data DATA2 may be image data that enables the image quality of the display panel to be improved. According to another embodiment of the present disclosure, the data processing portion 462 transmits the generated second image data DATA2 to the shift register portion 471 of the second circuit 470 mounted on the second IC 20.

[0093] According to another embodiment of the present disclosure, the data processing portion 462 calculates checksum data CHKSUM for the second image data DATA2 and transmits the checksum data to the second circuit 470. According to another embodiment of the present disclosure, errors that occur during the transmission of the image data may be corrected by using the checksum data CHKSUM to minimize the loss of the image data.

[0094] According to another embodiment of the present disclosure, the second circuit 470 includes a shift register portion 471.

[0095] The shift register section 471 controls the timing at which the second image data DATA2 is sequentially stored in the latch section 481 of the third circuit 480. Specifically, the shift register section 471 outputs a sampling signal using a data control signal DCS. The shift register section 471 outputs a sampling signal by sequentially shifting a source start pulse according to a source sampling clock. The shift register section 471 sends the sampling signal to the latch section 481 of the third circuit 480.

[0096] The shift register section 471 receives a source start pulse and a source sampling clock from the timing control unit 410, and sequentially shifts the source start pulse according to the source sampling clock to output a sampling signal. The shift register section 471 sends the sampling signal to the third circuit 480.

[0097] According to another embodiment of the present disclosure, the third circuit 480 includes a latch section 481, a level shifter 482, a digital-to-analog converter 483, and a buffer section 484.

[0098] According to another embodiment of the present disclosure, the number of wires between the first circuit 460 including the interface section 461 and the data processing section 462 and mounted on the first IC 10 and the second circuit 470 including the shift register section 471 and mounted on the second IC 20 can be minimized. Since the number of wires connected between the data processing section 462 of the first IC 10 and the shift register section 471 of the second IC 20 can be reduced, the number of wires between the first IC 10 and the second IC 20 can be minimized.

[0099] According to the present disclosure, the circuits constituting the driver IC are divided and formed in two integrated circuits, and the two integrated circuits are combined so that the driver IC can be miniaturized, and thus there is an effect that the size of the bezel of the display device on which the corresponding driver IC is mounted can be reduced.

[0100] In addition, according to the present disclosure, the driver IC is manufactured by a wafer-on-wafer process, so that the number of masks required for each wafer can be reduced, and thus there is an effect that the cost of manufacturing the driver IC can be minimized.

[0101] In addition, according to the present disclosure, the loss of image data can be reduced, and thus there is an effect that the image quality of the display device can be improved.

[0102] In addition, according to the present disclosure, there is an effect that the number of wires used for image data can be minimized.

[0103] It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the present disclosure. Accordingly, it is intended that the present disclosure cover modifications and variations of the present disclosure that fall within the scope of the appended claims and their equivalents.

[0104] Cross-reference to Related Applications

[0105] This application claims the benefit of Korean Patent Application No. 10-2019-0141110, filed on Nov. 6, 2019, and Korean Patent Application No. 10-2020-0130816, filed on Oct. 12, 2020, which are hereby incorporated by reference herein in their entirety as if fully set forth herein.

Claims

1. A driver integrated circuit (IC), the driver integrated circuit IC comprises: a first IC; a second IC, the second IC being combined with the first IC; a first circuit configured to receive first image data and generate second image data by correcting the first image data; a second circuit configured to sample the second image data; and a third circuit configured to convert the sampled second image data into a source signal, wherein the first circuit is mounted on the first IC, the second circuit is mounted on one of the first IC and the second IC, and the third circuit is mounted on the second IC.

2. The driver integrated circuit IC according to claim 1, wherein the second circuit is mounted on the first IC and includes a shift register portion and a first level shifter, the shift register portion being configured to receive a source start pulse and a source sampling clock and output a sampling signal by sequentially shifting the source start pulse according to the source sampling clock, the first level shifter being configured to amplify the voltage level of the second image data.

3. The driver integrated circuit IC according to claim 1, wherein the second circuit is mounted on the second IC and includes a shift register portion configured to receive a source start pulse and a source sampling clock and output a sampling signal by sequentially shifting the source start pulse according to the source sampling clock.

4. The driver integrated circuit IC according to claim 1, wherein the third circuit comprises: a latch portion configured to sequentially sample and latch the sampled second image data in a predetermined unit; a second level shifter configured to amplify the voltage level of the latched second image data; a digital-to-analog converter configured to convert the amplified second image data into the source signal as an analog signal; and a buffer portion configured to buffer the source signal according to a source output enable signal generated by a timing control circuit and output the buffered source signal to a display panel.

5. The driver integrated circuit IC according to claim 1, wherein the first circuit includes a data processing portion configured to receive the first image data and transmit the second image data by processing the first image data.

6. The driver integrated circuit IC according to claim 5, wherein the data processing portion calculates checksum data for the second image data and transmits the checksum data to the second circuit.

7. The driver integrated circuit IC according to claim 5, wherein the second circuit includes a shift register portion configured to receive a source start pulse and a source sampling clock and output a sampling signal by sequentially shifting the source start pulse according to the source sampling clock, and The shift register section includes a register configured to store checksum data for the second image data.

8. The driver integrated circuit IC according to claim 5, wherein, the third circuit includes a latch section configured to sequentially sample and latch the sampled second image data, and the latch section includes a latch configured to store checksum data for the second image data.

9. The driver integrated circuit IC according to claim 1, wherein, the first IC and the second IC are combined by one of wire bonding, flip chip bonding, and through-silicon via bonding.

10. The driver integrated circuit IC according to claim 1, wherein, the driver integrated circuit IC is a driver integrated circuit IC for driving a display that outputs an image signal to a display panel.

11. A display device including a data driving unit configured to transmit a source signal to a data line of a display panel; wherein, the data driving unit includes: a first integrated circuit IC; a second IC combined with the first IC; a first circuit configured to receive first image data and generate second image data by correcting the first image data; a second circuit configured to sample the second image data; and a third circuit configured to convert the sampled second image data into a source signal and send the source signal to the data line, wherein the first circuit is mounted on the first IC, the second circuit is mounted on one of the first IC and the second IC, and the third circuit is mounted on the second IC.

12. The display device according to claim 11, wherein, the second circuit is mounted on the first IC and includes a shift register section and a first level shifter. The shift register section is configured to receive a source start pulse and a source sampling clock, and output a sampling signal by sequentially shifting the source start pulse according to the source sampling clock. The first level shifter is configured to amplify the voltage level of the second image data.

13. The display device according to claim 11, wherein, the second circuit is mounted on the second IC and includes a shift register section configured to receive a source start pulse and a source sampling clock, and output a sampling signal by sequentially shifting the source start pulse according to the source sampling clock.

14. The display device according to claim 11, wherein, the third circuit includes: a latch section configured to sequentially sample and latch the sampled second image data in a predetermined unit; a second level shifter configured to amplify the voltage level of the latched second image data; a digital-to-analog converter configured to convert the amplified second image data into the source signal as an analog signal; and A buffer section configured to buffer the source signal according to a source output enable signal generated by a timing control circuit and output the buffered source signal to the display panel.

15. The display device according to claim 11, wherein, the first circuit includes a data processing section configured to receive the first image data and transmit the second image data by processing the first image data.

16. The display device according to claim 15, wherein, the data processing section calculates checksum data for the second image data and transmits the checksum data to the second circuit.

17. The display device according to claim 11, wherein, the first IC and the second IC are combined by one of wire bonding, flip chip bonding, and through-silicon via bonding.

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