Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises: a method for forming a semiconductor structure, comprising: providing a layer to be etched; forming an initial sidewall on the layer to be etched; performing at least one modification etching process on the initial sidewall to form a sidewall on the layer to be etched, wherein the modification etching process comprises: performing modification processing on the initial sidewall to form a transition layer on the top surface and the sidewall surface of the initial sidewall; and removing the transition layer by an atomic layer etching process. The semiconductor structure formed by the method has good performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the advancement of semiconductor manufacturing technology, in order to achieve faster computing speed, larger data storage capacity and more functions, semiconductor devices have adopted many different methods in the prior art to reduce the feature size (CD) and increase the integration density of semiconductor chips, including the use of self-aligned double-patterning (SADP) and self-aligned quadruple-patterning (SAQP).

[0003] Both the self-aligned double imaging technology and the self-aligned quadruple imaging technology have achieved a doubling of spatial pattern density. However, due to the manufacturing process limitations of the self-aligned double imaging technology and the self-aligned quadruple imaging technology, the performance of semiconductor devices is reduced. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0005] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a layer to be etched; forming an initial side wall on the layer to be etched; performing at least one modification etching treatment on the initial side wall to form a side wall on the layer to be etched, the modification etching treatment including: performing a modification treatment on the initial side wall to form a transition layer on the top surface and the side wall surface of the initial side wall; and removing the transition layer using an atomic layer etching process.

[0006] Optionally, the initial sidewall surface has a first roughness; the sidewall has a second roughness, and the first roughness is greater than the second roughness.

[0007] Optionally, the top of the initial side wall has a top angle, and the top of the side wall has a rounded corner.

[0008] Optionally, the modification process is a plasma treatment process.

[0009] Optionally, the material of the initial sidewall spacer is silicon nitride, and the gas used in the modification process includes oxygen.

[0010] Optionally, the process parameters of the plasma treatment include: the gas used includes O 2 , Ar and C 4 H 6, the pressure is 10 mTorr to 50 mTorr, the O 2 , Ar and C 4 H 6 The flow rate range is 5 standard ml / min to 800 standard ml / min, the RF power is 30 watts to 500 watts, and the bias power is 10 watts to 200 watts.

[0011] Optionally, the atomic layer etching process includes: performing a passivation process; and performing an etching process after the passivation process.

[0012] Optionally, the passivation process includes: using a passivation gas to react with the surface of the transition layer to form a passivation layer on at least a portion of the transition layer; and the etching process includes: using an etching gas to react with the passivation layer to remove the passivation layer.

[0013] Optionally, the material of the transition layer includes: Si-ON group.

[0014] Optionally, the passivation gas includes: fluorocarbon gas; the fluorocarbon gas includes C 4 F 6 , CH 3 F or CHF 3 .

[0015] Optionally, the etching gas includes: Ar or He.

[0016] Optionally, the RF bias voltage range of the atomic layer etching process is 10 watts to 250 watts.

[0017] Optionally, the layer to be etched includes a substrate and a buffer layer located on the surface of the substrate.

[0018] Optionally, the method for forming the initial side wall includes: forming a plurality of mutually discrete sacrificial layers on the surface of the layer to be etched; forming a side wall material film on the surface of the layer to be etched, and on the top and side wall surfaces of the sacrificial layers; back-etching the side wall material film until the surface of the layer to be etched and the top surface of the sacrificial layer are exposed to form the initial side wall; after forming the initial side wall, removing the sacrificial layer.

[0019] Optionally, the sacrificial layer is formed by a self-aligned multi-patterning process.

[0020] Optionally, the method further includes: after forming the side wall, etching the layer to be etched using the side wall as a mask.

[0021] Optionally, it also includes: after forming the side wall, forming an additional side wall located on the side wall surface of the side wall on the surface of the layer to be etched; after forming the additional side wall, removing the side wall; and etching the layer to be etched using the additional side wall as a mask.

[0022] Optionally, the method for forming the additional side wall includes: forming an additional side wall material film on the surface of the layer to be etched, and the top surface of the side wall and the side wall surface; back etching the additional side wall material film until the top surface of the side wall and the surface of the layer to be etched are exposed to form the additional side wall.

[0023] Correspondingly, the technical solution of the present invention also provides a semiconductor structure formed by any of the above methods.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0025] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the transition layer is formed by modifying the initial sidewall, and the transition layer can improve the morphology of the top surface of the initial sidewall, and at the same time can improve the roughness of the sidewall surface of the initial sidewall. The transition layer is removed by an atomic layer etching process, and the atomic layer etching process can etch the transition layer at the atomic level, that is, the transition layer is accurately removed, thereby ensuring that the top morphology of the formed sidewall is good and the roughness of the sidewall surface is reduced. In summary, the method can form a sidewall with a good top morphology and a low sidewall surface roughness, thereby improving the performance of the formed semiconductor structure.

[0026] Furthermore, through the modification process, part of the initial sidewall spacer forms the transition layer, that is, part of the initial sidewall spacer is consumed. Furthermore, the size of the sidewall spacer formed by the subsequent removal of the transition layer is smaller than the size of the initial sidewall spacer, which is conducive to forming a semiconductor structure with a further reduced feature size, thereby improving the performance of the formed semiconductor structure.

[0027] Furthermore, through the modification treatment, when the gas used reacts with the top of the initial side wall to form a transition layer, since the top of the initial side wall has a top angle, the degree of reaction of the gas used with the protruding part of the top of the initial side wall is greater than the degree of reaction of the non-protruding part of the top, thereby weakening the difference between the protruding part and the smooth part. Therefore, the morphology of the top of the initial side wall can be improved, and the top of the side wall formed after removing the transition layer has a rounded corner, that is, the morphology is better, so that the performance of the formed semiconductor structure is better.

[0028] Furthermore, through the modification treatment, when the gas used reacts with the surface of the initial side wall to form a transition layer, due to the uneven surface of the initial side wall, the degree of reaction of the gas with the protruding part of the side wall surface is greater than the degree of reaction with the concave part of the side wall surface, thereby weakening the difference between the protruding part and the concave part of the side wall. Therefore, the roughness of the initial side wall can be reduced, so that the second roughness of the side wall formed after removing the transition layer is less than the first roughness, which is beneficial to improving the performance of the formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figures 1 to 5 is a cross-sectional schematic diagram of various steps of a method for forming a semiconductor structure;

[0030] Figures 6 to 17 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0031] As described in the background art, semiconductor structures have poor performance.

[0032] The following is a detailed description of the reasons for the poor performance of the semiconductor structure with reference to the accompanying drawings. Figures 1 to 5 The invention is a cross-sectional schematic diagram of each step of a method for forming a semiconductor structure.

[0033] Please refer to Figure 1 , a layer 20 to be etched is formed on the semiconductor substrate 10.

[0034] Please refer to Figure 2 A sacrificial material layer to be etched (not shown) is formed on the surface of the layer to be etched 20 , and the sacrificial material layer to be etched is etched to form a patterned sacrificial layer 30 , exposing a portion of the surface of the layer to be etched 20 .

[0035] Please refer to Figure 3 A sidewall material layer (not shown) is formed on the top surface and sidewall surface of the patterned sacrificial layer 30 and the surface of the layer to be etched 20 , and the sidewall material layer is etched to form a sidewall 40 on the sidewall surface of the patterned sacrificial layer 30 .

[0036] Please refer to Figure 4 , remove the patterned sacrificial layer 30.

[0037] Please refer to Figure 5 , using the sidewall 40 as a mask, the layer to be etched 20 is etched to form a pattern 21 in the layer to be etched 20 .

[0038] In the above method, the sidewall material layer is etched to form the sidewall 40. By controlling the deposition process parameters, the thickness of the formed sidewall material layer can be controlled, and a thinner sidewall material layer can usually be formed, which correspondingly makes the formed sidewall 40 thinner, thereby meeting the requirement of smaller and smaller semiconductor structure size.

[0039] However, as the critical dimensions of semiconductor structures become smaller and smaller, due to the limitations of existing processes, such as the exposure limit of the photolithography process, the loss during the etching process, etc., it is easy for the formed sidewall 40 to have a large roughness, and the top of the sidewall 40 has a top angle, that is, the morphology is poor, resulting in the subsequent etching of the etched layer 20 using the sidewall 40 as a mask to form a poor morphology of the pattern. At the same time, the roughness of the sidewall surface of the sidewall 40 is large, which further affects the accuracy of the formed pattern, resulting in poor performance of the formed semiconductor structure.

[0040] It should be noted that the top angle means that the side wall 40 has a first side (not shown in the figure) and a second side (not shown in the figure) opposite to each other, and the height of the first side is different from the height of the second side.

[0041] To solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a layer to be etched; forming an initial sidewall on the layer to be etched; performing at least one modification etching process on the initial sidewall to form a sidewall on the layer to be etched, wherein the modification etching process comprises: performing modification processing on the initial sidewall to form a transition layer on the top surface and the sidewall surface of the initial sidewall; and removing the transition layer by an atomic layer etching process. The method improves the performance of the formed semiconductor structure.

[0042] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0043] Figures 6 to 17 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0044] Please refer to Figure 6 , providing a layer 200 to be etched.

[0045] In this embodiment, the layer to be etched 200 includes a substrate 201 and a buffer layer 202 located on the surface of the substrate 201 .

[0046] The buffer layer 202 is used to protect the surface of the substrate 201 to reduce damage to the surface of the substrate 201 caused by subsequent processes.

[0047] The material of the substrate 201 is a semiconductor material. In this embodiment, the material of the substrate 201 is silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator. Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0048] The material of the buffer layer 202 includes silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonitride oxide or silicon nitride oxide.

[0049] In this embodiment, the material of the buffer layer 202 is silicon oxide.

[0050] Next, an initial sidewall spacer is formed on the to-be-etched layer 200. For details on the process of forming the initial sidewall spacer, please refer to Figures 7 to 9 .

[0051] Please refer to Figure 7 , a plurality of mutually separate sacrificial layers 210 are formed on the surface of the layer to be etched 200 .

[0052] In this embodiment, the sacrificial layer 210 is formed by a self-aligned multi-patterning process.

[0053] Specifically, the method for forming the sacrificial layer 210 includes: forming a plurality of mutually discrete patterned layers (not shown in the figure) on the surface of the layer to be etched 200; forming a sacrificial material film (not shown in the figure) on the surface of the layer to be etched 200, and the top surface and side wall surface of the patterned layer; back-etching the sacrificial material film until the surface of the layer to be etched 200 and the surface of the patterned layer are exposed, and forming the plurality of mutually discrete sacrificial layers 210 on the surface of the layer to be etched 200; after forming the sacrificial layer 210, removing the patterned layer.

[0054] The material of the sacrificial layer 210 includes: amorphous silicon, amorphous carbon, polysilicon, silicon oxide, silicon oxycarbide or silicon oxyhydrogencarbide.

[0055] In other embodiments, a plurality of mutually separate sacrificial layers may be formed by a photomask process.

[0056] Please refer to Figure 8 A spacer material film 220 is formed on the surface of the layer to be etched 200 and the top surface and sidewall surface of the sacrificial layer 210 .

[0057] The spacer material film 220 provides material for subsequently forming an initial spacer.

[0058] The material of the spacer material film 220 includes silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonitride oxide or silicon nitride oxide.

[0059] In this embodiment, the material of the spacer material film 220 is silicon nitride.

[0060] The formation process of the spacer material film 220 includes: chemical vapor deposition process, physical vapor deposition process or atomic layer deposition process.

[0061] In this embodiment, the atomic layer deposition process is used to form the sidewall material film 220, which is conducive to forming a sidewall material film 220 with uniform thickness and good morphology. The sidewall material film 220 is then subsequently etched back to form a sidewall with uniform thickness and good morphology, which is conducive to improving the performance of the formed semiconductor structure.

[0062] Please refer to Fig. 9 , the sidewall material film 220 is etched back until the surface of the layer to be etched 200 and the top surface of the sacrificial layer 210 are exposed, so as to form an initial sidewall 221 .

[0063] The surface of the initial sidewall 221 has a first roughness.

[0064] Due to the limitation of the existing etching process, the first roughness of the surface of the initial sidewall 221 is relatively large.

[0065] The top of the initial sidewall 221 has a top angle a.

[0066] In this embodiment, the present invention further includes: after forming the initial spacer 221, removing the sacrificial layer 210

[0067] After forming the initial sidewall spacer 221, the initial sidewall spacer 221 is subjected to at least one modification etching process to form a sidewall spacer on the to-be-etched layer 200. The modification etching process includes: performing modification processing on the initial sidewall spacer 221 to form a transition layer on the top surface and the sidewall surface of the initial sidewall spacer 221; and removing the transition layer by an atomic layer etching process. For details on the process of performing the modification etching process once, please refer to Fig.10 To figure.

[0068] Please refer to Fig.10 and Fig.11 , Fig.11 for Fig.10 The partial enlarged view of the middle area A shows that the initial sidewall 221 is modified so that a transition layer 230 is formed on the top surface and the sidewall surface of the initial sidewall 221 .

[0069] In this embodiment, the modification process is a plasma treatment process.

[0070] The gas used in the modification process includes oxygen.

[0071] Specifically, in this embodiment, the process parameters of the plasma treatment include: the gas used includes O 2 , Ar and C 4 H 6 , the pressure is 10 mTorr to 50 mTorr, the O 2 , Ar and C 4 H 6The flow rate range is 5 standard ml / min to 800 standard ml / min, the RF power is 30 watts to 500 watts, and the bias power is 10 watts to 200 watts.

[0072] In this embodiment, since the material of the initial sidewall spacer 221 is silicon nitride, after the modification process, the material of the formed transition layer 230 includes Si—ON groups.

[0073] The transition layer 230 is formed by modifying the initial sidewall 221 . The transition layer 230 can improve the morphology of the top surface of the initial sidewall 221 and improve the roughness of the sidewall surface of the initial sidewall 221 .

[0074] Specifically, through the modification treatment, when the gas used reacts with the top of the initial side wall 221 to form the transition layer 230, since the top of the initial side wall 221 has a top angle, the degree of reaction of the gas used with the protruding part of the top of the initial side wall 221 is greater than the degree of reaction of the non-protruding part of the top, thereby weakening the difference between the protruding part and the smooth part of the top, and therefore, the morphology of the top of the initial side wall 221 can be improved, and then the top of the side wall formed after the subsequent removal of the transition layer 230 has a rounded corner, that is, the morphology is better, so that the performance of the formed semiconductor structure is better.

[0075] Specifically, through the modification treatment, when the gas used reacts with the side wall surface of the initial side wall 221 to form the transition layer 230, due to the uneven side wall surface of the initial side wall 221, the degree of reaction of the gas with the protruding part of the side wall surface is greater than the degree of reaction with the concave part of the side wall surface, thereby weakening the difference between the protruding part and the concave part of the side wall. Therefore, the roughness of the initial side wall 221 can be reduced, so that the second roughness of the side wall formed after the subsequent removal of the transition layer 230 is less than the first roughness, which is beneficial to improving the performance of the formed semiconductor structure.

[0076] Through the modification process, part of the initial spacer 221 forms the transition layer 230, that is, part of the initial spacer 221 is consumed. Furthermore, the size of the spacer formed by removing the transition layer is smaller than the size of the initial spacer, which is conducive to forming a semiconductor structure with a further reduced feature size, thereby improving the performance of the formed semiconductor structure.

[0077] Next, the transition layer is removed by an atomic layer etching process. The atomic layer etching process includes: performing a passivation process; and performing an etching process after the passivation process. For details on the process of performing the atomic layer etching process, please refer to Figures 12 to 15 .

[0078] Please refer to Fig.12 and Fig.13 , Fig.13 for Fig.12 In the partial enlarged view of the B area, a passivation gas is used to react with the transition layer 230 on the surface of the initial sidewall 221 , so that at least a portion of the transition layer 230 forms a passivation layer 231 .

[0079] In this embodiment, the transition layer 230 located on the surface of the initial sidewall spacer 221 forms a passivation layer 231 .

[0080] The passivation gas includes: fluorocarbon gas; the fluorocarbon gas includes C 4 F 6 , CH 3 F or CHF 3 .

[0081] Please refer to Fig.14 and Fig.15 , Fig.15 for Fig.14 The partially enlarged view of the middle area C shows that the passivation layer 231 is removed by reacting the etching gas with the passivation layer 231 .

[0082] The etching gas includes: Ar or He.

[0083] The radio frequency bias voltage of the atomic layer etching process ranges from 10 watts to 250 watts.

[0084] The significance of selecting the RF bias range is that if the RF bias is less than 10 watts, the etching reaction rate is too low, which is not conducive to improving the production rate; if the RF bias is greater than 250 watts, it is not conducive to controlling the etching reaction rate, and the ion penetration depth is large, which easily causes excessive loss of the initial side wall 221, thereby reducing the accuracy of the characteristic size of the side wall finally formed subsequently.

[0085] The atomic layer etching process has a high etching selectivity for the transition layer 230 and the initial side wall 221. The atomic layer etching process has a high etching selectivity for the transition layer 230 and the layer to be etched 200, thereby ensuring that while removing the transition layer 230, the etching damage to the initial side wall 221 and the layer to be etched 200 is small, which is beneficial to the stability of pattern transfer.

[0086] The transition layer 230 is removed by an atomic layer etching process. The atomic layer etching process can etch the transition layer 230 at the atomic level, that is, precisely remove the transition layer 230 .

[0087] Please refer to Fig.16 , the initial sidewall 221 is subjected to the modification treatment for multiple times to form a sidewall 240 on the surface of the layer to be etched 200 .

[0088] After multiple modification processes, a sidewall spacer 240 is formed on the to-be-etched layer 200 . The sidewall spacer 240 has a second roughness that is smaller than the first roughness of the initial sidewall spacer 221 .

[0089] The transition layer 230 is formed by modifying the initial sidewall 221. The transition layer 230 can improve the morphology of the top surface of the initial sidewall 221 and the roughness of the sidewall surface of the initial sidewall 221. The transition layer 230 is removed by an atomic layer etching process. The atomic layer etching process can etch the transition layer at the atomic level, that is, accurately remove the transition layer 230, thereby ensuring that the top morphology of the formed sidewall 240 is good and the roughness of the sidewall surface is reduced. In summary, the method can form a sidewall 240 with a good top morphology and a low sidewall surface roughness, thereby improving the performance of the formed semiconductor structure.

[0090] The top of the sidewall 240 has a rounded corner b.

[0091] It should be noted that the rounded corner b means that the side wall 40 has a first side (not shown in the figure) and a second side (not shown in the figure) opposite to each other, and the height of the first side is the same as that of the second side or the difference is small.

[0092] Please refer to Fig.17 After the sidewall 240 is formed, the to-be-etched layer 200 is etched using the sidewall 240 as a mask.

[0093] Since the top of the sidewall 240 has a good morphology and the roughness of the sidewall surface of the sidewall 240 is low, the accuracy of pattern transfer can be improved when the sidewall 240 is used as a mask to etch the layer 200 to be etched.

[0094] In other embodiments, the method for forming the semiconductor structure also includes: after forming the side wall, forming an additional side wall located on the side wall surface of the side wall on the surface of the layer to be etched; after forming the additional side wall, removing the side wall; and etching the layer to be etched using the additional side wall as a mask.

[0095] The method for forming the additional sidewall includes: forming an additional sidewall material film on the surface of the layer to be etched, and the top surface of the sidewall and the sidewall surface; etching back the additional sidewall material film until the top surface of the sidewall and the surface of the layer to be etched are exposed to form the additional sidewall.

[0096] Correspondingly, the embodiment of the present invention further provides a semiconductor structure formed by the above method, please refer to Fig.16 , including: a layer to be etched 200; and a sidewall 240 located on the layer to be etched.

[0097] The top of the sidewall 240 has a rounded corner b.

[0098] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a layer to be etched; forming an initial sidewall spacer on the layer to be etched; The initial sidewall spacer is subjected to at least one modification etching process to form a sidewall spacer on the layer to be etched, wherein the modification etching process comprises: Performing modification treatment on the initial sidewall so that a transition layer is formed on the top surface and the sidewall surface of the initial sidewall; The transition layer is removed by an atomic layer etching process, and the initial sidewall after the transition layer is removed serves as the sidewall; By performing at least one modification etching process on the initial sidewall, the roughness of the sidewall surface of the initial sidewall is reduced.

2. The method for forming a semiconductor structure according to claim 1, wherein: The initial sidewall surface has a first roughness; the sidewall has a second roughness, and the first roughness is greater than the second roughness.

3. The method for forming a semiconductor structure according to claim 1, wherein: The top of the initial sidewall has a top angle, and the top of the sidewall has a rounded corner.

4. The method for forming a semiconductor structure according to claim 1, wherein: The modification process is a plasma treatment process.

5. The method for forming a semiconductor structure according to claim 4, wherein: The material of the initial sidewall is silicon nitride, and the gas used in the modification process includes oxygen.

6. The method for forming a semiconductor structure according to claim 5, wherein: The process parameters of the plasma treatment include: the gases used include O2, Ar and C4H6, the pressure is 10 mTorr to 50 mTorr, the flow range of O2, Ar and C4H6 is 5 standard ml / min to 800 standard ml / min, the RF power is 30 W to 500 W, and the bias power is 10 W to 200 W.

7. The method for forming a semiconductor structure according to any one of claims 1 to 4, characterized in that: The atomic layer etching process includes: performing a passivation process; and performing an etching process after the passivation process.

8. The method for forming a semiconductor structure according to claim 7, wherein: The passivation process includes: using a passivation gas to react with the surface of the transition layer to form a passivation layer on at least a portion of the transition layer; the etching process includes: using an etching gas to react with the passivation layer to remove the passivation layer.

9. The method for forming a semiconductor structure according to claim 8, wherein: The material of the transition layer includes: Si-ON group.

10. The method for forming a semiconductor structure according to claim 9, wherein: The passivation gas includes: fluorocarbon gas; the fluorocarbon gas includes C4F6, CH3F or CHF3.

11. The method for forming a semiconductor structure according to claim 9, wherein: The etching gas includes: Ar or He.

12. The method for forming a semiconductor structure according to claim 9, wherein: The radio frequency bias voltage of the atomic layer etching process ranges from 10 watts to 250 watts.

13. The method for forming a semiconductor structure according to claim 1, wherein: The layer to be etched includes a substrate and a buffer layer located on the surface of the substrate.

14. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the initial side wall includes: forming a plurality of mutually discrete sacrificial layers on the surface of the layer to be etched; forming a side wall material film on the surface of the layer to be etched, as well as on the top and side wall surfaces of the sacrificial layers; etching back the side wall material film until the surface of the layer to be etched and the top surface of the sacrificial layer are exposed to form the initial side wall; after forming the initial side wall, removing the sacrificial layer.

15. The method for forming a semiconductor structure according to claim 14, wherein: The sacrificial layer is formed by a self-aligned multiple patterning process.

16. The method for forming a semiconductor structure according to claim 15, wherein: Also includes: After the sidewalls are formed, the layer to be etched is etched using the sidewalls as a mask.

17. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: After forming the sidewall, forming an additional sidewall on the surface of the to-be-etched layer and located on the sidewall surface of the sidewall; After forming the additional sidewall, removing the sidewall; The layer to be etched is etched using the additional sidewall as a mask.

18. The method for forming a semiconductor structure according to claim 17, wherein: The method for forming the additional sidewall includes: forming an additional sidewall material film on the surface of the layer to be etched, and the top surface of the sidewall and the sidewall surface; etching back the additional sidewall material film until the top surface of the sidewall and the surface of the layer to be etched are exposed to form the additional sidewall.

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