Differential input buffer circuit, differential signal buffer circuit and FPGA chip

Abstract

The embodiment of the present application provides a sub-input buffer circuit, a differential signal buffer circuit and an FPGA chip, which relates to the field of integrated circuit technology and can expand the common mode and differential mode input range. The differential input buffer circuit includes: the differential input circuit includes a first sub-differential input circuit and a second sub-differential input circuit, the first sub-differential input circuit outputs an amplified first current under the control of a first control voltage terminal, and the second sub-differential input circuit outputs an amplified second current under the control of a second control voltage terminal; the differential output circuit includes a first sub-differential output circuit and a second sub-differential output circuit, the first sub-differential output circuit outputs a first level after receiving the first current, and the second sub-differential output circuit outputs a second level after receiving the second current; the first level is opposite to the second level, and the voltage input from the first control voltage terminal to the first sub-differential input circuit and the voltage input from the second control voltage terminal to the second sub-differential input circuit are unequal arbitrary values.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and more specifically, to a differential input buffer circuit, a differential signal buffer circuit and an FPGA chip. Background Art

[0002] The traditional differential signal input circuit is directly implemented using an N-type MOS (metal oxide semiconductor) differential input pair tube or a P-type MOS differential input pair tube. When this type of comparison circuit is used in a high-speed single-ended input standard, the input common-mode level range is limited and is only applicable to inputs of high levels that meet the high voltage threshold or low levels that meet the low voltage threshold.

[0003] For high-speed differential input standards, such as LVDS_25, LVDSEXT_25, HT_25, etc., wider common-mode input range and differential-mode input range are required. Summary of the invention

[0004] The embodiments of the present application provide a differential input buffer circuit, a differential signal buffer circuit and an FPGA chip to improve the above-mentioned problems.

[0005] In a first aspect, a differential input buffer circuit is provided, comprising: a differential input circuit and a differential output circuit. The differential input circuit comprises a first sub-differential input circuit and a second sub-differential input circuit, wherein the first sub-differential input circuit outputs an amplified first current under the control of a first control voltage terminal, and the second sub-differential input circuit outputs an amplified second current under the control of a second control voltage terminal. The differential output circuit comprises a first sub-differential output circuit and a second sub-differential output circuit, wherein the first sub-differential output circuit outputs a first level after receiving the first current, and the second sub-differential output circuit outputs a second level after receiving the second current; wherein the first level is opposite to the second level, and the voltage input from the first control voltage terminal to the first sub-differential input circuit and the voltage input from the second control voltage terminal to the second sub-differential input circuit are unequal arbitrary values.

[0006] In a second aspect, a differential signal buffer circuit is provided, comprising a comparison circuit and the differential input buffer circuit described in the first aspect. The comparison circuit comprises a first input terminal and a second input terminal, the first input terminal receiving a first level input by the first sub-differential output circuit, and the second input terminal receiving a second level input by the second sub-differential output circuit; the comparison circuit is configured to output a comparison result according to the first level and the second level.

[0007] In a third aspect, a FPGA chip is provided, comprising the differential signal buffer circuit described in the second aspect.

[0008] In the differential input buffer circuit, differential signal buffer circuit and FPGA chip provided in the embodiments of the present application, the differential input buffer circuit includes a differential input circuit and a differential output circuit, the differential input circuit includes a first sub-differential input circuit and a second sub-differential input circuit, and the differential output circuit includes a first sub-differential output circuit and a second sub-differential output circuit. The first sub-differential input circuit outputs an amplified first current under the control of the first control voltage terminal IN_N, and then inputs it to the first sub-differential output circuit and outputs it in the form of a large voltage (first level PRE_OUT_N); the second sub-differential input circuit outputs an amplified second current under the control of the second control voltage terminal IN_P, and then inputs it to the second sub-differential output circuit and outputs it in the form of a large voltage (second level PRE_OUT_P). Since the voltage input to the first sub-differential input circuit by the first control voltage terminal IN_N and the voltage of the second sub-differential input circuit by the second control voltage terminal IN_P are not equal, the first level PRE_OUT_N and the second level PRE_OUT_P are amplified to different degrees, and the difference between the first level PRE_OUT_N and the second level PRE_OUT_P increases, and then the first level PRE_OUT_N can be regarded as a high level and the second level PRE_OUT_P as a low level, or the first level PRE_OUT_N can be regarded as a low level and the second level PRE_OUT_P as a high level. In this way, as long as the voltage input to the first sub-differential input circuit by the first control voltage terminal IN_N and the voltage of the second sub-differential input circuit by the second control voltage terminal IN_P are unequal arbitrary values, the differential input buffer circuit of the present application can be used to output the opposite first level PRE_OUT_N and second level PRE_OUT_P, thereby expanding the common mode input range and the differential mode input range. On this basis, the first level PRE_OUT_N and the second level PRE_OUT_P can also be used as the power supply circuit of the next stage circuit to provide the working voltage for the next stage circuit, thereby reducing the power consumption of the entire circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0010] Figure 1 A module relationship diagram of a differential input buffer circuit provided in an embodiment of the present application;

[0011] Figure 2 A circuit diagram of a differential input buffer circuit provided in an embodiment of the present application;

[0012] Figure 3 A module relationship diagram of a differential signal buffer circuit provided in an embodiment of the present application;

[0013] Figure 4 A circuit diagram of a differential signal buffer circuit provided in an embodiment of the present application;

[0014] Figure 5 A circuit diagram of a differential signal buffer circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0015] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations. It should be noted that the features in the embodiments of the present application can be combined with each other without conflict.

[0016] like Figure 1 As shown, the embodiment of the present application provides a differential input buffer circuit, including a differential input circuit 10 and a differential output circuit 20. The differential input circuit 10 includes a first sub-differential input circuit 11 and a second sub-differential input circuit 12. The differential output circuit 20 includes a first sub-differential output circuit 21 and a second sub-differential output circuit 22.

[0017] The first sub-differential input circuit 11 outputs an amplified first current under the control of the first control voltage terminal IN_N, and the first sub-differential output circuit 21 outputs a first level PRE_OUT_N after receiving the first current. The second sub-differential input circuit 12 outputs an amplified second current under the control of the second control voltage terminal IN_P, and the second sub-differential output circuit 22 outputs a second level PRE_OUT_P after receiving the second current.

[0018] The first level PRE_OUT_N is opposite to the second level PRE_OUT_P, and the voltage inputted from the first control voltage terminal IN_N to the first sub-differential input circuit 11 and the voltage inputted from the second control voltage terminal IN_P to the second sub-differential input circuit 12 are unequal arbitrary values.

[0019] Specifically, Figure 2As shown, the first sub-differential input circuit 101 includes a first N-type transistor N1, a first P-type transistor P1, and a second P-type transistor P2, and the second sub-differential input circuit 102 includes a second N-type transistor N2, a third P-type transistor P3, and a fourth P-type transistor P4. The first sub-differential output circuit 201 includes a third N-type transistor N3, and the second sub-differential output circuit 202 includes a fourth N-type transistor N4.

[0020] The gate of the first N-type transistor N1 is electrically connected to the first control voltage terminal IN_N, the first electrode is electrically connected to the gate of the first P-type transistor P1, the gate of the second P-type transistor P2, and the second electrode, and the second electrode is grounded. The gate of the second N-type transistor N2 is electrically connected to the second control voltage terminal IN_P, the first electrode is electrically connected to the gate of the third P-type transistor P3, the gate of the fourth P-type transistor P4, and the second electrode is grounded. The first electrode of the first P-type transistor P1, the first electrode of the second P-type transistor P2, the first electrode of the third P-type transistor P3, and the first electrode of the fourth P-type transistor P4 are connected to the first voltage terminal V1, and the second electrode of the first P-type transistor P1 is electrically connected to the first sub-differential output circuit 201. The second electrode of the third P-type transistor P3 is electrically connected to the second sub-differential output circuit 202. Among them, the voltage of the first voltage terminal V1 is greater than the voltage of the first control voltage terminal IN_N and the second control voltage terminal IN_P.

[0021] The gate and first electrode of the third N-type transistor N3 are electrically connected to the second electrode of the first P-type transistor P1, and the second electrode is grounded. The gate and first electrode of the fourth N-type transistor N4 are electrically connected to the second electrode of the third P-type transistor P3, and the second electrode is grounded.

[0022] Assume that the level of the first control voltage terminal IN_N is a low level, the level of the second control voltage terminal IN_P is a high level, and the voltage input to the first voltage terminal V1 is a large voltage.

[0023] Under the control of the first control voltage terminal IN_N, the first N-type transistor N1 is disconnected, the first P-type transistor P1 and the second P-type transistor P2 are also disconnected, the current does not flow from the first P-type transistor P1 to the third N-type transistor N3, and the current on the third N-type transistor N3 is almost zero. Therefore, the first level PRE_OUT_N output from the third N-type transistor N3 is also zero. At this time, the first level PRE_OUT_N can be regarded as a low level.

[0024] Under the control of the second control voltage terminal IN_P, the second N-type transistor N2 is turned on. Since the second electrode of the second N-type transistor N2 is grounded, there is a tendency to pull the second N-type transistor N2 down. Further, the voltage of the first electrode of the second N-type transistor N2 is reduced. When the voltage of the first electrode of the second N-type transistor N2 is reduced to a low level, the third P-type transistor P3 and the fourth P-type transistor P4 are turned on. The third P-type transistor P3 converts the voltage of the first voltage terminal V1 into a current and sends it to the fourth N-type transistor N4. Since the voltage of the first voltage terminal V1 is a large voltage, the current flowing to the fourth N-type transistor N4 is a large current. The fourth N-type transistor N4 can be equivalent to a resistor. After receiving the large current sent by the third P-type transistor P3, the fourth N-type transistor N4 can output the second level PRE_OUT_P in the form of voltage. At this time, the second level PRE_OUT_P can be regarded as a high level.

[0025] Assuming that the level of the first control voltage terminal IN_N and the level of the second control voltage terminal IN_P are neither high nor low, and the voltage of the first control voltage terminal IN_N is greater than the voltage of the second control voltage terminal IN_P, the voltage input to the first voltage terminal V1 is a large voltage.

[0026] Under the control of the second control voltage terminal IN_N, the first N-type transistor N1 is turned on. Since the second electrode of the first N-type transistor N1 is grounded, there is a tendency to pull the first N-type transistor N1 down. Further, the voltage of the first electrode of the first N-type transistor N1 is reduced. When the voltage of the first electrode of the first N-type transistor N1 is reduced to a low level, the first P-type transistor P1 and the second P-type transistor P2 are turned on. The first P-type transistor P1 converts the voltage of the first voltage terminal V1 into a current and sends it to the third N-type transistor N3. Since the voltage of the first voltage terminal V1 is a large voltage, the current flowing to the third N-type transistor N3 is a large current. The third N-type transistor N3 can be equivalent to a resistor. After receiving the large current sent by the first P-type transistor P1, the third N-type transistor N3 can output the second level PRE_OUT_N in the form of voltage.

[0027] Under the control of the second control voltage terminal IN_P, the second N-type transistor N2 is turned on. Since the second electrode of the second N-type transistor N2 is grounded, there is a tendency to pull the second N-type transistor N2 down. Further, the voltage of the first electrode of the second N-type transistor N2 is reduced. When the voltage of the first electrode of the second N-type transistor N2 is reduced to a low level, the third P-type transistor P3 and the fourth P-type transistor P4 are turned on. The third P-type transistor P3 converts the voltage of the first voltage terminal V1 into a current and sends it to the fourth N-type transistor N4. Since the voltage of the first voltage terminal V1 is a large voltage, the current flowing to the fourth N-type transistor N4 is a large current. The fourth N-type transistor N4 can be equivalent to a resistor. After receiving the large current sent by the third P-type transistor P3, the fourth N-type transistor N4 can output the second level PRE_OUT_P in the form of voltage.

[0028] like Figure 2 As shown, the differential input buffer circuit also includes an eleventh N-type transistor N11, which is turned on under the control of the voltage terminal NN_BIAS. Since the voltage of the first control voltage terminal IN_N is greater than the voltage of the second control voltage terminal IN_P, more current on the eleventh N-type transistor N11 is drawn away by the first N-type transistor N1, and the current of the first N-type transistor N1 is greater than the current of the second N-type transistor N2. Furthermore, the current of the first P-type transistor P1 is greater than the current of the third P-type transistor P3. Compared with the third P-type transistor P3, the first P-type transistor P1 obtains more voltage from the first voltage terminal V2, that is, the first current is greater than the second current. The first current flows to the third N-type transistor N3 and is converted into the first level PRE_OUT_N. The second current flows to the fourth N-type transistor N4 and is converted into the second level PRE_OUT_P. Since the first level PRE_OUT_N and the second level PRE_OUT_P are both amplified levels, the difference between the first level PRE_OUT_N and the second level PRE_OUT_P increases, the first level PRE_OUT_N can be regarded as a high level, and the second level PRE_OUT_P can be regarded as a low level.

[0029] Among them, the voltage of the first voltage terminal V1 is greater than the voltage of the first control voltage terminal IN_N and the second control voltage terminal IN_P. Those skilled in the art should know that for a transistor, the voltage input to the first pole is much larger than the voltage input to the gate. Therefore, the voltage of the first voltage terminal V1 is larger than the voltage of the first control voltage terminal IN_N and the second control voltage terminal IN_P. When the third P-type transistor P3 operates in the saturation region, the voltage of the first voltage terminal V1 can be output in the form of a large current through the first pole and the second pole of the third P-type transistor P3.

[0030] Of course, the level of the first control voltage terminal IN_N can also be a high level, and the level of the second control voltage terminal IN_P can also be a low level. In this case, the first level PRE_OUT_N output by the third N-type transistor N3 is a high level, and the second level PRE_OUT_P output by the fourth N-type transistor N4 is a low level. Alternatively, assume that the levels of the first control voltage terminal IN_N and the second control voltage terminal IN_P are neither high nor low, and the voltage of the first control voltage terminal IN_N is less than the voltage of the second control voltage terminal IN_P. In this case, the first level PRE_OUT_N can be regarded as a low level, and the second level PRE_OUT_P can be regarded as a high level.

[0031] In some embodiments, those skilled in the art usually set a high-level threshold and a low-level threshold. A voltage higher than the high-level threshold is a high level, and a voltage lower than the low-level threshold is a low level. Among them, the high-level threshold and the low-level threshold are not equal. The voltages of the first control voltage terminal IN_N and the second control voltage terminal IN_P of the present application can be either high levels or low levels, or neither high nor low levels.

[0032] In some embodiments, the first pole is the source electrode, and the second pole is the drain electrode; or, the first pole is the drain electrode, and the second pole is the source electrode. As long as the first pole is the input pole and the second pole is the output pole.

[0033] In some embodiments, the first N-type transistor N1, the first P-type transistor P1, and the second P-type transistor P2, and the second sub-differential input circuit 102 includes the second N-type transistor N2, the third P-type transistor P3, and the fourth P-type transistor P4 can be field effect transistors, and the field effect transistors are used to convert the large voltage input from the first voltage terminal V1 into a large current output.

[0034] An embodiment of the present application provides a differential input buffer circuit, including a differential input circuit 10 and a differential output circuit 20. The differential input circuit 10 includes a first sub-differential input circuit 11 and a second sub-differential input circuit 12. The differential output circuit 20 includes a first sub-differential output circuit 21 and a second sub-differential output circuit 22. The first sub-differential input circuit 11 outputs an amplified first current under the control of the first control voltage terminal IN_N, and then inputs it to the first sub-differential output circuit 21 and outputs it in the form of a large voltage (first level PRE_OUT_N); the second sub-differential input circuit 12 outputs an amplified second current under the control of the second control voltage terminal IN_P, and then inputs it to the second sub-differential output circuit 22 and outputs it in the form of a large voltage (second level PRE_OUT_P). Since the voltage input from the first control voltage terminal IN_N to the first sub-differential input circuit 11 and the voltage input from the second control voltage terminal IN_P to the second sub-differential input circuit 12 are not equal, the first level PRE_OUT_N and the second level PRE_OUT_P are amplified to different degrees, and the difference between the first level PRE_OUT_N and the second level PRE_OUT_P increases, so that the first level PRE_OUT_N can be regarded as a high level and the second level PRE_OUT_P as a low level, or the first level PRE_OUT_N can be regarded as a low level and the second level PRE_OUT_P as a high level. In this way, as long as the voltage input from the first control voltage terminal IN_N to the first sub-differential input circuit 11 and the voltage from the second control voltage terminal IN_P to the second sub-differential input circuit 12 are unequal arbitrary values, the differential input buffer circuit of the present application can be used to output opposite first level PRE_OUT_N and second level PRE_OUT_P, thereby expanding the common mode input range and the differential mode input range. On this basis, the first level PRE_OUT_N and the second level PRE_OUT_P can also be used as the power supply circuit of the next stage circuit to provide the working voltage for the next stage circuit, thereby reducing the power consumption of the entire circuit.

[0035] Optional, such as Figure 2 As shown, the first sub-differential output circuit 21 further includes a fifth P-type transistor P5, and the second sub-differential output circuit 22 further includes a sixth P-type transistor P6. The gate of the fifth P-type transistor P5 is electrically connected to the second control voltage terminal V2, the first electrode is electrically connected to the second voltage terminal V2, and the second electrode is electrically connected to the gate and the first electrode of the third N-type transistor N3. The gate of the sixth P-type transistor P6 is electrically connected to the first control voltage terminal V1, the first electrode is electrically connected to the second voltage terminal V2, and the second electrode is electrically connected to the gate and the first electrode of the fourth N-type transistor N4.

[0036] On this basis, the differential input buffer circuit can also include a tenth P-type transistor P10, the gate of the tenth P-type transistor P10 is electrically connected to P_BIAS, the first electrode is electrically connected to the second voltage terminal, and the second electrode is respectively electrically connected to the first electrode of the fifth P-type transistor P5 and the first electrode of the sixth P-type transistor P6.

[0037] Assume that the level of the first control voltage terminal IN_N is a low level, and the level of the second control voltage terminal IN_P is a high level.

[0038] Under the control of the first control voltage terminal IN_N, the sixth P-type transistor P6 is turned on; under the control of the second control voltage terminal IN_P, the fifth P-type transistor P5 is turned off. The voltage on the second voltage terminal V2 (that is, the tenth P-type transistor P10) is all divided by the sixth P-type transistor P6, and after being converted into current by the sixth P-type transistor P6, it is converted into voltage output again by the fourth N-type transistor N4, further increasing the voltage value of the second level PRE_OUT_P, thereby further increasing the difference between the first level PRE_OUT_N and the second level PRE_OUT_P.

[0039] Similarly, when the level of the first control voltage terminal IN_N is high and the level of the second control voltage terminal IN_P is low, the voltage value of the first level PRE_OUT_N can be further increased, thereby further increasing the difference between the first level PRE_OUT_N and the second level PRE_OUT_P.

[0040] Of course, when the level of the first control voltage terminal IN_N and the level of the second control voltage terminal IN_P are neither high level nor low level, the above circuit is also applicable.

[0041] In some embodiments, the voltage input to the second voltage terminal V2 is a large voltage, so that the fifth P-type transistor P5 or the sixth P-type transistor P6 receives more current, and thus the difference between the first level PRE_OUT_N and the second level PRE_OUT_P is larger.

[0042] Optionally, the size of the first N-type transistor N1 is the same as the size of the second N-type transistor N2, the size of the first P-type transistor P1 is the same as the size of the third P-type transistor P3, the size of the second P-type transistor P2 is the same as the size of the fourth P-type transistor P4, and the size of the third N-type transistor N3 is the same as the size of the fourth N-type transistor N4.

[0043] In this way, the first N-type transistor N1 has the same characteristics as the second N-type transistor N2, the first P-type transistor P1 has the same characteristics as the third P-type transistor P3, the second P-type transistor P2 has the same characteristics as the fourth P-type transistor P4, and the third N-type transistor N3 has the same characteristics as the fourth N-type transistor N4, so as to facilitate the adjustment of the differential input buffer circuit.

[0044] like Figure 3 As shown, the present application further provides a differential signal buffer circuit, comprising a comparison circuit 30 and any of the differential input buffer circuits described above.

[0045] The comparison circuit 30 includes a first input terminal and a second input terminal, wherein the first input terminal receives the first level PRE_OUT_N inputted by the first sub-differential output circuit 21, and the second input terminal receives the second level PRE_OUT_P inputted by the second sub-differential output circuit 22. The comparison circuit 30 is configured to output a comparison result according to the first level PRE_OUT_N and the second level PRE_OUT_P.

[0046] Specifically, Figure 4 As shown, the comparison circuit 30 includes a fifth N-type transistor N5, a sixth N-type transistor N6, a seventh N-type transistor N7, an eighth N-type transistor N8, a seventh P-type transistor P7, an eighth P-type transistor P8, a ninth P-type transistor P9, and a first inverter INV_1.

[0047] The gate of the fifth N-type transistor N5 is electrically connected to the gate and the first electrode of the fourth N-type transistor N4, the first electrode is electrically connected to the gate of the eighth P-type transistor P8, the gate of the seventh P-type transistor P7, and the second electrode, and the second electrode is grounded. The gate of the sixth N-type transistor N6 is electrically connected to the gate and the first electrode of the third N-type transistor N3, the first electrode is electrically connected to the first node X, and the second electrode is grounded. The gate of the seventh N-type transistor N7 is electrically connected to the gate and the first electrode of the fourth N-type transistor N4, the first electrode is electrically connected to the second node Y, and the second electrode is grounded. The gate of the eighth N-type transistor N8 is electrically connected to the third control voltage terminal, the first electrode is electrically connected to the first node X, and the second electrode is grounded. The first electrode of the seventh P-type transistor P7 is electrically connected to the third voltage terminal V3. The first electrode of the eighth P-type transistor P8 is electrically connected to the third voltage terminal V3, and the second electrode is electrically connected to the first node X. The gate of the ninth P-type transistor P9 is electrically connected to the first node, the first electrode is electrically connected to the third voltage terminal V3, and the second electrode is electrically connected to the second node Y. An input terminal of the first inverter INV_1 is electrically connected to the second node Y, and the first inverter INV_1 is configured to output a comparison result of the comparison circuit 100 .

[0048] Taking the first level PRE_OUT_N as a low level, the second level PRE_OUT_P as a high level, and the voltage at the third voltage terminal as a large voltage as an example, under the control of the second level PRE_OUT_P, the fifth N-type transistor N5 is turned on. Since the second pole of the fifth N-type transistor N5 is grounded, there is a tendency to pull the fifth N-type transistor N5 down. Further, the voltage at the first pole of the fifth N-type transistor N5 is reduced. When the voltage at the first pole of the fifth N-type transistor N5 is reduced to a low level, the seventh P-type transistor P7 and the eighth P-type transistor P8 are turned on, and the eighth P-type transistor P8 transmits the voltage of the third voltage terminal V3 to the first node X. Although the seventh N-type transistor N7 is turned on under the control of the second level PRE_OUT_P, since the sixth N-type transistor N6 is turned off under the control of the first level PRE_OUT_N, the voltage of the first node is completely drawn away by the gate of the ninth P-type transistor P9, causing the ninth P-type transistor P9 to be turned off, and the voltage input to the second node Y by the ninth P-type transistor P9 drops sharply, and the second node Y is quickly pulled down. However, since the voltage of the second node Y may not be an absolute low level, but just a small voltage value, the voltage of the second node Y can be shaped and inverted by the first inverter INV_1, and the voltage of the second node Y can be shaped into a high level and output.

[0049] Similarly, when the first level PRE_OUT_N is a high level and the second level PRE_OUT_P is a low level, the Y node will be pulled high, and the voltage of the second node Y can be rectified into a low level and output by the first inverter INV_1.

[0050] The embodiment of the present application provides a differential signal buffer circuit, including a comparison circuit 30 and any of the differential input buffer circuits described above. Before using a comparator to compare two voltage values, the input signal can be pre-amplified by the differential input buffer circuit to expand the common mode input range and the differential mode input range. On this basis, the first level PRE_OUT_N and the second level PRE_OUT_P output by the differential input buffer circuit can also be used as a power supply circuit of the comparison circuit 30 to provide an operating voltage for the next stage circuit, thereby reducing the power consumption of the entire differential signal buffer circuit.

[0051] Optional, such as Figure 5 As shown, the comparison circuit 30 further includes a hysteresis circuit, an input end of the hysteresis circuit is electrically connected to the output end of the first inverter INV_1 , and the hysteresis circuit is configured to hysteresis output the comparison result.

[0052] Specifically, Figure 5As shown, the hysteresis circuit includes a second inverter INV_2, a third inverter INV_3, a ninth N-type transistor N9, and a tenth N-type transistor N10. The input terminal L of the second inverter INV_2 is electrically connected to the output terminal of the first inverter INV_1 and the gate of the ninth N-type transistor N9, and the output terminal R is electrically connected to the input terminal of the third inverter INV_3 and the gate of the tenth N-type transistor N10. The third inverter INV_3 is configured to output the comparison result of the comparison circuit 30.

[0053] The first electrode of the ninth N-type transistor is electrically connected to the first electrode (PD_1) of the second N-type transistor N2, and the second electrode is grounded. The first electrode of the tenth N-type transistor N10 is electrically connected to the first electrode (PD_2) of the first N-type transistor N1, and the second electrode is grounded.

[0054] Taking the example that the voltage of the first control voltage terminal IN_N is greater than the voltage of the second control voltage terminal IN_P, the second node is suddenly pulled high, the output terminal L of the first inverter INV_1 is low, and after further passing through the second inverter INV_2, the output terminal R of the second inverter INV_2 is high. Under the action of the output terminal R of the second inverter INV_2, the tenth N-type transistor N10 is turned on; under the action of the output terminal L of the first inverter INV_1, the ninth N-type transistor N9 is turned off. The second inverter INV_2 adds a current to the first electrode of the first N-type transistor N1 through the tenth N-type transistor N10, which is recorded as △I. As long as the voltage of the first control voltage terminal IN_N is greater than the voltage of the second control voltage terminal IN_P, the added current △I always belongs to the first N-type transistor N1. When the voltage of the second control voltage terminal IN_P increases to be equal to the voltage of the first control voltage terminal IN_N, I N4 =0.5I P10 +0.5I N11 , while I N3 =0.5I P10 +0.5I N11 +△I, so the voltage of the second control voltage terminal IN_P needs to be increased by △V corresponding to the applied current △I to make the comparison circuit 30 output the opposite result.

[0055] Where, ΔI=K N9 ×[(V gs_N9 +VCC-V THN9 ) 2 -(V gs_N9 -V TH_N9 ) 2 ], Formula 1.

[0056] ΔI P4 =K P4 ×[(|V gs_P4 |+ΔV-|VTH_P4 |) 2 -(V gs_P4 -V TH_P4 ) 2 ], Formula 2.

[0057] ΔI=ΔI P4 , according to formula 1 and formula 2, we get:

[0058]

[0059] in, W represents the channel width of the transistor, and L represents the channel length of the transistor.

[0060] VCC is the sum of the voltage input to the first control voltage terminal IN_N and the voltage input to the second control voltage terminal IN_P.

[0061] In this way, the user can adjust the ratio of the channel length to the channel width of the ninth N-type transistor N9 according to actual design requirements to adjust the hysteresis amount.

[0062] Similarly, when the voltage of the first control voltage terminal IN_N is less than the voltage of the second control voltage terminal IN_P, the hysteresis amount can be adjusted by adjusting the ratio of the channel length to the channel width of the tenth N-type transistor N10.

[0063] In the embodiment of the present application, by setting a hysteresis circuit, the comparison result can be output with hysteresis, thereby improving the noise tolerance and enhancing the anti-interference ability of the differential signal buffer circuit. For example, before the hysteresis, the noise generates a voltage of 10mV. By setting a certain hysteresis amount, the noise tolerance can be increased to 70mV. In this way, the 70mV noise tolerance can neutralize the 10mV noise.

[0064] The present application also provides an FPGA chip, comprising the differential signal buffer circuit described in any of the above embodiments. For its explanation and beneficial effects, reference may be made to the above embodiments.

[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A differential input buffer circuit, It is characterized in that include: A differential input circuit, comprising a first sub-differential input circuit and a second sub-differential input circuit, wherein the first sub-differential input circuit outputs an amplified first current under the control of a first control voltage terminal, and the second sub-differential input circuit outputs an amplified second current under the control of a second control voltage terminal; A differential output circuit, comprising a first sub-differential output circuit and a second sub-differential output circuit, wherein the first sub-differential output circuit outputs a first level after receiving the first current, and the second sub-differential output circuit outputs a second level after receiving the second current; Wherein, the first level is opposite to the second level, and the voltage input from the first control voltage terminal to the first sub-differential input circuit and the voltage input from the second control voltage terminal to the second sub-differential input circuit are unequal arbitrary values; The first sub-differential input circuit includes a first N-type transistor, a first P-type transistor, and a second P-type transistor, and the second sub-differential input circuit includes a second N-type transistor, a third P-type transistor, and a fourth P-type transistor; The gate of the first N-type transistor is electrically connected to the first control voltage terminal, the first electrode is electrically connected to the gate of the first P-type transistor, the gate of the second P-type transistor and the second electrode, and the second electrode is grounded; The gate of the second N-type transistor is electrically connected to the second control voltage terminal, the first electrode is electrically connected to the gate of the third P-type transistor, the gate of the fourth P-type transistor and the second electrode, and the second electrode is grounded; The first electrode of the first P-type transistor, the first electrode of the second P-type transistor, the first electrode of the third P-type transistor, and the first electrode of the fourth P-type transistor are electrically connected to the first voltage terminal; The second electrode of the first P-type transistor is electrically connected to the first sub-differential output circuit; The second electrode of the third P-type transistor is electrically connected to the second sub-differential output circuit; Wherein, the voltage of the first voltage terminal is greater than the voltage of the first control voltage terminal and the voltage of the second control voltage terminal; The differential input buffer circuit also includes an eleventh N-type transistor, a gate of the eleventh N-type transistor is connected to the bias voltage terminal, a first electrode of the eleventh N-type transistor is connected to the second electrode of the first N-type transistor and the second electrode of the second N-type transistor, and a second electrode of the eleventh N-type transistor is grounded.

2. The differential input buffer circuit according to claim 1, It is characterized in that The first sub-differential output circuit includes a third N-type transistor, and the second sub-differential output circuit includes a fourth N-type transistor; The gate and the first electrode of the third N-type transistor are electrically connected to the second electrode of the first P-type transistor, and the second electrode is grounded; The gate and the first electrode of the fourth N-type transistor are electrically connected to the second electrode of the third P-type transistor, and the second electrode is grounded.

3. The differential input buffer circuit according to claim 2, It is characterized in that The first sub-differential output circuit further includes a fifth P-type transistor, and the second sub-differential output circuit further includes a sixth P-type transistor; The gate of the fifth P-type transistor is electrically connected to the second control voltage terminal, the first electrode is electrically connected to the second voltage terminal, and the second electrode is electrically connected to the gate and the first electrode of the third N-type transistor; The gate of the sixth P-type transistor is electrically connected to the first control voltage terminal, the first electrode is electrically connected to the second voltage terminal, and the second electrode is electrically connected to the gate and the first electrode of the fourth N-type transistor.

4. The differential input buffer circuit according to any one of claims 2 to 3, It is characterized in that The size of the first N-type transistor is the same as that of the second N-type transistor, the size of the first P-type transistor is the same as that of the third P-type transistor, the size of the second P-type transistor is the same as that of the fourth P-type transistor, and the size of the third N-type transistor is the same as that of the fourth N-type transistor.

5. A differential signal buffer circuit, It is characterized in that A differential input buffer circuit comprising a comparison circuit and any one of claims 1 to 4; The comparison circuit comprises a first input terminal and a second input terminal, the first input terminal receiving a first level input by the first sub-differential output circuit, and the second input terminal receiving a second level input by the second sub-differential output circuit; The comparison circuit is configured to output a comparison result according to the first level and the second level.

6. The differential signal buffer circuit according to claim 5, It is characterized in that In the case where the first sub-differential output circuit includes a third N-type transistor and the second sub-differential output circuit includes a fourth N-type transistor, the comparison circuit further includes a fifth N-type transistor, a sixth N-type transistor, a seventh N-type transistor, an eighth N-type transistor, a seventh P-type transistor, an eighth P-type transistor, a ninth P-type transistor, and a first inverter; The gate of the fifth N-type transistor is electrically connected to the gate of the fourth N-type transistor and a first electrode, the first electrode is electrically connected to the gate of the eighth P-type transistor, the gate of the seventh P-type transistor and a second electrode, and the second electrode is grounded; The gate of the sixth N-type transistor is electrically connected to the gate of the third N-type transistor and a first electrode, the first electrode is electrically connected to the first node, and the second electrode is grounded; The gate of the seventh N-type transistor is electrically connected to the gate of the fourth N-type transistor and a first electrode, the first electrode is electrically connected to the second node, and the second electrode is grounded; The gate of the eighth N-type transistor is electrically connected to the third control voltage terminal, the first electrode is electrically connected to the first node, and the second electrode is grounded; The first electrode of the seventh P-type transistor is electrically connected to the third voltage terminal; A first electrode of the eighth P-type transistor is electrically connected to the third voltage terminal, and a second electrode is electrically connected to the first node; The gate of the ninth P-type transistor is electrically connected to the first node, the first electrode is electrically connected to the third voltage terminal, and the second electrode is electrically connected to the second node; An input terminal of the first inverter is electrically connected to the second node, and the first inverter is configured to output a comparison result of the comparison circuit.

7. The differential signal buffer circuit according to claim 6, It is characterized in that The comparison circuit further includes a hysteresis circuit, an input end of the hysteresis circuit is electrically connected to an output end of the first inverter, and the hysteresis circuit is configured to output the comparison result with hysteresis.

8. The differential signal buffer circuit according to claim 7, It is characterized in that The hysteresis circuit includes a second inverter, a third inverter, a ninth N-type transistor, and a tenth N-type transistor; the input end of the second inverter is electrically connected to the output end of the first inverter and the gate of the ninth N-type transistor, and the output end is electrically connected to the input end of the third inverter and the gate of the tenth N-type transistor; The third inverter is configured to output a comparison result of the comparison circuit; A first electrode of the ninth N-type transistor is electrically connected to the first electrode of the second N-type transistor, and a second electrode is grounded; A first electrode of the tenth N-type transistor is electrically connected to the first electrode of the first N-type transistor, and a second electrode is grounded.

9. An FPGA chip, It is characterized in that The differential signal buffer circuit comprises the differential signal buffer circuit as described in any one of claims 5 to 8.

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