Display panel and display device

Abstract

The present invention discloses a display panel and a display device, which relate to the field of display technology. The display panel comprises: a driving circuit, the driving circuit comprises N-stage shift registers cascaded to each other, N≥2; the shift register comprises: a first control unit, a second control unit and a third control unit; the third control unit is used to receive a first voltage signal and a second voltage signal, and in response to a signal of a second node and a signal of a third node, control an output signal, the third node is connected to the first node, the first voltage signal is a high-level signal, and the second voltage signal is a low-level signal; wherein the second control unit comprises an adjustment unit, and the adjustment unit is used to maintain the low-level signal of the first node when the signal of the first node and the signal of the third node are both low-level signals and the second clock signal is a low-level signal. The present invention solves the problem of unstable output signal of the driving circuit in the prior art.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and more particularly, to a display panel and a display device. Background Art

[0002] At present, display technology is widely used in televisions, mobile phones and public information display, bringing great convenience to people's daily life and work. In the prior art, a display panel used to display images needs to use a scanning driving circuit to provide a driving signal to a pixel circuit to control the display panel to implement the scanning function, so that the image data input to the display panel can be refreshed in real time, thereby realizing dynamic display.

[0003] However, the output signal of the existing scan driving circuit is unstable, which affects the display effect. Summary of the invention

[0004] In view of this, the present invention provides a display panel and a display device to solve the problem of unstable output signals of a driving circuit in the prior art.

[0005] The present invention provides a display panel, comprising: a driving circuit, the driving circuit comprising N-stage shift registers cascaded to each other, N≥2; the shift register comprising: a first control unit, the first control unit is used to receive an input signal and control a signal of a first node in response to a first clock signal; a second control unit, the second control unit is used to receive a first voltage signal and a second voltage signal, and control the signal of the second node in response to the signal of the first node, the first clock signal, and the second clock signal; a third control unit, the third control unit is used to receive the first voltage signal and the second voltage signal, and control an output signal in response to the signal of the second node and the signal of the third node, the third node is connected to the first node, the first voltage signal is a high-level signal, and the second voltage signal is a low-level signal; wherein the second control unit comprises an adjusting unit, the adjusting unit is used to maintain the low-level signal of the first node when the signal of the first node and the signal of the third node are both low-level signals and the second clock signal is a low-level signal.

[0006] Based on the same concept, the present invention further provides a display device, which includes the above-mentioned display panel.

[0007] Compared with the prior art, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0008] In the display panel provided by the present invention, the second control unit includes an adjusting unit, which is used to maintain the low level signal of the first node when the signal of the first node and the signal of the third node are both low level signals and the second clock signal is a low level signal, thereby maintaining the low level signal of the third node, thereby improving the stability of the output signal generated by the third control unit, thereby improving the stability of the signal output by the driving circuit.

[0009] Of course, any product implementing the present invention does not necessarily need to achieve all of the above-mentioned technical effects at the same time.

[0010] Further features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0012] Figure 1 It is a circuit diagram of a shift register in the prior art;

[0013] Figure 2 yes Figure 1 A driving timing diagram of the shift register;

[0014] Figure 3 is a plan view schematic diagram of a display panel provided by the present invention;

[0015] Figure 4 It is a structural schematic diagram of a driving circuit provided by the present invention;

[0016] Figure 5 It is a schematic diagram of the framework structure of a shift register provided by the present invention;

[0017] Figure 6 It is a schematic diagram of the framework structure of another shift register provided by the present invention;

[0018] Figure 7 It is a schematic diagram of the framework structure of another shift register provided by the present invention;

[0019] Figure 8 It is a circuit diagram of another shift register provided by the present invention;

[0020] Fig. 9 It is a circuit diagram of another shift register provided by the present invention;

[0021] Fig.10 It is a circuit diagram of another shift register provided by the present invention;

[0022] Fig.11 It is a circuit diagram of another shift register provided by the present invention;

[0023] Fig.12 It is a circuit diagram of another shift register provided by the present invention;

[0024] Fig.13 It is a driving timing diagram of the shift register provided by the present invention;

[0025] Fig.14 is another driving timing diagram of the shift register provided by the present invention;

[0026] Fig.15 It is another driving timing diagram of the shift register provided by the present invention;

[0027] Fig.16 It is a plan schematic diagram of a display device provided by the present invention. DETAILED DESCRIPTION

[0028] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless otherwise specifically stated.

[0029] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0030] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0031] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0032] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0033] In order to solve the problem of unstable output signal of the driving circuit in the display panel, the inventors conducted the following research: Figure 1 It is a circuit diagram of a shift register in the prior art. Figure 2 yes Figure 1 The driving timing diagram of the shift register is shown in FIG. Figure 1 and Figure 2In the T1 period, the input signal IN is at a high level, the clock signal CK is at a low level, the transistor M13 is turned on, the input signal IN is transmitted to the first node N1, so that the first node N1 is at a high level, the transistor M12 is turned on, the potential of the first node N1 is transmitted to the third node N3, the third node N3 is at a high level, the transistor M6 is turned on, the fourth node N4 is at a low level, the transistor M3 is turned on, the fifth node N5 is at a high level, the clock signal XCK is at a high level, the second node N2 remains at a high level, and the output signal OUT remains at a low level.

[0034] During the T2 period, the input signal IN is at a high level, the clock signal CK is at a high level, the transistor M13 is turned off, the first node N1 remains at a high level, the transistor M12 is turned on, the potential of the first node N1 is transmitted to the third node N3, the third node N3 remains at a high level, the transistor M6 is turned off, the fourth node N4 remains at a low level, the transistor M3 is turned on, the fifth node N5 is at a high level, the clock signal XCK is at a low level, the second node N2 becomes a low level, and the output signal OUT outputs a high level.

[0035] During the T3 period, the input signal IN is at a high level, the clock signal CK is at a low level, the transistor M13 is turned on, the input signal IN is transmitted to the first node N1, so that the first node N1 is at a high level, the transistor M12 is turned on, the potential of the first node N1 is transmitted to the third node N3, the third node N3 is at a high level, the transistor M6 is turned on, the fourth node N4 is at a low level, the transistor M3 is turned on, the fifth node N5 is at a high level, the clock signal XCK is at a high level, the second node N2 remains at a low level, and the output signal OUT remains at a high level.

[0036] During the T4 period, the input signal IN is at a low level, the clock signal CK is at a high level, the transistor M13 is turned off, the first node N1 remains at a high level, the transistor M12 is turned on, the potential of the first node N1 is transmitted to the third node N3, the third node N3 remains at a high level, the transistor M6 is turned off, the fourth node N4 remains at a low level, the transistor M3 is turned on, the fifth node N5 is at a high level, the clock signal XCK is at a low level, the second node N2 becomes a low level, and the output signal OUT maintains an output high level.

[0037] During the T5 period, the input signal IN is at a low level, the clock signal CK is at a low level, the transistor M13 is turned on, the input signal IN is transmitted to the first node N1, so that the first node N1 is at a low level, the transistor M12 is turned on, the potential of the first node N1 is transmitted to the third node N3, the third node N3 is at a low level, the transistor M6 is turned on, the fourth node N4 is at a low level, the transistor M3 is turned on, the fifth node N5 is at a high level, the clock signal XCK is at a high level, the transistor M10 is turned on, the second node N2 is at a high level, and the output signal OUT maintains an output low level.

[0038] During the T6 period, the input signal IN is at a low level, the clock signal CK is at a high level, the transistor M13 is turned off, the first node N1 remains at a low level, the transistor M12 is turned on, the potential of the first node N1 is transmitted to the third node N3, the third node N3 remains at a low level, the transistor M6 is turned off, the seventh transistor M7 is turned on, the fourth node N4 is at a high level, the transistor M3 is turned on, the fifth node N5 is at a high level, the clock signal XCK is at a low level, the second node N2 becomes a high level, and the output signal OUT maintains an output low level.

[0039] Since in the T5 period, the clock signal CK is at a low level, the clock signal XCK is at a high level, the first node N1 is at a low level, the transistor M1 is turned off, the transistor M3 is turned on, and the fifth node N5 is at a high level. In the T6 period, the clock signal CK is at a high level, the clock signal XCK is at a low level, the transistor M3 is turned off, the transistor M13 is turned off, the first node N1 and the fifth node N5 are both floating nodes, the transistor M1 is turned on, and the charge is turned on at the first node N1 and the fifth node N5. Since the first node N1 is at a low level and the fifth node N5 is at a high level, the first node N1 pulls down the potential of the fifth node N5, and the fifth node N5 raises the potential of the first node N1. The rise of the potential of the first node N1 will cause the potential of the third node N3 to rise, thereby affecting the state of the transistor M15, thereby causing the problem of unstable output signal OUT.

[0040] Based on the above research, the present application provides a display panel and a display device, which solves the problem of unstable output signals of the driving circuit in the prior art. The display panel with the above technical effects provided by the present application is described in detail as follows:

[0041] Figure 3 is a schematic plan view of a display panel provided by the present invention, with reference to Figure 3 This embodiment provides a display panel, including: a driving circuit 100 and a plurality of pixels 200, each pixel 200 is provided with a pixel circuit 210. The driving circuit 100 is connected to the pixel circuit 210 through a signal line to provide a driving signal to the pixel circuit 210, so that the pixel circuit 210 drives the pixel 200 to emit light and display a picture.

[0042] It should be noted that Figure 3 In the following, only one display panel structure is used as an example for explanation. Figure 3 It is exemplarily shown that the driving circuit 200 is located on one side of the display panel. In other embodiments of the present invention, the driving circuit 200 may also be located on both sides of the display panel, which will not be described in detail herein.

[0043] Figure 4is a schematic diagram of the structure of a driving circuit provided by the present invention, Figure 5 is a schematic diagram of the framework structure of a shift register provided by the present invention, with reference to Figure 4 and Figure 5 In the embodiment of the present invention, the driving circuit 100 in the display panel includes N stages of shift registers 110 cascaded to each other, where N≥2;

[0044] The shift register 110 in the driving circuit 100 includes a first control unit 10 , a second control unit 20 and a third control unit 30 .

[0045] The first control unit 10 is used to receive an input signal IN and control a signal of the first node N1 in response to a first clock signal CK;

[0046] The second control unit 20 is used to receive the first voltage signal VGH and the second voltage signal VGL, and control the signal of the second node N2 in response to the signal of the first node N1, the first clock signal CK, and the second clock signal XCK;

[0047] The third control unit 30 is used to receive the first voltage signal VGH and the second voltage signal VGL, and in response to the signal of the second node N2 and the signal of the third node N3, controls the output signal OUT, the third node N3 is connected to the first node N1, the first voltage signal VGH is a high level signal, and the second voltage signal VGL is a low level signal.

[0048] The second control unit 20 includes an adjusting unit 230, which is used to maintain the low level signal of the first node N1 when the signal of the first node N1 and the signal of the third node N3 are both low level signals and the second clock signal XCK is a low level signal, thereby maintaining the low level signal of the third node N3, which can improve the stability of the output signal OUT generated by the third control unit 30, thereby improving the stability of the signal output by the driving circuit 100.

[0049] Figure 6 is a schematic diagram of the framework structure of another shift register provided by the present invention, referring to Figure 6 In some optional embodiments, the second control unit 20 includes a first sub-control unit 21, a second sub-control unit 22 and a third sub-control unit 23.

[0050] The first sub-control unit 21 is used to at least receive the second voltage signal VGL, and control the signal of the fourth node N4 in response to the first clock signal CK and the signal of the first node N1;

[0051] The second sub-control unit 22 is used to receive the first voltage signal VGH and the signal of the fourth node N4, and control the signal of the second node N2 in response to the second clock signal XCK and the signal of the first node N1;

[0052] The third sub-control unit 23 is connected between the first voltage signal VGH and the first node N1 , and the third sub-control unit 23 includes a regulating unit 230 .

[0053] Figure 7 is a schematic diagram of the framework structure of another shift register provided by the present invention, referring to Figure 7 In some optional embodiments, the third sub-control unit 23 includes a first transistor M1, a source of the first transistor M1 is connected to the fifth node N5, and a drain is connected to the first node N1, wherein the fifth node N5 is coupled to the first voltage signal VGH. It can be understood that the fifth node N5 can be directly connected to the first voltage signal VGH, and a transistor can also be arranged between the fifth node N5 and the first voltage signal VGH, and the fifth node N5 is connected to the first voltage signal VGH through the transistor.

[0054] The regulating unit 230 in the third sub-control unit 23 is used to control the signal of the fifth node N5, or to control the turning on and off of the first transistor M1, so as to achieve that when the signal of the first node N1 and the signal of the third node N3 are both low-level signals and the second clock signal XCK is a low-level signal, the low-level signal of the first node N1 is maintained.

[0055] Figure 8 is a circuit diagram of another shift register provided by the present invention, referring to Figure 8 In some optional embodiments, the regulating unit 230 is used to control the first transistor M1 to remain turned off when the signal at the first node N1 and the signal at the third node N3 are both low-level signals, the first clock signal CK is a high-level signal, and the second clock signal XCK is a low-level signal, thereby achieving the goal of maintaining the low-level signal of the first node N1 when the signal at the first node N1 and the signal at the third node N3 are both low-level signals and the second clock signal XCK is a low-level signal.

[0056] Continue to refer Figure 8 In some optional embodiments, when the signal at the first node N1 and the signal at the third node N3 are both low-level signals, the first clock signal CK is a high-level signal, the second clock signal XCK is a low-level signal, and the signal at the fourth node N4 is a high-level signal, the adjustment unit 230 is used to receive the second clock signal XCK, and in response to the signal at the fourth node N4, control the gate potential of the first transistor M1, thereby controlling the first transistor M1 to remain turned off.

[0057] In some optional embodiments, the first transistor M1 is a PMOS transistor, and when the gate of the first transistor M1 receives a high-level signal, the first transistor M1 remains off. It should be noted that, in this embodiment, the first transistor M1 is exemplarily shown as a PMOS transistor, and in other embodiments of the present invention, the first transistor M1 may also be an NMOS transistor, and when the gate of the first transistor M1 receives a low-level signal, the first transistor M1 remains off.

[0058] Continue to refer Figure 8 In some optional embodiments, the regulating unit 230 includes a second transistor M2, a gate of the second transistor M2 is connected to the fourth node N4, a source is used to receive the second clock signal XCK, and a drain is connected to the gate of the first transistor M1.

[0059] When the signal of the first node N1 and the signal of the third node N3 are both low-level signals, the first clock signal CK is a high-level signal, and the second clock signal XCK is a low-level signal, the signal of the fourth node N4 is a high-level signal, and the second transistor M2 is controlled to be turned off. The low-level signal of the second clock signal XCK cannot be transmitted to the gate of the first transistor M1, and the gate of the first transistor M1 maintains a high-level signal, thereby controlling the first transistor M1 to remain turned off.

[0060] Continue to refer Figure 8 In some optional embodiments, the fifth node N5 is directly connected to the first voltage signal VGH, that is, the signal of the fifth node N5 is maintained as the first voltage signal VGH for a long time, and the signal of the first node N1 and the signal of the third node N3 are both low-level signals, the first clock signal CK is a high-level signal, and the second clock signal XCK is a low-level signal. The first node N1 is a low-level signal, and the first transistor M1 is controlled to remain turned off, thereby avoiding the first voltage signal VGH from interfering with the signal of the first node N1, so that the first node N1 maintains a low-level signal.

[0061] Fig. 9 is a circuit diagram of another shift register provided by the present invention, referring to Fig. 9 In some optional embodiments, the third sub-control unit 23 includes a third transistor M3, a source of the third transistor M3 is connected to the first voltage signal VGH, a drain is connected to the fifth node N5, and a gate is coupled to the fourth node N4. When the signal of the fourth node N4 is a low-level signal, the third transistor M3 is turned on, and the first voltage signal VGH is transmitted to the fifth node N5.

[0062] When the signal of the first node N1 and the signal of the third node N3 are both low-level signals, the first clock signal CK is a high-level signal, and the second clock signal XCK is a low-level signal, the first node N1 is a low-level signal, and the fifth node N5 is the first voltage signal VGH, and the first transistor M1 is controlled to remain turned off, thereby preventing the first voltage signal VGH from interfering with the signal of the first node N1, so that the first node N1 maintains a low-level signal.

[0063] Fig.10 is a circuit diagram of another shift register provided by the present invention, referring to Fig.10 In some optional embodiments, the third sub-control unit 23 includes a fourth transistor M4, a source of the fourth transistor M4 is connected to the fourth node N4, a gate is connected to the second clock signal XCK, and a drain is connected to the gate of the third transistor M3. When the second clock signal XCK is a high-level signal, the fourth transistor M4 is turned off, and the low-level signal of the fourth node N4 cannot be transmitted to the third transistor M3. The third transistor M3 is turned off, so that the first voltage signal VGH cannot be transmitted to the fifth node N5.

[0064] When the signal of the first node N1 and the signal of the third node N3 are both low-level signals, the first clock signal CK is a high-level signal, and the second clock signal XCK is a low-level signal, the first node N1 is a low-level signal, and the first transistor M1 is controlled to remain turned off, further preventing the first voltage signal VGH from interfering with the signal of the first node N1 through the fifth node N5, so that the first node N1 maintains a low-level signal.

[0065] Fig.11 is a circuit diagram of another shift register provided by the present invention, referring to Fig.11 In some optional embodiments, the regulating unit 230 is used to control the disconnection between the fifth node N5 and the first voltage signal VGH when the signal at the first node N1 and the signal at the third node N3 are both low-level signals, the first clock signal CK is a low-level signal, and the second clock signal XCK is a high-level signal, so that the first voltage signal VGH cannot be transmitted to the fifth node N5.

[0066] Therefore, when the signal at the first node N1 and the signal at the third node N3 are both low-level signals, the first clock signal CK is a high-level signal, and the second clock signal XCK is a low-level signal, the first node N1 is a low-level signal, thereby preventing the first voltage signal VGH from interfering with the signal at the first node N1 through the fifth node N5, so that the first node N1 maintains a low-level signal.

[0067] Continue to refer Fig.11In some optional embodiments, the third sub-control unit 23 includes a third transistor M3, a source of the third transistor M3 is connected to the first voltage signal VGH, a drain is connected to the fifth node N5, and a gate is coupled to the adjustment unit 230. The adjustment unit 230 is used to receive a signal from the fourth node N4 and control the gate potential of the third transistor M3 in response to the second clock signal XCK.

[0068] When the signal of the first node N1 and the signal of the third node N3 are both low-level signals, the first clock signal CK is a low-level signal, and the second clock signal XCK is a high-level signal, the regulating unit 230 is turned off, the low-level signal of the fourth node N4 cannot be transmitted to the gate of the third transistor M3, so that the third transistor M3 is turned off, and the first voltage signal VGH cannot be transmitted to the fifth node N5.

[0069] Therefore, when the signal at the first node N1 and the signal at the third node N3 are both low-level signals, the first clock signal CK is a high-level signal, and the second clock signal XCK is a low-level signal, the first node N1 is a low-level signal, and the high level of the fourth node N4 is transmitted to the gate of the third transistor M3, thereby controlling the third transistor M3 to be turned off, preventing the first voltage signal VGH from interfering with the signal of the first node N1 through the fifth node N5, so that the first node N1 maintains a low-level signal.

[0070] Continue to refer Fig.11 In some optional embodiments, the regulating unit 230 includes a fourth transistor M4, a source of the fourth transistor M4 is connected to the fourth node N4, a gate is connected to the second clock signal XCK, and a drain is connected to the gate of the third transistor M3.

[0071] When the signal of the first node N1 and the signal of the third node N3 are both low-level signals, the first clock signal CK is a low-level signal, and the second clock signal XCK is a high-level signal, the fourth transistor M4 is turned off, and the low-level signal of the fourth node N4 cannot be transmitted to the gate of the third transistor M3, so that the third transistor M3 is turned off, and the first voltage signal VGH cannot be transmitted to the fifth node N5.

[0072] Therefore, when the signal at the first node N1 and the signal at the third node N3 are both low-level signals, the first clock signal CK is a high-level signal, and the second clock signal XCK is a low-level signal, the first node N1 is a low-level signal, the fourth transistor M4 is turned on, and the high level of the fourth node N4 is transmitted to the gate of the third transistor M3, thereby controlling the third transistor M3 to be turned off, preventing the first voltage signal VGH from interfering with the signal of the first node N1 through the fifth node N5, so that the first node N1 maintains a low-level signal.

[0073] Continue to refer Fig.11, the third transistor M3 and the fourth transistor M4 are both PMOS transistors. It should be noted that in other embodiments of the present invention, the third transistor M3 and the fourth transistor M4 may also be NMOS transistors, and the corresponding control signals are also changed accordingly.

[0074] Fig.12 is a circuit diagram of another shift register provided by the present invention, referring to Fig.12 In some optional embodiments, the regulating unit 230 is used to control the signal of the fifth node N5 to be a low level signal when the signal of the first node N1 and the signal of the third node N3 are both low level signals and the first clock signal CK is a high level signal.

[0075] Therefore, when the signal at the first node N1 and the signal at the third node N3 are both low-level signals, the first clock signal CK is a high-level signal, and the second clock signal XCK is a low-level signal, the first node N1 is a low-level signal, avoiding interference with the signal of the first node N1 when the fifth node N5 is a high-level signal, so that the first node N1 maintains a low-level signal.

[0076] Continue to refer Fig.12 In some optional embodiments, the third sub-control unit 23 includes a third transistor M3, a source of the third transistor M3 is connected to the first voltage signal VGH, a drain is connected to the fifth node N5, and a gate is coupled to the fourth node N4. The adjustment unit 230 is used to receive the second voltage signal VGL and control the signal of the fifth node N5 in response to the signal of the fourth node N4.

[0077] Thus, when the signal at the first node N1 and the signal at the third node N3 are both low-level signals, the first clock signal CK is a high-level signal, and the second clock signal XCK is a low-level signal, the first node N1 is a low-level signal, and the fourth node N4 is a high-level signal, the adjustment unit 230 controls the signal at the fifth node N5 to be a low-level signal, and the high level of the fourth node N4 is transmitted to the gate of the third transistor M3, controlling the third transistor M3 to be turned off, preventing the first voltage signal VGH from being transmitted to the fifth node N5, so that the fifth node N5 maintains a low-level signal and the first node N1 maintains a low-level signal.

[0078] The switching on and off of the regulating unit 230 is controlled by the signal of the fourth node N4. In some optional embodiments, when the signal of the fourth node N4 is a high-level signal, the regulating unit 230 is turned on, and when the signal of the fourth node N4 is a low-level signal, the regulating unit 230 is turned off.

[0079] Continue to refer Fig.12In some optional embodiments, the regulating unit 230 includes a fifth transistor M5, a source of the fifth transistor M5 is connected to the second voltage signal VGL, a drain is connected to the fifth node N5, and a gate is connected to the fourth node N4.

[0080] When the signal of the first node N1 and the signal of the third node N3 are both low-level signals, the first clock signal CK is a high-level signal, and the second clock signal XCK is a low-level signal, the first node N1 is a low-level signal, the fourth node N4 is a high-level signal, the fifth transistor M5 is turned on, the second voltage signal VGL is transmitted to the fifth node N5, and the high level of the fourth node N4 is transmitted to the gate of the third transistor M3, and the third transistor M3 is controlled to be turned off, so as to prevent the first voltage signal VGH from being transmitted to the fifth node N5, so that the fifth node N5 maintains the second voltage signal VGL, so that the fifth node N5 will not pull up the signal of the first node N1, so that the first node N1 maintains a low-level signal.

[0081] In some optional embodiments, the first transistor M1 and the third transistor M3 are both PMOS transistors, and the fifth transistor M5 is an NMOS transistor.

[0082] It should be noted that, in other embodiments of the present invention, the third transistor M1, the third transistor M3 and the fifth transistor M5 may also be other transistors, and correspondingly, the control signals of the third transistor M1, the third transistor M3 and the fifth transistor M5 are also changed accordingly.

[0083] Based on any of the above embodiments, Figures 8 to 12 As shown, optionally, the first sub-control unit 21 includes a sixth transistor M6 and a seventh transistor M7.

[0084] The source of the sixth transistor M6 is connected to the second voltage signal VGL, the drain is connected to the fourth node N4, and the gate is connected to the first clock signal CK; the source of the seventh transistor M7 is connected to the first clock signal CK, the drain is connected to the fourth node N4, and the gate is connected to the first node N1.

[0085] The second sub-control unit 22 includes an eighth transistor M8, a ninth transistor M9, a tenth transistor M10 and a first capacitor C1.

[0086] Among them, the source of the eighth transistor M8 is connected to the second clock signal XCK, the drain is connected to the sixth node N6, and the gate is connected to the fourth node N4; the source of the ninth transistor M9 is connected to the sixth node N6, the drain is connected to the second node N2, and the gate is connected to the second clock signal XCK; the source of the tenth transistor M10 is connected to the first voltage signal VGH, the drain is connected to the second node N2, and the gate is connected to the first node N1; the first plate of the first capacitor C1 is connected to the fourth node N4, and the second plate is connected to the sixth node N6.

[0087] Based on any of the above embodiments, Figures 8 to 12 As shown, optionally, the second sub-control unit 22 further includes an eleventh transistor M11 and a twelfth transistor M12.

[0088] Among them, the source of the eleventh transistor M11 is connected to the fourth node N4, the drain is connected to the gate of the eighth transistor M8, and the gate is connected to the second voltage signal VGL; the source of the twelfth transistor M12 is connected to the first node N1, the drain is connected to the third node N3, and the gate is connected to the second voltage signal VGL.

[0089] Based on any of the above embodiments, Figures 8 to 12 As shown, optionally, the first control unit 10 includes a thirteenth transistor M13, wherein the source of the thirteenth transistor M13 is connected to the input signal IN, the drain is connected to the first node N1, and the gate is connected to the first clock signal CK.

[0090] The third control unit 30 includes a fourteenth transistor M14, a fifteenth transistor M15, a second capacitor C2 and a third capacitor C3.

[0091] Among them, the source of the fourteenth transistor M14 is connected to the first voltage signal VGH, the drain is connected to the output signal OUT, and the gate is connected to the second node N2; the source of the fifteenth transistor M15 is connected to the second voltage signal VGL, the drain is connected to the output signal OUT, and the gate is connected to the third node N3; the first plate of the second capacitor C2 is connected to the first voltage signal VGH, and the second plate is connected to the second node N2; the first plate of the third capacitor C3 is connected to the third node N3, and the second plate is connected to the second voltage signal VGH or the output signal OUT.

[0092] The working process of the shift register of the present invention is described below in conjunction with the timing diagram of each signal in the shift register.

[0093] Fig.13 This is a driving timing diagram of the shift register provided by the present invention. Figure 8 and Fig.13 .

[0094] During the T1 period, the input signal IN is at a high level, the first clock signal CK is at a low level, the thirteenth transistor M13 is turned on, and the input signal IN is transmitted to the first node N1, so that the first node N1 is at a high level; the twelfth transistor M12 is turned on, and the potential of the first node N1 is transmitted to the third node N3, and the third node N3 is at a high level; the sixth transistor M6 is turned on, and the second voltage signal VGL is transmitted to the fourth node N4, and the fourth node N4 is at a low level; the fifth node N5 is at a high level; the second transistor M2 is turned on, the second clock signal XCK is at a high level, and the signal of the second clock signal XCK is transmitted to the gate of the first transistor M1, and the first transistor M1 is turned off; the third node N3 is at a high level, the fifteenth transistor M15 is turned off, the second node N2 remains at a high level, the fourteenth transistor M14 is turned off, and the output signal OUT remains at a low level.

[0095] During the T2 period, the input signal IN is at a high level, the first clock signal CK is at a high level, the thirteenth transistor M13 is turned off, and the first node N1 remains at a high level; the twelfth transistor M12 is turned on, the potential of the first node N1 is transmitted to the third node N3, and the third node N3 remains at a high level; the sixth transistor M6 is turned off, and the fourth node N4 remains at a low level; the fifth node N5 is at a high level; the second transistor M2 is turned on, the second clock signal XCK is at a low level, and the signal of the second clock signal XCK is transmitted to the gate of the first transistor M1, and the first transistor M1 is turned on; the third node N3 is at a high level, the fifteenth transistor M15 is turned off, the second clock signal XCK is at a low level, the second node N2 becomes a low level, the fourteenth transistor M14 is turned on, the first voltage signal VGH is transmitted to the output signal OUT, and the output signal OUT outputs a high level.

[0096] During the T3 period, the input signal IN is at a high level, the first clock signal CK is at a low level, the thirteenth transistor M13 is turned on, and the input signal IN is transmitted to the first node N1, so that the first node N1 is at a high level; the twelfth transistor M12 is turned on, and the potential of the first node N1 is transmitted to the third node N3, and the third node N3 is at a high level; the sixth transistor M6 is turned on, and the second voltage signal VGL is transmitted to the fourth node N4, and the fourth node N4 is at a low level; the fifth node N5 is at a high level; the second transistor M2 is turned on, the second clock signal XCK is at a high level, and the signal of the second clock signal XCK is transmitted to the gate of the first transistor M1, and the first transistor M1 is turned off; the third node N3 is at a high level, the fifteenth transistor M15 is turned off, the second node N2 remains at a low level, the fourteenth transistor M14 is turned on, the first voltage signal VGH is transmitted to the output signal OUT, and the output signal OUT outputs a high level.

[0097] During the T4 period, the input signal IN is at a low level, the first clock signal CK is at a high level, the thirteenth transistor M13 is turned off, and the first node N1 remains at a high level; the twelfth transistor M12 is turned on, the potential of the first node N1 is transmitted to the third node N3, and the third node N3 remains at a high level; the sixth transistor M6 is turned off, and the fourth node N4 remains at a low level; the fifth node N5 is at a high level; the second transistor M2 is turned on, the second clock signal XCK is at a low level, and the signal of the second clock signal XCK is transmitted to the gate of the first transistor M1, and the first transistor M1 is turned on; the third node N3 is at a high level, the fifteenth transistor M15 is turned off, the second clock signal XCK is at a low level, the second node N2 remains at a low level, the fourteenth transistor M14 is turned on, the first voltage signal VGH is transmitted to the output signal OUT, and the output signal OUT outputs a high level.

[0098] During the T5 period, the input signal IN is at a low level, the first clock signal CK is at a low level, the thirteenth transistor M13 is turned on, and the input signal IN is transmitted to the first node N1, so that the first node N1 is at a low level; the twelfth transistor M12 is turned on, and the potential of the first node N1 is transmitted to the third node N3, and the third node N3 is at a low level; the sixth transistor M6 is turned on, and the second voltage signal VGL is transmitted to the fourth node N4, and the fourth node N4 is at a low level; the fifth node N5 is at a high level; the second transistor M2 is turned on, the second clock signal XCK is at a high level, and the signal of the second clock signal XCK is transmitted to the gate of the first transistor M1, and the first transistor M1 is turned off; the second node N2 is at a high level, the fourteenth transistor M14 is turned off, the third node N3 is at a low level, the fifteenth transistor M15 is turned on, the second voltage signal VGL is transmitted to the output signal OUT, and the output signal OUT outputs a low level.

[0099] During the T6 period, the input signal IN is at a low level, the first clock signal CK is at a high level, the thirteenth transistor M13 is turned off, and the first node N1 remains at a low level; the twelfth transistor M12 is turned on, the potential of the first node N1 is transmitted to the third node N3, and the third node N3 remains at a low level; the fifth node N5 is at a high level; the sixth transistor M6 is turned off, the tenth transistor M10 is turned on, the eleventh transistor M11 is turned on, the second clock signal XCK is at a low level, the ninth transistor M9 is turned on, the first voltage signal VGH is transmitted to the fourth node N4, and the fourth node N4 is at a high level; the second transistor M2 is turned off, and the first transistor M1 remains turned off; the second clock signal XCK is at a low level, the second node N2 remains at a high level, the fourteenth transistor M14 is turned off, the third node N3 is at a low level, the fifteenth transistor M15 is turned on, the second voltage signal VGL is transmitted to the output signal OUT, and the output signal OUT outputs a low level.

[0100] The first transistor M1 is in the on state only when the fourth node N4 and the second clock signal XCK are both at low levels. Therefore, the first transistor M1 is in the off state in the T5 period and the T6 period, thereby avoiding the high-level signal of the fifth node N5 affecting the low-level signal of the first node N1 in the T6 period. The low-level signal of the first node N1 can be maintained, thereby maintaining the low-level signal of the third node N3, and improving the stability of the output signal OUT generated by the third control unit 30, thereby improving the stability of the signal output by the driving circuit 100.

[0101] Fig. 9 In the shift register, a third transistor M3 is added. However, during the period T1 to T6, the levels of the first node N1, the second node N2, the third node N3, the fourth node N4, the fifth node N5 and the output signal OUT are the same as those in the above process, that is, Fig. 9 The timing diagram of the signals at each node in the shift register shown is also as shown in Fig.13 shown.

[0102] therefore, Fig. 9 In the shift register, the first transistor M1 is in the on state only when the fourth node N4 and the second clock signal XCK are both at low levels. Therefore, in the T5 period and the T6 period, the first transistor M1 is in the off state, thereby avoiding the high-level signal of the fifth node N5 affecting the low-level signal of the first node N1 in the T6 period. The low-level signal of the first node N1 can be maintained, thereby maintaining the low-level signal of the third node N3, and improving the stability of the output signal OUT generated by the third control unit 30, thereby improving the stability of the signal output by the drive circuit 100.

[0103] Fig.10 In the shift register, a third transistor M3 and a fourth transistor M4 are added. However, during the period T1 to T6, the levels of the first node N1, the second node N2, the third node N3, the fourth node N4, the fifth node N5 and the output signal OUT are the same as those in the above process, that is, Fig.10 The timing diagram of the signals at each node in the shift register shown is also as shown in Fig.13 shown.

[0104] Fig.10In the shift register, during the T5 period, the second clock signal XCK is a high-level signal, the fourth transistor M4 is turned off, the low-level signal of the fourth node N4 cannot be transmitted to the third transistor M3, the third transistor M3 is turned off, and the first voltage signal VGH cannot be transmitted to the fifth node N5. During the T6 period, the second clock signal XCK is a low-level signal, the fourth transistor M4 is turned on, the high-level signal of the fourth node N4 is transmitted to the gate of the third transistor M3, the third transistor M3 is turned off, and the first voltage signal VGH cannot be transmitted to the fifth node N5, that is, during the T5 period and the T6 period, the fifth node N5 is in a floating state and does not continue to be charged with the first voltage signal VGH, thereby reducing the influence of the fifth node N5 on the first node N1, and can maintain the low-level signal of the first node N1, thereby maintaining the low-level signal of the third node N3, and can improve the stability of the output signal OUT generated by the third control unit 30, thereby improving the stability of the signal output by the driving circuit 100.

[0105] Moreover, the first transistor M1 is in the on state only when the fourth node N4 and the second clock signal XCK are both at low levels. Therefore, the first transistor M1 is in the off state in the T5 period and the T6 period, thereby avoiding the high-level signal of the fifth node N5 affecting the low-level signal of the first node N1 in the T6 period. The low-level signal of the first node N1 can be maintained, thereby maintaining the low-level signal of the third node N3, and improving the stability of the output signal OUT generated by the third control unit 30, thereby improving the stability of the signal output by the drive circuit 100.

[0106] Fig.14 This is another driving timing diagram of the shift register provided by the present invention. Fig.11 and Fig.14 .

[0107] During the T1 period, the input signal IN is at a high level, the first clock signal CK is at a low level, the thirteenth transistor M13 is turned on, and the input signal IN is transmitted to the first node N1, so that the first node N1 is at a high level; the twelfth transistor M12 is turned on, and the potential of the first node N1 is transmitted to the third node N3, and the third node N3 is at a high level; the sixth transistor M6 is turned on, the second voltage signal VGL is transmitted to the fourth node N4, and the fourth node N4 is at a low level; the second clock signal XCK is at a high level, the fourth transistor M4 is turned off, the first transistor M1 is turned off, and the fifth node N5 is at a low level; the third node N3 is at a high level, the fifteenth transistor M15 is turned off, the second node N2 remains at a high level, the fourteenth transistor M14 is turned off, and the output signal OUT remains at a low level.

[0108] During the T2 period, the input signal IN is at a high level, the first clock signal CK is at a high level, the thirteenth transistor M13 is turned off, and the first node N1 remains at a high level; the twelfth transistor M12 is turned on, the potential of the first node N1 is transmitted to the third node N3, and the third node N3 remains at a high level; the sixth transistor M6 is turned off, and the fourth node N4 remains at a low level; the second clock signal XCK is at a low level, the fourth transistor M4 is turned on, the first transistor M1 is turned on, and the fifth node N5 is at a high level; the third node N3 is at a high level, the fifteenth transistor M15 is turned off, the second node N2 becomes a low level, the fourteenth transistor M14 is turned on, the first voltage signal VGH is transmitted to the output signal OUT, and the output signal OUT outputs a high level.

[0109] During the T3 period, the input signal IN is at a high level, the first clock signal CK is at a low level, the thirteenth transistor M13 is turned on, and the input signal IN is transmitted to the first node N1, so that the first node N1 is at a high level; the twelfth transistor M12 is turned on, and the potential of the first node N1 is transmitted to the third node N3, and the third node N3 is at a high level; the sixth transistor M6 is turned on, the second voltage signal VGL is transmitted to the fourth node N4, and the fourth node N4 is at a low level; the second clock signal XCK is at a high level, the fourth transistor M4 is turned off, the first transistor M1 is turned off, and the fifth node N5 remains at a high level; the third node N3 is at a high level, the fifteenth transistor M15 is turned off, the second node N2 remains at a low level, the fourteenth transistor M14 is turned on, the first voltage signal VGH is transmitted to the output signal OUT, and the output signal OUT outputs a high level.

[0110] During the T4 period, the input signal IN is at a low level, the first clock signal CK is at a high level, the thirteenth transistor M13 is turned off, and the first node N1 remains at a high level; the twelfth transistor M12 is turned on, the potential of the first node N1 is transmitted to the third node N3, and the third node N3 remains at a high level; the sixth transistor M6 is turned off, and the fourth node N4 remains at a low level; the second clock signal XCK is at a low level, the fourth transistor M4 is turned on, the first transistor M1 is turned on, the third transistor M3 is turned on, and the fifth node N5 is at a high level; the third node N3 is at a high level, the fifteenth transistor M15 is turned off, the clock signal XCK is at a low level, the second node N2 remains at a low level, the fourteenth transistor M14 is turned on, the first voltage signal VGH is transmitted to the output signal OUT, and the output signal OUT outputs a high level.

[0111] During the T5 period, the input signal IN is at a low level, the first clock signal CK is at a low level, the thirteenth transistor M13 is turned on, and the input signal IN is transmitted to the first node N1, so that the first node N1 is at a low level; the twelfth transistor M12 is turned on, the potential of the first node N1 is transmitted to the third node N3, and the third node N3 is at a low level; the sixth transistor M6 is turned on, the second voltage signal VGL is transmitted to the fourth node N4, and the fourth node N4 is at a low level; the second clock signal XCK is at a high level, the fourth transistor M4 is turned off, the first transistor M1 is turned off, and the fifth node N5 remains at a high level; the second node N2 is at a high level, the fourteenth transistor M14 is turned off, the third node N3 is at a low level, the fifteenth transistor M15 is turned on, the second voltage signal VGL is transmitted to the output signal OUT, and the output signal OUT outputs a low level.

[0112] During the T6 period, the input signal IN is at a low level, the first clock signal CK is at a high level, the thirteenth transistor M13 is turned off, and the first node N1 remains at a low level; the twelfth transistor M12 is turned on, the potential of the first node N1 is transmitted to the third node N3, and the third node N3 remains at a low level; the sixth transistor M6 is turned off, the tenth transistor M10 is turned on, the eleventh transistor M11 is turned on, the second clock signal XCK is at a low level, the ninth transistor M9 is turned on, the first voltage signal VGH is transmitted to the fourth node N4, and the fourth node N4 is at a high level; the second clock signal XCK is at a low level, the fourth transistor M4 is turned on, the first transistor M1 is turned on, the signal of the fourth node N4 is transmitted to the gate of the third transistor M3, the third transistor M3 is turned off, and the fifth node N5 is in a floating state; the second node N2 remains at a high level, the fourteenth transistor M14 is turned off, the third node N3 is at a low level, the fifteenth transistor M15 is turned on, the second voltage signal VGL is transmitted to the output signal OUT, and the output signal OUT outputs a low level.

[0113] Fig.11 In the shift register, the third transistor M3 is in the on state only in the T2th and T4th periods. At this time, the first transistor M1 is also in the on state, the first node N1 is at a high level, and the fifth node N5 is at a high level, which is conducive to stabilizing the high level of the first node N1.

[0114] During the T5 period, the second clock signal XCK is a high-level signal, the fourth transistor M4 is turned off, the low-level signal of the fourth node N4 cannot be transmitted to the third transistor M3, the third transistor M3 is turned off, and the first voltage signal VGH cannot be transmitted to the fifth node N5, and the first node N1 is charged with the second voltage signal VGL. During the T6 period, the second clock signal XCK is a low-level signal, the fourth transistor M4 is turned on, the high-level signal of the fourth node N4 is transmitted to the gate of the third transistor M3, the third transistor M3 is turned off, the first voltage signal VGH cannot be transmitted to the fifth node N5, the fifth node N5 is in a floating state, and the first voltage signal VGH is not continuously charged, the signal of the fifth node N5 can basically eliminate the raising of the signal of the first node N1, the low-level signal of the first node N1 can be maintained, and the low-level signal of the third node N3 can be maintained, so that the stability of the output signal OUT generated by the third control unit 30 can be improved, thereby improving the stability of the signal output by the driving circuit 100.

[0115] Fig.15 This is another driving timing diagram of the shift register provided by the present invention. Fig.12 and Fig.15 .

[0116] During the T1 period, the input signal IN is at a high level, the first clock signal CK is at a low level, the thirteenth transistor M13 is turned on, and the input signal IN is transmitted to the first node N1, so that the first node N1 is at a high level; the twelfth transistor M12 is turned on, and the potential of the first node N1 is transmitted to the third node N3, and the third node N3 is at a high level; the sixth transistor M6 is turned on, the second voltage signal VGL is transmitted to the fourth node N4, and the fourth node N4 is at a low level, the fifth transistor M5 is turned off, the third transistor M3 is turned on, the first voltage signal VGH is transmitted to the fifth node N5, and the fifth node N5 is at a high level; the second clock signal XCK is at a high level, and the first transistor M1 is turned off; the third node N3 is at a high level, the fifteenth transistor M15 is turned off, the second node N2 remains at a high level, the fourteenth transistor M14 is turned off, and the output signal OUT remains at an output low level.

[0117] During the T2 period, the input signal IN is at a high level, the first clock signal CK is at a high level, the thirteenth transistor M13 is turned off, and the first node N1 remains at a high level; the twelfth transistor M12 is turned on, and the potential of the first node N1 is transmitted to the third node N3, and the third node N3 remains at a high level; the sixth transistor M6 is turned off, the fourth node N4 remains at a low level, the fifth transistor M5 is turned off, the third transistor M3 is turned on, the first voltage signal VGH is transmitted to the fifth node N5, and the fifth node N5 is at a high level; the second clock signal XCK is at a low level, and the first transistor M1 is turned on; the third node N3 is at a high level, the fifteenth transistor M15 is turned off, the second node N2 becomes a low level, the fourteenth transistor M14 is turned on, the first voltage signal VGH is transmitted to the output signal OUT, and the output signal OUT outputs a high level.

[0118] During the T3 period, the input signal IN is at a high level, the first clock signal CK is at a low level, the thirteenth transistor M13 is turned on, and the input signal IN is transmitted to the first node N1, so that the first node N1 is at a high level; the twelfth transistor M12 is turned on, and the potential of the first node N1 is transmitted to the third node N3, and the third node N3 is at a high level; the sixth transistor M6 is turned on, the second voltage signal VGL is transmitted to the fourth node N4, and the fourth node N4 is at a low level, the fifth transistor M5 is turned off, the third transistor M3 is turned on, the first voltage signal VGH is transmitted to the fifth node N5, and the fifth node N5 is at a high level; the second clock signal XCK is at a high level, and the first transistor M1 is turned off; the third node N3 is at a high level, the fifteenth transistor M15 is turned off, the second node N2 remains at a low level, the fourteenth transistor M14 is turned on, the first voltage signal VGH is transmitted to the output signal OUT, and the output signal OUT outputs a high level.

[0119] During the T4 period, the input signal IN is at a low level, the first clock signal CK is at a high level, the thirteenth transistor M13 is turned off, and the first node N1 remains at a high level; the twelfth transistor M12 is turned on, and the potential of the first node N1 is transmitted to the third node N3, and the third node N3 remains at a high level; the sixth transistor M6 is turned off, the fourth node N4 remains at a low level, the fifth transistor M5 is turned off, the third transistor M3 is turned on, the first voltage signal VGH is transmitted to the fifth node N5, and the fifth node N5 is at a high level; the second clock signal XCK is at a low level, and the first transistor M1 is turned on; the third node N3 is at a high level, the fifteenth transistor M15 is turned off, the clock signal XCK is at a low level, the second node N2 remains at a low level, the fourteenth transistor M14 is turned on, the first voltage signal VGH is transmitted to the output signal OUT, and the output signal OUT outputs a high level.

[0120] During the T5 period, the input signal IN is at a low level, the first clock signal CK is at a low level, the thirteenth transistor M13 is turned on, and the input signal IN is transmitted to the first node N1, so that the first node N1 is at a low level; the twelfth transistor M12 is turned on, and the potential of the first node N1 is transmitted to the third node N3, and the third node N3 is at a low level; the sixth transistor M6 is turned on, the second voltage signal VGL is transmitted to the fourth node N4, and the fourth node N4 is at a low level, the fifth transistor M5 is turned off, the third transistor M3 is turned on, the first voltage signal VGH is transmitted to the fifth node N5, and the fifth node N5 is at a high level; the second clock signal XCK is at a high level, and the first transistor M1 is turned off; the second node N2 is at a high level, the fourteenth transistor M14 is turned off, the third node N3 is at a low level, the fifteenth transistor M15 is turned on, the second voltage signal VGL is transmitted to the output signal OUT, and the output signal OUT outputs a low level.

[0121] During the T6 period, the input signal IN is at a low level, the first clock signal CK is at a high level, the thirteenth transistor M13 is turned off, and the first node N1 remains at a low level; the twelfth transistor M12 is turned on, and the potential of the first node N1 is transmitted to the third node N3, and the third node N3 remains at a low level; the sixth transistor M6 is turned off, the tenth transistor M10 is turned on, the eleventh transistor M11 is turned on, the second clock signal XCK is at a low level, the ninth transistor M9 is turned on, the first voltage signal VGH is transmitted to the fourth node N4, and the fourth node N4 is at a high level, the fifth transistor M5 is turned on, the third transistor M3 is turned off, the second voltage signal VGL is transmitted to the fifth node N5, and the fifth node N5 is at a low level; the second clock signal XCK is at a low level, and the first transistor M1 is turned on; the second node N2 remains at a high level, the fourteenth transistor M14 is turned off, the third node N3 is at a low level, the fifteenth transistor M15 is turned on, the second voltage signal VGL is transmitted to the output signal OUT, and the output signal OUT outputs a low level.

[0122] During the T6 period, the second voltage signal VGL is transmitted to the fifth node N5, and the fifth node N5 is at a low level, which can maintain the low level signal of the first node N1, thereby maintaining the low level signal of the third node N3, and can improve the stability of the output signal OUT generated by the third control unit 30, thereby improving the stability of the signal output by the driving circuit 100.

[0123] In some optional embodiments, in the T5 period, when the first clock signal CK rises from a low level to a high level, the fourth node N4 changes from a low level to a high level, the fifth transistor M5 is turned on, the third transistor M3 is turned off, the second voltage signal VGL is transmitted to the fifth node N5, and the fifth node N5 is at a low level. Therefore, in the T6 period, the second clock signal XCK is at a low level, and when the first transistor M1 is turned on, the fifth node N5 is already a low level signal, and the fifth node N5 will not raise the low level signal of the first node N1, and further maintain the low level signal of the first node N1, thereby maintaining the low level signal of the third node N3, which can improve the stability of the output signal OUT generated by the third control unit 30, thereby improving the stability of the signal output by the driving circuit 100.

[0124] In some alternative embodiments, please refer to Fig.16 , Fig.16 1 is a schematic plan view of a display device provided by the present invention. The display device 1000 provided by this embodiment includes the display panel 000 provided by the above embodiment of the present invention. Fig.16 The embodiment only takes a mobile phone as an example to illustrate the display device 1000. It can be understood that the display device 1000 provided in the embodiment of the present invention can also be a computer, a television, a car display device or other display device 1000 with a display function, and the present invention does not specifically limit this. The display device 1000 provided in the embodiment of the present invention has the beneficial effects of the display panel 100 provided in the embodiment of the present invention. For details, please refer to the specific description of the display panel 1000 in the above embodiments, and this embodiment will not be repeated here.

[0125] It can be seen from the above embodiments that the display panel and the display device provided by the present invention achieve at least the following beneficial effects:

[0126] In the display panel provided by the present invention, the second control unit includes an adjusting unit, which is used to maintain the low level signal of the first node when the signal of the first node and the signal of the third node are both low level signals and the second clock signal is a low level signal, thereby maintaining the low level signal of the third node, thereby improving the stability of the output signal generated by the third control unit, thereby improving the stability of the signal output by the driving circuit.

[0127] Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that the above embodiments may be modified without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A display panel, characterized in that: include: A driving circuit, the driving circuit comprising N stages of shift registers cascaded to each other, N≥2; The shift register comprises: a first control unit configured to receive an input signal and control a signal of a first node in response to a first clock signal; A second control unit, comprising a first sub-control unit, a second sub-control unit and a third sub-control unit; The first sub-control unit is used to receive at least a second voltage signal, and control a signal of a fourth node in response to the first clock signal and a signal of the first node; The second sub-control unit is used to receive the first voltage signal and the signal of the fourth node, and control the signal of the second node in response to the second clock signal and the signal of the first node; a third control unit, the third control unit being used to receive the first voltage signal and the second voltage signal, and controlling the output signal in response to the signal of the second node and the signal of the third node, the third node being connected to the first node, the first voltage signal being a high level signal, and the second voltage signal being a low level signal; wherein, The third sub-control unit is connected between the first voltage signal and the first node, and the third sub-control unit includes an adjustment unit, which is used to maintain the low level signal of the first node when the signal of the first node and the signal of the third node are both low level signals and the second clock signal is a low level signal.

2. The display panel according to claim 1, characterized in that: The third sub-control unit comprises a first transistor, a source of the first transistor is connected to a fifth node, and a drain of the first transistor is connected to the first node, wherein the fifth node is coupled to the first voltage signal; The regulating unit is used to control the signal of the fifth node, or to control the turning on and off of the first transistor.

3. The display panel according to claim 2, characterized in that: The regulating unit is used for controlling the first transistor to remain turned off when the signal of the first node and the signal of the third node are both low-level signals, the first clock signal is a high-level signal, and the second clock signal is a low-level signal.

4. The display panel according to claim 3, characterized in that: The regulating unit is used to receive the second clock signal and control the gate potential of the first transistor in response to the signal of the fourth node.

5. The display panel according to claim 4, characterized in that: The regulating unit includes a second transistor, a gate of the second transistor is connected to the fourth node, a source is used to receive the second clock signal, and a drain is connected to the gate of the first transistor.

6. The display panel according to claim 5, characterized in that: The fifth node is directly connected to the first voltage signal.

7. The display panel according to claim 6, characterized in that: The third sub-control unit includes a third transistor, a source of the third transistor is connected to the first voltage signal, a drain is connected to the fifth node, and a gate is coupled to the fourth node.

8. The display panel according to claim 7, characterized in that: The third sub-control unit includes a fourth transistor, a source of the fourth transistor is connected to the fourth node, a gate is connected to the second clock signal, and a drain is connected to the gate of the third transistor.

9. The display panel according to claim 2, characterized in that: The regulating unit is used to control the disconnection between the fifth node and the first voltage signal when the signal of the first node and the signal of the third node are both low-level signals, the first clock signal is a low-level signal, and the second clock signal is a high-level signal.

10. The display panel according to claim 9, characterized in that: The third sub-control unit comprises a third transistor, a source of the third transistor is connected to the first voltage signal, a drain is connected to the fifth node, and a gate is coupled to the regulating unit; The regulating unit is used to receive the signal of the fourth node and control the gate potential of the third transistor in response to the second clock signal.

11. The display panel according to claim 10, characterized in that: The regulating unit includes a fourth transistor, a source of the fourth transistor is connected to the fourth node, a gate is connected to the second clock signal, and a drain is connected to the gate of the third transistor.

12. The display panel according to claim 2, characterized in that: The regulating unit is used for controlling the signal of the fifth node to be a low level signal when the signal of the first node and the signal of the third node are both low level signals and the first clock signal is a high level signal.

13. The display panel according to claim 12, characterized in that: The third sub-control unit comprises a third transistor, a source of the third transistor is connected to the first voltage signal, a drain is connected to the fifth node, and a gate is coupled to the fourth node; The regulating unit is used to receive the second voltage signal, and control the signal of the fifth node in response to the signal of the fourth node.

14. The display panel according to claim 13, characterized in that: When the signal of the fourth node is a high level signal, the regulating unit is turned on; When the signal at the fourth node is a low level signal, the regulating unit is turned off.

15. The display panel according to claim 13, characterized in that: The regulating unit includes a fifth transistor, a source of the fifth transistor is connected to the second voltage signal, a drain is connected to the fifth node, and a gate is connected to the fourth node.

16. The display panel according to claim 15, characterized in that: The first transistor and the third transistor are both PMOS transistors; The fifth transistor is an NMOS transistor.

17. The display panel according to claim 1, characterized in that: The first sub-control unit comprises: a sixth transistor, wherein a source of the sixth transistor is connected to the second voltage signal, a drain of the sixth transistor is connected to the fourth node, and a gate of the sixth transistor is connected to the first clock signal; a seventh transistor, wherein a source of the seventh transistor is connected to the first clock signal, a drain of the seventh transistor is connected to the fourth node, and a gate of the seventh transistor is connected to the first node; The second sub-control unit comprises: an eighth transistor, wherein a source of the eighth transistor is connected to the second clock signal, a drain of the eighth transistor is connected to the sixth node, and a gate of the eighth transistor is connected to the fourth node; a ninth transistor, wherein a source of the ninth transistor is connected to the sixth node, a drain of the ninth transistor is connected to the second node, and a gate of the ninth transistor is connected to the second clock signal; a tenth transistor, wherein a source of the tenth transistor is connected to the first voltage signal, a drain of the tenth transistor is connected to the second node, and a gate of the tenth transistor is connected to the first node; A first capacitor, wherein a first electrode plate of the first capacitor is connected to the fourth node, and a second electrode plate of the first capacitor is connected to the sixth node.

18. The display panel according to claim 17, characterized in that: The second sub-control unit further includes an eleventh transistor and a twelfth transistor; The source of the eleventh transistor is connected to the fourth node, the drain is connected to the gate of the eighth transistor, and the gate is connected to the second voltage signal; The source of the twelfth transistor is connected to the first node, the drain is connected to the third node, and the gate is connected to the second voltage signal.

19. The display panel according to claim 1, characterized in that: The first control unit comprises: a thirteenth transistor, wherein a source of the thirteenth transistor is connected to the input signal, a drain of the thirteenth transistor is connected to the first node, and a gate of the thirteenth transistor is connected to the first clock signal; The third control unit comprises: a fourteenth transistor, wherein a source of the fourteenth transistor is connected to the first voltage signal, a drain of the fourteenth transistor is connected to the output signal, and a gate of the fourteenth transistor is connected to the second node; a fifteenth transistor, wherein a source of the fifteenth transistor is connected to the second voltage signal, a drain of the fifteenth transistor is connected to the output signal, and a gate of the fifteenth transistor is connected to the third node; a second capacitor, wherein a first plate of the second capacitor is connected to the first voltage signal, and a second plate is connected to the second node; A third capacitor, wherein a first plate of the third capacitor is connected to the third node, and a second plate of the third capacitor is connected to the second voltage signal or the output signal.

20. A display device, characterized in that: A display panel comprising any one of claims 1-19.

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