Memory device and method of manufacturing the same

Abstract

A memory device and a method of manufacturing the same are provided. The memory device may include: a substrate; a first stacked structure including a plurality of first gate layers and a plurality of first interlayer insulating layers alternately stacked on the substrate; a second stacked structure including a plurality of second gate layers and a plurality of second interlayer insulating layers alternately stacked on the first stacked structure; and a channel structure passing through the first stacked structure and the second stacked structure, wherein the channel structure includes a first portion located in a first channel hole passing through the first stacked structure, a second portion located in a second channel hole passing through the second stacked structure, and a first protrusion located in a first recess, the first recess being recessed from a side portion of the first channel hole into one of the plurality of first interlayer insulating layers.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0146172, filed on November 14, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to storage devices and methods for manufacturing storage devices. Background Technology

[0004] With the increasing demand for multifunctional, high-performance, and miniaturized electronic devices, the demand for large capacity and high integration of memory devices will also increase. Therefore, vertical memory devices that stack multiple arrays of memory cells in a vertical direction have been proposed. For example, vertical memory devices comprising multiple stacked gate layers and a channel structure perpendicularly passing through the multiple stacked gate layers have been proposed. Summary of the Invention

[0005] This disclosure provides a memory device with improved process yield and a method for manufacturing the memory device.

[0006] According to one aspect of this disclosure, a memory device is provided, comprising: a substrate; a first stacked structure including a plurality of first gate layers and a plurality of first interlayer insulating layers alternately stacked on the substrate; a second stacked structure including a plurality of second gate layers and a plurality of second interlayer insulating layers alternately stacked on the first stacked structure; and a channel structure passing through the first stacked structure and the second stacked structure, wherein the channel structure includes a first portion located in a first channel hole passing through the first stacked structure, a second portion located in a second channel hole passing through the second stacked structure, and a first protrusion located in a first recess, the first recess being recessed from a side portion of the first channel hole into one of the plurality of first interlayer insulating layers.

[0007] According to another aspect of this disclosure, a memory device is provided, comprising: a substrate; a first stacked structure including a plurality of first gate layers and a plurality of first interlayer insulating layers alternately stacked on the substrate; a second stacked structure including a plurality of second gate layers and a plurality of second interlayer insulating layers alternately stacked on the first stacked structure; and a channel structure passing through the first stacked structure and the second stacked structure, wherein the plurality of first gate layers includes a plurality of first active gate layers stacked on the substrate and an upper first dummy gate layer located on the plurality of first active gate layers, wherein the plurality of first interlayer insulating layers... The insulating layer includes an upper first interlayer insulating layer located on the upper first dummy gate layer and a lower first interlayer insulating layer located below the upper first dummy gate layer, wherein the planar area of ​​the portion of the channel structure passing through the upper first dummy gate layer is greater than the planar area of ​​the portion of the channel structure passing through the upper first interlayer insulating layer and the planar area of ​​the portion of the channel structure passing through the lower first interlayer insulating layer, wherein the planar area of ​​the portion of the channel structure passing through the lowest of the plurality of second gate layers is smaller than the planar area of ​​the portion of the channel structure passing through the upper first interlayer insulating layer.

[0008] According to another aspect of this disclosure, a memory device is provided, comprising: a substrate; a first stacked structure including a plurality of first active gate layers on the substrate, a plurality of first dummy gate layers on the plurality of first active gate layers, and a plurality of first interlayer insulating layers separating the plurality of first active gate layers and the plurality of first dummy gate layers from each other; a second stacked structure including a plurality of second gate layers on the first stacked structure and a plurality of second interlayer insulating layers separating the plurality of second gate layers from each other; and a plurality of channel structures, each of the plurality of channel structures passing through the first stacked structure and the second stacked structure, wherein each of the plurality of channel structures includes a first portion passing through the first stacked structure, a second portion passing through the second stacked structure, and a plurality of protrusions projecting from a side surface of the first portion.

[0009] According to another aspect of this disclosure, a method of manufacturing a memory device is provided, comprising: forming a first preliminary stack structure, the first preliminary stack structure including a plurality of first sacrificial layers and a plurality of first interlayer insulating layers alternately stacked on a substrate; forming a first channel via through the first preliminary stack structure; forming a recess from a side portion of the first channel via into at least one of the plurality of first interlayer insulating layers; forming a channel etch stop layer in the first channel via and the at least one recess; forming a second preliminary stack structure, the second preliminary stack structure including a plurality of second sacrificial layers and a plurality of second interlayer insulating layers alternately stacked on the first preliminary stack structure; forming a second channel via through the second preliminary stack structure and exposing a portion of the top surface of the channel etch stop layer; removing the channel etch stop layer; forming a channel structure in the first channel via, the second channel via, and the at least one recess; and replacing the plurality of first sacrificial layers and the plurality of second sacrificial layers with a plurality of first gate layers and a plurality of second gate layers, respectively.

[0010] According to another aspect of this disclosure, a method of manufacturing a memory device is provided, comprising: forming a first preliminary stack structure, the first preliminary stack structure including a plurality of first sacrificial layers and a plurality of first interlayer insulating layers alternately stacked on a substrate; forming a first channel via through the first preliminary stack structure; forming a recess from a side portion of the first channel via into at least one of the plurality of first sacrificial layers; forming a channel etch stop layer in the first channel via and the at least one recess; forming a second preliminary stack structure, the second preliminary stack structure including a plurality of second sacrificial layers and a plurality of second interlayer insulating layers alternately stacked on the first preliminary stack structure; forming a second channel via through the second preliminary stack structure and exposing a portion of the top surface of the channel etch stop layer; removing the channel etch stop layer; forming a channel structure in the first channel via, the second channel via, and the at least one recess; and replacing the plurality of first sacrificial layers and the plurality of second sacrificial layers with a plurality of first gate layers and a plurality of second gate layers, respectively.

[0011] According to another aspect of this disclosure, a method of manufacturing a memory device is provided, comprising: forming a first preliminary stack structure, the first preliminary stack structure including a plurality of first sacrificial layers and a plurality of first interlayer insulating layers alternately stacked on a substrate; forming a second preliminary stack structure, the second preliminary stack structure including a plurality of second sacrificial layers and a plurality of second interlayer insulating layers alternately stacked on the first preliminary stack structure; forming a channel structure through the first preliminary stack structure and the second preliminary stack structure; and replacing the plurality of first sacrificial layers and the plurality of second sacrificial layers with a plurality of first gate layers and a plurality of second gate layers, wherein the channel structure includes a first portion located in a first channel hole through the first preliminary stack structure, a second portion located in a second channel hole through the second preliminary stack structure, and a plurality of protrusions located in a plurality of recesses, the plurality of recesses being horizontally recessed from the side of the first channel hole of the channel structure. Attached Figure Description

[0012] Embodiments of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 This is a schematic diagram of a storage device according to an embodiment of the present disclosure;

[0014] Figure 2A This is a schematic cross-sectional view of a storage device according to an embodiment of the present disclosure;

[0015] Figure 2B yes Figure 2A A magnified view of region B1;

[0016] Figure 3A This is a schematic cross-sectional view of a storage device according to an embodiment of the present disclosure;

[0017] Figure 3B yes Figure 3A A magnified view of region B1a;

[0018] Figure 4A This is a schematic cross-sectional view of a storage device according to an embodiment of the present disclosure;

[0019] Figure 4B yes Figure 4A A magnified view of region B1b;

[0020] Figure 5 This is a schematic cross-sectional view of a storage device according to an embodiment of the present disclosure;

[0021] Figure 6A This is a schematic cross-sectional view of a storage device according to an embodiment of the present disclosure;

[0022] Figure 6B yes Figure 6A A magnified view of region B2;

[0023] Figure 7 This is a flowchart illustrating a method for manufacturing a storage device according to an embodiment of the present disclosure;

[0024] Figures 8A to 8P and Figure 9 This is a schematic cross-sectional view illustrating a method of manufacturing a storage device according to an embodiment of the present disclosure;

[0025] Figure 10 A flowchart illustrating, schematically, a method for manufacturing a storage device according to an embodiment of the present disclosure; and

[0026] Figures 11A to 11E This is a schematic cross-sectional view illustrating a method of manufacturing a storage device according to an embodiment of the present disclosure. Detailed Implementation

[0027] Figure 1 The circuit diagram of the storage device 10 according to an embodiment of the present disclosure is shown schematically.

[0028] Reference Figure 1 The storage device 10 may include multiple NAND strings NS11 to NS33. Although Figure 1 The diagram shows that the memory device 10 may include nine NAND strings NS11 to NS33, but the number of NAND strings included in a single memory device 10 is not limited to this. Each NAND string NS11 to NS33 may include at least one ground select transistor GST, a plurality of first memory cells MC1 and MC2, a plurality of first dummy cells DC1 and DC2, a plurality of second dummy cells DC3 and DC4, a plurality of second memory cells MC3 and MC4, and at least one string select transistor SST connected in series. Figure 1 In each NAND string NS11 to NS33, there may be a ground selection transistor GST, two first memory cells MC1 and MC2, two first dummy cells DC1 and DC2, two second dummy cells DC3 and DC4, two second memory cells MC3 and MC4, and a string selection transistor SST. However, the number of ground selection transistors, first memory cells, first dummy cells, second dummy cells, second memory cells, and string selection transistors included in each NAND string NS11 to NS33 is not limited to this.

[0029] NAND strings NS11 to NS33 can be connected between bit lines BL1 to BL3 and the common source line CSL. The gate of each ground select transistor GST can be connected to one of the ground select lines GSL1 to GSL3. The gates of the first memory cells MC1 and MC2 can be connected to the first active word lines WL1 and WL2, respectively. The gates of the first dummy cells DC1 and DC2 can be connected to the first dummy word lines DWL1 and DWL2, respectively. The gates of the second dummy cells DC3 and DC4 can be connected to the second dummy word lines DWL3 and DWL4, respectively. The gates of the second memory cells MC3 and MC4 can be connected to the second active word lines WL3 and WL4, respectively. The gate of each string select transistor SST can be connected to one of the string select lines SSL1 to SSL3.

[0030] Figure 2A This is a schematic cross-sectional view of a storage device 100 according to an embodiment of the present disclosure. Figure 2B yes Figure 2A A magnified view of region B1.

[0031] Reference Figure 2A and Figure 2B The memory device 100 may include a substrate 110, a first stacked structure SSa on the substrate 110, a second stacked structure SSb on the first stacked structure SSa, and a plurality of channel structures 130 passing through the first stacked structure SSa and the second stacked structure SSb. In some embodiments, the memory device 100 may further include a common source line CSL located between the substrate 110 and the first stacked structure SSa. In some embodiments, the memory device 100 may further include a bottom etch stop layer 120 located between the common source line CSL and the first stacked structure SSa. In some embodiments, the memory device 100 may further include an insulating structure 150 passing through the first stacked structure SSa and the second stacked structure SSb.

[0032] The substrate 110 may include a semiconductor material, including group IV semiconductor materials, group III-V semiconductor materials, group II-VI semiconductor materials, or combinations thereof. Group IV semiconductor materials may include, for example, silicon (Si), germanium (Ge), or combinations thereof. Group III-V semiconductor materials may include, for example, gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimonide (InSb), or combinations thereof. Group II-VI semiconductor materials may include, for example, zinc telluride (ZnTe), cadmium sulfide (CdS), or combinations thereof.

[0033] The first stacked structure SSa may include a plurality of first gate layers GL1, GL2, DGL1, and DGL2 alternately stacked on a substrate 110, and a plurality of first interlayer insulating layers IL1 to IL5. The plurality of first gate layers GL1, GL2, DGL1, and DGL2 may include a plurality of first active gate layers GL1 and GL2 stacked on the substrate 110, and a plurality of first dummy gate layers DGL1 and DGL2 located on the plurality of first active gate layers GL1 and GL2. The plurality of first interlayer insulating layers IL1 to IL5 may separate the plurality of first active gate layers GL1 and GL2 and the plurality of first dummy gate layers DGL1 and DGL2 from each other. The plurality of first dummy gate layers DGL1 and DGL2 may include an upper first dummy gate layer DGL2 and a lower first dummy gate layer DGL1 located below the upper first dummy gate layer DGL2. The uppermost layer IL5 among the plurality of first interlayer insulating layers IL1 to IL5 may also be referred to as the upper first interlayer insulating layer IL5. The upper first interlayer insulating layer IL5 can be located on the upper first dummy gate layer DGL2. The next highest layer IL4 among the multiple first interlayer insulating layers IL1 to IL5 can also be referred to as the lower first interlayer insulating layer IL4. The lower first interlayer insulating layer IL4 can be located between the upper first dummy gate layer DGL2 and the lower first dummy gate layer DGL1.

[0034] Multiple first active gate layers GL1 and GL2 can be respectively included in multiple first memory cells MC1 and MC2 (see...) Figure 1 ), and can be connected to multiple first active word lines WL1 and WL2 respectively (see Figure 1 Multiple first dummy gate layers DGL1 and DGL2 can be included in multiple first dummy cells DC1 and DC2, respectively (see...). Figure 1 And can be connected to multiple first dummy word lines DWL1 and DWL2 respectively (see Figure 1 In some embodiments, the first stacked structure SSa may further include an additional first active word line (not shown) located below the plurality of first active word lines WL1 and WL2, and the additional first active word line (not shown) may be included in the ground select transistor GST and may be connected to one of the plurality of ground select lines GSL1 to GSL3 (see [link to documentation]). Figure 1 ).exist Figure 2A In the first stacked structure SSa, there may be two first active gate layers GL1 and GL2, two first dummy gate layers DGL1 and DGL2, and five first interlayer insulating layers IL1 to IL5, but the number of first active gate layers, first dummy gate layers and first interlayer insulating layers included in the first stacked structure SSa is not limited to this.

[0035] The second stacked structure SSb may include a plurality of second gate layers DGL3, DGL4, GL3, and GL4 alternately stacked on the first stacked structure SSa, and a plurality of second interlayer insulating layers IL6 to IL9. The plurality of second gate layers DGL3, DGL4, GL3, and GL4 may include a plurality of second dummy gate layers DGL3 and DGL4 located on the first stacked structure SSa, and a plurality of second active gate layers GL3 and GL4 located on the plurality of second dummy gate layers DGL3 and DGL4. The plurality of second interlayer insulating layers IL6 to IL9 may separate the plurality of second dummy gate layers DGL3 and DGL4 and the plurality of second active gate layers GL3 and GL4 from each other.

[0036] Multiple second dummy gate layers DGL3 and DGL4 can be included in multiple second dummy cells DC3 and DC4, respectively (see...). Figure 1 ), and can be connected to multiple second dummy word lines DWL3 and DWL4 respectively (see Figure 1 Multiple second active gate layers GL3 and GL4 can be included in multiple second memory cells MC3 and MC4, respectively (see...). Figure 1 It can be connected to multiple second active word lines WL3 and WL4 (see...) Figure 1 In some embodiments, the second stacked structure SSb may further include additional second active word lines (not shown) located on the plurality of second active word lines WL3 and WL4, and the additional second active word lines (not shown) may be included in the string select transistor SST and may be connected to one of the string select lines SSL1 to SSL3 (see...). Figure 1 ).exist Figure 2A In the second stacked structure SSb, there may be two second dummy gate layers DGL3 and DGL4, two second active gate layers GL3 and GL4, and four second interlayer insulating layers IL6 to IL9, but the number of second dummy gate layers, second active gate layers and second interlayer insulating layers included in the second stacked structure SSb is not limited to this.

[0037] The plurality of first active gate layers GL1 and GL2 and the plurality of second active gate layers GL3 and GL4 may comprise conductive materials such as copper (Cu), gold (Au), silver (Ag), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or combinations thereof. The chemical composition of the gate layers in the plurality of first dummy gate layers DGL1 and DGL2 and the plurality of second dummy gate layers DGL3 and DGL4 may be substantially the same as the chemical composition of the plurality of first active gate layers GL1 and GL2 and the plurality of second active gate layers GL3 and GL4. In this specification, two objects having substantially the same chemical composition means that the difference in the chemical composition of the two objects is within the range of chemical composition differences that may occur due to process limitations when the two objects are formed simultaneously in the same device using the same source and process conditions. The plurality of first dummy gate layers DGL1 and DGL2 and the plurality of second dummy gate layers DGL3 and DGL4 may include conductive materials, such as copper (Cu), gold (Au), silver (Ag), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or combinations thereof. In some embodiments, the plurality of first gate layers GL1, GL2, DGL1 and DGL2 and the plurality of second gate layers DGL3, DGL4, GL3 and GL4 may each have a thickness of approximately 10 nanometers (nm) to approximately 30 nm.

[0038] The plurality of first interlayer insulating layers IL1 to IL5 and the plurality of second interlayer insulating layers IL6 to IL9 may comprise an insulating material, including, for example, silicon oxide, silicon nitride, or combinations thereof. In some embodiments, the plurality of first interlayer insulating layers IL1 to IL5 and the plurality of second interlayer insulating layers IL6 to IL9 may be free of (i.e., may not contain) nitrides. Furthermore, the plurality of first interlayer insulating layers IL1 to IL5 and the plurality of second interlayer insulating layers IL6 to IL9 may each have a thickness of approximately 10 nm to approximately 30 nm.

[0039] The channel structure 130 can pass through the first stacked structure SSa and the second stacked structure SSb. The channel structure 130 may include a first portion 130a passing through the first stacked structure SSa, a second portion 130b passing through the second stacked structure SSb, and a plurality of protrusions 130p1 and 130p2 projecting from the side surface of the first portion 130a of the channel structure 130. The plurality of protrusions 130p1 and 130p2 of the channel structure 130 may include, for example, a first protrusion 130p1 and a second protrusion 130p2 located below the first protrusion 130p1. The second portion 130b of the channel structure 130 may contact the first portion 130a of the channel structure 130.

[0040] The first protrusion 130p1 of the channel structure 130 can be located in the upper first interlayer insulating layer IL5. That is, the first protrusion 130p1 of the channel structure 130 can be disposed between the upper first dummy gate layer DGL2 and the lowest DGL3 among the plurality of second gate layers DGL3, DGL4, GL3 and GL4. The second protrusion 130p2 of the channel structure 130 can be located in the lower first interlayer insulating layer IL4. That is, the second protrusion 130p2 of the channel structure 130 can be disposed between the upper first dummy gate layer DGL2 and the lower first dummy gate layer DGL1.

[0041] A first portion 130a of the channel structure 130 may be located in a first channel hole CHHa passing through a first stacked structure SSa. A second portion 130b of the channel structure 130 may be located in a second channel hole CHHb passing through a second stacked structure SSb. A first protrusion 130p1 of the channel structure 130 may be located in a first recess CHR1, which is recessed from the side surface (i.e., the side, not the top or bottom) of the first channel hole CHHa into the uppermost IL5 of a plurality of first interlayer insulating layers IL1 to IL5. A second protrusion 130p2 of the channel structure 130 may be located in a second recess CHR2, which is recessed from the side surface of the first channel hole CHHa into the next higher layer IL4 of a plurality of first interlayer insulating layers IL1 to IL5.

[0042] In some embodiments, the first recess CHR1 may be defined by the lower surface of the lowest of a plurality of second gate layers DGL3, DGL4, GL3 and GL4, the side surface of the upper first interlayer insulating layer IL5, and the upper surface of the upper first dummy gate layer DGL2. The second recess CHR2 may be defined by the lower surface of the upper first dummy gate layer DGL2, the side surface of the lower first interlayer insulating layer IL4, and the upper surface of the lower first dummy gate layer DGL1.

[0043] In this specification, the planar area of ​​an object refers to the area of ​​the object's projection onto the XY plane. The planar area of ​​the portion 130-2-1 of the channel structure 130 passing through the upper first interlayer insulating layer IL5 can be greater than the planar area of ​​the portion 130-2-2 of the channel structure 130 passing through the upper first dummy gate layer DGL2 and the planar area of ​​the portion 130-1-1 of the channel structure 130 passing through the lowest DGL3 among the plurality of second gate layers DGL3, DGL4, GL3, and GL4. In some embodiments, the planar area of ​​the portion 130-2-2 of the channel structure 130 passing through the upper first dummy gate layer DGL2 can be greater than the planar area of ​​the portion 130-1-1 of the channel structure 130 passing through the lowest DGL3 among the plurality of second gate layers DGL3, DGL4, GL3, and GL4. The planar area of ​​the portion 130-2-3 of the channel structure 130 passing through the lower first interlayer insulating layer IL4 can be greater than the planar area of ​​the portion 130-2-2 of the channel structure 130 passing through the upper first dummy gate layer DGL2 and the planar area of ​​the portion 130-2-4 of the channel structure 130 passing through the lower first dummy gate layer DGL1.

[0044] The channel structure 130 may include a gate insulating layer 131 located in the first channel hole CHHa, the plurality of recesses CHR1 and CHR2, and the second channel hole CHHb, and may include a channel layer 132 located on the gate insulating layer 131. In some embodiments, the channel structure 130 may further include a channel filling layer 133 located on the channel layer 132. In some embodiments, the channel structure 130 may further include a pad layer 134 blocking the upper end of the second channel hole CHHb.

[0045] The gate insulating layer 131 may include a barrier insulating layer 131a, a charge storage layer 131b, and a tunneling insulating layer 131c located in the first channel via CHHa, the plurality of recesses CHR1 and CHR2, and the second channel via CHHb. The barrier insulating layer 131a may include, for example, silicon oxide, silicon nitride, a metal oxide with a dielectric constant greater than that of silicon oxide, or a combination thereof. The metal oxide may include, for example, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or a combination thereof. In some embodiments, the thickness of the barrier insulating layer 131a may be from about 1 nm to about 10 nm. The charge storage layer 131b may include, for example, silicon nitride, boron nitride, polysilicon, or a combination thereof. In some embodiments, the thickness of the charge storage layer 131b may be from about 1 nm to about 10 nm. The tunneling insulating layer 131c may include, for example, a metal oxide. In some embodiments, the thickness of the tunneling insulating layer 131c may be from about 1 nm to about 10 nm. In some embodiments, the barrier insulating layer 131a, the charge storage layer 131b, and the tunneling insulating layer 131c may respectively comprise oxides, nitrides, and oxides.

[0046] A portion of the gate insulating layer 131 may be located within the plurality of recesses CHR1 and CHR2, and the remainder of the gate insulating layer 131 may be located outside the plurality of recesses CHR1 and CHR2. Figure 2A and Figure 2B In some embodiments shown, a portion of the blocking insulating layer 131a is located within the plurality of recesses CHR1 and CHR2, and the entire tunneling insulating layer 131c may be located outside the plurality of recesses CHR1 and CHR2. Therefore, the plurality of recesses CHR1 and CHR2 may not contain the tunneling insulating layer 131c. However, in other embodiments, a portion of the tunneling insulating layer 131c may also be located within the plurality of recesses CHR1 and CHR2. Figure 2A and Figure 2B In some embodiments shown, a portion of the charge storage layer 131b may be located within the plurality of recesses CHR1 and CHR2, but in other embodiments, the charge storage layer 131b may be located entirely outside the plurality of recesses CHR1 and CHR2.

[0047] exist Figure 2A and Figure 2B In some embodiments shown, the channel layer 132 may be located outside the plurality of recesses CHR1, CHR2; however, in other embodiments, a portion of the channel layer 132 may be located within the plurality of recesses CHR1 and CHR2. The channel layer 132 may include a semiconductor material. A channel fill layer 133 may fill the space surrounded by the channel layer 132. The channel fill layer 133 may include, for example, an insulating material. The pad layer 134 may include, for example, a semiconductor material.

[0048] The channel layer 132 and channel fill layer 133 of the channel structure 130 may further extend through the common source line CSL. The common source line CSL may extend through the gate insulating layer 131 of the channel structure 130 and contact the channel layer 132 of the channel structure 130. The common source line CSL may include, for example, a semiconductor material. The channel structure 130 may further extend through the bottom etch stop layer 120. The insulating structure 150 may extend through the second stacked structure SSb, the first stacked structure SSa, and the bottom etch stop layer 120, and the lower end of the insulating structure 150 may extend to the common source line CSL. The insulating structure 150 may be located in the word line cutout WLC extending through the first stacked structure SSa and the second stacked structure SSb. The insulating structure 150 may include an insulating material.

[0049] Figure 3A This is a schematic cross-sectional view of a storage device 100a according to an embodiment of the present disclosure. Figure 3B yes Figure 3A A magnified view of region B1a.

[0050] Reference Figure 3A and Figure 3B The central axis AX1 of the first portion 130a of the channel structure 130 and the central axis AX2 of the second portion 130b of the channel structure 130 may be misaligned. For example, the central axis AX1 of the first portion 130a of the channel structure 130 and the central axis AX2 of the second portion 130b of the channel structure 130 may not be perpendicularly aligned in the Z direction. In some embodiments, due to the misalignment, the second portion 130b of the channel structure 130 may not only contact the first portion 130a of the channel structure 130, but may also further contact the first protrusion 130p1 of the channel structure 130.

[0051] Figure 4A This is a schematic cross-sectional view of a storage device 100b according to an embodiment of the present disclosure. Figure 4B yes Figure 4A A magnified view of region B1b.

[0052] Reference Figure 4A and Figure 4BThe central axis AX1 of the first portion 130a of the channel structure 130 and the central axis AX2 of the second portion 130b of the channel structure 130 may be misaligned. For example, the central axis AX2 of the second portion 130b of the channel structure 130 may not be collinear with the central axis AX1 of the first portion 130a of the channel structure 130. In some embodiments, due to the misalignment, the second portion 130b of the channel structure 130 may not only contact the first portion 130a of the channel structure 130, but may also further contact the first protrusion 130p1 and the second protrusion 130p2 of the channel structure 130. The second portion 130b of the channel structure 130 may pass through the upper first interlayer insulating layer IL5, the upper first dummy gate layer DGL2, and the lower first interlayer insulating layer IL4. In some embodiments, the second portion 130b of the channel structure 130 may further pass through the lower first dummy gate layer DGL1. However, the second portion 130b of the channel structure 130 may not further pass through the plurality of first active gate layers GL1 and GL2.

[0053] Reference Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A and Figure 4B In the memory devices 100, 100a, and 100b according to embodiments of the present disclosure, even if the second portion 130b of the channel structure 130 is not aligned with the first portion 130a of the channel structure 130, the second portion 130b of the channel structure 130 may not extend too deeply into the first stacked structure SSa. Therefore, the second portion 130b of the channel structure 130 can be prevented from passing through the first active gate layers GL1 and GL2 located below the first dummy gate layers DGL1 and DGL2, and the second portion 130b of the channel structure 130 can be prevented from failing to exhibit the desired operating characteristics of the memory devices 100, 100a, and 100b. Therefore, the memory devices 100, 100a, and 100b according to embodiments of the present disclosure can have improved process yields. Figure 4A and Figure 4B As shown in the embodiment, when the central axis AX2 of the second portion 130b of the channel structure 130 is not aligned with the central axis AX1 of the first portion 130a of the channel structure 130 (i.e., collinear), increasing the number of recesses CHR2 and CHR1 and increasing the number of protrusions 130p1 and 130p2 of the channel structure 130 can particularly effectively prevent / avoid a decrease in process yield.

[0054] Furthermore, even if the height H2 (i.e., vertical thickness) of the topmost first interlayer insulating layer IL5 in the vertical direction (Z direction) of the first stacked structure SSa is reduced, the second portion 130b of the channel structure 130 can be prevented from passing through the first active gate layers GL1 and GL2 due to misalignment. Therefore, even if the current of memory devices 100, 100a, and 100b is increased and the threshold voltage of memory devices 100, 100a, and 100b is reduced by decreasing the height H2 of the topmost first interlayer insulating layer IL5 in the first stacked structure SSa, the process yield will not be significantly reduced. For example, the height H2 of the topmost first interlayer insulating layer IL5 in the vertical direction (Z direction) of the first stacked structure SSa can be reduced to be substantially the same (i.e., substantially equal) as the height H1 (i.e., vertical thickness) of one of the remaining plurality of first interlayer insulating layers IL1 to IL4 (e.g., IL4) in the vertical direction (Z direction). In this specification, two objects having substantially the same dimensions means that the size difference between the two objects is designed such that the two objects have the same dimensions within the range of size differences that may occur due to process limitations. However, in another embodiment, the height H2 of the topmost first interlayer insulating layer IL5 of the first stacked structure SSa in the vertical direction (Z direction) may be greater than the height H1 of one of the remaining plurality of first interlayer insulating layers IL1 to IL4 (e.g., IL4) in the vertical direction (Z direction).

[0055] Figure 5 This is a schematic cross-sectional view of a storage device 100c according to an embodiment of the present disclosure.

[0056] Reference Figure 5 Although the storage device 100 may include Figure 2A and Figure 2B The two stacked structures SSa and SSb in the text, but Figure 5 The memory device 100c may include more than two stacked structures SSa, SSb, and SSc. For example, the memory device 100c may include a first stacked structure SSa, a second stacked structure SSb, and a third stacked structure SSc. The integration density of the memory device 100c can be increased by increasing the number of stacked structures (e.g., SSa, SSb, and SSc) stacked on the substrate 110.

[0057] The first stacked structure SSa may include: a plurality of first active gate layers GL1 and GL2 stacked on the substrate 110, a plurality of first dummy gate layers DGL1 and DGL2 stacked on the plurality of first active gate layers GL1 and GL2, and a plurality of first interlayer insulating layers IL1 to IL5 separating the plurality of first gate layers GL1, GL2, DGL1 and DGL2 from each other. The second stacked structure SSb may include a plurality of second dummy gate layers DGL3 and DGL4 stacked on the first stacked structure SSa, a plurality of second active gate layers GL3 and GL4 located on the plurality of second dummy gate layers DGL3 and DGL4, a plurality of second dummy gate layers DGL5 and DGL6 stacked on the plurality of second active gate layers GL3 and GL4, and a plurality of second interlayer insulating layers IL6 to IL11 separating the plurality of second gate layers DGL3, DGL4, GL3, GL4, DGL5 and DGL6 from each other. The third stacked structure SSc may include a plurality of third dummy gate layers DGL7 and DGL8 stacked on the second stacked structure SSb, a plurality of third active gate layers GL5 and GL6 located on the plurality of third dummy gate layers DGL7 and DGL8, and a plurality of third interlayer insulating layers IL12 to IL15 separating the plurality of third gate layers DGL7, DGL8, GL5 and GL6 from each other.

[0058] The channel structure 130 of the storage device 100c can pass through the first stacked structure SSa, the second stacked structure SSb, and the third stacked structure SSC. The channel structure 130 can be formed in a first channel hole CHHa passing through the first stacked structure SSa, a second channel hole CHHb passing through the second stacked structure SSb and connected to the first channel hole CHHa, a third channel hole CHHc passing through the third stacked structure SSC and connected to the second channel hole CHHb, a plurality of recesses CHR1 and CHR2 recessed from the side surface of the first channel hole CHHa into a plurality of first interlayer insulating layers IL4 and IL5, respectively, and a plurality of recesses CHR3 and CHR4 recessed from the side surface of the second channel hole CHHb into a plurality of second interlayer insulating layers IL10 and IL11, respectively.

[0059] Figure 6A This is a schematic cross-sectional view of a storage device 200 according to an embodiment of the present disclosure. Figure 6B yes Figure 6A A magnified view of region B2.

[0060] Reference Figure 6A and Figure 6BThe channel structure 130' may include a first portion 130a passing through the first stacked structure SSa, a second portion 130b passing through the second stacked structure SSb, and a plurality of protrusions 130p1' and 130p2' projecting from the side surface of the first portion 130a of the channel structure 130. The plurality of protrusions 130p1' and 130p2' of the channel structure 130' may include a first protrusion 130p1' and a second protrusion 130p2' located below the first protrusion 130p1'.

[0061] The first protrusion 130p1' of the channel structure 130' can be located in the upper first dummy gate layer DGL2. That is, the first protrusion 130p1' of the channel structure 130' can be disposed between the upper first interlayer insulating layer IL5 and the lower first interlayer insulating layer IL4. The second protrusion 130p2' of the channel structure 130' can be located in the lower first dummy gate layer DGL1. That is, the second protrusion 130p2' of the channel structure 130' can be disposed between the lower first interlayer insulating layer IL4 and the first interlayer insulating layer IL3 (also called the third highest layer IL3) among the plurality of first interlayer insulating layers IL1 to IL5.

[0062] The first portion 130a of the channel structure 130' may be located in a first channel via CHHa passing through the first stacked structure SSa. The second portion 130b of the channel structure 130' may be located in a second channel via CHHb passing through the second stacked structure SSb. The first protrusion 130p1' of the channel structure 130' may be located in a first recess CHR1' recessed from the side surface of the first channel via CHHa into the upper first dummy gate layer DGL2. The second protrusion 130p2' of the channel structure 130' may be located in a second recess CHR2' recessed from the side surface of the first channel via CHHa into the lower first dummy gate layer DGL1.

[0063] In some embodiments, the first recess CHR1' may be defined by the lower surface of the upper first interlayer insulating layer IL5, the side surface of the upper first dummy gate layer DGL2, and the upper surface of the lower first interlayer insulating layer IL4. The second recess CHR2' may be defined by the lower surface of the lower first interlayer insulating layer IL4, the side surface of the lower first dummy gate layer DGL1, and the upper surface of the third highest layer IL3 among the plurality of first interlayer insulating layers IL1 to IL5.

[0064] The planar area of ​​the portion 130-2-2' of the channel structure 130' passing through the upper first dummy gate layer DGL2 can be greater than the planar area of ​​the portion 130-2-1' of the channel structure 130' passing through the upper first interlayer insulating layer IL5 and the planar area of ​​the portion 130-2-3' of the channel structure 130' passing through the lower first interlayer insulating layer IL4. In some embodiments, the planar area of ​​the portion 130-1-1' of the channel structure 130' passing through the lowest DGL3 among the plurality of second gate layers DGL3, DGL4, GL3 and GL4 can be smaller than the planar area of ​​the portion 130-2-1' of the channel structure 130' passing through the upper first interlayer insulating layer IL5. The planar area of ​​the portion 130-2-4' of the channel structure 130' passing through the lower first dummy gate layer DGL1 can be greater than the planar area of ​​the portion 130-2-3' of the channel structure 130' passing through the lower first interlayer insulating layer IL4 and the planar area of ​​the portion 130-2-5' of the channel structure 130' passing through the third highest layer IL3 among the multiple first interlayer insulating layers IL1 to IL5.

[0065] Figure 7 The flowchart illustrates schematically a method 1000 for manufacturing a storage device according to an embodiment of the present disclosure. Figures 8A to 8P and Figure 9 This is a schematic cross-sectional view illustrating a method 1000 for manufacturing a storage device according to an embodiment of the present disclosure.

[0066] Reference Figure 7 and Figure 8A A first preliminary stacked structure PSa can be formed on substrate 110 (S1100). The first preliminary stacked structure PSa may include a plurality of first sacrificial layers SL1 to SL4 and a plurality of first interlayer insulating layers IL1 to IL5 alternately stacked on substrate 110. That is, the first preliminary stacked structure PSa can be formed by alternately forming a plurality of first sacrificial layers SL1 to SL4 and a plurality of first interlayer insulating layers IL1 to IL5 on substrate 110. In some embodiments, the method 1000 for manufacturing a memory device may also sequentially form a lower sacrificial layer SL and a lower etch stop layer 120 on substrate 110 before forming the first preliminary stacked structure PSa (S1100). The plurality of first sacrificial layers SL1 to SL4 and the lower sacrificial layer SL may include any material having etch selectivity relative to the plurality of first interlayer insulating layers IL1 to IL5, such as silicon nitride. The lower etch stop layer 120 may include any material having etch selectivity relative to the lower sacrificial layer SL, such as polysilicon.

[0067] Reference Figure 7 and Figure 8BA first channel via CHHa (S1200) can be formed through the first preliminary stacked structure PSa. In some embodiments, the first channel via CHHa can further penetrate the lower etch stop layer 120 and the lower sacrificial layer SL.

[0068] Reference Figure 8C A sacrificial fill layer FL can be formed in the first channel hole CHHa. This sacrificial fill layer FL exposes the sidewalls of at least one of the plurality of first interlayer insulating layers IL1 to IL5 (e.g., upper first interlayer insulating layer IL5 and lower first interlayer insulating layer IL4) to the first channel hole CHHa and covers the remaining first interlayer insulating layers (e.g., IL1 to IL3) of the plurality of first interlayer insulating layers IL1 to IL5. Specifically, the sacrificial fill layer FL is filled in the first channel hole CHHa, and the upper portion of the sacrificial fill layer FL can be removed such that at least one of the plurality of first interlayer insulating layers IL1 to IL5 (e.g., IL4 and IL5) is exposed to the first channel hole CHHa through the sacrificial fill layer FL. The sacrificial fill layer FL can comprise any material having etch selectivity relative to the plurality of first interlayer insulating layers IL1 to IL5 and the plurality of first sacrificial layers SL1 to SL4, such as a spin-coated hard mask, polysilicon, metal, or a combination thereof.

[0069] Reference Figure 7 , Figure 8D and Figure 8E At least one recess (e.g., CHR1 and CHR2) can be formed from the side surface of the first channel hole CHHa into at least one first interlayer insulating layer (e.g., IL4 and IL5) exposed by the sacrificial fill layer FL (S1300). Specifically, the first recess CHR1 in the upper first interlayer insulating layer IL5 and the second recess CHR2 in the lower first interlayer insulating layer IL4 can be formed by removing (e.g., horizontally etching) portions of the upper first interlayer insulating layer IL5 and the lower first interlayer insulating layer IL4 exposed to the first channel hole CHHa. To selectively etch the first interlayer insulating layers IL5 and IL4, an etchant can be used that has a higher etching rate for the materials constituting the first interlayer insulating layers IL5 and IL4 than for the materials constituting the lower first sacrificial layer SL4. After forming at least one recess CHR1 and CHR2, the sacrificial fill layer FL can be removed.

[0070] Reference Figure 7 and Figure 8FThe first channel via CHHa and at least one recess (e.g., CHR1 and CHR2) can be filled with a channel etch stop layer ESL (S1400). The channel etch stop layer ESL can comprise any material having etch selectivity relative to the plurality of first interlayer insulating layers IL1 to IL5 and the plurality of first sacrificial layers SL1 to SL4, such as spin-coated hard masks, polysilicon, metals, or combinations thereof.

[0071] In some embodiments, with Figures 8D to 8F The difference shown is that, after forming at least one recess CHR1 and CHR2, a channel etch stop layer ESL can be formed on the sacrificial fill layer FL instead of removing the sacrificial fill layer FL, as illustrated. Figure 9 As shown. In some embodiments, the sacrificial fill layer FL and the channel etch stop layer ESL may comprise substantially the same material. In another embodiment, the sacrificial fill layer FL and the channel etch stop layer ESL may comprise different materials.

[0072] Reference Figure 7 , Figure 8G and Figure 8H A second preliminary stacked structure PSb can be formed on the first preliminary stacked structure PSa (S1500). The second preliminary stacked structure PSb may include a plurality of second sacrificial layers SL5 to SL8 and a plurality of second interlayer insulating layers IL6 to IL9 alternately stacked on the first preliminary stacked structure PSa. That is, the second preliminary stacked structure PSb can be formed by alternately forming a plurality of second sacrificial layers SL5 to SL8 and a plurality of second interlayer insulating layers IL6 to IL9 on the first preliminary stacked structure PSa. The plurality of second sacrificial layers SL5 to SL8 may include any material having etch selectivity relative to the plurality of second interlayer insulating layers IL6 to IL9, such as silicon nitride.

[0073] Next, a second channel via CHHb can be formed through the second preliminary stack structure PSb and expose a portion of the top surface of the channel etch stop layer ESL (S1600). When etching the second channel via CHHb (S1600), the channel etch stop layer ESL can prevent the second channel via CHHb from being etched too deeply into the first preliminary stack structure PSa. Forming at least one recess CHR1 and CHR2 can increase the planar area of ​​the channel etch stop layer ESL, thereby increasing the allowable misalignment range between the first channel via CHHa and the second channel via CHHb. Therefore, by forming at least one recess CHR1 and CHR2, the process yield of the operation (S1600) for forming the second channel via CHHb can be improved. In addition, even if the thickness of the upper first interlayer insulating layer IL5 is reduced to improve device characteristics, the reduction in process yield can still be prevented because the second channel via CHHb can be prevented from being etched too deeply into the first preliminary stack structure PSa. After forming the second channel via CHHb, the channel etch stop layer ESL (S1700) can be removed.

[0074] Reference Figure 7 and Figure 8I A channel structure 130 can be formed in the first channel hole CHHa, the second channel hole CHHb, and at least one recess CHR1 and CHR2 (S1800). Specifically, a gate insulating layer 131 and a channel layer 132 can be sequentially formed in / on the first channel hole CHHa, at least one recess CHR1 and CHR2, and the second channel hole CHHb. Specifically, the gate insulating layer 131 can be formed by sequentially forming a barrier insulating layer 131a, a charge storage layer 131b, and a tunneling insulating layer 131c in the first channel hole CHHa, at least one recess CHR1 and CHR2, and the second channel hole CHHb. In some embodiments, a channel filling layer 133 can be further formed on the channel layer 132. Subsequently, a pad layer 134 blocking the upper end of the second channel hole CHHb can be further formed.

[0075] Reference Figure 8J A word line cutout (WLC) can be formed through the first preliminary stack structure PSa, the second preliminary stack structure PSb, and the lower etch stop layer 120. The word line cutout (WLC) can expose the lower sacrificial layer SL.

[0076] Reference Figure 8K A capping layer SP can be formed, which covers the upper surface of the uppermost IL9 among the multiple second interlayer insulating layers IL6 to IL9 and the side surface of the word line cutout WLC, but may not cover the lower end of the word line cutout WLC. Specifically, a deposition method that does not have excellent step coverage characteristics can be used to form the capping layer SP. Therefore, the lower sacrificial layer SL can be exposed to the word line cutout WLC through the capping layer SP.

[0077] Reference Figure 8K and Figure 8L A gap Ga can be formed between the substrate 110 and the lower etch stop layer 120 by removing the lower sacrificial layer SL. A portion of the sidewall of the channel structure 130 can be exposed in the gap Ga between the substrate 110 and the lower etch stop layer 120. Etch can be transferred to the lower sacrificial layer SL through the word line cutout WLC. The lower etch stop layer 120 and the capping layer SP can protect the first preliminary stack structure PSa and the second preliminary stack structure PSb from being etched / prevent the first preliminary stack structure PSa and the second preliminary stack structure PSb from being etched when the lower sacrificial layer SL is removed.

[0078] Reference Figure 8L and Figure 8M The channel layer 132 can be exposed to the gap Ga between the substrate 110 and the lower etch stop layer 120 by removing a portion of the gate insulating layer 131 exposed by the gap Ga between the substrate 110 and the lower etch stop layer 120.

[0079] Reference Figure 8M and Figure 8N A common source line (CSL) can be filled in the Ga gap between the substrate 110 and the lower etch stop layer 120. The common source line (CSL) can be formed to contact the channel layer 132.

[0080] Reference Figure 7 and Figures 8N to 8P Multiple first sacrificial layers SL1 to SL4 and multiple second sacrificial layers SL5 to SL8 can be replaced with multiple first gate layers GL1, GL2, DGL1 and DGL2 and multiple second gate layers DGL3, DGL4, GL3 and GL4, respectively (S1900). Specifically, the multiple first sacrificial layers SL1 to SL4 and multiple second sacrificial layers SL5 to SL8 can be exposed to the word line cutout WLC by removing the cover layer SP. Subsequently, multiple gaps Gb to Gi can be formed between the multiple first interlayer insulating layers IL1 to IL4 and multiple second interlayer insulating layers IL5 to IL9 by removing the multiple first sacrificial layers SL1 to SL4 and multiple second sacrificial layers SL5 to SL8. Etch can be transferred to the multiple first sacrificial layers SL1 to SL4 and multiple second sacrificial layers SL5 to SL8 through the word line cutout WLC. The multiple gaps Gb to Gi can expose a portion of the side surface of the channel structure 130. Next, multiple first gate layers GL1, GL2, DGL1 and DGL2 and multiple second gate layers DGL3, DGL4, GL3 and GL4 can be formed in multiple gaps Gb to Gi between multiple first interlayer insulating layers IL1 to IL4 and multiple second interlayer insulating layers IL5 to IL9.

[0081] Reference Figure 2A An insulating structure 150 can be formed in the letter line cutout WLC. This can be done according to the reference. Figures 8A to 8P The described method 1000 for manufacturing storage devices is used to manufacture... Figure 2A The memory device 100 is shown in the figure. According to the method 1000 for manufacturing a memory device of the present disclosure, even if the second channel via CHHb is not aligned with the first channel via CHHa, the manufacturing yield of the memory device 100 can still be improved because the second channel via CHHb can be prevented from passing through the first active gate layers GL1 and GL2. In addition, since the need to form a thick upper first interlayer insulating layer IL5 to prevent the second channel via CHHb from passing through the first active gate layers GL1 and GL2 is reduced, a memory device 10 with increased current and reduced threshold voltage can be manufactured by reducing the height of the upper first interlayer insulating layer IL5 without significantly reducing the manufacturing yield (see [reference]). Figure 1 ).

[0082] Figure 10 The flowchart illustrates schematically a method 2000 for manufacturing a storage device according to an embodiment of the present disclosure. Figures 11A to 11E This is a schematic cross-sectional view illustrating a method 2000 for manufacturing a storage device according to an embodiment of the present disclosure.

[0083] according to Figure 10 The method 2000 for manufacturing a storage device shown in the figure can manufacture... Figure 6A and Figure 6B The storage device 200 is shown in the image. After comparison... Figure 7 and Figure 10 The method 2000 for manufacturing a memory device may include an operation (S1300') of forming at least one recess in at least one first sacrificial layer of a first preliminary stacked structure, instead of the operation (S1300) of forming at least one recess in at least one first interlayer insulating layer of the first preliminary stacked structure. Referring below... Figure 11A and Figure 11B The operation of forming at least one recess is described in more detail (S1300').

[0084] Reference Figure 11AA sacrificial fill layer FL can be formed in the first channel hole CHHa. This sacrificial fill layer FL exposes at least one of the plurality of first sacrificial layers SL1 to SL4 (e.g., upper first sacrificial layer SL4 and lower first sacrificial layer SL3) to the first channel hole CHHa and covers the remaining first sacrificial layers (e.g., SL1 and SL2) among the plurality of first sacrificial layers SL1 to SL4. Specifically, the sacrificial fill layer FL is filled in the first channel hole CHHa, and the upper part of the sacrificial fill layer FL can be removed, such that at least one of the plurality of first sacrificial layers SL1 to SL4 (e.g., SL3 and SL4) is exposed to the first channel hole CHHa through the sacrificial fill layer FL.

[0085] Reference Figure 11B At least one recess (e.g., CHR1' and CHR2') can be formed from the side surface of the first channel hole CHHa into at least one first sacrificial layer (e.g., SL3 and SL4) exposed by the sacrificial fill layer FL. Specifically, the first recess CHR1' in the upper first sacrificial layer SL4 and the second recess CHR2' in the lower first sacrificial layer SL3 can be formed by removing (e.g., horizontally etching) portions of the upper first sacrificial layer SL4 and the lower first sacrificial layer SL3 exposed to the first channel hole CHHa. To selectively etch the first sacrificial layers SL3 and SL4, an etchant can be used that has a higher etching rate for the materials constituting the first sacrificial layers SL3 and SL4 than for the materials constituting the first interlayer insulating layers IL4 and IL5.

[0086] The operation of replacing the plurality of first sacrificial layers SL1 to SL4 of the first preliminary stacked structure and the plurality of second sacrificial layers SL5 to SL8 of the second preliminary stacked structure with the plurality of first gate layers GL1, GL2, DGL1 and DGL2 and the plurality of second gate layers DGL3, DGL4, GL3 and GL4 respectively (S1900, see Figure 10 During this period, the upper first sacrificial layer SL4 and the lower first sacrificial layer SL3 can be replaced with the upper first dummy gate layer DGL2 respectively (see...). Figure 11E ) and the first dummy gate layer DGL1 (see Figure 11E ).

[0087] Figure 11C It shows Figure 10 The method for manufacturing a storage device 2000 includes the operation of forming the second channel hole CHHb (S1600).

[0088] Reference Figure 6A , Figure 6B and Figure 11C When the second channel pore CHHb(S1600) is formed, see Figure 10During the etching process, because the planar area of ​​the channel etch stop layer ESL increases with the depth d1' of the first recess CHR1' in the horizontal direction (X direction) and the depth d2' of the second recess CHR2' in the horizontal direction (X direction), even if the second channel hole CHHb is not aligned with the first channel hole CHHa, it can still advantageously prevent / prevent the second channel hole CHHb from being recessed too deeply into the first preliminary stacked structure PSa. Therefore, as the depth d1' of the first recess CHR1' in the horizontal direction (X direction) and the depth d2' of the second recess CHR2' in the horizontal direction (X direction) increases, the operation of forming the second channel hole CHHb (S1600, see...) Figure 10 The yield of the process can be improved.

[0089] Figure 11D and Figure 11E It shows Figure 10 The method of manufacturing a memory device 2000 includes the operation of replacing a plurality of first sacrificial layers SL1 to SL4 and a plurality of second sacrificial layers SL5 to SL8 with a plurality of first gate layers GL1, GL2, DGL1 and DGL2 and a plurality of second gate layers DGL3, DGL4, GL3 and GL4 respectively (S1900).

[0090] Simultaneously refer to Figure 6A , Figure 6B , Figure 11D and Figure 11EWhen the depth d1' of the first recess CHR1' in the horizontal direction (X direction) or the depth d2' of the second recess CHR2' in the horizontal direction (X direction) is greater than approximately 10 nm, it may be difficult to remove the portion of the upper first sacrificial layer SL4 located between the first recesses CHR1' or the portion of the lower first sacrificial layer SL3 located between the second recesses CHR2' because the distance dHH1 between adjacent first recesses CHR1' in the horizontal direction (X direction) or the distance dHH2 between adjacent second recesses CHR2' in the horizontal direction (X direction) is reduced too much. Alternatively, when the depth d1' of the first recess CHR1' in the horizontal direction (X direction) or the depth d2' of the second recess CHR2' in the horizontal direction (X direction) is greater than approximately 10 nm, a void VD may be formed in the upper first dummy gate layer DGL2 or the lower first dummy gate layer DGL1 because the distance dHH1 between adjacent first recesses CHR1' in the horizontal direction (X direction) or the distance dHH2 between adjacent second recesses CHR2' in the horizontal direction (X direction) is reduced excessively. Therefore, when the depth d1' of the first recess CHR1' in the horizontal direction (X direction) or the depth d2' of the second recess CHR2' in the horizontal direction (X direction) exceeds approximately 10 nm, the process yield of replacing multiple first sacrificial layers SL1 to SL4 and multiple second sacrificial layers SL5 to SL8 with multiple first gate layers GL1, GL2, DGL1 and DGL2 and multiple second gate layers DGL3, DGL4, GL3 and GL4 respectively (S1900) will decrease.

[0091] Therefore, in Figure 6A and Figure 6B In the storage device 200 shown, the depth d1' of the first recess CHR1' in the horizontal direction (X direction) and the depth d2' of the second recess CHR2' in the horizontal direction (X direction) can both be greater than 0 nm and less than or equal to approximately 10 nm. That is, the protrusion length d1' of the first protrusion 130p1' of the channel structure 130' in the horizontal direction (X direction) and the protrusion length d2' of the second protrusion 130p2' of the channel structure 130' in the horizontal direction (X direction) can both be greater than 0 nm and less than or equal to approximately 10 nm.

[0092] At the same time, Figure 2A and Figure 2BIn the memory device 100 shown, since the first recess CHR1 and the second recess CHR2 can be formed in the upper first interlayer insulating layer IL5 and the lower first interlayer insulating layer IL4, respectively, the depth d1 of the first recess CHR1 in the horizontal direction (X direction) and the depth d2 of the second recess CHR2 in the horizontal direction (X direction) do not significantly affect the replacement operation (S1900) of the method 1000 for manufacturing the memory device. Therefore, in some embodiments, the depth d1 of the first recess CHR1 in the horizontal direction (X direction) or the depth d2 of the second recess CHR2 in the horizontal direction (X direction) can be greater than approximately 10 nm.

[0093] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the scope of the appended claims.

Claims

1. A storage device, the storage device comprising: Substrate; A first stacked structure, the first stacked structure comprising a plurality of first gate layers and a plurality of first interlayer insulating layers alternately stacked on the substrate; A second stacked structure, the second stacked structure comprising a plurality of second gate layers and a plurality of second interlayer insulating layers alternately stacked on the first stacked structure; as well as A channel structure that passes through the first stacked structure and the second stacked structure. The channel structure includes a first portion located in a first channel hole passing through the first stacked structure, a second portion located in a second channel hole passing through the second stacked structure, and a first protrusion located in a first recess, wherein the first recess extends from the side of the first channel hole into one of the plurality of first interlayer insulating layers. The channel structure further includes a second protrusion located in the second recess, the second recess extending from the side of the first channel hole into another of the plurality of first interlayer insulating layers. The channel structure includes a gate insulating layer, a channel layer, and a channel filling layer, wherein the channel filling layer has a step at a portion adjacent to the first protrusion, and The first stacked structure is connected to the second stacked structure.

2. The storage device according to claim 1, wherein, The first layer among the plurality of first interlayer insulation layers is the uppermost layer among the plurality of first interlayer insulation layers.

3. The storage device according to claim 1, in, The channel structure includes a gate insulating layer located in the first channel hole, the first recess, and the second channel hole, and a channel layer located on the gate insulating layer. The channel layer is located outside the first recess.

4. The storage device according to claim 3, in, The first portion of the gate insulating layer is located inside the first recess, and The second portion of the gate insulating layer is located outside the first recess.

5. The storage device according to claim 4, in, The gate insulating layer includes a barrier insulating layer located in the first channel via, the first recess, and the second channel via, a charge storage layer located on the barrier insulating layer, and a tunneling insulating layer located on the charge storage layer. The first portion of the barrier insulating layer is located inside the first recess. The second portion of the barrier insulating layer is located outside the first recess, and The tunneling insulation layer is located entirely outside the first recess.

6. The storage device according to claim 5, in, The first portion of the charge storage layer is located inside the first recess, and The second portion of the charge storage layer is located outside the first recess.

7. The storage device according to claim 5, wherein, The charge storage layer is located entirely outside the first recess.

8. The storage device according to claim 1, wherein, The second portion of the channel structure contacts the first portion and the first protrusion of the channel structure.

9. The storage device according to claim 1, wherein, The vertical thickness of the uppermost layer of the plurality of first interlayer insulation layers is substantially equal to the vertical thickness of the second highest layer of the plurality of first interlayer insulation layers in the vertical direction.

10. The storage device according to claim 1, in, The other layer in the plurality of first interlayer insulation layers is the second highest layer in the plurality of first interlayer insulation layers, and The dummy gate layer in the plurality of first gate layers is located between one of the plurality of first interlayer insulating layers and the other of the plurality of first interlayer insulating layers.

11. The storage device according to claim 1, wherein, The second portion of the channel structure contacts the first portion, the first protrusion, and the second protrusion of the channel structure.

12. A storage device, the storage device comprising: Substrate; A first stacked structure, the first stacked structure comprising a plurality of first gate layers and a plurality of first interlayer insulating layers alternately stacked on the substrate; A second stacked structure, the second stacked structure comprising a plurality of second gate layers and a plurality of second interlayer insulating layers alternately stacked on the first stacked structure; as well as A channel structure that passes through the first stacked structure and the second stacked structure. The plurality of first gate layers include a plurality of first active gate layers stacked on the substrate and an upper first dummy gate layer located on the plurality of first active gate layers. The plurality of first interlayer insulating layers include an upper first interlayer insulating layer located on the upper first dummy gate layer and a lower first interlayer insulating layer located below the upper first dummy gate layer. Wherein, the planar area of ​​the portion of the channel structure passing through the upper first dummy gate layer is greater than the planar area of ​​the portion of the channel structure passing through the upper first interlayer insulating layer and the planar area of ​​the portion of the channel structure passing through the lower first interlayer insulating layer, and Wherein, the planar area of ​​the portion of the channel structure passing through the lowest of the plurality of second gate layers is smaller than the planar area of ​​the portion of the channel structure passing through the upper first interlayer insulating layer. The plurality of first gate layers further includes a lower first dummy gate layer located between the plurality of first active gate layers and the upper first dummy gate layer, and Wherein, the planar area of ​​the portion of the channel structure passing through the lower first dummy gate layer is greater than the planar area of ​​the portion of the channel structure passing through the lower first interlayer insulating layer.

13. The storage device according to claim 12, wherein, The chemical composition of the first dummy gate layer is substantially the same as that of one of the plurality of first active gate layers.

14. A storage device, the storage device comprising: Substrate; A first stacked structure, the first stacked structure including a plurality of first active gate layers located on the substrate, a plurality of first dummy gate layers located on the plurality of first active gate layers, and a plurality of first interlayer insulating layers separating the plurality of first active gate layers and the plurality of first dummy gate layers from each other; The second stacked structure includes a plurality of second gate layers located on the first stacked structure and a plurality of second interlayer insulating layers that separate the plurality of second gate layers from each other; as well as Multiple channel structures, all of which pass through the first stacked structure and the second stacked structure. Each of the plurality of channel structures includes a first portion passing through the first stacked structure, a second portion passing through the second stacked structure, and a plurality of protrusions protruding from the side surface of the first portion. The channel structure includes a gate insulating layer, a channel layer, and a channel filling layer, wherein the channel filling layer has a step at a portion adjacent to the plurality of protrusions, and The first stacked structure is connected to the second stacked structure.

15. The storage device according to claim 14, wherein, Some of the protrusions of each of the plurality of channel structures are located between the plurality of first dummy gate layers.

16. The storage device according to claim 14, wherein, The plurality of protruding portions of each of the plurality of channel structures are located in some of the plurality of first interlayer insulation layers.

17. The storage device according to claim 14, wherein, The plurality of protruding portions of each of the plurality of channel structures are respectively located in the plurality of first dummy gate layers.

18. The storage device according to claim 17, wherein, The protrusions of each of the plurality of channel structures have a horizontal protrusion length greater than 0 nm and less than or equal to 10 nm.

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