Digital time converter calibration method, device, digital phase-locked loop and electronic equipment

Abstract

The present invention relates to the field of digital circuit technology, and in particular to a digital time converter calibration method, device, digital phase-locked loop and electronic equipment. The digital time converter calibration method, device, digital phase-locked loop and electronic equipment of the present invention obtain a resolution deviation according to the fractional part of the reference phase and the fractional phase error; obtain a gain factor according to the resolution deviation; perform gain processing on the fractional part of the reference phase according to the gain factor to generate the delay control signal, and output the delay control signal to the digital time converter; through the above method, on the basis of eliminating the noise of other components of the digital phase-locked loop, the noise of the time-to-digital converter and the digital-to-time converter is further eliminated, and the calibration accuracy of the digital time converter is improved; high-precision gain calibration of the digital time converter is achieved, and power consumption is greatly reduced.

Description

[Technical field]

[0001] The present invention relates to the technical field of digital circuits, and in particular to a digital time converter calibration method, device, digital phase-locked loop and electronic equipment. [Background technology]

[0002] In an all-digital phase-locked loop (ADPLL), the time-digital converter (TDC) is used as a fractional phase detector. Its quantization noise greatly affects the final phase noise performance of the phase-locked loop. Improving the resolution of TDC has become an effective way to improve the performance of ADPLL. The TDC assisted by the digital-time converter (DTC) is conducive to reducing the power consumption of the all-digital phase-locked loop. The DTC delays the input reference clock for a certain period of time. At this time, the time difference between the delayed reference clock and the output clock of the phase-locked loop is within the dynamic range of the TDC.

[0003] However, the resolution of DTC is affected by non-ideal factors such as process, power supply, temperature (PVT) deviation or nonlinearity, resulting in the actual delay of the reference clock being different from the expected delay, which becomes the noise contributed by DTC. The calibration device in the prior art does not consider eliminating the noise of DTC, resulting in low calibration accuracy, inability to achieve high-precision gain calibration of the time converter, and poor effect of reducing power consumption. [Summary of the invention]

[0004] The object of the present invention is to provide a digital time converter calibration method, device, digital phase-locked loop and electronic equipment to solve the technical problems of low calibration accuracy and poor power consumption reduction effect in the prior art.

[0005] The technical solution of the present invention is as follows: a digital time converter calibration method is provided, which is applied to a digital phase-locked loop, wherein the digital phase-locked loop comprises a digital time converter and a time digital converter, wherein the digital time converter is used to delay a reference clock signal according to a delay control signal to generate a delayed reference clock signal; the time digital converter is used to generate a fractional phase error according to the delayed reference clock signal and an output clock signal of the digital phase-locked loop, wherein the fractional phase error is used to indicate a phase difference between the delayed reference clock signal and the output clock signal, and comprises:

[0006] Respectively acquiring a fractional part of a reference phase and the fractional phase error output by the time-to-digital converter, wherein the reference phase is generated according to a reference clock signal, the reference phase is used to indicate phase information of the reference clock signal, and the reference phase includes an integer part and a fractional part;

[0007] Obtaining a resolution deviation according to the fractional part of the reference phase and the fractional phase error;

[0008] Acquire a gain factor according to the resolution deviation;

[0009] Performing gain processing on the fractional part of the reference phase according to the gain factor to generate the delay control signal, and outputting the delay control signal to the digital-to-time converter.

[0010] Preferably, obtaining the resolution deviation according to the fractional part of the reference phase and the fractional phase error comprises:

[0011] Filtering the fractional phase error to obtain the filtered fractional phase error;

[0012] Inverting the decimal part of the reference phase, and summing the inverted decimal part of the reference phase with the first parameter to obtain a first calculated value;

[0013] The filtered fractional phase error is divided by the first calculated value to obtain a resolution deviation.

[0014] Preferably, obtaining a gain factor according to the resolution deviation comprises:

[0015] multiplying the resolution deviation by a second parameter to obtain a third calculated value;

[0016] The third calculated values ​​are accumulated to obtain the gain factor.

[0017] -

[0018] Preferably, performing gain processing on the fractional part of the reference phase according to the gain factor to generate the delay control signal comprises:

[0019] Inverting the decimal part of the reference phase, and summing the inverted decimal part of the reference phase with a second parameter to obtain a second calculated value;

[0020] The second calculated value is divided by the gain factor to obtain a third calculated value, and the delay control signal is generated according to the third calculated value.

[0021] Another technical solution of the present invention is as follows: a digital time converter calibration device is provided, which is applied to a digital phase-locked loop, wherein the digital phase-locked loop comprises a digital time converter and a time digital converter, wherein the digital time converter is used to delay a reference clock signal according to a delay control signal to generate a delayed reference clock signal; the time digital converter is used to generate a fractional phase error according to the delayed reference clock signal and an output clock signal of the digital phase-locked loop, wherein the fractional phase error is used to indicate a phase difference between the delayed reference clock signal and the output clock signal, and the calibration device comprises:

[0022] an error detection module, used to respectively obtain a fractional part of a reference phase and the fractional phase error output by the time-to-digital converter, and obtain a resolution deviation according to the fractional part of the reference phase and the fractional phase error, wherein the reference phase is generated according to a reference clock signal, the reference phase is used to indicate phase information of the reference clock signal, and the reference phase includes an integer part and a fractional part;

[0023] A calculation module, used for obtaining a gain factor according to the resolution deviation;

[0024] A gain module is used to perform gain processing on the fractional part of the reference phase according to the gain factor, generate the delay control signal, and output the delay control signal to the digital-to-time converter.

[0025] Preferably, the error detection module comprises:

[0026] A filter, used for filtering the fractional phase error to obtain the filtered fractional phase error;

[0027] A first adder, configured to sum the decimal part of the inverted reference phase and the first parameter to obtain a first calculated value;

[0028] The first divider is used to divide the filtered fractional phase error by the first calculated value to obtain a resolution deviation.

[0029] Preferably, the calculation module includes a multiplier and an accumulator, wherein:

[0030] The multiplier is used to multiply the resolution deviation by the second parameter to obtain a third calculated value;

[0031] The accumulator is used to accumulate the third calculated value to obtain the gain factor and output it.

[0032] Preferably, the gain module comprises:

[0033] A third adder, used for summing the decimal part of the inverted reference phase and the second parameter to obtain a second calculated value;

[0034] The second divider is used for dividing the second calculated value by the gain factor to obtain a third calculated value, and outputting the third calculated value as the delay control signal to the digital-to-time converter.

[0035] Another technical solution of the present invention is as follows: a digital phase-locked loop is provided, comprising:

[0036] The digital time converter calibration device mentioned above;

[0037] A first counter, used to generate a reference phase according to a reference clock signal, wherein the reference phase is used to indicate phase information of the reference clock signal, and the reference phase includes an integer part and a fractional part;

[0038] A second counter, used to generate a variable phase according to the output clock signal, wherein the variable phase is used to indicate phase information of the output clock signal;

[0039] A digital time converter, used for delaying the reference clock signal according to a delay control signal to generate a delayed reference clock signal;

[0040] a time-to-digital converter, configured to generate a fractional phase error based on the delayed reference clock signal and the output clock signal, wherein the fractional phase error is used to indicate a phase difference between the delayed reference clock signal and the output clock signal;

[0041] a phase detector for generating a phase error based on the integer part of the reference phase, the fractional phase error and the variable phase;

[0042] A digital loop filter, used for smoothing the phase error;

[0043] A digitally controlled oscillator is used to generate an adjustment value of a frequency control word according to the phase error after smoothing, and to generate the output clock signal according to the adjustment value of the frequency control word.

[0044] Another technical solution of the present invention is as follows: an electronic device is provided, the electronic device comprises a chip, and the chip comprises the above-mentioned digital phase-locked loop.

[0045] The beneficial effects of the present invention are as follows: the digital time converter calibration method, device, digital phase-locked loop and electronic device of the present invention obtain a resolution deviation according to the fractional part of the reference phase and the fractional phase error; obtain a gain factor according to the resolution deviation; perform gain processing on the fractional part of the reference phase according to the gain factor to generate the delay control signal, and output the delay control signal to the digital time converter; in the above manner, on the basis of eliminating the noise of other components of the digital phase-locked loop, the noise of the time-to-digital converter and the digital-to-time converter is further eliminated, thereby improving the calibration accuracy of the digital time converter; achieving high-precision gain calibration of the digital time converter, and greatly reducing power consumption.

Brief Description of the Drawings

[0046] Figure 1 A circuit diagram of a digital phase-locked loop according to a first embodiment of the present invention;

[0047] Figure 2 A circuit diagram of a digital-to-time converter calibration device according to a second embodiment of the present invention;

[0048] Figure 3 is a flow chart of a digital-to-time converter calibration method according to a third embodiment of the present invention;

[0049] Figure 4 A comparison diagram of phase error results of a comparative example and an application example of the present invention;

[0050] Figure 5 A comparison chart of gain factor results of comparative examples and application examples of the present invention;

[0051] Figure 6 FIG. 4 is a structural block diagram of an electronic device according to a fourth embodiment of the present invention. [Specific implementation method]

[0052] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0053] The terms "first", "second" and "third" in the present invention are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second" and "third" can explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. All directional indications (such as up, down, left, right, front, back...) in the embodiments of the present invention are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0054] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0055] For ease of understanding, the digital phase-locked loop provided by the present invention is first described.

[0056] The first embodiment of the present invention provides a digital phase-locked loop 100. Figure 1 As shown, the digital phase-locked loop 100 includes a first counter 21 , a second counter 22 , a digital-to-time converter 23 , a time-to-digital converter 24 , a phase detector 25 , a digital loop filter 26 , a digitally controlled oscillator 27 and a digital-to-time converter calibration device 10 .

[0057] The digital phase-locked loop 100 of the present embodiment is a fully digital phase-locked loop assisted by a digital time converter. In the digital phase-locked loop 100, the frequency of the output clock signal CKV of the digital phase-locked loop is set to a preset multiple of the frequency of the reference clock signal FREF. The preset multiple is called a frequency control word FCW (Frequency command word, FCW). In the present embodiment, the frequency control word FCW is not an integer, but includes an integer part and a decimal part. For example, when the frequency of the reference clock signal FREF is 100MHz, if you want to get an output clock signal CKV of 225MHz, you can set the frequency control word FCW to 2.25.

[0058] The first counter 21 receives the reference clock signal FREF, and generates a reference phase PHR according to the reference clock signal FREF, wherein the reference phase PHR is used to indicate the phase information of the reference clock signal, and the reference phase PHR includes an integer part PHR i and the fractional part PHR F Specifically, the first counter 21 accumulates the first preset value according to the frequency of the reference clock signal FREF to generate the reference phase PHR.

[0059] The second counter 22 is used to generate a variable phase PHV_INT according to the output clock signal CKV, wherein the variable phase PHV_INT is used to indicate the phase information of the output clock signal. Specifically, the second counter 22 accumulates the second preset value according to the frequency of the output clock signal CKV to generate the variable phase PHV_INT.

[0060] In this embodiment, the first preset value may be set to the frequency control word FCW, and the second preset value may be set to 1. That is, in this embodiment, the first counter 21 accumulates the frequency control word FCW according to the frequency of the reference clock signal FREF to generate the reference phase PHR; the second counter 22 accumulates 1 according to the frequency of the output clock signal CKV to generate the variable phase PHV_INT.

[0061] The digital-to-time converter 23 is used to delay the reference clock signal FREF according to the delay control signal to generate a delayed reference clock signal.

[0062] The time-to-digital converter 24 is used to generate a fractional phase error PHE according to the delayed reference clock signal and the output clock signal CKV. F , where the fractional phase error PHE F The phase difference between the reference clock signal and the output clock signal CKV is used to indicate the delay.

[0063] The phase detector 25 is used to detect the integer part PHR of the reference phase.i , the fractional phase error PHE F The variable phase PHV_INT generates a phase error. Further, the phase detector 25 includes a fourth adder, which adds the integer part PHR of the reference phase i , fractional phase error PHE F The inversion of the variable phase PHV_INT is added to obtain the phase error.

[0064] A digital loop filter (DLF) 26 is used to smooth the phase error.

[0065] The digital controlled oscillator (DCO) 27 is used to generate an adjustment value of the frequency control word according to the smoothed phase error, and to generate the output clock signal CKV according to the adjustment value of the frequency control word.

[0066] The digital time converter calibration device 10 is used to perform gain calibration on the digital time converter 23, control the delay amount of the digital time converter 23, change the corresponding relationship between the frequency control word FCW and the delay amount of the digital time converter 23, and receive the fractional part PHR of the reference phase output by the first counter 21. F and the fractional phase error PHE output by the time-to-digital converter 24 F , the digital time converter calibration device 10 outputs a delay control signal DTC ctrl to the digital-to-time converter 23. The structure and working mode of the digital-to-time converter calibration device 10 are specifically described in the second embodiment below.

[0067] The second embodiment of the present invention provides a digital time converter calibration device 10, which is applied to the digital phase-locked loop of the first embodiment, see Figure 2 As shown, the digital-to-time converter calibration device 10 comprises: an error detection module 11, a calculation module 12 and a gain module 13, wherein the error detection module 11 is used to receive the fractional part PHR of the reference phase output by the first counter 21 respectively. F and the fractional phase error PHE output by the time-to-digital converter 24 F , according to the fractional part of the reference phase PHR F and the fractional phase error PHE F Obtain the resolution deviation and output the resolution deviation to the calculation module 12; the calculation module 12 is used to calculate the gain factor K according to the resolution deviation output by the error detection module 11 dtc , the gain factor K dtc Output to the gain module 13; the gain module 13 is used to output the gain factor K according to the gain factor K. dtcThe fractional part PHR of the reference phase output by the first counter 21 F Perform gain processing to generate a delay control signal DTC ctrl , the delay control signal DTC ctrl The digital-to-time converter 23 is outputted to achieve gain calibration of the digital-to-time converter 23 .

[0068] In an optional implementation, the error detection module 11 includes a filter 111 , a first adder 112 , and a first divider 113 .

[0069] The filter 111 receives the fractional phase error PHE output by the time-to-digital converter 24. F , the fractional phase error PHE F Perform filtering to obtain a filtered fractional phase error, specifically, the filtered fractional phase error is the phase error contributed by the resolution deviation of the digital time converter 23; the filter 111 is a bandpass filter, the passband frequency is centered on fr×min(FCW_F, 1-FCW_F), and can be modified to a suitable passband frequency with different FCW_F, so that it can work normally at any frequency. Since the error signal used for iterative calculation will appear repeatedly in the ADPLL at a certain frequency (first frequency), and the above frequency (first frequency) varies with different frequency control words, therefore, the use of the bandpass filter of the preferred embodiment can avoid the situation where the calibration algorithm does not converge due to the use of a fixed frequency IIR filter.

[0070] The first adder 112 is used to invert the fractional part of the reference phase PHR. F The first calculated value is obtained by summing the first parameter with the first parameter. In this embodiment, the first parameter is 1, and the first calculated value is 1-PHR F .

[0071] Among them, the first divider 113 receives the filtered fractional phase error output by the filter 111 and the first calculated value output by the first adder 112 respectively, divides the filtered fractional phase error by the first calculated value to obtain a resolution deviation, and outputs the resolution deviation to the calculation module 12.

[0072] In an optional embodiment, the calculation module 12 includes a multiplier 121 and an accumulator 122, wherein the multiplier 121 receives the resolution deviation output by the error detection module 11, multiplies the resolution deviation by the second parameter μ, obtains a third calculation value, and outputs the third calculation value to the accumulator 122; the accumulator 122 receives the third calculation value output by the multiplier 121 and accumulates the third calculation value, and the accumulated result is the gain factor K dtc Furthermore, the value of the second parameter μ is preferably 10 -3 , that is, 0.001. In practical applications, when the gain factor K dtc When the speed of convergence to a stable value is slow, the value of the second parameter μ can be increased; when calculating the gain factor K dtc When oscillation occurs, the value of the second parameter μ can be reduced.

[0073] In an optional embodiment, the gain module 13 includes a third adder 131 and a second divider 132, wherein the third adder 131 is used to convert the inverted fractional part PHR of the reference phase F The second calculated value is obtained by summing the second parameter. In this embodiment, the second parameter is 1, and the second calculated value is 1-PHR F The second divider 132 divides the second calculated value by the gain factor K dtc Obtain a third calculated value, and use the third calculated value as the delay control signal DTC ctrl The digital-to-time converter 23 is outputted to achieve gain calibration of the digital-to-time converter 23 .

[0074] The digital phase-locked loop 100 of the first embodiment and the digital time converter calibration device 10 of the second embodiment of the present invention can be applied to a cellular communication system. For example, the digital phase-locked loop 100 is applied to an integrated circuit of a vehicle-mounted radar. The digital phase-locked loop 100 provides an intrinsic electrical signal for the vehicle-mounted radar to better help the above-mentioned integrated circuit process the electrical signal received and transmitted by the antenna.

[0075] The third embodiment of the present invention provides a digital time converter calibration method, which is applied to the digital phase-locked loop of the first embodiment and is implemented by using the digital time converter calibration device 10 of the second embodiment. Figure 3 FIG. 1 is a flow chart of a method for calibrating a digital-to-time converter according to a third embodiment of the present invention. It should be noted that the method of the present invention is not limited to the method of calibrating a digital-to-time converter according to a third embodiment of the present invention if substantially the same results are achieved. Figure 3 The process sequence shown is limited. Figure 3 As shown, the digital-to-time converter calibration method comprises the steps of:

[0076] S301, respectively obtain the fractional part of the reference phase and the fractional phase error output by the time-to-digital converter, wherein the reference phase is generated according to a reference clock signal, the reference phase is used to indicate the phase information of the reference clock signal, and the reference phase includes an integer part and a fractional part.

[0077] The reference phase PHR is generated by the first counter 21 , and the fractional phase error is generated by the time-to-digital converter 24 based on the phase difference between the delayed reference clock signal and the output clock signal CKV.

[0078] S302: Obtain a resolution deviation according to the fractional part of the reference phase and the fractional phase error.

[0079] Among them, first, the fractional phase error is filtered to obtain the filtered fractional phase error; then, the decimal part of the reference phase is inverted, and the inverted decimal part of the reference phase is summed with the first parameter to obtain a first calculated value; then, the filtered fractional phase error is divided by the first calculated value to obtain a resolution deviation.

[0080] S303: Obtain a gain factor according to the resolution deviation.

[0081] Among them, first, the resolution deviation is multiplied by the second parameter to obtain a third calculated value, and the third calculated value is input into an accumulator; then, the accumulator accumulates the third calculated value to obtain the gain factor and outputs it.

[0082] S304, performing gain processing on the fractional part of the reference phase according to the gain factor to generate the delay control signal, and outputting the delay control signal to the digital-to-time converter.

[0083] Among them, first, the decimal part of the reference phase is inverted, and the inverted decimal part of the reference phase is summed with the second parameter to obtain a second calculated value; then, the second calculated value is divided by the gain factor to obtain a third calculated value, and the delay control signal is generated according to the third calculated value.

[0084] It should be noted that the implementation of the digital time converter calibration method of the third embodiment of the present invention is similar to that of the digital time converter calibration device of the second embodiment, so the description is relatively simple, and the relevant parts can refer to the partial description of the second embodiment.

[0085] Application Examples

[0086] The digital phase-locked loop of the first embodiment of the present invention is applied, the digital time converter calibration device 10 in the digital phase-locked loop is turned on, the reference clock signal is multiplied by a specified factor to obtain an output clock signal and output it, the phase error detected by the phase detector 25 in the digital phase-locked loop is monitored, and the gain factor K output by the calculation module 12 in the digital phase-locked loop is calculated. dtc Monitor and see the results Figure 4 and Figure 5 shown.

[0087] Comparative Example

[0088] The digital phase-locked loop of the first embodiment of the present invention is applied, the digital time converter calibration device 10 in the digital phase-locked loop is turned on and the connection between the digital time converter calibration device 10 and the digital time converter 23 in the digital phase-locked loop is disconnected, the reference clock signal is multiplied by a specified factor to obtain an output clock signal and output it, the phase error detected by the phase detector 25 in the digital phase-locked loop is monitored, and the gain factor K output by the calculation module 12 in the digital phase-locked loop is dtc Monitor and see the results Figure 4 and Figure 5 shown.

[0089] In the application example, the digital-to-time converter calibration device 10 performs gain calibration on the digital-to-time converter 23; in the comparative example, since the connection between the digital-to-time converter calibration device 10 and the digital-to-time converter 23 is disconnected, the gain calibration of the digital-to-time converter 23 is not performed. Figure 4 As shown, compared with the comparative example, the dynamic range of the phase error detected by the phase detector 25 of the application example is greatly reduced, and the power consumption of the phase detector 25 is greatly reduced. Figure 4 and Figure 5 As shown, in the comparative example, the digital-to-time converter 23 is not gain calibrated, and the gain factor deviation is large, resulting in a phase error distribution in the range of [-0.05 0.05]. In the application example, after the digital-to-time converter 23 is gain calibrated, the gain factor can be automatically adjusted to a stable value, so that the phase error is close to 0.

[0090] A fourth embodiment of the present invention provides an electronic device 40, see Figure 6 As shown, the electronic device 40 includes a chip 41, and the chip 41 includes a digital phase-locked loop 100. For the structure, working mode and application effect of the digital phase-locked loop 100, please refer to the description of the first embodiment, the second embodiment and the third embodiment.

[0091] The above description is only an implementation mode of the present invention. It should be pointed out that, for ordinary technicians in this field, improvements can be made without departing from the creative concept of the present invention, but these all belong to the protection scope of the present invention.

Claims

1. A digital-to-time converter calibration method, applied to a digital phase-locked loop, the digital phase-locked loop comprising a digital-to-time converter and a time-to-digital converter, the digital-to-time converter being used to delay a reference clock signal according to a delay control signal to generate a delayed reference clock signal; the time-to-digital converter being used to generate a fractional phase error according to the delayed reference clock signal and an output clock signal of the digital phase-locked loop, wherein: The fractional phase error is used to indicate the phase difference between the delayed reference clock signal and the output clock signal, and is characterized by comprising: Respectively acquiring a fractional part of a reference phase and the fractional phase error output by the time-to-digital converter, wherein the reference phase is generated according to a reference clock signal, the reference phase is used to indicate phase information of the reference clock signal, and the reference phase includes an integer part and a fractional part; Obtaining a resolution deviation according to the fractional part of the reference phase and the fractional phase error; Acquire a gain factor according to the resolution deviation; Performing gain processing on the fractional part of the reference phase according to the gain factor to generate the delay control signal, and outputting the delay control signal to the digital-to-time converter.

2. The method for calibrating a digital-to-time converter according to claim 1, characterized in that: The obtaining of the resolution deviation according to the fractional part of the reference phase and the fractional phase error comprises: Filtering the fractional phase error to obtain the filtered fractional phase error; Inverting the decimal part of the reference phase, and summing the inverted decimal part of the reference phase with the first parameter to obtain a first calculated value; The filtered fractional phase error is divided by the first calculated value to obtain a resolution deviation.

3. The method for calibrating a digital-to-time converter according to claim 1 or 2, characterized in that: The obtaining a gain factor according to the resolution deviation comprises: multiplying the resolution deviation by a second parameter to obtain a third calculated value; The third calculated values ​​are accumulated to obtain the gain factor.

4. The method for calibrating a digital-to-time converter according to claim 3, characterized in that: The step of performing gain processing on the fractional part of the reference phase according to the gain factor to generate the delay control signal comprises: Inverting the decimal part of the reference phase, and summing the inverted decimal part of the reference phase with a second parameter to obtain a second calculated value; The second calculated value is divided by the gain factor to obtain a third calculated value, and the delay control signal is generated according to the third calculated value.

5. A digital-to-time converter calibration device, applied to a digital phase-locked loop, the digital phase-locked loop comprising a digital-to-time converter and a time-to-digital converter, the digital-to-time converter being used to delay a reference clock signal according to a delay control signal to generate a delayed reference clock signal; the time-to-digital converter being used to generate a fractional phase error according to the delayed reference clock signal and an output clock signal of the digital phase-locked loop, wherein: The fractional phase error is used to indicate the phase difference between the delayed reference clock signal and the output clock signal, and is characterized in that the calibration device comprises: an error detection module, used to respectively obtain a fractional part of a reference phase and the fractional phase error output by the time-to-digital converter, and obtain a resolution deviation according to the fractional part of the reference phase and the fractional phase error, wherein the reference phase is generated according to a reference clock signal, the reference phase is used to indicate phase information of the reference clock signal, and the reference phase includes an integer part and a fractional part; A calculation module, used for obtaining a gain factor according to the resolution deviation; A gain module is used to perform gain processing on the fractional part of the reference phase according to the gain factor, generate the delay control signal, and output the delay control signal to the digital-to-time converter.

6. The digital-to-time converter calibration device according to claim 5, characterized in that: The error detection module comprises: A filter, used for filtering the fractional phase error to obtain the filtered fractional phase error; A first adder, configured to sum the decimal part of the inverted reference phase and the first parameter to obtain a first calculated value; The first divider is used to divide the filtered fractional phase error by the first calculated value to obtain a resolution deviation.

7. The digital-to-time converter calibration device according to claim 5, characterized in that: The calculation module includes a multiplier and an accumulator, wherein: The multiplier is used to multiply the resolution deviation by the second parameter to obtain a third calculated value; The accumulator is used to accumulate the third calculated value to obtain the gain factor and output it.

8. The digital-to-time converter calibration device according to claim 5, characterized in that: The gain module comprises: A third adder, used for summing the decimal part of the inverted reference phase and the second parameter to obtain a second calculated value; The second divider is used for dividing the second calculated value by the gain factor to obtain a third calculated value, and outputting the third calculated value as the delay control signal to the digital-to-time converter.

9. A digital phase-locked loop, characterized in that: include: The digital-to-time converter calibration device according to any one of claims 5 to 8; A first counter, used to generate a reference phase according to a reference clock signal, wherein the reference phase is used to indicate phase information of the reference clock signal, and the reference phase includes an integer part and a fractional part; A second counter, used to generate a variable phase according to the output clock signal, wherein the variable phase is used to indicate phase information of the output clock signal; A digital time converter, used for delaying the reference clock signal according to a delay control signal to generate a delayed reference clock signal; a time-to-digital converter, configured to generate a fractional phase error based on the delayed reference clock signal and the output clock signal, wherein the fractional phase error is used to indicate a phase difference between the delayed reference clock signal and the output clock signal; a phase detector for generating a phase error based on the integer part of the reference phase, the fractional phase error and the variable phase; A digital loop filter, used for smoothing the phase error; A digitally controlled oscillator is used to generate an adjustment value of a frequency control word according to the phase error after smoothing, and to generate the output clock signal according to the adjustment value of the frequency control word.

10. An electronic device, characterized in that: The electronic device comprises a chip, and the chip comprises the digital phase-locked loop according to claim 9.

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