Organic Light-Emitting Display Device

Abstract

An organic light emitting display device may include: a display panel including a first display area and a second display area, and displaying an image on a first surface of the display panel, the first display area including a first sub-pixel area and having a first resolution, the second display area including a second sub-pixel area and a first transmissive area, and having a second resolution lower than the first resolution; and a first optical module disposed on a second surface of the display panel opposite to the first surface of the display panel to overlap with the second display area. Accordingly, an image can be displayed even at a portion where the optical module is disposed.

Description

Technical Field

[0001] Embodiments generally relate to an organic light emitting display device. More specifically, embodiments of the inventive concept relate to an organic light emitting display device including an optical module. Background Art

[0002] Flat panel display devices are used as display devices for replacing cathode ray tube display devices due to their light weight and thinness. As a representative example of such flat panel display devices, there are liquid crystal display devices and organic light emitting display devices.

[0003] The organic light emitting display device may include a non-display area and a display area for displaying an image, and the optical module may be disposed in the non-display area. For example, the optical module may include at least one of a camera module for capturing an image of an object located above a first surface of the organic light emitting display device, a face recognition sensor module for detecting a user's face, a pupil recognition sensor module for detecting a user's pupil, an acceleration sensor module and a geomagnetic sensor module for determining movement of the organic light emitting display device, a proximity sensor module and an infrared sensor module for detecting proximity to the front side of the organic light emitting display device, and an illuminance sensor module for measuring brightness when placed in a pocket or a bag. Since the optical module is disposed in the non-display area of the organic light emitting display device, an image may not be displayed in a portion where the optical module is disposed. Summary of the Invention

[0004] Problems to be Solved

[0005] Some embodiments provide an organic light emitting display device including an optical module.

[0006] However, the object of the inventive concept is not limited thereto. Thus, the object of the inventive concept may be extended without departing from the spirit and scope of the inventive concept.

[0007] Means for Solving the Problems

[0008] According to some embodiments, an organic light emitting display device includes a display panel and a first optical module. The display panel includes a first display area and a second display area. The first display area includes a first sub-pixel area and has a first resolution. The second display area includes a second sub-pixel area and a first transmissive area and has a second resolution lower than the first resolution. The display panel is configured to display an image on a first surface of the display panel. The first optical module is disposed on a second surface of the display panel opposite to the first surface to overlap with the second display area.

[0009] In an embodiment, the display panel may further include a first sub-pixel circuit and a second sub-pixel circuit. The first sub-pixel circuit may be disposed in a first display area. The second sub-pixel circuit may be disposed in a second display area and may be different from the first sub-pixel circuit.

[0010] In an embodiment, the number of transistors constituting the first sub-pixel circuit may be greater than the number of transistors constituting the second sub-pixel circuit.

[0011] In an embodiment, the display panel may further include: a first sub-pixel structure, a second sub-pixel structure, and a first transmissive window. The first sub-pixel structure may be disposed on the first sub-pixel circuit in a first sub-pixel area and may be electrically connected to the first sub-pixel circuit. The second sub-pixel structure may be disposed on the second sub-pixel circuit in a second sub-pixel area and may be electrically connected to the second sub-pixel circuit. The first transmissive window may be disposed in a first transmissive area adjacent to the second sub-pixel area.

[0012] In an embodiment, the first optical module may include a camera module, and the first optical module may be configured to identify an object located above a first surface of the display panel through the first transmissive window.

[0013] In an embodiment, the second sub-pixel circuit may not be disposed in the first transmissive area.

[0014] In an embodiment, the display panel may further include: a third display area and a third sub-pixel circuit. The third display area may be adjacent to the second display area and may include a third sub-pixel area and a second transmissive area. The third display area may have a third resolution between a first resolution and a second resolution. The third sub-pixel circuit may be disposed in the third display area and may be different from the first sub-pixel circuit and the second sub-pixel circuit.

[0015] In an embodiment, the number of transistors constituting the third sub-pixel circuit may be less than the number of transistors constituting the first sub-pixel circuit and may be greater than the number of transistors constituting the second sub-pixel circuit.

[0016] In an embodiment, the organic light-emitting display device may further include: a second optical module disposed on a second surface of the display panel to overlap with the third display area.

[0017] In an embodiment, the display panel may further include: a third sub-pixel structure and a second transmissive window. The third sub-pixel structure may be disposed on the third sub-pixel circuit in the third sub-pixel area and may be electrically connected to the third sub-pixel circuit. The second transmissive window may be disposed in the second transmissive area adjacent to the third sub-pixel area.

[0018] In an embodiment, the third sub-pixel circuit may not be disposed in the second transmissive region.

[0019] In an embodiment, the second optical module may include at least one of a face recognition sensor module, a pupil recognition sensor module, an acceleration sensor module, a proximity sensor module, an infrared sensor module, and an illuminance sensor module.

[0020] In an embodiment, the size of the first optical module may be equal to the size of the second display region, and the size of the second optical module may be equal to the size of the third display region.

[0021] In an embodiment, the area of the first display region may be greater than the area of the second display region.

[0022] In an embodiment, the second display region may be located on one side of the first surface of the display panel, and the first display region may surround the second display region.

[0023] In an embodiment, the display panel may further include: a first sub-pixel circuit disposed in the first display region; and a second sub-pixel circuit disposed in the second display region, and the first sub-pixel circuit and the second sub-pixel circuit may have the same configuration.

[0024] According to some embodiments, an organic light emitting display device includes: a display panel and a first optical module. The display panel is configured to display an image on a first surface of the display panel and includes: a substrate, a first sub-pixel circuit, a second sub-pixel circuit, a sub-pixel structure, and a first transmissive window. The substrate includes a first display region and a second display region. The first display region includes a first sub-pixel region and is configured to display an image at a first resolution. The second display region includes a second sub-pixel region and a first transmissive region, and is configured to display an image at a second resolution lower than the first resolution. The first sub-pixel circuit is disposed on the substrate in the first display region. The second sub-pixel circuit is disposed on the substrate in the second display region and is configured to expose the first transmissive region. The sub-pixel structure is disposed on the substrate in the first sub-pixel region and the second sub-pixel region. The first transmissive window is formed on the substrate in the first transmissive region. The first optical module is disposed on a second surface of the display panel opposite to the first surface to overlap with the second display region.

[0025] In an embodiment, the substrate may include a first groove formed in a part of the second surface overlapping with the second display region, and the first optical module may be embedded in the first groove.

[0026] In an embodiment, the organic light emitting display device may further include: an insulating layer structure disposed on the substrate; a planarization layer disposed on the insulating layer structure; and a pixel defining layer disposed on the planarization layer.

[0027] In an embodiment, in the first transmissive region, the insulating layer structure, the planarization layer, and the pixel defining layer may include a first opening exposing the substrate, and the first opening may be defined as a first transmissive window.

[0028] In an embodiment, the organic light emitting display device may further include: a capping layer disposed on the pixel defining layer. The capping layer may have a first thickness in the first sub-pixel region and a second thickness less than the first thickness in the second sub-pixel region and the first transmissive region.

[0029] In an embodiment, the substrate may further include: a third display region and a third sub-pixel circuit. The third display region may be adjacent to the second display region and may include a third sub-pixel region and a second transmissive region. The third display region may be configured to display an image at a second resolution. The third sub-pixel circuit may be disposed in the third display region and may have the same configuration as the second sub-pixel circuit.

[0030] In an embodiment, the number of transistors constituting the third sub-pixel circuit may be equal to the number of transistors constituting the second sub-pixel circuit.

[0031] In an embodiment, the organic light emitting display device may further include: a second optical module disposed on the second surface of the display panel to overlap with the third display region.

[0032] In an embodiment, the substrate may include a second groove formed in a part of the second surface overlapping with the third display region, and the second optical module may be embedded in the second groove.

[0033] In an embodiment, the substrate may further include: a third sub-pixel structure and a second transmissive window. The third sub-pixel structure may be disposed on the third sub-pixel circuit in the third sub-pixel region and may be electrically connected to the third sub-pixel circuit. The second transmissive window may be disposed in the second transmissive region adjacent to the third sub-pixel region.

[0034] In an embodiment, the third sub-pixel circuit may not be disposed in the second transmissive region.

[0035] In an embodiment, in the second transmissive region, the insulating layer structure, the planarization layer, and the pixel defining layer may include a second opening exposing the substrate, and the second opening may be defined as a second transmissive window.

[0036] In an embodiment, the first sub-pixel circuit may have the same configuration as each of the second sub-pixel circuit and the third sub-pixel circuit, and the size of the first transmissive window may be equal to the size of the second transmissive window.

[0037] In an embodiment, the configuration of the second sub-pixel circuit may be different from the configuration of the third sub-pixel circuit, and the size of the first transmissive window may be different from the size of the second transmissive window.

[0038] In an embodiment, the number of transistors constituting the third sub-pixel circuit may be greater than the number of transistors constituting the second sub-pixel circuit.

[0039] In an embodiment, the size of the second transmissive window may be smaller than the size of the first transmissive window.

[0040] In an embodiment, each of the first sub-pixel circuit and the second sub-pixel circuit may include at least one semiconductor element and at least one capacitor.

[0041] In an embodiment, each sub-pixel structure may include: a lower electrode disposed on the first sub-pixel circuit and the second sub-pixel circuit; a light-emitting layer disposed on the lower electrode; and an upper electrode disposed on the light-emitting layer.

[0042] In an embodiment, the upper electrode may not be disposed in the first transmissive region.

[0043] According to some embodiments, an organic light-emitting display device includes a display panel, a first optical module, and a second optical module. The display panel includes a first display region, a second display region, and a non-display region. The first display region includes a first sub-pixel region and has a first resolution. The second display region includes a second sub-pixel region and a first transmissive region, and has a second resolution lower than the first resolution. The non-display region includes a second transmissive region and does not display an image. The display panel is configured to display an image on a first surface of the display panel. The first optical module is disposed on a second surface of the display panel opposite to the first surface to overlap with the non-display region. The second optical module is disposed on the second surface of the display panel to overlap with the second sub-pixel region.

[0044] In an embodiment, the first optical module may include a camera module, and the first optical module may be configured to identify an object located above the first surface of the display panel through the second transmissive region.

[0045] In an embodiment, the second optical module may include at least one of a face recognition sensor module, a pupil recognition sensor module, an acceleration sensor module, a proximity sensor module, an infrared sensor module, and an illuminance sensor module.

[0046]

Advantages of the Invention

[0047] Since the organic light emitting display device according to an embodiment of the present invention includes a first display area having a first resolution and second and third display areas having a second resolution lower than the first resolution, an image can also be displayed in a portion where the first optical module and the second optical module are arranged. In addition, since the organic light emitting display device includes a first transmission window and a second transmission window, the first optical module and the second optical module can detect the surrounding environment or capture an image of an object located above the first surface of the display panel through the first transmission window and the second transmission window.

[0048] However, the effects of the present invention are not limited thereto. Therefore, the effects of the present invention can be extended without departing from the spirit and scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 is a perspective view showing an organic light emitting display device according to an embodiment of the present invention.

[0050] Figure 2 is a perspective view showing an optical module disposed on the rear surface of Figure 1 the organic light emitting display device.

[0051] Figure 3 is a plan view showing a first display area, a second display area, and a third display area of Figure 1 the organic light emitting display device.

[0052] Figure 4 is a partially enlarged plan view showing a part of Figure 3 the first display area.

[0053] Figure 5 is a circuit diagram showing a first sub-pixel circuit and a first organic light emitting diode disposed in Figure 4 the first display area.

[0054] Figure 6 is a partially enlarged plan view showing a part of Figure 3 the second display area.

[0055] Figure 7 is a partially enlarged plan view showing an example of Figure 3 the second display area.

[0056] Figure 8 is a circuit diagram showing a second sub-pixel circuit and a second organic light emitting diode disposed in Figure 6 the second display area.

[0057] Figure 9 is a partially enlarged plan view showing a part of Figure 3 the third display area.

[0058] Figure 10 is a circuit diagram showing a third sub-pixel circuit and a third organic light-emitting diode disposed in a third display area of Figure 9 .

[0059] Figure 11 is a cross-sectional view taken along line I-I' of an organic light-emitting display device of Figure 4 .

[0060] Figure 12 is a cross-sectional view taken along line II-II' of an organic light-emitting display device of Figure 6 .

[0061] Figure 13 is a cross-sectional view taken along line III-III' of an organic light-emitting display device of Figure 9 .

[0062] Figure 14 is a plan view showing an organic light-emitting display device according to an embodiment of the present invention.

[0063] Figure 15 is a partially enlarged plan view showing a part of a second display area of Figure 14 .

[0064] Figure 16 is a circuit diagram showing a second sub-pixel circuit and a second organic light-emitting diode disposed in a second display area of Figure 15 .

[0065] Figure 17 is a partially enlarged plan view showing a part of a third display area of Figure 14 .

[0066] Figure 18 is a circuit diagram showing a third sub-pixel circuit and a third organic light-emitting diode disposed in a third display area of Figure 15 .

[0067] Figure 19 is a plan view showing an organic light-emitting display device according to an embodiment of the present invention.

[0068] Figure 20 is a partially enlarged plan view showing a part of a third display area of Figure 19 .

[0069] Figure 21 is a circuit diagram showing a third sub-pixel circuit and a third organic light-emitting diode disposed in a third display area of Figure 20 .

[0070] Figure 22is a perspective view showing an organic light emitting display device according to an embodiment of the present invention.

[0071] Figure 23 is a perspective view showing an optical module embedded in Figure 22 the organic light emitting display device.

[0072] Figure 24 is a perspective view showing a groove formed in Figure 23 the organic light emitting display device.

[0073] Figure 25 is a plan view showing an organic light emitting display device according to an embodiment of the present invention.

[0074] Figure 26 is a plan view showing an enlarged Figure 25 non-display area of

[0075] Figure 27 is a cross-sectional view taken along line IV-IV’ of Figure 26 the organic light emitting display device. Detailed Description of the Invention

[0076] Hereinafter, an organic light emitting display device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same or similar reference numerals are used for the same or similar components.

[0077] Figure 1 is a perspective view showing an organic light emitting display device according to an embodiment of the present invention, Figure 2 is a perspective view showing an optical module disposed on the rear surface of Figure 1 the organic light emitting display device, and Figure 3 is a plan view showing Figure 1 the first display area, the second display area, and the third display area of the organic light emitting display device.

[0078] Referring to Figures 1 to 3 , the organic light emitting display device 100 may include a display panel 200, a first optical module 410, a second optical module 420, etc. The display panel 200 may have a first surface S1 for displaying an image and a second surface S2 opposite to the first surface S1. The first optical module 410 and the second optical module 420 may be disposed on one side of the second surface S2 of the display panel 200, and the first optical module 410 and the second optical module 420 may be adjacent to each other.

[0079] The display panel 200 may include a first display area 10, a second display area 20, and a third display area 30. In this case, each of the second display area 20 and the third display area 30 may be located on one side of the first surface S1 of the display panel 200, and the second display area 20 and the third display area 30 may be adjacent to each other. In addition, the first display area 10 may surround the second display area 20 and the third display area 30, and the area of the first display area 10 may be greater than the area of each of the second display area 20 and the third display area 30.

[0080] The first display area 10 may include a plurality of first sub-pixel areas (e.g., corresponding to the first sub-pixel area 11 of Figure 4 ), the second display area 20 may include a plurality of second sub-pixel areas and a plurality of first transmissive areas (e.g., corresponding to the second sub-pixel area 12 and the first transmissive area 21 of Figure 6 ), and the third display area 30 may include a plurality of third sub-pixel areas and a plurality of second transmissive areas (e.g., corresponding to the third sub-pixel area 13 and the second transmissive area 22 of Figure 9 ). In an embodiment, the display panel 200 may display images at different resolutions in the first display area 10 and in the second display area 20 and the third display area 30. For example, an image may be displayed at a first resolution in the first display area 10, and an image may be displayed at a second resolution lower than the first resolution in the second display area 20 and the third display area 30. In other words, the first display area 10 may have a first resolution, and each of the second display area 20 and the third display area 30 may have a second resolution.

[0081] The first optical module 410 may be disposed on the second surface S2 of the display panel 200 to overlap with the second display area 20. In other words, the size of the second display area 20 may be substantially equal to the size of the first optical module 410. That is to say, the shape of the second display area 20 may be defined according to the shape of the first optical module 410. The first optical module 410 may include a camera module for capturing (or recognizing) an image of an object located above the first surface S1 of the display panel 200.

[0082] The second optical module 420 may be disposed on the second surface S2 of the display panel 200 to overlap with the third display area 30. In other words, the size of the third display area 30 may be substantially equal to the size of the second optical module 420. That is to say, the shape of the third display area 30 may be defined according to the shape of the second optical module 420. The second optical module 420 may include at least one of a face recognition sensor module for detecting a user's face, a pupil recognition sensor module for detecting a user's pupil, an acceleration sensor module and a geomagnetic sensor module for determining the movement of the organic light-emitting display device 100, a proximity sensor module and an infrared sensor module for detecting proximity to the front side of the organic light-emitting display device 100, and an illuminance sensor module for measuring the brightness when placed in a pocket or a bag.

[0083] Figure 4 is a partially enlarged plan view of a part of the first display area, and Figure 3 and Figure 5 is a circuit diagram showing the first sub-pixel circuit and the first organic light-emitting diode disposed in Figure 4 the first display area.

[0084] Referring to Figure 3 、 Figure 4 and Figure 5 , the display panel 200 may further include a first sub-pixel circuit SPC1 and a first organic light-emitting diode OLED1. In addition, the display panel 200 may have a first display area 10, and the first display area 10 may include a plurality of first sub-pixel areas 11. For example, the first sub-pixel areas 11 may be arranged in a first direction D1 parallel to the first surface S1 of the display panel 200 and in a second direction D2 orthogonal to the first direction D1 within the first display area 10. In other words, the first sub-pixel areas 11 may be arranged throughout the first display area 10.

[0085] Each of the first sub-pixel circuits SPC1 may overlap with the first sub-pixel area 11, and the first organic light-emitting diode OLED1 (for example, corresponding to Figure 11 the first sub-pixel structure 300 of Figure 11The first semiconductor element 250 and the second semiconductor element 255 correspond to each other). An image can be displayed in the first sub-pixel region 11 through the first sub-pixel circuit SPC1 and the first organic light-emitting diode OLED1. In some embodiments, the first sub-pixel circuit SPC1 may overlap with a part of the first sub-pixel region 11 and a part of another first sub-pixel region 11 different from the first sub-pixel region 11 (for example, a part of the first sub-pixel region 11 adjacent to the first sub-pixel region 11). In addition, the first organic light-emitting diode OLED1 may be arranged by using an RGB stripe scheme in which rectangles of the same size are sequentially arranged, an S stripe scheme including a blue organic light-emitting diode having a relatively large area, a WRGB scheme further including a white organic light-emitting diode, or a honeycomb scheme in which an RG-GB pattern is repeatedly arranged, and the like.

[0086] However, although each of the first display region 10 and the first sub-pixel region 11 according to the present invention has been described as having a rectangular shape when viewed in a plan view, the shape is not limited thereto. For example, when viewed in a plan view, each of the first display region 10 and the first sub-pixel region 11 may have a triangular shape, a rhombus shape, a polygonal shape, a circular shape, an orbital shape, or an elliptical shape.

[0087] As Figure 5 shown, the first sub-pixel circuit SPC1 may include a first transistor to a seventh transistor TR1, TR2, TR3, TR4, TR5, TR6, and TR7, a storage capacitor CST, a high power supply voltage wiring, a low power supply voltage wiring, an initialization voltage wiring, a data signal wiring, a gate signal wiring, a gate initialization signal wiring, an emission control signal wiring, a diode initialization signal wiring, and the like. In addition, the first sub-pixel circuit SPC1 and the first organic light-emitting diode OLED1 may be electrically connected to each other.

[0088] The first organic light-emitting diode OLED1 (for example, corresponding to Figure 11 the first sub-pixel structure 300) may output light based on the driving current ID. The first organic light-emitting diode OLED1 may include a first terminal and a second terminal. The second terminal of the first organic light-emitting diode OLED1 may receive a low power supply voltage ELVSS. For example, the first terminal of the first organic light-emitting diode OLED1 may be an anode terminal, and the second terminal of the first organic light-emitting diode OLED1 may be a cathode terminal. In some embodiments, the first terminal of the first organic light-emitting diode OLED1 may be a cathode terminal, and the second terminal of the first organic light-emitting diode OLED1 may be an anode terminal. In an embodiment, the anode terminal of the first organic light-emitting diode OLED1 may be connected to Figure 11corresponds to the first lower electrode 290, and the cathode terminal of the first organic light-emitting diode OLED1 can be Figure 11 corresponding to the first upper electrode 340.

[0089] The first transistor TR1 (for example, corresponding to Figure 11 the first semiconductor element 250) may include a gate terminal, a first terminal, and a second terminal. In an embodiment, the first terminal of the first transistor TR1 may be a source terminal, and the second terminal of the first transistor TR1 may be a drain terminal. In some embodiments, the first terminal of the first transistor TR1 may be a drain terminal, and the second terminal of the first transistor TR1 may be a source terminal.

[0090] The first transistor TR1 may generate a driving current ID. In an embodiment, the first transistor TR1 may operate in the saturation region. In this case, the first transistor TR1 may generate the driving current ID based on the voltage difference between the gate terminal and the source terminal. Additionally, the gray level may be represented based on the magnitude of the driving current ID supplied to the first organic light-emitting diode OLED1. In some embodiments, the first transistor TR1 may operate in the linear region. In this case, the gray level may be represented based on the sum of the time during which the driving current is supplied to the organic light-emitting diode within one frame.

[0091] The second transistor TR2 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the second transistor TR2 may receive a gate signal GW. The first terminal of the second transistor TR2 may receive a data signal DATA. The second terminal of the second transistor TR2 may be connected to the first terminal of the first transistor TR1. In an embodiment, the first terminal of the second transistor TR2 may be a source terminal, and the second terminal of the second transistor TR2 may be a drain terminal. In some embodiments, the first terminal of the second transistor TR2 may be a drain terminal, and the second terminal of the second transistor TR2 may be a source terminal.

[0092] The second transistor TR2 may supply the data signal DATA to the first terminal of the first transistor TR1 during the activation period of the gate signal GW. In this case, the second transistor TR2 may operate in the linear region.

[0093] The third transistor TR3 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the third transistor TR3 may receive a gate signal GW. The first terminal of the third transistor TR3 may be connected to the gate terminal of the first transistor TR1. The second terminal of the third transistor TR3 may be connected to the second terminal of the first transistor TR1. In an embodiment, the first terminal of the third transistor TR3 may be a source terminal, and the second terminal of the third transistor TR3 may be a drain terminal. In some embodiments, the first terminal of the third transistor TR3 may be a drain terminal, and the second terminal of the third transistor TR3 may be a source terminal.

[0094] The third transistor TR3 may connect the gate terminal of the first transistor TR1 to the second terminal of the first transistor TR1 during an activation period of the gate signal GW. In this case, the third transistor TR3 may operate in the linear region. In other words, the third transistor TR3 may diode-connect the first transistor TR1 during the activation period of the gate signal GW. Since the first transistor TR1 is diode-connected, a voltage difference corresponding to the threshold voltage of the first transistor TR1 may be generated between the first terminal and the gate terminal of the first transistor TR1. As a result, during the activation period of the gate signal GW, a voltage obtained by adding the voltage difference (i.e., the threshold voltage) to the voltage of the data signal DATA supplied to the first terminal of the first transistor TR1 may be supplied to the gate terminal of the first transistor TR1. In other words, the data signal DATA may be compensated by the threshold voltage of the first transistor TR1, and the compensated data signal DATA may be supplied to the gate terminal of the first transistor TR1. Since the threshold voltage compensation is performed, the problem of non-uniform drive current caused by the deviation of the threshold voltage of the first transistor TR1 may be solved.

[0095] An input terminal of an initialization voltage wiring provided with an initialization voltage VINT may be connected to the first terminals of the fourth transistor TR4 and the seventh transistor TR7, and an output terminal of the initialization voltage wiring may be connected to the second terminal of the fourth transistor TR4 and the first terminal of the storage capacitor CST.

[0096] The fourth transistor TR4 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the fourth transistor TR4 may receive a gate initialization signal GI. The first terminal of the fourth transistor TR4 may receive the initialization voltage VINT. The second terminal of the fourth transistor TR4 may be connected to the gate terminal of the first transistor TR1. In an embodiment, the first terminal of the fourth transistor TR4 may be a source terminal, and the second terminal of the fourth transistor TR4 may be a drain terminal. In some embodiments, the first terminal of the fourth transistor TR4 may be a drain terminal, and the second terminal of the fourth transistor TR4 may be a source terminal.

[0097] The fourth transistor TR4 may supply an initialization voltage VINT to the gate terminal of the first transistor TR1 during the activation period of the gate initialization signal GI. In this case, the fourth transistor TR4 may operate in the linear region. In other words, the fourth transistor TR4 may initialize the gate terminal of the first transistor TR1 to the initialization voltage VINT during the activation period of the gate initialization signal GI. In an embodiment, the initialization voltage VINT may have a voltage level sufficiently lower than the voltage level of the data signal DATA maintained by the storage capacitor CST in the previous frame, and the initialization voltage VINT may be supplied to the gate terminal of the first transistor TR1 which is a P-channel metal oxide semiconductor (PMOS) transistor. In other embodiments, the initialization voltage VINT may have a voltage level sufficiently higher than the voltage level of the data signal DATA maintained by the storage capacitor CST in the previous frame, and the initialization voltage VINT may be supplied to the gate terminal of the first transistor TR1 which is an N-channel metal oxide semiconductor (NMOS) transistor.

[0098] In an embodiment, the gate initialization signal GI may be a signal substantially the same as the gate signal GW one horizontal time before. For example, the gate initialization signal GI supplied to the sub-pixel circuit in the nth row (where n is an integer greater than or equal to 2) among the plurality of sub-pixel circuits included in the organic light emitting display device 100 may be a signal substantially the same as the gate signal GW supplied to the sub-pixel circuit in the (n - 1)th row among the sub-pixel circuits. In other words, by supplying the activated gate signal GW to the first sub-pixel circuit in the (n - 1)th row among the first sub-pixel circuits SPC1, the activated gate initialization signal GI may be supplied to the first sub-pixel circuit in the nth row among the first sub-pixel circuits SPC1. As a result, when the data signal DATA is supplied to the sub-pixel circuit in the (n - 1)th row among the sub-pixel circuits, the gate terminal of the first transistor TR1 in the sub-pixel circuit in the nth row included in the first sub-pixel circuits SPC1 may be initialized to the initialization voltage VINT.

[0099] The fifth transistor TR5 may include a gate terminal, a first terminal, and a second terminal. The gate terminal may receive an emission control signal EM. The first terminal may be connected to a high power supply voltage wiring. The second terminal may be connected to the first terminal of the first transistor TR1. In an embodiment, the first terminal of the fifth transistor TR5 may be a source terminal, and the second terminal of the fifth transistor TR5 may be a drain terminal. In some embodiments, the first terminal of the fifth transistor TR5 may be a drain terminal, and the second terminal of the fifth transistor TR5 may be a source terminal.

[0100] The fifth transistor TR5 can supply a high power supply voltage ELVDD to the first terminal of the first transistor TR1 during the activation period of the emission control signal EM. Conversely, the fifth transistor TR5 can cut off the supply of the high power supply voltage ELVDD during the non-activation period of the emission control signal EM. In this case, the fifth transistor TR5 can operate in the linear region. Since the fifth transistor TR5 supplies the high power supply voltage ELVDD to the first terminal of the first transistor TR1 during the activation period of the emission control signal EM, the first transistor TR1 can generate a drive current ID. Additionally, since the fifth transistor TR5 cuts off the supply of the high power supply voltage ELVDD during the non-activation period of the emission control signal EM, the data signal DATA supplied to the first terminal of the first transistor TR1 can be supplied to the gate terminal of the first transistor TR1.

[0101] The sixth transistor TR6 (e.g., corresponding to Figure 11 the second semiconductor element 255) can include a gate terminal, a first terminal, and a second terminal. The gate terminal can receive the emission control signal EM. The first terminal can be connected to the second terminal of the first transistor TR1. The second terminal can be connected to the first terminal of the first organic light emitting diode OLED1. In an embodiment, the first terminal of the sixth transistor TR6 can be a source terminal, and the second terminal of the sixth transistor TR6 can be a drain terminal. In some embodiments, the first terminal of the sixth transistor TR6 can be a drain terminal, and the second terminal of the sixth transistor TR6 can be a source terminal.

[0102] The sixth transistor TR6 can supply the drive current ID generated by the first transistor TR1 to the first organic light emitting diode OLED1 during the activation period of the emission control signal EM. In this case, the sixth transistor TR6 can operate in the linear region. In other words, since the sixth transistor TR6 supplies the drive current ID generated by the first transistor TR1 to the first organic light emitting diode OLED1 during the activation period of the emission control signal EM, the first organic light emitting diode OLED1 can output light. Additionally, since the sixth transistor TR6 electrically isolates the first transistor TR1 from the first organic light emitting diode OLED1 during the non-activation period of the emission control signal EM, the data signal DATA (more precisely, the data signal that has undergone threshold voltage compensation) supplied to the second terminal of the first transistor TR1 can be supplied to the gate terminal of the first transistor TR1.

[0103] The seventh transistor TR7 may include a gate terminal, a first terminal, and a second terminal. The gate terminal may receive a diode initialization signal GB. The first terminal may receive an initialization voltage VINT. The second terminal may be connected to the first terminal of the first organic light-emitting diode OLED1. In an embodiment, the first terminal of the seventh transistor TR7 may be a source terminal, and the second terminal of the seventh transistor TR7 may be a drain terminal. In some embodiments, the first terminal of the seventh transistor TR7 may be a drain terminal, and the second terminal of the seventh transistor TR7 may be a source terminal.

[0104] The seventh transistor TR7 may supply the initialization voltage VINT to the first terminal of the first organic light-emitting diode OLED1 during an activation period of the diode initialization signal GB. In this case, the seventh transistor TR7 may operate in the linear region. In other words, the seventh transistor TR7 may initialize the first terminal of the first organic light-emitting diode OLED1 to the initialization voltage VINT during the activation period of the diode initialization signal GB.

[0105] In some embodiments, the gate initialization signal GI and the diode initialization signal GB may be substantially the same signal. The operation of initializing the gate terminal of the first transistor TR1 and the operation of initializing the first terminal of the first organic light-emitting diode OLED1 may not affect each other. In other words, the operation of initializing the gate terminal of the first transistor TR1 and the operation of initializing the first terminal of the first organic light-emitting diode OLED1 may be independent of each other. Therefore, the diode initialization signal GB may not be generated separately, so that the processing economic efficiency can be improved.

[0106] The storage capacitor CST may include a first terminal and a second terminal. The storage capacitor CST may be connected between a high power supply voltage wiring and the gate terminal of the first transistor TR1. For example, the first terminal of the storage capacitor CST may be connected to the gate terminal of the first transistor TR1, and the second terminal of the storage capacitor CST may be connected to the high power supply voltage wiring. The storage capacitor CST may maintain the voltage level of the gate terminal of the first transistor TR1 during a non-activation period of the gate signal GW. The non-activation period of the gate signal GW may include an activation period of the emission control signal EM, and during the activation period of the emission control signal EM, the driving current ID generated by the first transistor TR1 may be supplied to the first organic light-emitting diode OLED1. Therefore, the driving current ID generated by the first transistor TR1 based on the voltage level maintained by the storage capacitor CST may be supplied to the first organic light-emitting diode OLED1.

[0107] However, although the first sub-pixel circuit SPC1 according to the present invention is described as including seven transistors and one storage capacitor, the configuration of the present invention is not limited thereto. For example, the first sub-pixel circuit SPC1 may have a configuration including at least one transistor and at least one storage capacitor.

[0108] Figure 6 is a partially enlarged plan view of a part of the second display area showing Figure 3 and is a partially enlarged plan view of an example of the second display area showing Figure 7 and is a circuit diagram showing the second sub-pixel circuit and the second organic light-emitting diode arranged in the second display area of Figure 3 The second sub-pixel circuit SPC2 and the second organic light-emitting diode OLED2 illustrated in Figure 8 may have a configuration substantially the same as or similar to the configuration of the first sub-pixel circuit SPC1 and the first organic light-emitting diode OLED1 described with reference to Figure 6 In Figure 8 the redundant description of components substantially the same as or similar to the components described with reference to Figure 5 will be omitted. Figure 8 In Figure 5 reference to

[0109] Referring to Figure 3 , Figure 6 and Figure 8 , the display panel 200 may further include a second sub-pixel circuit SPC2 and a second organic light-emitting diode OLED2. Additionally, the display panel 200 may have a second display area 20, and the second display area 20 may include a plurality of second sub-pixel areas 12 and a plurality of first transmissive areas 21. For example, the second sub-pixel areas 12 may be arranged in the first direction D1 within the second display area 20, and the first transmissive areas 21 may be arranged in a row different from the row in which the second sub-pixel areas 12 are arranged in the first direction D1. In other words, the second sub-pixel areas 12 and the first transmissive areas 21 may be arranged throughout the entire second display area 20. In an embodiment, when compared with the first sub-pixel areas 11 arranged in the first display area 10 of Figure 4 , the second display area 20 may include a relatively small number of sub-pixel areas per unit area due to the first transmissive areas 21. In other words, the second resolution of the second display area 20 may be lower than the first resolution of the first display area 10.

[0110] Each of the second sub-pixel circuits SPC2 may overlap with the second sub-pixel areas 12, and the second organic light-emitting diodes OLED2 (for example, corresponding to the second sub-pixel structure 600 of Figure 12 ) may be arranged in the second sub-pixel circuits SPC2 (for example, corresponding toFigure 12 corresponding to the third semiconductor element 550 and the fourth semiconductor element 555). An image can be displayed in the second sub-pixel region 12 through the second sub-pixel circuit SPC2 and the second organic light-emitting diode OLED2.

[0111] In some embodiments, the second sub-pixel circuit SPC2 may overlap with a part of the second sub-pixel region 12 and a part of another second sub-pixel region 12 different from the second sub-pixel region 12 (e.g., a part of the second sub-pixel region 12 adjacent to the second sub-pixel region 12). Additionally, the second organic light-emitting diodes OLED2 may be arranged by using an RGB stripe scheme in which rectangles having the same size are sequentially arranged, an S stripe scheme including a blue organic light-emitting diode having a relatively large area, a WRGB scheme further including a white organic light-emitting diode, or a honeycomb scheme in which an RG-GB pattern is repeatedly arranged, and the like.

[0112] In addition, the first optical module 410 disposed on the second surface S2 of the display panel 200 may capture an image of an object located above the first surface S1 of the display panel 200 through the first transmissive region 21. In other words, the first transmissive region 21 may be substantially transparent.

[0113] In other embodiments, as Figure 7 shown, the second display region 20 may include a first transmissive region 31 having a relatively large area. In other words, the second display region 20 may include a relatively small number of sub-pixel regions per unit area due to the first transmissive region 31 having a relatively large area. In this case, even when the resolution of the second display region 20 becomes relatively low, the first optical module 410 may relatively easily identify an image of an object located above the first surface S1 of the display panel 200 due to the first transmissive region 31 having a relatively large area.

[0114] However, although each of the second display region 20, the second sub-pixel region 12, and the first transmissive region 21 according to the present invention is described as having a rectangular shape when viewed in a plan view, the shape is not limited thereto. For example, when viewed in a plan view, each of the second display region 20, the second sub-pixel region 12, and the first transmissive region 21 may have a triangular shape, a rhombus shape, a polygonal shape, a circular shape, an orbital shape, or an elliptical shape.

[0115] As Figure 8As shown, the second sub-pixel circuit SPC2 may include a first transistor to a seventh transistor TR1, TR2, TR3, TR4, TR5, TR6, and TR7, a storage capacitor CST, a high power supply voltage wiring, a low power supply voltage wiring, an initialization voltage wiring, a data signal wiring, a gate signal wiring, a gate initialization signal wiring, an emission control signal wiring, a diode initialization signal wiring, etc. Additionally, the second sub-pixel circuit SPC2 and the second organic light-emitting diode OLED2 may be electrically connected to each other. In this case, the first transistor TR1 of the second sub-pixel circuit SPC2 may correspond to Figure 12 the third semiconductor element 550, and the sixth transistor TR6 of the second sub-pixel circuit SPC2 may correspond to Figure 12 the fourth semiconductor element 555. Additionally, the second organic light-emitting diode OLED2 may correspond to Figure 12 the second sub-pixel structure 600, the anode terminal of the second organic light-emitting diode OLED2 may correspond to Figure 12 the second lower electrode 690, and the cathode terminal of the second organic light-emitting diode OLED2 may correspond to Figure 12 the second upper electrode 640.

[0116] In an embodiment, the second sub-pixel circuit SPC2 may not be disposed in the first transmissive region 21. In other words, the second sub-pixel circuit SPC2 may expose the first transmissive region 21.

[0117] Additionally, the configurations of the first sub-pixel circuit SPC1 and the first organic light-emitting diode OLED1 in the first display region 10 may be substantially the same as those of the second sub-pixel circuit SPC2 and the second organic light-emitting diode OLED2 in the second display region 20. In other words, the number of transistors included in the first sub-pixel circuit SPC1 in the first sub-pixel region 11 may be equal to the number of transistors included in the second sub-pixel circuit SPC2 in the second sub-pixel region 12.

[0118] Figure 9 is a partial enlarged plan view showing a part of the third display region of Figure 3 , and Figure 10 is a circuit diagram showing the third sub-pixel circuit and the third organic light-emitting diode disposed in the third display region of Figure 9 . Figure 10 The third sub-pixel circuit SPC3 and the third organic light-emitting diode OLED3 illustrated in Figure 5 may have configurations substantially the same as or similar to those of the first sub-pixel circuit SPC1 and the first organic light-emitting diode OLED1 described with reference to Figure 10 . In Figure 5Redundant descriptions of components described as substantially the same or similar components.

[0119] Referring to Figure 3 、 Figure 9 and Figure 10 ,the display panel 300 may further include a third sub-pixel circuit SPC3 and a third organic light-emitting diode OLED3. Additionally, the display panel 300 may have a third display area 30, and the third display area 30 may include a plurality of third sub-pixel areas 13 and a plurality of second transmissive areas 22. For example, the third sub-pixel areas 13 may be arranged in a first direction D1 within the third display area 30, and the second transmissive areas 22 may be arranged in a first direction D1 in rows different from the rows in which the third sub-pixel areas 13 are arranged. In other words, the third sub-pixel areas 13 and the second transmissive areas 22 may be arranged throughout the entire third display area 30. In an embodiment, when compared with the first sub-pixel areas 11 in the first display area 10 disposed in Figure 4 , the third display area 30 may include a relatively small number of sub-pixel areas per unit area due to the second transmissive areas 22. In other words, the second resolution of the third display area 30 may be lower than the first resolution of the first display area 10.

[0120] Each of the third sub-pixel circuits SPC3 may overlap with a third sub-pixel area 13, and the third organic light-emitting diode OLED3 (e.g., corresponding to the Figure 13 third sub-pixel structure 900) may be disposed on the third sub-pixel circuit SPC3 (e.g., corresponding to the Figure 13 fifth semiconductor element 850 and sixth semiconductor element 855). An image may be displayed in the third sub-pixel area 13 through the third sub-pixel circuit SPC3 and the third organic light-emitting diode OLED3.

[0121] In some embodiments, the third sub-pixel circuit SPC3 may overlap with a part of the third sub-pixel area 13 and a part of another third sub-pixel area 13 different from the third sub-pixel area 13 (e.g., a part of the third sub-pixel area 13 adjacent to the third sub-pixel area 13). Additionally, the third organic light-emitting diode OLED3 may be arranged by using an RGB stripe scheme in which rectangles having the same size are sequentially arranged, an S stripe scheme including a blue organic light-emitting diode having a relatively large area, a WRGB scheme further including a white organic light-emitting diode, or a honeycomb scheme in which an RG-GB pattern is repeatedly arranged, etc.

[0122] In addition, the second optical module 420 disposed in the third display area 30 on the second surface S2 of the display panel 200 may detect the surrounding environment or capture an image of an object located above the first surface S1 of the display panel 200 through the second transmissive area 22. In other words, the second transmissive area 22 may be substantially transparent.

[0123] However, although each of the third display area 30, the third sub-pixel area 13, and the second transmissive area 22 according to the present invention is described as having a rectangular shape when viewed in a plan view, the shape is not limited thereto. For example, when viewed in a plan view, each of the third display area 30, the third sub-pixel area 13, and the second transmissive area 22 may have a triangular shape, a rhombus shape, a polygonal shape, a circular shape, an orbital shape, or an elliptical shape.

[0124] As Figure 10 shown, the third sub-pixel circuit SPC3 may include first to seventh transistors TR1, TR2, TR3, TR4, TR5, TR6, and TR7, a storage capacitor CST, a high power supply voltage wiring, a low power supply voltage wiring, an initialization voltage wiring, a data signal wiring, a gate signal wiring, a gate initialization signal wiring, an emission control signal wiring, and a diode initialization signal wiring, etc. In addition, the third sub-pixel circuit SPC3 and the third organic light emitting diode OLED3 may be electrically connected to each other. In this case, the first transistor TR1 of the third sub-pixel circuit SPC3 may correspond to Figure 13 the fifth semiconductor element 850, and the sixth transistor TR6 of the third sub-pixel circuit SPC3 may correspond to Figure 13 the sixth semiconductor element 855. In addition, the third organic light emitting diode OLED3 may correspond to Figure 13 the third sub-pixel structure 900, the anode terminal of the third organic light emitting diode OLED3 may correspond to Figure 13 the third lower electrode 890, and the cathode terminal of the third organic light emitting diode OLED3 may correspond to Figure 13 the third upper electrode 940.

[0125] In an embodiment, the third sub-pixel circuit SPC3 may not be disposed in the second transmissive area 22. In other words, the third sub-pixel circuit SPC3 may expose the second transmissive area 22.

[0126] In addition, the configuration of the first sub-pixel circuit SPC1 and the first organic light emitting diode OLED1 in the first display area 10 may be substantially the same as the configuration of the third sub-pixel circuit SPC3 and the third organic light emitting diode OLED3 in the third display area 30. In other words, the number of transistors included in the first sub-pixel circuit SPC1 in the first sub-pixel area 11 may be equal to the number of transistors included in the third sub-pixel circuit SPC3 in the third sub-pixel area 13.

[0127] Figure 11 It is along Figure 4 A cross-sectional view of an organic light emitting display device taken along line II', Figure 12 It is along Figure 6 A cross-sectional view of an organic light emitting display device taken along line II-II', and Figure 13 It is along Figure 9 A cross-sectional view of an organic light emitting display device taken along line III-III'.

[0128] Reference Figure 11 , Figure 12 and Figure 13 , the organic light emitting display device 100 may include a display panel 200, a first optical module 410, a second optical module 420, etc. In this case, the display panel 200 may include a substrate 110, a first semiconductor element 250, a second semiconductor element 255, a third semiconductor element 550, a fourth semiconductor element 555, a fifth semiconductor element 850, a sixth semiconductor element 855, an insulating layer structure 260, a planarization layer 270, a pixel defining layer 310, a first sub-pixel structure 300, a second sub-pixel structure 600, a third sub-pixel structure 900, a capping layer 345, and an encapsulation substrate 450, etc.

[0129] In addition, the first semiconductor element 250 may include a first active layer 130, a first gate electrode 170, a first source electrode 210, and a first drain electrode 230, and the second semiconductor element 255 may include a second active layer 135, a second gate electrode 175, a second source electrode 215, and a second drain electrode 235. The third semiconductor element 550 may include a third active layer 430, a third gate electrode 470, a third source electrode 510, and a third drain electrode 530, and the fourth semiconductor element 555 may include a fourth active layer 435, a fourth gate electrode 475, a fourth source electrode 515, and a fourth drain electrode 535. The fifth semiconductor element 850 may include a fifth active layer 730, a fifth gate electrode 770, a fifth source electrode 810, and a fifth drain electrode 830, and the sixth semiconductor element 855 may include a sixth active layer 735, a sixth gate electrode 775, a sixth source electrode 815, and a sixth drain electrode 835. The insulating layer structure 260 may include a gate insulating layer 150 and an interlayer insulating layer 190.

[0130] In addition, the first sub-pixel structure 300 may include a first lower electrode 290, a first light-emitting layer 330, and a first upper electrode 340. The second sub-pixel structure 600 may include a second lower electrode 690, a second light-emitting layer 630, and a second upper electrode 640. And the third sub-pixel structure 900 may include a third lower electrode 890, a third light-emitting layer 930, and a third upper electrode 940. Since the display panel 200 includes a first display area 10 including the first sub-pixel area 11, a second display area 20 including the second sub-pixel area 12 and the first transmissive area 21, and a third display area 30 including the third sub-pixel area 13 and the second transmissive area 22, the substrate 110 may be divided into a first display area 10 including the first sub-pixel area 11, a second display area 20 including the second sub-pixel area 12 and the first transmissive area 21, and a third display area 30 including the third sub-pixel area 13 and the second transmissive area 22.

[0131] The substrate 110 may be provided including a transparent or opaque material. The substrate 100 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz (F-doped quartz) substrate, a soda-lime glass substrate, and a non-alkali glass substrate, etc.

[0132] In some embodiments, the substrate 110 may be a flexible transparent resin substrate. Examples of the transparent resin substrate that may be used as the substrate 110 include a polyimide substrate. In this case, the polyimide substrate may include a first polyimide layer, a barrier film layer, and a second polyimide layer, etc. For example, the polyimide substrate may have a configuration in which the first polyimide layer, the barrier film layer, and the second polyimide layer are sequentially stacked on a rigid glass substrate. In the method of manufacturing the organic light-emitting display device 100, after arranging an insulating layer (e.g., a buffer layer (not shown)) on the second polyimide layer of the polyimide substrate, an upper structure (e.g., the first semiconductor element to the sixth semiconductor elements 250, 255, 550, 555, 850, and 855, the first sub-pixel structure to the third sub-pixel structures 300, 600, and 900, etc.) may be formed on the insulating layer. After forming the upper structure, the rigid glass substrate may be removed. In other words, since the polyimide substrate is thin and flexible, it may be difficult to directly form the upper structure on the polyimide substrate. Considering the above fact, the upper structure is formed using a rigid glass substrate, and then the glass substrate is removed so that the polyimide substrate can be used as the substrate 110.

[0133] A buffer layer (not shown) may be disposed on the substrate 110. The buffer layer may be disposed throughout the substrate 110. The buffer layer may prevent metal atoms or impurities from diffusing from the substrate 110 to the upper structure. In addition, when the surface of the substrate 110 is uneven, the buffer layer may be used to improve the flatness of the surface of the substrate 110. Depending on the type of the substrate 110, at least two buffer layers may be provided on the substrate 110, or the buffer layer may not be provided. For example, the buffer layer may include an organic material or an inorganic material.

[0134] The first active layer 130, the second active layer 135, the third active layer 430, the fourth active layer 435, the fifth active layer 730, and the sixth active layer 735 may be disposed on the substrate 110. For example, the first active layer 130 and the second active layer 135 may be spaced apart from each other in the first display region 10 on the substrate 110, and the third active layer 430 and the fourth active layer 435 may be spaced apart from each other in the second display region 20 except for the first transmission region 21 on the substrate 110. The fifth active layer 730 and the sixth active layer 735 may be spaced apart from each other in the third display region 30 except for the second transmission region 22 on the substrate 110. Each of the first to sixth active layers 130, 135, 430, 435, 730, and 735 may include an oxide semiconductor, an inorganic semiconductor (e.g., amorphous silicon or polysilicon), and an organic semiconductor, etc.

[0135] The gate insulating layer 150 may be disposed on the first to sixth active layers 130, 135, 430, 435, 730, and 735 and the substrate 110. In an embodiment, the gate insulating layer 150 may not be disposed in the first transmission region 21 and the second transmission region 22. In other words, the gate insulating layer 150 may have openings exposing the top surface of the substrate 110 located in the first transmission region 21 and the second transmission region 22. For example, the gate insulating layer 150 may sufficiently cover the first to sixth active layers 130, 135, 430, 435, 730, and 735 on the substrate 110, and may have a substantially flat top surface without generating steps around the first to sixth active layers 130, 135, 430, 435, 730, and 735. In some embodiments, the gate insulating layer 150 may be disposed along the contours of the first to sixth active layers 130, 135, 430, 435, 730, and 735 with a uniform thickness to cover the first to sixth active layers 130, 135, 430, 435, 730, and 735 on the substrate 110. The gate insulating layer 150 may include a silicon compound and a metal oxide, etc. For example, the gate insulating layer 150 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x Ny ) Silicon oxycarbide (SiO x C y ) Silicon carbonitride (SiC x N y ) Aluminum oxide (AlO x ) Aluminum nitride (AlN x ) Tantalum oxide (TaO x ) Hafnium oxide (HfO x ) Zirconium oxide (ZrO x ) And titanium oxide (TiO x ) etc.

[0136] The first gate electrode 170, the second gate electrode 175, the third gate electrode 470, the fourth gate electrode 475, the fifth gate electrode 770, and the sixth gate electrode 775 may be spaced apart from each other on the gate insulating layer 150. For example, the first gate electrode 170 may be disposed on a portion of the gate insulating layer 150 where the first active layer 130 is located therebelow, the second gate electrode 175 may be disposed on a portion of the gate insulating layer 150 where the second active layer 135 is located therebelow, the third gate electrode 470 may be disposed on a portion of the gate insulating layer 150 where the third active layer 430 is located therebelow, the fourth gate electrode 475 may be disposed on a portion of the gate insulating layer 150 where the fourth active layer 435 is located therebelow, the fifth gate electrode 770 may be disposed on a portion of the gate insulating layer 150 where the fifth active layer 730 is located therebelow, and the sixth gate electrode 775 may be disposed on a portion of the gate insulating layer 150 where the sixth active layer 735 is located therebelow.

[0137] Each of the first to sixth gate electrodes 170, 175, 470, 475, 770, and 775 may include metals, alloys, metal nitrides, conductive metal oxides, and transparent conductive materials, etc. For example, each of the first to sixth gate electrodes 170, 175, 470, 475, 770, and 775 may include gold (Au), silver (Ag), aluminum (Al), tungsten (W), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), aluminum-containing alloys, aluminum nitride (AlN x ) Silver-containing alloys, tungsten nitride (WN x ) Copper-containing alloys, molybdenum-containing alloys, titanium nitride (TiN x ) Tantalum nitride (TaN x ) Strontium ruthenium oxide (SrRu x O y ) Zinc oxide (ZnO x ) Indium tin oxide (ITO), tin oxide (SnO x) Indium oxide (InO x ) Gallium oxide (GaO x ) and indium zinc oxide (IZO), etc. These can be used alone or in combination with each other. In some embodiments, each of the first gate electrode to the sixth gate electrode 170, 175, 470, 475, 770, and 775 may include a multi-layer structure including multiple layers.

[0138] The interlayer insulating layer 190 may be disposed on the first gate electrode to the sixth gate electrode 170, 175, 470, 475, 770, and 775 and the gate insulating layer 150. In an embodiment, the interlayer insulating layer 190 may not be disposed in the first transmission region 21 and the second transmission region 22. In other words, the interlayer insulating layer 190 may have an opening exposing the top surface of the substrate 110 in the first transmission region 21 and the second transmission region 22. The opening of the interlayer insulating layer 190 may overlap with the opening of the gate insulating layer 150.

[0139] For example, the interlayer insulating layer 190 may sufficiently cover the first gate electrode to the sixth gate electrode 170, 175, 470, 475, 770, and 775 on the gate insulating layer 150, and may have a substantially flat top surface without generating steps around the first gate electrode to the sixth gate electrode 170, 175, 470, 475, 770, and 775. In some embodiments, the interlayer insulating layer 190 may be disposed along the contour of the first gate electrode to the sixth gate electrode 170, 175, 470, 475, 770, and 775 with a uniform thickness to cover the first gate electrode to the sixth gate electrode 170, 175, 470, 475, 770, and 775 on the gate insulating layer 150. The interlayer insulating layer 190 may include silicon compounds and metal oxides, etc. Thus, an insulating layer structure 260 including the gate insulating layer 150 and the interlayer insulating layer 190 may be formed.

[0140] The first source electrode 210, the first drain electrode 230, the second source electrode 215, the second drain electrode 235, the third source electrode 510, the third drain electrode 530, the fourth source electrode 515, the fourth drain electrode 535, the fifth source electrode 810, the fifth drain electrode 830, the sixth source electrode 815, and the sixth drain electrode 835 may be disposed on the interlayer insulating layer 190. The first source electrode 210 may be connected to the source region of the first active layer 130 through a contact hole formed by removing the first portion of the gate insulating layer 150 and the interlayer insulating layer 190, and the first drain electrode 230 may be connected to the drain region of the first active layer 130 through a contact hole formed by removing the second portion of the gate insulating layer 150 and the interlayer insulating layer 190. Additionally, the second source electrode 215 may be connected to the source region of the second active layer 135 through a contact hole formed by removing the third portion of the gate insulating layer 150 and the interlayer insulating layer 190, and the second drain electrode 235 may be connected to the drain region of the second active layer 135 through a contact hole formed by removing the fourth portion of the gate insulating layer 150 and the interlayer insulating layer 190.

[0141] The third source electrode 510 may be connected to the source region of the third active layer 430 through a contact hole formed by removing the fifth portion of the gate insulating layer 150 and the interlayer insulating layer 190, and the third drain electrode 530 may be connected to the drain region of the third active layer 430 through a contact hole formed by removing the sixth portion of the gate insulating layer 150 and the interlayer insulating layer 190. Additionally, the fourth source electrode 515 may be connected to the source region of the fourth active layer 435 through a contact hole formed by removing the seventh portion of the gate insulating layer 150 and the interlayer insulating layer 190, and the fourth drain electrode 535 may be connected to the drain region of the fourth active layer 435 through a contact hole formed by removing the eighth portion of the gate insulating layer 150 and the interlayer insulating layer 190.

[0142] The fifth source electrode 810 may be connected to the source region of the fifth active layer 730 through a contact hole formed by removing the ninth portion of the gate insulating layer 150 and the interlayer insulating layer 190, and the fifth drain electrode 830 may be connected to the drain region of the fifth active layer 730 through a contact hole formed by removing the tenth portion of the gate insulating layer 150 and the interlayer insulating layer 190. Additionally, the sixth source electrode 815 may be connected to the source region of the sixth active layer 735 through a contact hole formed by removing the eleventh portion of the gate insulating layer 150 and the interlayer insulating layer 190, and the sixth drain electrode 835 may be connected to the drain region of the sixth active layer 735 through a contact hole formed by removing the twelfth portion of the gate insulating layer 150 and the interlayer insulating layer 190.

[0143] Each of the first source electrode to the sixth source electrodes 210, 215, 510, 515, 810, and 815 and the first drain electrode to the sixth drain electrodes 230, 235, 530, 535, 830, and 835 may include metals, alloys, metal nitrides, conductive metal oxides, and transparent conductive materials, etc. These may be used alone or in combination with each other. In some embodiments, each of the first source electrode to the sixth source electrodes 210, 215, 510, 515, 810, and 815 and the first drain electrode to the sixth drain electrodes 230, 235, 530, 535, 830, and 835 may have a multilayer structure including multiple layers.

[0144] Accordingly, a first semiconductor element 250 including a first active layer 130, a first gate electrode 170, a first source electrode 210, and a first drain electrode 230 may be formed, and a second semiconductor element 255 including a second active layer 135, a second gate electrode 175, a second source electrode 215, and a second drain electrode 235 may be formed. However, although only the first semiconductor element 250 (corresponding to the first transistor TR1 of Figure 11 has been shown in Figure 5 and the second semiconductor element 255 (corresponding to the sixth transistor TR6 of Figure 5 ), the second to fifth transistors and the seventh transistor TR2, TR3, TR4, TR5, and TR7 of Figure 5 and the storage capacitor CST may be shown in another cross-sectional view of the first sub-pixel region 11 of Figure 4 .

[0145] In addition, a third semiconductor element 550 including a third active layer 430, a third gate electrode 470, a third source electrode 510, and a third drain electrode 530 may be formed, and a fourth semiconductor element 555 including a fourth active layer 435, a fourth gate electrode 475, a fourth source electrode 515, and a fourth drain electrode 535 may be formed. However, although only the third semiconductor element 550 (corresponding to the first transistor TR1 of Figure 12 has been shown in Figure 8 and the fourth semiconductor element 555 (corresponding to the sixth transistor TR6 of Figure 8 ), the second to fifth transistors and the seventh transistor TR2, TR3, TR4, TR5, and TR7 of Figure 8 and the storage capacitor CST may be shown in another cross-sectional view of the second sub-pixel region 12 of Figure 6 .

[0146] In addition, a fifth semiconductor element 850 including a fifth active layer 730, a fifth gate electrode 770, a fifth source electrode 810, and a fifth drain electrode 830 may be formed, and a sixth semiconductor element 855 including a sixth active layer 735, a sixth gate electrode 775, a sixth source electrode 815, and a sixth drain electrode 835 may be formed. However, although only the fifth semiconductor element 850 (corresponding to the first transistor TR1 of Figure 13 has been shown in Figure 10 and the sixth semiconductor element 855 (corresponding to the sixth transistor TR6 of Figure 10 ), Figure 10 the second to fifth transistors and the seventh transistor TR2, TR3, TR4, TR5, and TR7 of Figure 9 and the storage capacitor CST may be shown in another cross-sectional view of the third sub-pixel region 13 of

[0147] In an embodiment, although each of the first to sixth semiconductor elements 250, 255, 550, 555, 850, and 855 is described as having a top gate structure, the configuration of the present invention is not limited thereto. For example, each of the first to sixth semiconductor elements 250, 255, 550, 555, 850, and 855 may have a bottom gate structure and / or a double gate structure.

[0148] A planarization layer 270 may be disposed on the interlayer insulating layer 190 and the first to sixth semiconductor elements 250, 255, 550, 555, 850, and 855, and the planarization layer 270 may have contact holes respectively exposing a part of the second drain electrode 235, a part of the fourth drain electrode 535, and a part of the sixth drain electrode 835. In an embodiment, the planarization layer 270 may have an opening exposing the top surface of the substrate 110 located in the first transmission region 21 and the second transmission region 22, and the opening of the planarization layer 270 may overlap with the opening of the gate insulating layer 150 and the opening of the interlayer insulating layer 190.

[0149] The planarization layer 270 may have a relatively thick thickness to sufficiently cover the first to sixth semiconductor elements 250, 255, 550, 555, 850, and 855. In this case, the planarization layer 270 may have a substantially flat top surface. In order to achieve such a flat top surface of the planarization layer 270, a planarization process may be additionally performed on the planarization layer 270. The planarization layer 270 may include an organic material or an inorganic material. In an embodiment, the planarization layer 270 may include an organic material. For example, the planarization layer 270 may include a photoresist, a polypropylene resin, a polyimide resin, a polyamide resin, a silicone resin, an acrylic resin, an epoxy resin, etc.

[0150] The first lower electrode 290, the second lower electrode 690, and the third lower electrode 890 may be disposed on the planarization layer 270. For example, the first lower electrode 290 may be disposed in the first sub-pixel region 11 on the planarization layer 270 and may be in direct contact with the second drain electrode 235 through a contact hole in the planarization layer 270, and the first lower electrode 290 may be electrically connected to the second semiconductor element 255. Additionally, the second lower electrode 690 may be disposed in the second sub-pixel region 12 on the planarization layer 270 and may be in direct contact with the fourth drain electrode 535 through a contact hole in the planarization layer 270, and the second lower electrode 690 may be electrically connected to the fourth semiconductor element 555. Furthermore, the third lower electrode 890 may be disposed in the third sub-pixel region 13 on the planarization layer 270 and may be in direct contact with the sixth drain electrode 835 through a contact hole in the planarization layer 270, and the third lower electrode 890 may be electrically connected to the sixth semiconductor element 855.

[0151] Each of the first lower electrode 290, the second lower electrode 690, and the third lower electrode 890 may include metals, alloys, metal nitrides, conductive metal oxides, and transparent conductive materials, etc. These may be used alone or in combination with each other. In some embodiments, each of the first lower electrode 290, the second lower electrode 690, and the third lower electrode 890 may have a multi-layer structure including multiple layers.

[0152] The pixel defining layer 310 may be disposed on a part of each of the first lower electrode 290, the second lower electrode 690, and the third lower electrode 890 and on the planarization layer 270. The pixel defining layer 310 may cover both side portions of each of the first lower electrode 290, the second lower electrode 690, and the third lower electrode 890, and may have an opening exposing a part of the top surface of each of the first lower electrode 290, the second lower electrode 690, and the third lower electrode 890.

[0153] In an embodiment, the pixel defining layer 310 may have openings exposing the top surfaces of the substrate 110 in the first transmissive region 21 and the second transmissive region 22, and the openings of the pixel defining layer 310 may overlap with the openings of the planarization layer 270, the interlayer insulating layer 190, and the gate insulating layer 150. In this case, the opening (e.g., the first opening) in the first transmissive region 21 may be defined as the first transmissive window 385, and the opening (e.g., the second opening) in the second transmissive region 22 may be defined as the second transmissive window 395. Since the insulating layer structure 260 is not disposed in the first transmissive region 21 and the second transmissive region 22, the transmittance of each of the first transmissive window 385 and the second transmissive window 395 may be relatively increased. The pixel defining layer 310 may be formed of an organic material or an inorganic material. In an embodiment, the pixel defining layer 310 may include an organic material.

[0154] The first light emitting layer 330 may be disposed on the first lower electrode 290 exposed by the pixel defining layer 310, the second light emitting layer 630 may be disposed on the second lower electrode 690 exposed by the pixel defining layer 310, and the third light emitting layer 930 may be disposed on the third lower electrode 890 exposed by the pixel defining layer 310. Each of the first light emitting layer 330, the second light emitting layer 630, and the third light emitting layer 930 may be formed by using at least one of light emitting materials for emitting light of different colors (i.e., red, green, blue, etc.) according to sub-pixels. Alternatively, each of the first light emitting layer 330, the second light emitting layer 630, and the third light emitting layer 930 may be formed by stacking a plurality of light emitting materials for generating different colors of light such as red, green, and blue to emit white light as a whole. In this case, a color filter may be disposed on each of the first light emitting layer 330, the second light emitting layer 630, and the third light emitting layer 930 (e.g., to overlap with each of the first light emitting layer 330, the second light emitting layer 630, and the third light emitting layer 930 on the top surface of the encapsulation substrate 450). The color filter may include at least one of a red color filter, a green color filter, and a blue color filter. In some embodiments, the color filter may include a yellow color filter, a cyan color filter, and a magenta color filter. The color filter may include a photosensitive resin or a color photoresist.

[0155] The first upper electrode 340, the second upper electrode 640, and the third upper electrode 940 may be disposed on the pixel defining layer 310 and the first light emitting layer 330, the second light emitting layer 630, and the third light emitting layer 930. In an embodiment, the second upper electrode 640 and the third upper electrode 940 may expose the top surfaces of the substrate 110 in the first transmissive region 21 and the second transmissive region 22. However, although the first upper electrode 340, the second upper electrode 640, and the third upper electrode 940 are in Figure 11 ,Figure 12 and Figure 13 are shown as being separated from each other in Figure 13 , but the first upper electrode 340, the second upper electrode 640, and the third upper electrode 940 may be electrically connected to each other and may be substantially formed as a single layer. For example, the first upper electrode 340, the second upper electrode 640, and the third upper electrode 940 may be integrally formed in the first display region 10, the second display region 20, and the third display region 30 except for the first transmission region 21 and the second transmission region 22. In some embodiments, the first upper electrode 340, the second upper electrode 640, and the third upper electrode 940 may be formed throughout the first display region 10, the second display region 20, and the third display region 30.

[0156] Each of the first upper electrode 340, the second upper electrode 640, and the third upper electrode 940 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In some embodiments, each of the first upper electrode 340, the second upper electrode 640, and the third upper electrode 940 may have a multilayer structure including multiple layers. Accordingly, a first sub-pixel structure 300 including a first lower electrode 290, a first light-emitting layer 330, and a first upper electrode 340, a second sub-pixel structure 600 including a second lower electrode 690, a second light-emitting layer 630, and a second upper electrode 640, and a third sub-pixel structure 900 including a third lower electrode 890, a third light-emitting layer 930, and a third upper electrode 940 may be formed.

[0157] The capping layer 345 may be disposed on the first upper electrode 340, the second upper electrode 640, and the third upper electrode 940. In an embodiment, the capping layer 345 may be disposed over the entire substrate 110. Additionally, the capping layer 345 may have a first thickness T1 in the first display region 10 and may have a second thickness T2 less than the first thickness T1 in the second display region 20 and the third display region 30. For example, the capping layer 345 may have a relatively thin thickness (e.g., the second thickness T2) in the first transmission region 21 and the second transmission region 22 such that the transmittance of each of the first transmission window 385 and the second transmission window 395 may be reduced relatively little. In some embodiments, the capping layer 345 may not be disposed in the first transmission region 21 and the second transmission region 22.

[0158] The capping layer 345 may protect the first sub-pixel structure 300, the second sub-pixel structure 300, and the third sub-pixel structure 900 and may include an organic material or an inorganic material. For example, the capping layer 345 may include a triamine derivative, an arylenediamine derivative, 4,4'-bis(N-carbazolyl)-1,1'-biphenyl (CBP), and tris(8-hydroxyquinoline)aluminum (Alq 3 ) etc.

[0159] The encapsulation substrate 450 may be disposed on the capping layer 345. The encapsulation substrate 450 may include substantially the same materials as the substrate 110. For example, the encapsulation substrate 450 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda-lime glass substrate, and a non-alkali glass substrate, etc. In other embodiments, the encapsulation substrate 450 may include a transparent inorganic material or a flexible plastic. For example, the encapsulation substrate 450 may include a flexible transparent resin substrate. In this case, in order to improve the flexibility of the organic light-emitting display device 100, the encapsulation substrate 450 may have a structure in which at least one inorganic layer and at least one organic layer are alternately stacked, and the capping layer 345 may not be provided. The stacked structure may include a first inorganic layer, an organic layer, and a second inorganic layer. For example, the flexible first inorganic layer may be disposed along the contour of the upper electrode 340, the flexible organic layer may be disposed on the first inorganic layer, and the flexible second inorganic layer may be disposed on the organic layer. In other words, the stacked structure may correspond to a thin-film encapsulation structure in direct contact with the upper electrode 340. Thus, a display panel 200 including the substrate 110, the first semiconductor element 250, the second semiconductor element 255, the third semiconductor element 550, the fourth semiconductor element 555, the fifth semiconductor element 850, the sixth semiconductor element 855, the insulating layer structure 260, the planarization layer 270, the pixel defining layer 310, the first sub-pixel structure 300, the second sub-pixel structure 600, the third sub-pixel structure 900, the capping layer 345, and the encapsulation substrate 450 may be formed.

[0160] The first optical module 410 may be disposed on the bottom surface of the substrate 110 (e.g., the second surface S2 of the display panel 200) to overlap with the second display area 20. The first optical module 410 may capture an image of an object located above the first surface S1 of the display panel 200 through the first transmission area 21. In an embodiment, the first optical module 410 may include a camera module.

[0161] The second optical module 420 may be disposed on the bottom surface of the substrate 110 to overlap with the third display area 30. The second optical module 420 may detect the surrounding environment or an image of an object located above the first surface S1 of the display panel 200 through the second transmission area 22. In an embodiment, the second optical module 420 may include at least one of a face recognition sensor module, a pupil recognition sensor module, an acceleration sensor module, a geomagnetic sensor module, a proximity sensor module, an infrared sensor module, and an illuminance sensor module. Thus, an organic light-emitting display device 100 including the display panel 200, the first optical module 410, and the second optical module 420 may be formed.

[0162] Since the organic light emitting display device 100 according to an embodiment of the present invention includes a first display area 10 having a first resolution and second and third display areas 20 and 30 having a second resolution lower than the first resolution, an image can also be displayed in a portion where the first optical module 410 and the second optical module 420 are arranged. In addition, since the organic light emitting display device 100 includes a first transmissive window 385 and a second transmissive window 395, the first optical module 410 and the second optical module 420 can detect the surrounding environment or capture an image of an object located above the first surface S1 of the display panel 200 through the first transmissive window 385 and the second transmissive window 395.

[0163] Figure 14 is a plan view showing an organic light emitting display device according to an embodiment of the present invention, Figure 15 is showing Figure 14 a partially enlarged plan view of a part of the second display area, Figure 16 is showing the arrangement in Figure 15 a circuit diagram of a second sub-pixel circuit and a second organic light emitting diode in the second display area, Figure 17 is showing Figure 14 a partially enlarged plan view of a part of the third display area, and Figure 18 is showing the arrangement in Figure 15 a circuit diagram of a third sub-pixel circuit and a third organic light emitting diode in the third display area. Figures 14 to 18 The organic light emitting display device 1000 illustrated in Figures 1 to 13 may have a configuration substantially the same as or similar to that of the organic light emitting display device 100 described with reference to Figures 14 to 18 In Figures 1 to 13 a redundant description of components substantially the same as or similar to those described with reference to

[0164] Referring to Figure 1 , Figure 2 and Figure 14 , the organic light emitting display device 1000 may include a display panel 200, a first optical module 410, a second optical module 420, etc. The display panel 200 may have a first surface S1 for displaying an image and a second surface S2 opposite to the first surface S1. The first optical module 410 and the second optical module 420 may be arranged on one side of the second surface S2 of the display panel 200, and the first optical module 410 and the second optical module 420 may be adjacent to each other.

[0165] The first display area 10 may include a plurality of first sub-pixel areas (for example, corresponding to the first sub-pixel area 11 of Figure 4 ), the second display area 20 may include a plurality of second sub-pixel areas and a plurality of first transmissive areas (for example, corresponding toFigure 15 The second sub-pixel region 12 corresponds to the first transmissive region 21), and the third display region 30 may include a plurality of third sub-pixel regions and a plurality of second transmissive regions (e.g., corresponding to Figure 17 the third sub-pixel region 13 and the second transmissive region 22). In an embodiment, the display panel 200 may display images at different resolutions in the first display region 10, as well as in the second display region 20 and the third display region 30. For example, an image may be displayed at a first resolution in the first display region 10, and an image may be displayed at a second resolution lower than the first resolution in the second display region 20 and the third display region 30. In other words, the first display region 10 may have a first resolution, and each of the second display region 20 and the third display region 30 may have a second resolution.

[0166] Referring to Figure 4 and Figure 5 , the display panel 200 may further include a first sub-pixel circuit SPC1 and a first organic light-emitting diode OLED1. Additionally, the display panel 200 may have a first display region 10, and the first display region 10 may include a plurality of first sub-pixel regions 11.

[0167] Each of the first sub-pixel circuits SPC1 may overlap with the first sub-pixel region 11, and the first organic light-emitting diode OLED1 may be disposed on the first sub-pixel circuit SPC1. An image may be displayed in the first sub-pixel region 11 through the first sub-pixel circuit SPC1 and the first organic light-emitting diode OLED1.

[0168] As Figure 5 shown, the first sub-pixel circuit SPC1 may include a first transistor to a seventh transistor TR1, TR2, TR3, TR4, TR5, TR6, and TR7, a storage capacitor CST, a high power supply voltage wiring, a low power supply voltage wiring, an initialization voltage wiring, a data signal wiring, a gate signal wiring, a gate initialization signal wiring, an emission control signal wiring, and a diode initialization signal wiring, etc. Additionally, the first sub-pixel circuit SPC1 and the first organic light-emitting diode OLED1 may be electrically connected to each other.

[0169] Referring to Figure 15 and Figure 16 , the display panel 200 may further include a second sub-pixel circuit SPC2 and a second organic light-emitting diode OLED2. Additionally, the display panel 200 may have a second display region 20, and the second display region 20 may include a plurality of second sub-pixel regions 12 and a plurality of first transmissive regions 21. In an embodiment, when compared with being disposed in Figure 4When compared with the first sub-pixel region 11 in the first display region 10, the second display region 20 may include a relatively small number of sub-pixel regions per unit area due to the first transmissive region 21. In other words, the second resolution of the second display region 20 may be lower than the first resolution of the first display region 10.

[0170] Each of the second sub-pixel circuits SPC2 may overlap with the second sub-pixel region 12, and the second organic light-emitting diode OLED2 may be disposed on the second sub-pixel circuit SPC2. An image may be displayed in the second sub-pixel region 12 through the second sub-pixel circuit SPC2 and the second organic light-emitting diode OLED2. Additionally, the first optical module 410 disposed on the second surface S2 of the display panel 200 may capture an image of an object located above the first surface S1 of the display panel 200 through the first transmissive region 21. In other words, the first transmissive region 21 may be substantially transparent.

[0171] As Figure 16 shown, the second sub-pixel circuit SPC2 may include a first transistor TR1 and a second transistor TR2, a storage capacitor CST, a high power supply voltage wiring, a low power supply voltage wiring, a data signal wiring, a gate signal wiring, etc. Additionally, the second sub-pixel circuit SPC2 and the second organic light-emitting diode OLED2 may be electrically connected to each other.

[0172] In an embodiment, the second sub-pixel circuit SPC2 may not be disposed in the first transmissive region 21. In other words, the second sub-pixel circuit SPC2 may expose the first transmissive region 21.

[0173] Additionally, the configurations of the first sub-pixel circuit SPC1 and the first organic light-emitting diode OLED1 in the first display region 10 may be different from the configurations of the second sub-pixel circuit SPC2 and the second organic light-emitting diode OLED2 in the second display region 20. In other words, the number of transistors included in the first sub-pixel circuit SPC1 in the first sub-pixel region 11 may be greater than the number of transistors included in the second sub-pixel circuit SPC2 in the second sub-pixel region 12.

[0174] Furthermore, when compared with Figure 6 the first transmissive region 21 of Figure 16 since the second sub-pixel circuit SPC2 of Figure 15The first transmissive region 21 may have a relatively large area. In this case, the first optical module 410 may relatively easily capture an image of an object located above the first surface S1 of the display panel 200 due to the first transmissive region 21 having a relatively large area.

[0175] Referring Figure 17 and Figure 18 , the display panel 300 may further include a third sub-pixel circuit SPC3 and a third organic light-emitting diode OLED3. Additionally, the display panel 300 may have a third display region 30, and the third display region 30 may include a plurality of third sub-pixel regions 13 and a plurality of second transmissive regions 22. In an embodiment, when compared with the first sub-pixel regions 11 in the first display region 10 disposed Figure 4 , the third display region 30 may include a relatively small number of sub-pixel regions per unit area due to the second transmissive regions 22. In other words, the second resolution of the third display region 30 may be lower than the first resolution of the first display region 10.

[0176] Each of the third sub-pixel circuits SPC3 may overlap with the third sub-pixel regions 13, and the third organic light-emitting diode OLED3 may be disposed on the third sub-pixel circuit SPC3. An image may be displayed in the third sub-pixel regions 13 through the third sub-pixel circuit SPC3 and the third organic light-emitting diode OLED3. Additionally, the second optical module 420 disposed on the second surface S2 of the display panel 200 may detect the surrounding environment or capture an image of an object located above the first surface S1 of the display panel 200 through the second transmissive regions 22. In other words, the second transmissive regions 22 may be substantially transparent.

[0177] As Figure 18 shown, the third sub-pixel circuit SPC3 may include a first transistor TR1 and a second transistor TR2, a storage capacitor CST, a high power supply voltage wiring, a low power supply voltage wiring, a data signal wiring, a gate signal wiring, etc. Additionally, the third sub-pixel circuit SPC3 and the third organic light-emitting diode OLED3 may be electrically connected to each other.

[0178] In an embodiment, the third sub-pixel circuit SPC3 may not be disposed in the second transmissive regions 22. In other words, the third sub-pixel circuit SPC3 may expose the second transmissive regions 22.

[0179] In addition, the configurations of the first sub-pixel circuit SPC1 and the first organic light-emitting diode OLED1 in the first display area 10 may be different from those of the third sub-pixel circuit SPC3 and the third organic light-emitting diode OLED3 in the third display area 30. In other words, the number of transistors in the first sub-pixel circuit SPC1 included in the first sub-pixel area 11 may be greater than the number of transistors in the third sub-pixel circuit SPC3 included in the third sub-pixel area 13. At the same time, the configurations of the second sub-pixel circuit SPC2 and the second organic light-emitting diode OLED2 may be the same as those of the third sub-pixel circuit SPC3 and the third organic light-emitting diode OLED3, and the number of transistors in the second sub-pixel circuit SPC2 included in the second sub-pixel area 12 may be equal to the number of transistors in the third sub-pixel circuit SPC3 included in the third sub-pixel area 13.

[0180] In addition, when compared with Figure 9 's second transmissive area 22, since Figure 18 's third sub-pixel circuit SPC3 does not include the third transistor TR3, the fourth transistor TR4, the fifth transistor TR5, the sixth transistor TR6, and the seventh transistor TR7, the initialization voltage wiring, the gate initialization signal wiring, the emission control signal wiring, and the diode initialization signal wiring, etc., Figure 17 's second transmissive area 22 may have a relatively large area. In this case, the second optical module 420 may easily detect the surrounding environment or easily capture an image of an object located above the first surface S1 of the display panel 200 due to the second transmissive area 22 having a relatively large area.

[0181] Figure 19 is a plan view showing an organic light-emitting display device according to an embodiment of the present invention, Figure 20 is showing Figure 19 a partially enlarged plan view of a part of the third display area of Figure 21 and is showing Figure 20 the circuit diagram of the third sub-pixel circuit and the third organic light-emitting diode arranged in the third display area of Figures 19 to 21 The organic light-emitting display device 1100 illustrated in Figures 14 to 18 may have a configuration that is substantially the same as or similar to the configuration of the organic light-emitting display device 1000 described with reference to Figures 19 to 21 In Figures 14 to 18 a redundant description of components that are substantially the same as or similar to the components described with reference to

[0182] Referring to Figure 4 , Figure 5 , Figure 15 , Figure 16 , Figure 19 ,Figure 20 and Figure 21 In this case, the organic light emitting display device 1100 may include a display panel 200, a first optical module 410, a second optical module 420, etc. In this case, the display panel 200 may include a first sub-pixel circuit SPC1, a first organic light emitting diode OLED1, a second sub-pixel circuit SPC2, a second organic light emitting diode OLED2, a third sub-pixel circuit SPC3, a third organic light emitting diode OLED3, etc.

[0183] In an embodiment, the display panel 200 may display an image at different resolutions in a first display area 10, a second display area 20, and a third display area 30. For example, an image may be displayed at a first resolution in the first display area 10, at a second resolution lower than the first resolution in the second display area 20, and at a third resolution between the first resolution and the second resolution in the third display area 30. In other words, the first display area 10 may have a first resolution, the second display area 20 may have a second resolution, and the third display area 30 may have a third resolution.

[0184] As Figure 4 and Figure 5 shown, the first sub-pixel circuit SPC1 may overlap with a first sub-pixel area 11 of the first display area 10, and the first sub-pixel circuit SPC1 may include a first transistor to a seventh transistor TR1, TR2, TR3, TR4, TR5, TR6, and TR7, a storage capacitor CST, a high power supply voltage wiring, a low power supply voltage wiring, an initialization voltage wiring, a data signal wiring, a gate signal wiring, a gate initialization signal wiring, an emission control signal wiring, and a diode initialization signal wiring, etc.

[0185] As Figure 15 and Figure 16 shown, the second sub-pixel circuit SPC2 may overlap with a second sub-pixel area 12 of the second display area 20, and the second sub-pixel circuit SPC2 may include a first transistor TR1 and a second transistor TR2, a storage capacitor CST, a high power supply voltage wiring, a low power supply voltage wiring, a data signal wiring, and a gate signal wiring, etc.

[0186] In an embodiment, when compared with the first sub-pixel area 11 disposed in the Figure 4 first display area 10, the second display area 20 may include a relatively small number of sub-pixel areas per unit area due to the first transmissive area 21. In other words, the second resolution of the second display area 20 may be lower than the first resolution of the first display area 10.

[0187] In an embodiment, the second sub-pixel circuit SPC2 may not be disposed in the first transmissive region 21. In other words, the second sub-pixel circuit SPC2 may expose the first transmissive region 21.

[0188] In addition, the configuration of the first sub-pixel circuit SPC1 and the first organic light-emitting diode OLED1 in the first display region 10 may be different from the configuration of the second sub-pixel circuit SPC2 and the second organic light-emitting diode OLED2 in the second display region 20. In other words, the number of transistors included in the first sub-pixel circuit SPC1 in the first sub-pixel region 11 may be greater than the number of transistors included in the second sub-pixel circuit SPC2 in the second sub-pixel region 12.

[0189] In addition, when compared with Figure 6 the first transmissive region 21 of Figure 16 since the second sub-pixel circuit SPC2 of Figure 15 does not include the third transistor TR3, the fourth transistor TR4, the fifth transistor TR5, the sixth transistor TR6, and the seventh transistor TR7, the initialization voltage wiring, the gate initialization signal wiring, the emission control signal wiring, and the diode initialization signal wiring, etc.,

[0190] As Figure 20 and Figure 21 shown in, the third sub-pixel circuit SPC3 may overlap with the third sub-pixel region 13 of the third display region 30, and the third sub-pixel circuit SPC3 may include the first transistor to the sixth transistor TR1, TR2, TR3, TR4, TR5, and TR6, the storage capacitor CST, the high power supply voltage wiring, the low power supply voltage wiring, the initialization voltage wiring, the data signal wiring, the gate signal wiring, the gate initialization signal wiring, and the emission control signal wiring, etc. In some embodiments, the number of transistors included in the third sub-pixel circuit SPC3 may be greater than the number of transistors included in the second sub-pixel circuit SPC2 and less than the number of transistors included in the first sub-pixel circuit SPC1.

[0191] In an embodiment, the third sub-pixel circuit SPC3 may not be disposed in the second transmissive region 22. In other words, the third sub-pixel circuit SPC3 may expose the second transmissive region 22.

[0192] In addition, the configurations of the first sub-pixel circuit SPC1 and the first organic light-emitting diode OLED1 in the first display area 10 and the configurations of the second sub-pixel circuit SPC2 and the second organic light-emitting diode OLED2 in the second display area 20 may be different from the configurations of the third sub-pixel circuit SPC3 and the third organic light-emitting diode OLED3 in the third display area 30. In other words, the number of transistors in the third sub-pixel circuit SPC3 included in the third sub-pixel area 13 may be less than the number of transistors in the first sub-pixel circuit SPC1 included in the first sub-pixel area 11 and may be greater than the number of transistors in the second sub-pixel circuit SPC2 included in the second sub-pixel area 12.

[0193] In addition, when compared with Figure 15 's first transmissive area 21, because Figure 21 's third sub-pixel circuit SPC3 includes a third transistor TR3, a fourth transistor TR4, a fifth transistor TR5, and a sixth transistor TR6, an initialization voltage wiring, a gate initialization signal wiring, an emission control signal wiring, etc., thus Figure 20 's second transmissive area 22 may have a relatively small area.

[0194] In other words, when compared with the second sub-pixel area 12 arranged in Figure 15 's second display area 20, the third display area 30 may include a relatively large number of sub-pixel areas per unit area due to the second transmissive area 22 having a relatively small area. That is to say, the third resolution of the third display area 30 may be lower than the first resolution of the first display area 10 and may be higher than the second resolution of the second display area 20.

[0195] Figure 22 is a perspective view showing an organic light-emitting display device according to an embodiment of the present invention, Figure 23 is a perspective view showing an optical module embedded in Figure 22 's organic light-emitting display device, and Figure 24 is a perspective view showing a groove formed in Figure 23 's organic light-emitting display device. Figures 22 to 24 The organic light-emitting display device 1200 illustrated in Figures 1 to 13 may have a configuration that is substantially the same as or similar to the configuration of the organic light-emitting display device 100 described with reference to Figures 22 to 24 . In Figures 1 to 13 , redundant descriptions of components that are substantially the same as or similar to the components described with reference to

[0196] Referring to Figure 3 , Figure 22 , Figure 23 and Figure 24, the organic light emitting display device 1200 may include a display panel 200, a first optical module 410, a second optical module 420, etc. The display panel 200 may have a first surface S1 for displaying an image and a second surface S2 opposite to the first surface S1. The display panel 200 may include a first display area 10, a second display area 20, and a third display area 30. In addition, a first groove 910 may be formed in a portion of the second surface S2 of the display panel 200 (or the substrate 110) that overlaps with the second display area 20, and a second groove 920 may be formed in a portion of the second surface S2 of the display panel 200 that overlaps with the third display area 30. Accordingly, the first optical module 410 may be embedded in the first groove 910, and the second optical module 420 may be embedded in the second groove 920. In this case, the display panel 200, the first optical module 410, and the second optical module 420 may be integrally manufactured.

[0197] Figure 25 is a plan view showing an organic light emitting display device according to an embodiment of the present invention, Figure 26 is showing Figure 25 an enlarged plan view of a non-display area of, and Figure 27 is a cross-sectional view taken along line IV-IV’ of Figure 26 . Figures 25 to 27 The organic light emitting display device 1300 illustrated in Figures 1 to 13 may have a configuration that is substantially the same as or similar to the configuration of the organic light emitting display device 100 described with reference to Figures 25 to 27 . In Figures 1 to 13 , redundant descriptions of components that are substantially the same as or similar to the components described with reference to

[0198] Referring to Figure 25 , Figure 26 and Figure 27 , the organic light emitting display device 1300 may include a display panel 200, a first optical module 410, a second optical module 420, etc. The display panel 200 may include a first display area 10, a second display area 30, and a non-display area 40.

[0199] The first display area 10 may include a plurality of first sub-pixel areas (e.g., corresponding to the first sub-pixel area 11 of Figure 4 ), the second display area 30 may include a plurality of second sub-pixel areas and a plurality of first transmissive areas (e.g., corresponding to the third sub-pixel area 13 and the second transmissive area 22 of Figure 9 ), and the non-display area 40 may include a second transmissive area (e.g., corresponding to Figure 26corresponds to the second transmissive region 41). In an embodiment, the display panel 200 may display images at different resolutions in the first display region 10 and the second display region 30. For example, an image may be displayed at a first resolution in the first display region 10, and an image may be displayed at a second resolution lower than the first resolution in the second display region 30. In other words, the first display region 10 may have the first resolution, and the second display region 30 may have the second resolution. Additionally, an image may not be displayed in the non-display region 40. In other words, only the first transmissive window 385 may be formed in the non-display region 40.

[0200] The first optical module 410 may be disposed on the second surface S2 of the display panel 200 to overlap with the non-display region 40. The first optical module 410 may include a camera module for capturing an image of an object located above the first surface S1 of the display panel 200.

[0201] In this case, the first optical module 410 may relatively easily capture an image of an object located above the first surface S1 of the display panel 200 due to the second transmissive region 41 having a relatively large area.

[0202] The foregoing is an illustration of embodiments and should not be construed as a limitation thereof. Although some embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. Accordingly, it is to be understood that the foregoing is an illustration of various embodiments and should not be construed as limited to the specific embodiments disclosed, and modifications to the disclosed embodiments as well as other embodiments are intended to be included within the scope of the appended claims.

[0203]

Industrial Applicability

[0204] The present invention can be applied to various electronic devices including an organic light emitting display device. For example, the present invention can be applied to a variety of electronic devices such as a vehicle display device, a ship display device, an aircraft display device, a portable communication device, a display device for display or for information transmission, a medical display device, and the like.

[0205]

Description of Reference Numerals

[0206] 10: First display region

[0207] 11: First sub-display region

[0208] 12: Second sub-display region

[0209] 13: Third sub-display region

[0210] 20: Second display area

[0211] 21: First transmissive area

[0212] 22: Second transmissive area

[0213] 30: Third display area

[0214] 40: Non-display area

[0215] 100, 1100, 1200, 1300: Organic light-emitting display device

[0216] 110: Substrate

[0217] 130: First active layer

[0218] 135: Second active layer

[0219] 150: Gate insulating layer

[0220] 170: First gate electrode

[0221] 175: Second gate electrode

[0222] 190: Interlayer insulating layer

[0223] 200: Display panel

[0224] 210: First source electrode

[0225] 215: Second source electrode

[0226] 230: First drain electrode

[0227] 235: Second drain electrode

[0228] 250: First semiconductor element

[0229] 255: Second semiconductor element

[0230] 260: Insulating layer structure

[0231] 270: Planarization layer

[0232] 290: First lower electrode

[0233] 300: First sub-pixel structure

[0234] 310: Pixel defining layer

[0235] 330: First light-emitting layer

[0236] 340: First upper electrode

[0237] 345: Capping layer

[0238] 385: First transmission window

[0239] 395: Second transmission window

[0240] 410: First optical module

[0241] 420: Second optical module

[0242] 430: Third active layer

[0243] 435: Fourth active layer

[0244] 450: Encapsulation substrate

[0245] 470: Third gate electrode

[0246] 475: Fourth gate electrode

[0247] 510: Third source electrode

[0248] 515: Fourth source electrode

[0249] 530: Third drain electrode

[0250] 535: Fourth drain electrode

[0251] 550: Third semiconductor element

[0252] 555: Fourth semiconductor element

[0253] 600: Second sub-pixel structure

[0254] 630: Second light-emitting layer

[0255] 640: Second upper electrode

[0256] 690: Second lower electrode

[0257] 730: Fifth active layer

[0258] 735: Sixth active layer

[0259] 770: Fifth gate electrode

[0260] 775: Sixth gate electrode

[0261] 810: Fifth source electrode

[0262] 815: Sixth source electrode

[0263] 830: Fifth drain electrode

[0264] 835: Sixth drain electrode

[0265] 850: Fifth semiconductor element

[0266] 855: The sixth semiconductor element

[0267] 890: The third lower electrode

[0268] 900: The third sub-pixel structure

[0269] 910: The first groove

[0270] 920: The second groove

[0271] 930: The third light-emitting layer

[0272] 940: The third upper electrode

Claims

1. An organic light emitting display device, comprising: a display panel including a first display area, a second display area, and a third display area adjacent to the second display area, and configured to display an image on a first surface of the display panel, the first display area including a first sub-pixel area and having a first resolution, the second display area including a second sub-pixel area and a first transmissive area and having a second resolution lower than the first resolution, the third display area including a third sub-pixel area and a second transmissive area and having a third resolution between the first resolution and the second resolution; a first optical module disposed on a second surface of the display panel opposite to the first surface to overlap with the second display area; and a second optical module disposed on the second surface of the display panel to overlap with the third display area, wherein an area of the third display area is smaller than an area of the second display area, an area of the first transmissive area is larger than an area of the second sub-pixel area, an area of the second transmissive area is larger than an area of the third sub-pixel area, a width of the first transmissive area in a first direction and a width of the first transmissive area in a second direction intersecting with the first direction are respectively larger than a width of the second sub-pixel area in the first direction and a width of the second sub-pixel area in the second direction, and a width of the second transmissive area in the first direction is larger than a width of the third sub-pixel area in the first direction.

2. The organic light emitting display device according to claim 1, wherein, the display panel further includes: a first sub-pixel circuit disposed in the first display area; and a second sub-pixel circuit disposed in the second display area and different from the first sub-pixel circuit.

3. The organic light emitting display device according to claim 2, wherein, a number of transistors constituting the first sub-pixel circuit is larger than a number of transistors constituting the second sub-pixel circuit.

4. The organic light emitting display device according to claim 2, wherein, the display panel further includes: a first sub-pixel structure disposed on the first sub-pixel circuit in the first sub-pixel area and electrically connected to the first sub-pixel circuit; a second sub-pixel structure disposed on the second sub-pixel circuit in the second sub-pixel area and electrically connected to the second sub-pixel circuit; and a first transmissive window disposed in the first transmissive area adjacent to the second sub-pixel area.

5. The organic light emitting display device according to claim 4, wherein, the first optical module includes a camera module, and the first optical module is configured to identify an object located above the first surface of the display panel through the first transmissive window.

6. The organic light emitting display device according to claim 4, wherein, the second sub-pixel circuit is not disposed in the first transmissive area.

7. The organic light emitting display device according to claim 2, wherein, The display panel further includes: A third sub-pixel circuit, which is arranged in the third display area and is different from the first sub-pixel circuit and the second sub-pixel circuit.

8. The organic light-emitting display device according to claim 7, wherein, The number of transistors constituting the third sub-pixel circuit is less than the number of transistors constituting the first sub-pixel circuit and greater than the number of transistors constituting the second sub-pixel circuit.

9. The organic light-emitting display device according to claim 7, wherein, The display panel further includes: A third sub-pixel structure, which is arranged on the third sub-pixel circuit in the third sub-pixel area and is electrically connected to the third sub-pixel circuit; and A second transmissive window, which is arranged in the second transmissive area adjacent to the third sub-pixel area.

10. The organic light-emitting display device according to claim 9, wherein, The third sub-pixel circuit is not arranged in the second transmissive area.

11. The organic light-emitting display device according to claim 9, wherein, The second optical module includes at least one of a face recognition sensor module, a pupil recognition sensor module, an acceleration sensor module, a proximity sensor module, an infrared sensor module, and an illuminance sensor module.

12. The organic light-emitting display device according to claim 7, wherein, The size of the first optical module is equal to the size of the second display area, and The size of the second optical module is equal to the size of the third display area.

13. The organic light-emitting display device according to claim 1, wherein, The area of the first display area is larger than the area of the second display area.

14. The organic light-emitting display device according to claim 1, wherein, The second display area is located on one side of the first surface of the display panel, and The first display area surrounds the second display area.

15. The organic light-emitting display device according to claim 1, wherein, The display panel further includes: A first sub-pixel circuit, which is arranged in the first display area; and A second sub-pixel circuit, which is arranged in the second display area, and The first sub-pixel circuit and the second sub-pixel circuit have the same configuration.

16. An organic light-emitting display device, comprising: A display panel, which is configured to display an image on the first surface of the display panel and includes: A substrate, which includes a first display area, a second display area, and a third display area adjacent to the second display area. The first display area includes a first sub-pixel area and is configured to display an image at a first resolution. The second display area includes a second sub-pixel area and a first transmissive area, and is configured to display an image at a second resolution lower than the first resolution. The third display area includes a third sub-pixel area and a second transmissive area, and is configured to display an image at a third resolution between the first resolution and the second resolution; A first sub-pixel circuit, which is arranged on the substrate in the first display area; A second sub-pixel circuit, which is disposed on the substrate in the second display area and is configured to expose the first transmissive area; A sub-pixel structure, which is disposed on the substrate in the first sub-pixel area and the second sub-pixel area; and A first transmissive window, which is formed on the substrate in the first transmissive area; A first optical module, which is disposed on a second surface of the display panel opposite to the first surface to overlap with the second display area; and A second optical module, which is disposed on the second surface of the display panel to overlap with the third display area, wherein the area of the third display area is smaller than the area of the second display area, the area of the first transmissive area is larger than the area of the second sub-pixel area, the area of the second transmissive area is larger than the area of the third sub-pixel area, the width of the first transmissive area in a first direction and the width of the first transmissive area in a second direction intersecting with the first direction are respectively larger than the width of the second sub-pixel area in the first direction and the width of the second sub-pixel area in the second direction, and the width of the second transmissive area in the first direction is larger than the width of the third sub-pixel area in the first direction.

17. The organic light-emitting display device according to claim 16, wherein, the substrate includes a first groove formed in a part of the second surface overlapping with the second display area, and the first optical module is embedded in the first groove.

18. The organic light-emitting display device according to claim 16, further comprising: An insulating layer structure disposed on the substrate; A planarization layer disposed on the insulating layer structure; and A pixel defining layer disposed on the planarization layer.

19. The organic light-emitting display device according to claim 18, wherein, in the first transmissive area, the insulating layer structure, the planarization layer and the pixel defining layer include a first opening exposing the substrate, and the first opening is defined as the first transmissive window.

20. The organic light-emitting display device according to claim 18, further comprising: A capping layer disposed on the pixel defining layer, wherein the capping layer has a first thickness in the first sub-pixel area and a second thickness smaller than the first thickness in the second sub-pixel area and the first transmissive area.

21. The organic light-emitting display device according to claim 18, wherein, the substrate further includes: A third sub-pixel circuit, which is disposed in the third display area and has the same configuration as the second sub-pixel circuit.

22. The organic light-emitting display device according to claim 21, wherein, the number of transistors constituting the third sub-pixel circuit is equal to the number of transistors constituting the second sub-pixel circuit.

23. The organic light-emitting display device according to claim 21, wherein, the substrate includes a second groove formed in a part of the second surface overlapping with the third display area, and The second optical module is embedded in the second groove.

24. The organic light emitting display device according to claim 21, wherein, the substrate further includes: a third sub-pixel structure disposed on the third sub-pixel circuit in the third sub-pixel region and electrically connected to the third sub-pixel circuit; and a second transmissive window disposed in the second transmissive region adjacent to the third sub-pixel region.

25. The organic light emitting display device according to claim 24, wherein, the third sub-pixel circuit is not disposed in the second transmissive region.

26. The organic light emitting display device according to claim 24, wherein, in the second transmissive region, the insulating layer structure, the planarization layer and the pixel defining layer include a second opening exposing the substrate, and the second opening is defined as the second transmissive window.

27. The organic light emitting display device according to claim 26, wherein, the first sub-pixel circuit has the same configuration as each of the second sub-pixel circuit and the third sub-pixel circuit, and the size of the first transmissive window is equal to the size of the second transmissive window.

28. The organic light emitting display device according to claim 26, wherein, the configuration of the second sub-pixel circuit is different from the configuration of the third sub-pixel circuit, and the size of the first transmissive window is different from the size of the second transmissive window.

29. The organic light emitting display device according to claim 28, wherein, the number of transistors constituting the third sub-pixel circuit is greater than the number of transistors constituting the second sub-pixel circuit.

30. The organic light emitting display device according to claim 29, wherein, the size of the second transmissive window is smaller than the size of the first transmissive window.

31. The organic light emitting display device according to claim 16, wherein, each of the first sub-pixel circuit and the second sub-pixel circuit includes at least one semiconductor element and at least one capacitor.

32. The organic light emitting display device according to claim 16, wherein, each of the sub-pixel structures includes: a lower electrode disposed on the first sub-pixel circuit and the second sub-pixel circuit; a light emitting layer disposed on the lower electrode; and an upper electrode disposed on the light emitting layer.

33. The organic light emitting display device according to claim 32, wherein, the upper electrode is not disposed in the first transmissive region.

34. An organic light emitting display device, comprising: a display panel including a first display region, a second display region and a non-display region, and configured to display an image on a first surface of the display panel, the first display region including a first sub-pixel region and having a first resolution, the second display region including a second sub-pixel region and a first transmissive region and having a second resolution lower than the first resolution, the non-display region including a second transmissive region and not displaying an image; A first optical module, which is disposed on a second surface of the display panel opposite to the first surface to overlap with the non-display area, and A second optical module, which is disposed on the second surface of the display panel to overlap with the second sub-pixel area, wherein an area of the second display area is smaller than an area of the non-display area, an area of the first transmissive area is larger than an area of the second sub-pixel area, and a width of the first transmissive area in a first direction and a width of the first transmissive area in a second direction intersecting with the first direction are respectively larger than a width of the second sub-pixel area in the first direction and a width of the second sub-pixel area in the second direction.

35. The organic light emitting display device according to claim 34, wherein, the first optical module includes a camera module, and the first optical module is configured to identify an object located above the first surface of the display panel through the second transmissive area.

36. The organic light emitting display device according to claim 34, wherein, the second optical module includes at least one of a face recognition sensor module, a pupil recognition sensor module, an acceleration sensor module, a proximity sensor module, an infrared sensor module, and an illuminance sensor module.

Images