A new LDO circuit suitable for large-capacity SIM card chips

Abstract

The present invention provides a novel LDO circuit suitable for a large-capacity SIM card chip, the LDO circuit comprising an error amplifier, a first sampling resistor, a second sampling resistor, a first power tube, a current source VCC, a core voltage VDD, a control signal, a reference current, a reference voltage and a state conversion control circuit, wherein the state conversion control circuit comprises a pulse generating circuit and an auxiliary bias circuit; the state conversion control circuit of the present invention uses a control signal to control the gate terminal voltage of the first power tube MP1 at the moment of conversion, so that the first power tube continues to output a sufficiently large current until the state switching of the novel LDO circuit is completed, so as to maintain the stability of the core voltage VDD and avoid the risk of system reset. At the same time, the novel LDO circuit of the present invention effectively avoids the problem of resetting the core voltage VDD, and ensures that the novel LDO circuit can respond to external wake-up commands quickly and timely.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits of SIM cards, and in particular to a novel LDO circuit suitable for large-capacity SIM card chips. Background Art

[0002] In large-capacity SIM card chips, the LDO (Low Drop Out Regulator) circuit completes the function of converting the input power supply VCC into the core voltage VDD. In actual work, the LDO circuit has two working states: 1) Active state; 2) Sleep state. In the Active state, the LDO circuit has high power consumption and strong driving ability, and can output large current for the digital circuit to assist the system in completing data communication, processing and storage functions. In the Sleep state, the LDO circuit has low power consumption and weak driving ability, and only provides current for the system in standby state, meeting the system's power consumption requirements in the Sleep state.

[0003] In the transition from standby to normal operation, the system requires the LDO circuit to quickly switch working states while maintaining the core voltage stable, restore driving capabilities, and provide large currents for the digital system to process, so that the system can respond to wake-up commands in time. However, in the Sleep state, the LDO circuit has extremely low power consumption and a slow response. How to provide large currents while maintaining the stability of the output voltage during the state transition process has become a difficult point in LDO circuit design.

[0004] Figure 1 It is an existing LDO circuit structure. The LDO circuit is composed of an error amplifier, a first sampling resistor R1, a second sampling resistor R2 and a power tube MP1. IB and Vref are the reference current and reference voltage provided by the LDO circuit respectively.

[0005] The working state of the LDO circuit is controlled by the control signal Vsleep. When the control signal Vsleep = "0", the LDO circuit works in the active state, the error amplifier consumes about 40uA, and the loop response is fast; when Vsleep = "1", the LDO circuit works in the sleep state, the error amplifier consumes about 1uA, and the loop response is slow.

[0006] When the LDO circuit is in steady state, whether in active state or sleep state, the loop working principle of the LDO circuit is: when the core voltage VDD drops, the sampling signal Vsample of the sampling resistor R1 and the sampling resistor R2 drops, the error amplifier outputs a signal to the first power tube MP1, the gate terminal voltage VC of the first power tube MP1 drops, the output current of the first power tube MP1 increases, and the core voltage VDD increases; conversely, the gate terminal voltage VC of the first power tube MP1 increases, the output current of the power tube MP1 decreases, and the core voltage VDD drops, and finally VDD=Vref*((R1+R2) / R2).

[0007] However, when switching from the sleep state to the active state, there are two factors that may cause the output core voltage VDD to be too low, causing the system to reset.

[0008] 1) Since the system needs to respond quickly to the wake-up command, at the moment of conversion, the oscillator, clock tree, RAM, ROM and other modules in the system will be started at the same time, and the core voltage VDD will have a momentary high current load;

[0009] 2) During the switching, the bias current of the error amplifier changes, the operating point needs to be re-established, the LDO circuit loop fails temporarily, and the gate voltage VC of the first power tube MP1 may be pulled up instantly, reducing the output current of the power tube and further exacerbating the reduction of the core voltage VDD;

[0010] Figure 2 It is a specific embodiment of the existing LDO circuit structure. Figure 2The dotted box is an error amplifier circuit, in which the eighth power tube MP8 and the ninth power tube MP9 form an input amplifier pair; the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9, as well as the sixth power tube MP6 and the seventh power tube MP7 form a 1:4 current amplifier, providing a 4-fold transconductance gain; the fourth power tube MN4 and the fifth power tube MN5 form a cascode tube, increasing the output impedance of the error amplifier; the third NMOS transistor MN3 is diode-connected, providing a bias voltage for the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5; the first NMOS transistor MN1 and the second NMOS transistor MN2 and the second power tube MP2, the third power tube MP3, the fourth power tube MP4 and the fifth power tube MP5 are current mirror circuits, providing current sources of different directions and sizes; the control signal Vsleep controls the output of the current source fifth power tube MP5 to switch the working state of the LDO circuit. When Vsleep = "1", the switch is turned off and the LDO circuit works in the sleep state; when Vsleep = "0", the switch is turned on and the LDO circuit works in the active state.

[0011] CM is a Miller capacitor, which adopts a zero-eliminating connection method and is connected to the source terminal of the fifth NMOS transistor MN5 to ensure the stability of the LDO circuit.

[0012] Reference current input IB = 0.5uA; the mirror ratio of the first NMOS transistor MN1 and the second NMOS transistor MN2 is 1:1; the mirror ratio of the second power tube MP2, the third power tube MP3, the fourth power tube MP4 and the fifth power tube MP5 is 1:1:0.5:20. It can be obtained:

[0013] In the active state, Vsleep = "0", the first switch S1 is turned on, and the error amplifier current consumption current is 35.875uA, wherein the seventh power tube MP7, the fifth NMOS transistor MN5 and the ninth NMOS transistor MN9 branch current are 20.5uA; in the sleep state, Vsleep = "1", the switch S1 is closed, and the error amplifier power consumption current is 0.875uA, wherein the seventh power tube MP7, the fifth NMOS transistor MN5 and the ninth NMOS transistor MN9 branch current are 0.5uA.

[0014] When the LDO circuit switches from the sleep state to the active state, the core voltage VDD has an instantaneous high power consumption, and the gate voltage VC of the first power tube MP1 is temporarily pulled up. The two together cause the core voltage VDD to drop rapidly, resulting in the risk of chip reset.

[0015] Figure 3 The figure is a diagram showing the state change of the existing LDO circuit. During the conversion process of the existing LDO circuit, the input current isink of the ninth NMOS transistor MN9 and the output current isource of the seventh power tube MP7 both rise from 0.5uA to 20.5uA instantly. Since the Miller capacitor CM is equivalent to an AC resistor under transient conditions, there is a transient current i from the core voltage VDD to the drain of the ninth NMOS transistor MN9. cm ; According to Ohm's law, we can get: At this moment, the current Δi (Δi=i source -i cm ) charges the gate terminal of the first power tube MP1, pulls up the gate terminal voltage VC of the first power tube MP1, and reduces the output current of the first power tube MP1. At the same time, the core voltage VDD load has an instantaneous high power consumption i load , the core voltage VDD is pulled down instantly, which can easily trigger a system reset. Summary of the invention

[0016] In view of the deficiencies in the above-mentioned prior art, an object of the present invention is to provide a new LDO circuit suitable for a large-capacity SIM card chip. The new LDO circuit includes a state transition control circuit. The state transition control circuit outputs a large current during the conversion process of the LDO circuit to maintain the stability of the VDD voltage and avoid the risk of system reset.

[0017] In order to achieve the above technical purpose, the technical solution adopted by the present invention is:

[0018] A novel LDO circuit suitable for a large-capacity SIM card chip, the LDO circuit comprising an error amplifier, a first sampling resistor, a second sampling resistor, a first power tube, a current source VCC, a core voltage VDD, a control signal, a reference current, a reference voltage and a state conversion control circuit, wherein the state conversion control circuit comprises a pulse generation circuit and an auxiliary bias circuit;

[0019] The pulse generating circuit is connected to the control signal and generates a pulse signal, the pulse signal is connected to and controls the auxiliary bias circuit, the auxiliary bias circuit is connected to the output end of the error amplifier, and the gate end of the first power tube is connected to the auxiliary bias circuit;

[0020] The pulse generating circuit utilizes the change from low to high of the control signal during switching to generate a pulse signal. Under the control of the pulse signal, the auxiliary bias circuit forces the gate terminal voltage of the first power tube to drop when the state of the LDO circuit is switched. The output current of the first power tube meets the core voltage load requirement. After the state switching of the LDO circuit is completed, the control signal no longer generates high-low conversion, and the LDO circuit is automatically closed.

[0021] Preferably, the pulse generating circuit is composed of an inverter, a capacitor and a NOR gate, the inverter is connected to the capacitor, and the capacitor is connected to the NOR gate.

[0022] Preferably, the auxiliary bias circuit is composed of a current source power tube, a switch and a capacitor.

[0023] The novel LDO circuit of the present invention adopts a state switching control circuit, and thus has the beneficial effect that the state switching control circuit uses a control signal to control the gate voltage of the first power tube MP1 at the switching moment, so that the first power tube continues to output a sufficiently large current until the state switching of the novel LDO circuit is completed, thereby maintaining the stability of the core voltage VDD and avoiding the risk of system reset.

[0024] Furthermore, the state transition control circuit of the present invention utilizes the control signal Vsleep to assist the novel LDO circuit to output a large current during the state transition process, thereby maintaining the stability of the core voltage VDD.

[0025] Compared with the existing LDO circuit, the novel LDO circuit of the present invention effectively avoids the problem of core voltage VDD being reset when switching from an active state to a sleep state, because the load current of the novel LDO circuit is too large and the working point cannot be established in time, thereby ensuring that the novel LDO circuit can respond to an external wake-up command quickly and timely. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0027] Figure 1 This is a diagram of the existing LDO circuit structure.

[0028] Figure 2 FIG. 5 is a diagram showing a specific embodiment of an existing LDO circuit structure.

[0029] Figure 3 This is a diagram showing the switching state changes of an existing LDO circuit.

[0030] Figure 4 It is a structural diagram of the novel LDO circuit of the present invention.

[0031] Figure 5 It is a specific embodiment of the novel LDO circuit structure of the present invention.

[0032] Figure 6It is a specific embodiment of the timing diagram of the pulse generating circuit of the present invention.

[0033] Figure 7 It is a timing diagram of key node voltages when the novel LDO circuit of the present invention switches states. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] See also Figure 4 The figure shows the structure diagram of the novel LDO circuit of the present invention. The novel LDO circuit suitable for a large-capacity SIM card chip includes an error amplifier, a first sampling resistor R1, a second sampling resistor R2, a first power tube MP1, a current source VCC, a core voltage VDD, a control signal Vsleep, a reference current IB, a reference voltage Vref and a state conversion control circuit, wherein the state conversion control circuit includes a pulse generating circuit and an auxiliary bias circuit; the pulse generating circuit is connected to the control signal Vsleep and generates a pulse signal Vpulse, the pulse signal Vpulse is connected to and controls the auxiliary bias circuit, the auxiliary bias circuit is connected to the output end of the error amplifier, and the gate end of the first power tube MP1 is connected to the auxiliary bias circuit.

[0037] See also Figure 4 As shown, the pulse generating circuit utilizes the change from low to high of the control signal Vsleep during switching to generate the pulse signal Vpulse. Under the control of the pulse signal Vpulse, the auxiliary bias circuit forces the gate terminal voltage VC of the first power tube MP1 to decrease when the state of the LDO circuit is switched. The output current of the first power tube MP1 meets the load requirement of the core voltage VDD. After the state switching of the LDO circuit is completed, the control signal Vsleep no longer generates a high-low change, and the LDO circuit is automatically turned off.

[0038] See also Figure 5 As shown in FIG. 1 , a specific embodiment of the novel LDO circuit structure of the present invention is shown. Figure 5In the dotted box shown, the current source eighth power tube MP8, the second switch S2 and the first capacitor C1 are added to the bias circuit composed of the third power tube MP3 and the third NMOS transistor MN3 in the original error amplifier; the eighth power tube MP8, the second switch S2 and the first capacitor C1 constitute an auxiliary bias circuit. The inverter I1, the second capacitor C2 and the NOR gate I2 constitute a pulse generating circuit, the inverter I1 is connected to the second capacitor C2, and the second capacitor C2 is connected to the NOR gate I2; the pulse signal Vpulse generated by the pulse generating circuit controls the second switch S2, which is turned on when high and turned off when low.

[0039] See also Figure 6 As shown in FIG. 1 , a specific embodiment of the timing diagram of the pulse generating circuit of the present invention is shown. When the LDO circuit switches from the sleep state to the active state, the voltage of the control signal Vsleep changes from high to low; due to the effect of the second capacitor C2, the control signal Vsleep_N at the output end of the inverter I1 will increase from low to high after a delay; the output of the NOR gate I2 will briefly output a high pulse; the pulse size t pulse Depends on the size of the second capacitor C2, Figure 6 Specific embodiment design C2 = 0.5pF, t pulse =0.1uS.

[0040] See also Figure 6 In the specific embodiment shown, at t pulse During this period, the second switch S2 is turned on, the current source eighth power tube MP8 is briefly turned on, generating a pulse current ipulse to charge the node VB, the node VB voltage rises instantly, pulling the fifth NMOS transistor MN5 to generate i sink1 , the size of isink1 depends on the size of the current source eighth power tube MP8, Figure 6 The specific embodiment ensures that isink1 is greater than isink and isource and does not generate excessive current glitches. Figure 6 In the specific embodiment, the mirror ratio of the eighth power tube MP8 to the third power tube MP3 is 40:1, and Δi=isink1-isink in the figure.

[0041] From Ohm's law, we know that sink1 After the generation, 1) the parasitic capacitance of the gate voltage VC node of the first power tube MP1 begins to discharge, the discharge current is Δi, and the VC voltage drops; 2) the Miller capacitor CM reversely charges the core voltage VDD, and the charging current is also Δi, which replenishes the charge consumed by the core voltage VDD; the decrease of the gate voltage VC of the first power tube MP1 drives the first power tube MP1 to output a large current, which effectively supplements the transient large power consumption iload generated by the system when the new LDO circuit is switched, ensuring the stability of the core voltage VDD.

[0042] The function of the first capacitor C1 is to store i pulse Charging the charge and ensuring that after the second switch S2 is turned off, the voltage at the node VB slowly drops to the original working point, and no large disturbance is generated on the gate terminal voltage VC of the first power tube MP1; Figure 6 In the specific embodiment, if the first capacitor C1 is too large, the node VB voltage cannot be pulled up instantly, and the core voltage VDD cannot be saved; if the first capacitor C1 is too small, the node VB voltage overshoots too much, and the core voltage VDD may produce a large upward overshoot voltage; as a compromise, the first capacitor C1 takes a value of 0.2pF.

[0043] See also Figure 7 As shown in FIG. 1 , it is a timing diagram of the voltage at key nodes when the novel LDO circuit of the present invention switches state. Figure 6 and Figure 3 As shown, from Figure 7 From the comparison of the core voltage VDD shown, it can be seen that the new LDO circuit using the state transition control circuit can effectively eliminate the drop of the core voltage VDD during the state transition, avoid the reset risk of the new LDO circuit, and ensure that the new LDO circuit can respond to the external wake-up command quickly and promptly.

[0044] It should be noted that the above embodiments are only schematic illustrations of the basic concept of the present invention, and the component circuits related to the present invention are not drawn according to the number, shape, device arrangement, and connection method of the component circuits in actual implementation. The type, number, connection method, device arrangement, and device parameters of each circuit in actual implementation can be changed at will.

[0045] The above-described embodiments are only preferred embodiments of the present invention and cannot limit the extension of the technical solution of the present invention. Any modification, equivalent change and obvious replacement of the known technology made by those skilled in the art on the basis of the technical solution of the present invention shall fall within the protection scope of the present invention.

Claims

1. A new LDO circuit suitable for large-capacity SIM card chips, characterized in that: The LDO circuit includes an error amplifier, a first sampling resistor, a second sampling resistor, a first power tube, a current source VCC, a core voltage VDD, a control signal, a reference current, a reference voltage and a state conversion control circuit, wherein the state conversion control circuit includes a pulse generation circuit and an auxiliary bias circuit; The pulse generating circuit is connected to the control signal and generates a pulse signal, the pulse signal is connected to and controls the auxiliary bias circuit, the auxiliary bias circuit is connected to the output end of the error amplifier, and the gate end of the first power tube is connected to the auxiliary bias circuit; The pulse generating circuit generates a pulse signal by utilizing the change from low to high of the control signal during switching. Under the control of the pulse signal, the auxiliary bias circuit forces the gate terminal voltage of the first power tube to drop when the state of the LDO circuit is switched. The output current of the first power tube meets the core voltage load requirement. After the state switching of the LDO circuit is completed, the control signal no longer generates a high-low change, and the LDO circuit is automatically turned off. The auxiliary bias circuit is composed of a current source power tube, a switch and a capacitor; the switch is controlled by a pulse signal generated by a pulse generating circuit; when the pulse signal is at a high level, the switch is turned on, the current source power tube is briefly turned on, and then a discharge current is generated that can force the gate terminal voltage of the first power tube to drop; the drop in the gate terminal voltage of the first power tube drives the first power tube to output a current that meets the core voltage load requirement.

2. The novel LDO circuit suitable for a large-capacity SIM card chip as claimed in claim 1, characterized in that: The pulse generating circuit is composed of an inverter, a capacitor and a NOR gate, the inverter is connected to the capacitor, and the capacitor is connected to the NOR gate.

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