Memory controller, memory system, and operating method of memory system

Abstract

A memory controller, a memory system, and an operating method of a memory system are provided. The operating method includes setting, for each of a plurality of operating states of a memory chip among a plurality of memory chips, a parameter indicating a number of memory chips allowed to operate in parallel based on information related to power consumption of each of the plurality of operating states of the memory chip; obtaining information related to an operating state of each of the plurality of memory chips; and scheduling data accesses through a plurality of channels respectively corresponding to the plurality of memory chips based on the parameter and the information related to the operating state of each of the plurality of memory chips.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2019-0148089, filed November 18, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The inventive concept relates to a memory controller, a memory system, and an operating method of a memory system. BACKGROUND

[0003] A memory system can include a plurality of memory chips, a memory controller, and a plurality of channels connecting the memory chips to the memory controller. Power can be managed in the memory system by applying a method of preventing operation of some channels or by reducing an operation frequency. However, from a quality of service (QoS) perspective, such a method can severely degrade performance and cannot dynamically adapt, thus resulting in a case where total power consumption exceeds an allowable power amount. SUMMARY

[0004] At least one embodiment of the inventive concept provides a memory controller, a memory system, and an operating method of a memory system that schedules data transmission or reception of a plurality of channels based on information about operation states of a plurality of chips, thereby preventing total power consumption from exceeding an allowable power level and maximizing memory utilization.

[0005] According to an exemplary embodiment of the inventive concept, there is provided an operating method of a memory system including a memory device including a plurality of memory chips. The operating method includes setting, for each of a plurality of operation states of a memory chip among the plurality of memory chips, a parameter indicating a number of memory chips allowed to operate in parallel based on information about power consumption of each of the plurality of operation states of the memory chip; obtaining information about an operation state of each of the plurality of memory chips; and scheduling data access on a plurality of channels corresponding to the plurality of memory chips based on the parameter and the information about the operation state of each of the plurality of memory chips.

[0006] According to exemplary embodiments of the inventive concept, there is provided a memory system including a memory device including a plurality of memory chips, a memory controller configured to control an operation of the memory device, and a plurality of channels configured to connect each of the plurality of memory chips to the memory controller. The memory controller is configured to check an operation state of each of the plurality of memory chips, and based on information related to power consumption of each of a plurality of operation states of the memory chips among the plurality of memory chips, schedule data access on the plurality of channels by using a parameter and the checked operation state of each of the plurality of memory chips, the parameter indicating a number of memory chips that are allowed to operate in parallel for each of the plurality of operation states.

[0007] According to exemplary embodiments of the inventive concept, there is provided a memory controller for controlling an operation of a memory device including a plurality of memory chips, the memory controller including a memory interface (I / F) configured to transmit or receive data via a plurality of channels connecting each of the plurality of memory chips to the memory controller, and a channel arbitration module configured to, when a request for approval of data transmission or reception via a first channel has been received from the memory I / F, obtain information related to an operation state of each of the plurality of memory chips, and based on power consumption of each of a plurality of operation states of the memory chips, determine whether to approve the first channel based on a parameter and the information related to the operation state of each of the plurality of memory chips, the parameter indicating a number of memory chips that are allowed to operate in parallel for each of the plurality of operation states, and provide a result of the determination to the memory I / F. BRIEF DESCRIPTION OF DRAWINGS

[0008] The exemplary embodiments of the inventive concept will become more fully understood from the detailed description given herein below, and the accompanying drawings, wherein:

[0009] Figure 1 is a block diagram of a computing system according to exemplary embodiments of the inventive concept;

[0010] Figure 2A and Figure 2B is a parameter table according to exemplary embodiments of the inventive concept;

[0011] Figure 3 is a table showing information related to respective operation states of a plurality of memory chips according to exemplary embodiments of the inventive concept;

[0012] Figures 4A to 4CA method of scheduling data transmission or reception for each operating lane of a memory chip according to example embodiments of the inventive concept is shown;

[0013] Figure 5 A block diagram of a memory system according to example embodiments of the inventive concept is shown;

[0014] Figure 6 A block diagram of a memory controller according to example embodiments of the inventive concept is shown;

[0015] Figure 7 A block diagram of a lane arbitration module according to example embodiments disclosed is shown;

[0016] Figure 8A And Figure 8B A method of generating a job schedule according to example embodiments of the inventive concept is shown;

[0017] Figure 9 A block diagram of a method of scheduling data transmission or reception for a lane according to example embodiments of the inventive concept is shown;

[0018] Figure 10 A flowchart of a method of scheduling data transmission or reception for a plurality of lanes according to example embodiments of the inventive concept is shown;

[0019] Figure 11 A flowchart of a method of scheduling data transmission or reception for a plurality of lanes according to example embodiments of the inventive concept is shown;

[0020] Figure 12 A flowchart of a method of determining whether to approve or disapprove a target lane according to example embodiments of the inventive concept is shown;

[0021] Figure 13 A flowchart of a method of determining whether to approve or disapprove a target lane according to example embodiments of the inventive concept is shown;

[0022] Figure 14 A block diagram of a computing system according to example embodiments of the inventive concept is shown;

[0023] Figure 15 A block diagram of a memory system according to example embodiments of the inventive concept is shown;

[0024] Figure 16 A block diagram of a memory system according to example embodiments of the inventive concept is shown;

[0025] Figure 17 A block diagram of a memory device according to example embodiments of the inventive concept is shown;

[0026] Figure 18is a view for explaining a three-dimensional (3D) V-NAND structure according to an exemplary embodiment of the inventive concept;

[0027] Figure 19 is a view for explaining a BVNAND structure according to an exemplary embodiment of the inventive concept;

[0028] Figure 20 is a block diagram of a system to which a storage device is applied according to an exemplary embodiment of the inventive concept; and

[0029] Figure 21 is a block diagram of a universal flash storage (UFS) system for explaining an exemplary embodiment according to the inventive concept. DETAILED DESCRIPTION

[0030] Figure 1 is a block diagram of a computing system 10 according to an exemplary embodiment of the inventive concept.

[0031] Referring to Figure 1 , the computing system 10 includes a host 100 (e.g., a host device) and a memory system 200. The memory system 200 includes a memory controller 210 (e.g., a control circuit) and a memory device 220.

[0032] The host 100 provides a command CMD or data DATA associated with the command CMD for a memory operation to the memory system 200. For example, the host 100 can provide a write or read request of data to the memory system 200. According to a data erase request from the host 100, the memory system 200 can perform an erase operation for data of an area indicated by the host 100. According to an embodiment, the host 100 can correspond to a central processing unit (CPU), a processor, a microprocessor, or an application processor (AP). According to one exemplary embodiment, the host 100 can be implemented as a system on chip (SoC). Although the transmission or reception of the command CMD or the data DATA between the host 100 and the memory system 200 is performed via different channels in Figure 1 , embodiments of the inventive concept are not limited thereto. According to one exemplary embodiment, the transmission or reception of the command CMD or the data DATA can be performed via a single channel.

[0033] The memory system 200 can include a storage medium for storing data according to a request from the host 100. For example, the memory system 200 can include one or more solid state drives (SSDs). However, the inventive concept is not limited thereto, and the memory system 200 can be implemented as any one of various types of devices such as an embedded multi-media card (eMMC), a universal flash storage (UFS), or a compact flash (CF) card, a secure digital (SD) card, a micro secure digital (Micro-SD) card, a mini secure digital (Mini-SD) card, an extreme digital (xD) card, or a memory stick.

[0034] When the memory system 200 includes an SSD, the memory device 220 can include a plurality of flash memory chips (e.g., NAND memory chips) that store data in a non-volatile manner. Alternatively, the memory device 220 can correspond to one flash memory device, or the memory device 220 can include a memory card including one or more flash memory chips.

[0035] When the memory system 200 includes a flash memory, the flash memory can include a two-dimensional (2D) NAND memory array or a three-dimensional (3D) (or vertical) NAND (VNAND) memory array. The 3D memory array is formed monolithically on one or more physical levels in an array of memory cells having active regions disposed on or above a silicon base, or in a circuit formed on or above or within the silicon base as circuitry related to the operation of the memory cells. The term "monolithically" indicates that the layers of each level constituting the array are directly stacked above the layers of each underlying level of the array.

[0036] According to an embodiment of the inventive concept, the 3D memory array includes vertical NAND strings arranged in a vertical direction such that at least one memory cell is located on or above another memory cell. The at least one memory cell can include a charge-trapping layer.

[0037] Suitable configurations of the 3D memory array are described in the following patent documents, which are hereby incorporated by reference in their entirety, wherein the 3D memory array is configured as a plurality of levels sharing word lines and / or bit lines between the plurality of levels: U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and U.S. Patent Publication No. 2011 / 0233648.

[0038] As another example, the memory system 200 can include various other types of memory. For example, the memory system 200 can include non-volatile memory. Examples of non-volatile memory can include various types of memory such as magnetic random access memory (MRAM), spin-transfer torque MRAM, conductive-bridging RAM (CBRAM), ferroelectric RAM (FeRAM), phase-change RAM (PRAM), resistive RAM, nanotube RAM, polymer RAM (PoRAM), nanofloating gate memory (NFGM), holographic memory, molecular electronic memory, and phase change memory.

[0039] The memory controller 210 can control memory operations such as data writing and data reading with respect to the memory device 220. The memory controller 210 can control memory operations with respect to the memory device 220 via one or more channels. For example, the memory controller 210 can be connected to the memory device 220 via n (where n is a positive integer) channels CH1 to CHn, and can write or read data. The memory controller 210 can control the memory devices 220 connected to different channels in parallel.

[0040] According to one example embodiment, the memory device 220 includes a plurality of memory chips. The memory device 220 can include one or more memory chips to correspond to each of the n channels CH1 to CHn. The memory controller 210 can queue commands CMD for each of the n channels CH1 to CHn according to commands CMD (or requests) received from the host 100, and can transmit or receive the commands CMD or data DATA related to the commands CMD to or from the memory device 220 via the n channels CH1 to CHn. For example, the memory controller 210 can include a buffer in which the commands CMD are stored until they are executed.

[0041] According to one example embodiment of the inventive concept, the memory controller 210 includes a channel arbitration module 211 that arbitrates (or manages) the n channels CH1 to CHn. The channel arbitration module 211 can be implemented in various ways, and can be included in the memory controller 210. For example, the channel arbitration module 211 can be implemented as hardware such as a circuit that arbitrates a plurality of channels. Alternatively, the channel arbitration module 211 can be implemented as software including a program, and a processing unit can perform various types of processing related to arbitration of a plurality of channels by executing the channel arbitration module 211 loaded in an operating memory. Alternatively, the channel arbitration module 211 can be implemented as a combination of hardware and software. Although the channel arbitration module 211 is described as being included in the memory controller 210, the channel arbitration module 211 can be included in the memory device 220. Figure 1The channel arbitration module 211 is included in the memory controller 210, but embodiments of the inventive concept are not limited thereto. For example, the channel arbitration module 211 can be disposed outside the memory controller 210, but within the memory system 200.

[0042] In one exemplary embodiment, the channel arbitration module 211 supports a function of arbitrating a plurality of channels connecting the memory controller 210 to the memory device 220. For example, the channel arbitration module 211 can check operating states of a plurality of memory chips of the memory device 220, and arbitrate the n channels CH1 to CHn based on the checked operating states and information about power consumption of each operation.

[0043] In one exemplary embodiment, the channel arbitration module 211 calculates a current total power consumption (e.g., power consumption of the memory system 200 or the memory device 220) based on the checked operating states of the plurality of memory chips and the information about power consumption of each operation, and predicts whether the total power consumption will exceed the allowable power amount when the memory device 220 additionally performs memory operations corresponding to the queued commands CMD. When it is predicted that the total power consumption will exceed the allowable power amount, the channel arbitration module 211 defers transmission of the queued commands CMD, and can restrict data transmission or reception through channels corresponding to the respective queued commands CMD. On the other hand, when it is predicted that the total power consumption will not exceed the allowable power amount, the channel arbitration module 211 transmits the queued commands CMD, and can allow data transmission or reception through channels corresponding to the queued commands CMD.

[0044] Accordingly, it is possible to prevent power consumption from exceeding the allowable power amount while the memory controller 210 transmits a plurality of commands CMD to the memory device 220, and the memory device 220 performs memory operations (or processing of commands) corresponding to the plurality of commands CMD.

[0045] The operations of the memory chips can include at least one of a program operation, a read operation, an erase operation, and an idle state. The program operation can be divided into a plurality of detailed operations. For example, the program operation can be divided into a data input / output (I / O) operation (referred to as a first program operation for convenience of explanation) and a data write operation (referred to as a second program operation for convenience of explanation). The I / O operation corresponds to an operation in which a program command CMD and data DATA are input to the memory chip through a channel and are buffered in an I / O buffer (not shown) included in the memory chip. The data write operation corresponds to an operation in which the data DATA buffered in the I / O buffer included in the memory chip is programmed or written to a memory cell array. Each of the first program operation and the second program operation constitutes a part of the entire program operation, but the two operations can be distinguished from each other because of a large difference in power consumption between the two operations. For example, the I / O operation can consume a first amount of power, and the data write operation can consume a second amount of power different from the first amount.

[0046] The above-described operation types of the memory chips are merely examples, and embodiments of the inventive concept are not limited thereto. For example, the read operation can be divided into an operation of reading data DATA from the memory cell array and an operation of inputting the read data DATA to the memory controller 210 via the channel.

[0047] According to one exemplary embodiment of the inventive concept, the channel arbitration module 211 sets a parameter based on information related to power consumption of each operation and arbitrates the n channels CH1 to CHn by using the set parameter and operation states of the plurality of memory chips. The parameter can be the number of memory chips that can perform each storage operation in parallel as long as the total power consumption does not exceed a preset power amount (i.e., an allowable power amount). For example, the parameter can be the maximum number of memory chips that can perform the first program operation in parallel as long as the total power consumption does not exceed the allowable power amount. Because the operations of the memory chips can include the second program operation, the read operation, and the erase operation in addition to the first program operation, different parameters (e.g., sub-parameters) can be set for these different operations, respectively. The above-described plurality of parameters can be included in a single parameter table. The parameter table can be stored in the memory controller 210 or the memory device 220. The method of setting the parameter is not limited to the above-described exemplary method.

[0048] As one example of arbitration using a parameter, the channel arbitration module 211 can allow data transmission or reception through a number of channels corresponding to the parameter. For example, the channel arbitration module 211 can allow data transmission or reception through a number of channels corresponding to the parameter including a channel corresponding to a memory chip that is currently performing an operation. For example, the channel arbitration module 211 can allow data transmission or reception through only a channel connected to a memory chip that is currently performing an operation. In other words, when the number of memory chips that are currently performing an operation is less than the parameter, the channel arbitration module 211 can allow data transmission or reception through a channel corresponding to a queued command CMD. On the other hand, when the number of memory chips that are currently performing an operation is equal to the parameter, the channel arbitration module 211 does not allow data transmission or reception of a channel corresponding to a queued command CMD.

[0049] Accordingly, the channel arbitration module 211 can manage power consumption of the memory system 200 via comparison with a preset parameter without calculating power consumption, and thus can reduce the number of calculations performed.

[0050] The computing system 10 according to the above-described embodiments can maximize memory utilization by scheduling data transmission or reception through a plurality of channels based on information about operating states of a plurality of chips within the memory device 220 and information about power consumption of each operation (or a parameter set based on information about power consumption of each operation). Accordingly, the computing system 10 according to the above-described embodiments can ensure higher system performance and ensure high QoS by preventing total power consumption from exceeding an allowable power level, as compared with a conventional inefficient power management method.

[0051] Figure 2A and Figure 2B is a parameter table according to exemplary embodiments of the inventive concept.

[0052] Referring to Figure 2A , the parameter table TABLE A can include different parameters for each operation of a memory chip or each combination of operations of memory chips. Each operation of a memory chip can include at least one of the first programming operation PG, the second programming operation tPROG, the read operation RD, and the erase operation ER described above with reference to Figure 1 , and the combination of operations of memory chips can include at least one of a combination of the first programming operation PG and the erase operation ER (see, e.g., parameter 5), a combination of the erase operation ER and the read operation RD (see, e.g., parameter 6), a combination of the first programming operation PG and the read operation RD (see, e.g., parameter 7), and a combination of the first programming operation PG, the erase operation ER, and the read operation RD (see, e.g., parameter 8). Each operation of a memory chip or each combination of operations of memory chips is not limited thereto.

[0053] The columns of the parameter table TABLE A indicate parameters (first parameter to eighth parameter) corresponding to each operation of the memory chip or each combination of operations of the memory chip. For example, in the parameter table TABLE A, the first parameter (e.g., parameter 1) can indicate a parameter corresponding to the first program operation PG, the seventh parameter (e.g., parameter 7) can indicate a parameter corresponding to a combination of the first program operation PG and the read operation RD, and the eighth parameter (e.g., parameter 8) can indicate a parameter corresponding to a combination of the first program operation PG, the erase operation ER, and the read operation RD.

[0054] The rows of the parameter table TABLE A can represent the number of memory chips capable of performing an operation corresponding to a corresponding parameter. For example, in the parameter table TABLE A, X1 of the first parameter corresponding to the first program operation PG can represent the maximum number of memory chips capable of performing the first program operation PG. X3 and Y2 of the fifth parameter corresponding to a combination of the first program operation PG and the erase operation ER can represent the maximum number of memory chips capable of performing the first program operation PG and the maximum number of memory chips capable of performing the erase operation ER, respectively.

[0055] Figure 1 The channel arbitration module 211 of the memory system 200 can check a parameter corresponding to an operation of a current memory chip from the parameter table TABLE A, and can approve data transmission or reception through a number of channels corresponding to the parameter. For example, when the current memory chip performs the first program operation PG, the channel arbitration module 211 can check X1 (e.g., 3) as a parameter corresponding to the first program operation PG, and can approve data transmission or reception through a number of channels (e.g., 3 channels) corresponding to X1.

[0056] A plurality of parameter tables as described above can be set. According to one exemplary embodiment, different parameter tables are set according to different temperature ranges. The power consumption due to the operation of the memory chip can vary according to the temperature of the memory system. Accordingly, in order to perform power management suitable for the temperature of the memory system, the channel arbitration module 211 can set different parameter tables according to different temperature ranges, and can schedule data transmission or reception of a plurality of channels by using a parameter table corresponding to the temperature of the memory system.

[0057] Referring to Figure 2BParameter table B may correspond to a temperature range B that is different from the temperature range A of parameter table A. Similar to parameter table A, in parameter table B, columns may indicate parameters (first to eighth parameters) corresponding to each operation of the memory chip or each combination of operations of the memory chip, and rows may indicate the number of memory chips capable of performing the operation corresponding to the respective parameter. Temperature range B may be higher or lower than temperature range A. In an exemplary embodiment, when temperature range B is higher than temperature range A, the parameters included in parameter table B have values ​​smaller than the values ​​of the parameters included in parameter table A.

[0058] Figure 1 The channel arbitration module 211 can check TABLE B, which corresponds to the temperature of the current memory system, from multiple parameter tables (e.g., Table A and Table B), check parameters in TABLE B that correspond to the operation of the current memory chip, and approve data transmission or reception through the number of channels corresponding to those parameters. In one exemplary embodiment, the memory system 200 includes a temperature sensor, and the channel arbitration module 211 selects a suitable parameter table from the multiple parameter tables based on the temperature output by the temperature sensor, and checks the parameters corresponding to the selected parameter table to determine which channels should be approved for data transmission or reception.

[0059] Although it has been referenced Figure 2B The description describes channel arbitration module 211 managing power by using multiple parameter tables to take into account the temperature of the memory system based on a temperature range; however, embodiments of the inventive concept are not limited thereto. For example, channel arbitration module 211 may manage power by using an existing parameter table that has been corrected using a reference temperature and the current temperature.

[0060] Figure 3 This is a table showing information relating to the operating states of a plurality of memory chips according to exemplary embodiments of the inventive concept.

[0061] Reference Figure 3 This allows for the examination of operational status information representing the operational status of the eight memory chips Chip 1 to Chip 8 included in the memory device. Although already referenced... Figure 3 Eight memory chips are shown and described, but more or fewer memory chips can be implemented.

[0062] According to one exemplary embodiment, the information related to the operating state of the memory chip can include one or more bits. For example, when the operating state information has a value of three or more bits for each memory chip, each of the values can represent at least one of a first programming operation, a second programming operation, a read operation, an erase operation, and an idle state.

[0063] Referring to Figure 3 , the first chip Chip 1 and the eighth chip Chip 8 among the eight memory chips Chip 1 to Chip 8 are performing the first programming operation PG, the fourth chip Chip 4 is performing the read operation RD, and the remaining chips (i.e., the second chip Chip 2, the third chip Chip 3, the fifth chip Chip 5, the sixth chip Chip 6, and the seventh chip Chip 7) are in the idle state (e.g., ID).

[0064] Figures 4A to 4C A method of scheduling data transmission or reception of a channel for each operation of a memory chip is illustrated. Figures 4A to 4C A command is transmitted for each of a plurality of channels (i.e., first to eighth channels CH1 to CH8) according to time. Referring to Figures 1 to 3 The description given above is equally applicable to the present embodiment.

[0065] Figure 4A An embodiment in which a plurality of memory chips perform a first programming operation PG is illustrated. When the channel arbitration module 211 according to the exemplary embodiment of the inventive concept checks that a memory chip is performing a first programming operation PG, the channel arbitration module 211 can check a parameter table TABLE A to determine X1 as a parameter corresponding to the first programming operation PG. The channel arbitration module 211 can approve data transmission or reception through a number of channels corresponding to the parameter X1.

[0066] For example, when the parameter X1 corresponding to the first programming operation PG is 6, the channel arbitration module 211 can approve transmission or reception through a total of 6 channels. Referring to Figure 4A At a first time point t1, the channel arbitration module 211 receives a request signal for requesting approval of transmission or reception through the first channel CH1 and the fourth channel CH4. Since there is no channel corresponding to a memory chip performing a first programming operation PG at the first time point t1, the channel arbitration module 211 can approve transmission or reception through the first channel CH1 and the fourth channel CH4. Between the first time point t1 and a second time point t2, the channel arbitration module 211 can sequentially approve transmission or reception through the third channel CH3, the sixth channel CH6, the seventh channel CH7, and the second channel CH2. The memory chips corresponding to the channels through which transmission or reception has been approved can perform a first programming operation PG.

[0067] Because at the second time point t2, a total of 6 channels correspond to the memory chips that are executing the first programming operation PG, the channel arbitration module 211 does not approve transmission or reception through the fifth channel CH5 and the eighth channel CH8. Thus, transmission of commands via the fifth channel CH5 and the eighth channel CH8 is pending.

[0068] At the third time point t3, the channel arbitration module 211 can determine that the first programming operation PG of the memory chips corresponding to the first channel CH1 and the fourth channel CH4 has completed. In other words, because at the third time point t3, a total of 4 channels correspond to the memory chips that are executing the first programming operation PG, the channel arbitration module 211 can approve transmission or reception of the fifth channel CH5 and the eighth channel CH8, which are channels via which transmission of commands has been pending. For example, the channel arbitration module 211 can approve transmission or reception of the fifth channel CH5 and the eighth channel CH8 at or after the third time point t3.

[0069] Figure 4B Embodiments are shown in which a plurality of memory chips are executing the first programming operation PG and the second programming operation tPROG. When the channel arbitration module 211 according to embodiments of the inventive concept determines that the memory chips are executing the second programming operation tPROG, the channel arbitration module 211 can check the parameter table TABLE A to determine X2 and W1 as parameters corresponding to the second programming operation tPROG. The channel arbitration module 211 can approve transmission or reception of data associated with the first programming operation PG of a number of channels corresponding to the checked parameter X2, and can approve transmission or reception of data associated with the second programming operation tPROG of a number of channels corresponding to the checked parameter W1.

[0070] For example, when the parameter X2 corresponding to the first programming operation PG is 1 and the parameter W1 corresponding to the second programming operation tPROG is 3, the channel arbitration module 211 can approve transmission or reception of data associated with the first programming operation PG of a total of one channel, and can approve transmission or reception of data associated with the second programming operation tPROG of a total of three channels.

[0071] Referring to Figure 4B Because at the fourth time point t4, there are no channels corresponding to the memory chips that are executing the second programming operation tPROG, the channel arbitration module 211 can approve transmission or reception of the first channel CH1 through the third channel CH3. Because at the fourth time point t4, there are no channels corresponding to the memory chips that are executing the first programming operation PG, the channel arbitration module 211 can approve transmission or reception of the sixth channel CH6.

[0072] Because a total of one channel corresponds to the memory chip performing the first programming operation PG between the fifth time point t5 and the sixth time point t6, the channel arbitration module 211 does not approve transmission or reception through the fourth channel CH4, the fifth channel CH5, the seventh channel CH7, and the eighth channel CH8. Accordingly, command transmission via the fourth channel CH4, the fifth channel CH5, the seventh channel CH7, and the eighth channel CH8 is suspended.

[0073] At the sixth time point t6, the channel arbitration module 211 determines that the first programming operation PG of the memory chip corresponding to the sixth channel CH6 has been completed. In other words, because no channel corresponds to the memory chip performing the first programming operation PG at the sixth time point t6, the channel arbitration module 211 can approve transmission or reception through one of the channels via which command transmission has been suspended. The channel arbitration module 211 can approve transmission or reception through the channels via which command transmission has been suspended according to the order in which request signals for requesting approval of transmission or reception are received. For example, the channel arbitration module 211 can first approve transmission or reception of the fifth channel CH5 corresponding to the first received request signal among the fourth channel CH4, the fifth channel CH5, the seventh channel CH7, and the eighth channel CH8, which are channels via which command transmission has been suspended.

[0074] Figure 4C An embodiment in which a plurality of memory chips perform the first programming operation PG and the read operation RD is illustrated. When the channel arbitration module 211 according to the embodiment of the inventive concept determines that the memory chips are performing the first programming operation PG and the read operation RD, the channel arbitration module 211 can check the parameter table TABLE A to determine X4 and Z3 as parameters corresponding to the first programming operation PG and the read operation RD. In one exemplary embodiment, the channel arbitration module 211 determines that the memory chips are performing the first programming operation PG and the read operation RD at a certain time when at least one of the memory chips has been running the first programming operation PG at the certain time and at least one of the memory chips has been running the read operation RD at the certain time. The channel arbitration module 211 can approve transmission or reception of data associated with the first programming operation PG through a number of channels corresponding to the checked parameter X4, and can approve transmission or reception of data associated with the read operation RD through a number of channels corresponding to the checked parameter Z3.

[0075] For example, when the parameter X4 corresponding to the first programming operation PG is 3 and the parameter Z3 corresponding to the read operation RD is 3, the channel arbitration module 211 can approve transmission or reception through a total of 6 channels. Referring to Table 1, when the parameter X4 is 3 and the parameter Z3 is 3, the channel arbitration module 211 can approve transmission or reception through the first channel CH1, the second channel CH2, the third channel CH3, the fourth channel CH4, the fifth channel CH5, and the sixth channel CH6.Figure 4C At time point t7, the channel arbitration module 211 receives request signals for requesting approval for transmission or reception through the first channel CH1, the fourth channel CH4, and the seventh channel CH7. Because there are no channels corresponding to memory chips performing the first program operation PG or the read operation RD at the seventh time point t7, the channel arbitration module 211 can approve transmission or reception through the first channel CH1, the fourth channel CH4, and the seventh channel CH7. Between the time point t7 and a time point t8, the channel arbitration module 211 can sequentially approve transmission or reception through the third channel CH3, the sixth channel CH6, and the second channel CH2. Thus, three memory chips have been approved to perform the first program operation PG, and three other memory chips have been approved to perform the read operation.

[0076] Because there are a total of 6 channels corresponding to memory chips performing the first program operation PG and the read operation RD at the time point t8, the channel arbitration module 211 does not approve transmission or reception through the fifth channel CH5 and the eighth channel CH8. Thus, transmission of commands via the fifth channel CH5 and the eighth channel CH8 is suspended.

[0077] At a time point t9, the channel arbitration module 211 can determine that the read operation corresponding to the channels CH4 and CH7 has been completed, and the program operation corresponding to the channel CH1 has been completed. In other words, because there are a total of 3 channels corresponding to memory chips performing the first program operation PG and / or the read operation RD at the time point t9, the channel arbitration module 211 can approve transmission or reception of the fifth channel CH5 and the eighth channel CH8, which are channels for which transmission of commands has been suspended. For example, the channel arbitration module 211 can approve transmission or reception of the fifth channel CH5 and the eighth channel CH8 at or after the time point t9.

[0078] Figure 5 is a block diagram of a memory system 300 according to exemplary embodiments of the inventive concept.

[0079] Referring to Figures 1 to 5 , the memory system 300 includes a memory controller 310 (e.g., a control circuit) including a channel arbitration module 311 and a memory interface (I / F) 313 (e.g., an interface circuit), and a memory device 320 which can include n memory chips (NVMs) 321_1 to 321_n. The channel arbitration module 311 can correspond to Figure 1 the channel arbitration module 211 of FIG. 2.

[0080] The memory I / F 313 can transmit or receive data via n channels CH1 to CHn connecting the memory controller 310 to n memory chips 321_1 to 321_n of the memory device 320, respectively. The memory I / F 313 can queue commands CMD for each of the n channels CH1 to CHn, and can transmit or receive the commands CMD or data DATA via the n channels CH1 to CHn under the control of the memory controller 310. For example, the memory I / F 313 can include a buffer temporarily storing the commands CMD until they are executed.

[0081] According to one exemplary embodiment of the inventive concept, the memory I / F 313 transmits a request signal Req to the channel arbitration module 311 for requesting approval for transmission or reception via the first channel CH1 before transmitting the queued command CMD through the first channel CH1. When receiving an allowance signal Grant corresponding to the request signal Req from the channel arbitration module 311, the memory I / F 313 can transmit or receive the queued command CMD and data DATA related to the queued command CMD via the first channel CH1. On the other hand, when not receiving the allowance signal Grant corresponding to the request signal Req from the channel arbitration module 311, the memory I / F 313 defers transmission or reception via the first channel CH1.

[0082] According to one exemplary embodiment of the inventive concept, the channel arbitration module 311 receives the request signal Req from the memory I / F 313. In response to the request signal Req, the channel arbitration module 311 can obtain information Status related to respective operating states of the n memory chips 321_1 to 321_n. The information Status related to the respective operating states of the n memory chips 321_1 to 321_n can indicate which operating state among a first programming operation, a second programming operation, a read operation, an erase operation, and an idle state each of the n memory chips 321_1 to 321_n is in.

[0083] The channel arbitration module 311 can obtain the information Status related to the respective operating states of the n memory chips 321_1 to 321_n from the memory I / F 313 via various methods. For example, the channel arbitration module 311 can transmit a request (e.g., a signal) for the information Status related to the respective operating states to the memory I / F 313 in response to the request signal Req, and can receive the information Status related to the respective operating states from the memory I / F 313 in response to the transmitted request. Alternatively, the channel arbitration module 311 can continuously receive signals representing the respective operating states of the n memory chips 321_1 to 321_n from the memory I / F 313 via a specific hardware component, and can generate the information Status related to the respective operating states by using the signals in response to the request signal Req. Alternatively, the channel arbitration module 311 can receive the information on the operating states from the memory I / F 313 periodically regardless of the request signal Req.

[0084] The channel arbitration module 311 can determine whether the first channel CH1 is approved based on the information Status related to the respective operating states of the n memory chips 321_1 to 321_n and the parameters 312 set based on the power consumption of each operation of the memory chip. The parameters 312 can include different parameters for each operation of the memory chip or a combination of operations of the memory chip. For example, as in the above-described example of Figure 2A or Figure 2B The parameters 312 can be the maximum number of memory chips that can perform a program operation, a read operation, or an erase operation within the allowed amount of power, and can be the maximum number of memory chips that can perform operations included in each combination of the program operation, the read operation, and the erase operation within the allowed amount of power.

[0085] The parameters 312 can be stored in a memory (not shown) or a buffer (not shown) within the memory controller 310 and read therefrom by the channel arbitration module 311, or can be stored in a memory (not shown) within the channel arbitration module 311. The channel arbitration module 311 or the memory controller 310 can calculate the parameters 312 by using the power consumption of each operation and store the calculated parameters 312.

[0086] As an example of determining approval or disapproval of the first channel CH1 by using the information Status and the parameters 312 related to the respective operating states of the n memory chips 321_1 to 321_n, the channel arbitration module 311 can first determine a parameter corresponding to the current operation of the memory chips 321_1 to 321_n from the parameters 312 based on the information Status related to the respective operating states of the memory chips 321_1 to 321_n. For example, when the channel arbitration module 311 determines that the memory chips 321_1 to 321_n perform the first programming operation, the channel arbitration module 311 can determine a parameter corresponding to the first programming operation.

[0087] The channel arbitration module 311 can compare the determined parameter with the information Status related to the respective operating states of the n memory chips 321_1 to 321_n, and thus can determine whether the number of memory chips currently being operated has reached the maximum number. When the number of memory chips currently being operated does not reach the maximum number, even when the memory chips additionally perform the operation of the queued command CMD, the total power consumption does not exceed the allowable power amount, and thus the channel arbitration module 311 determines to approve the first channel CH1. On the other hand, when the number of memory chips currently being operated reaches the maximum number, the channel arbitration module 311 determines to disapprove the first channel CH1 to prevent the total power consumption from exceeding the allowable power amount.

[0088] The channel arbitration module 311 can transmit the result of the determination to the memory I / F 313. For example, when the channel arbitration module 311 determines to approve the first channel CH1, the channel arbitration module 311 transmits an approval signal Grant to the memory I / F 313. On the other hand, when the channel arbitration module 311 determines to disapprove the first channel CH1, the channel arbitration module 311 does not transmit the approval signal Grant to the memory I / F 313.

[0089] According to one example embodiment of the inventive concept, the memory I / F 313 transmits an end signal End instead of the request signal Req to the channel arbitration module 311. For example, when the operation of one of the memory chips 321_1 to 321_n has ended, the memory I / F 313 transmits the end signal End to the channel arbitration module 311. In response to the end signal End, the channel arbitration module 311 can again determine whether to approve or disapprove the first channel CH1. For example, when it has been determined that the first channel CH1 is not approved in response to the request signal Req, since the operation of one of the memory chips 321_1 to 321_n has ended, the channel arbitration module 311 re-determines whether the total power consumption does not exceed the allowable power amount even when the operation corresponding to the queued command CMD for the first channel CH1 is performed. When the channel arbitration module 311 has transmitted the grant signal Grant for the first channel CH1 in response to the request signal Req, the operation of re-determining whether to approve or disapprove the first channel CH1 can be omitted. The operation of determining whether to approve or disapprove the first channel CH1 in response to the end signal End performed by the channel arbitration module 311 is substantially the same as the above-described operation of determining whether to approve or disapprove the first channel, and thus, a redundant description thereof is omitted.

[0090] Figure 6 is a block diagram of a memory controller 400 according to an example embodiment of the inventive concept.

[0091] Referring to Figures 1 to 6 , the memory controller 400 can include a host I / F 410 (e.g., a circuit), a processor 420, a memory 430, a temperature sensor 440 (e.g., a thermocouple), and a memory I / F 450. The memory 430 includes a channel arbitration module 431. The channel arbitration module 431 can correspond to one of the channel arbitration module 211 of Figure 1 and the channel arbitration module 311 of Figure 5 .

[0092] The host I / F 410 can communicate with a host HOST (e.g., a host device) via various I / F. According to one embodiment, the host I / F 410 can communicate with the host HOST via various I / F such as a Universal Serial Bus (USB), a Multimedia Card (MMC), a PCI Express (PCI-E), an AT Attachment (ATA), a Serial AT Attachment (SATA), a Parallel AT Attachment (PATA), a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), an Enhanced Small Disk Interface (ESDI), and an Integrated Drive Electronics (IDE). For example, the host I / F can implement a Non-Volatile Memory Express (NVMe) as an I / F optimized for a memory system such as an SSD.

[0093] According to one exemplary embodiment of the inventive concept, the host I / F 410 receives specification information of the host HOST from the host HOST. The specification information can include, for example, information on a device type, model information, and information on a required amount of power consumption of the memory system. The information included in the specification information is not limited thereto.

[0094] The channel arbitration module 431 can set the parameter based on the received specification information of the host HOST. For example, because the allowable amount of power can vary according to the type of the host HOST, the channel arbitration module 431 can set the parameter based on the allowable amount of power corresponding to the specification information of the host HOST. For example, the channel arbitration module 431 can set different parameters for each host for which it receives the specification information.

[0095] The processor 420 can include a CPU or a microprocessor, and can control the overall operation of the memory controller 400 by executing instructions stored in the memory 430. Figure 6 One processor 420 is shown. However, embodiments of the inventive concept are not limited thereto, because the memory controller 400 can include a plurality of processors 420.

[0096] The memory 430 can operate under the control of the processor 420, and can be implemented as a volatile memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), or can be implemented as a non-volatile memory such as a phase change random access memory (PRAM) or a flash memory. The channel arbitration module 431 can be implemented as firmware or software, and can be loaded in the memory 430. Although the channel arbitration module 431 is loaded in the memory 430 in Figure 6 However, embodiments of the inventive concept are not limited thereto. For example, the channel arbitration module 431 can be loaded in a memory (not shown) located outside the memory controller 400, and can be arranged to be implemented as a special component of hardware inside or outside the memory controller 400.

[0097] The temperature sensor 440 can sense a temperature. According to one exemplary embodiment, the temperature sensor 440 is arranged inside the memory controller 400 to sense an ambient temperature, and outputs a voltage corresponding to the sensed temperature as temperature information. Although the temperature sensor 440 is included in the memory controller 400 in Figure 6 However, embodiments of the inventive concept are not limited thereto. For example, the temperature sensor 440 can be arranged inside or near the memory device, and can sense an ambient temperature around the memory device. Figure 6 One temperature sensor 440 is shown. However, according to another embodiment, the memory controller 400 includes a plurality of temperature sensors 440.

[0098] According to one exemplary embodiment of the inventive concept, the channel arbitration module 431 sets different parameters according to different temperature ranges. Since the allowable power amount can vary according to the temperature of the memory system, the channel arbitration module 431 can set different parameters according to the allowable power amounts corresponding to different temperature ranges, respectively. For example, when the temperature is relatively high, the channel arbitration module 431 can set the parameters based on a relatively low allowable power amount. In one exemplary embodiment, when the temperature is a first temperature value, the channel arbitration module 431 sets a first parameter based on a first allowable power amount, and when the temperature is a second temperature value, the channel arbitration module 431 sets a second parameter based on a second allowable power amount, wherein the first allowable power amount is lower than the second allowable power amount when the first temperature value is higher than the second temperature value.

[0099] When the channel arbitration module 431 receives a request signal for requesting approval of transmission or reception through a specific channel from the memory I / F 450, the channel arbitration module 431 can obtain temperature information from the temperature sensor 440, and can obtain information about respective operating states of the plurality of memory chips of the memory device. The channel arbitration module 431 can determine a parameter corresponding to the temperature of the memory system from among a plurality of parameters by using the obtained temperature information, and can schedule transmission or reception of data through a plurality of channels by using the determined parameter and the operating states of the plurality of memory chips of the memory device. In Figure 6 In the above-described embodiment, the memory controller 400 includes the temperature sensor 440. However, according to another embodiment, the temperature sensor 440 is omitted.

[0100] According to one exemplary embodiment of the inventive concept, the parameters can be set by further considering specification information or temperature information of the host in addition to power consumption of each operation of the memory chip, and data transmission or reception of the plurality of channels can be controlled using parameters conforming to the situation (e.g., condition or state) of the memory system, thereby resulting in more optimized power management of the memory system.

[0101] Figure 7 is a block diagram of a channel arbitration module 500 according to an exemplary embodiment of the present disclosure.

[0102] Referring to Figures 1 to 7 , the channel arbitration module 500 includes a parameter 510, an arbitration core 520, a job scheduler 530, and a state checker 540. The parameter 510 is substantially the same as the parameter 312 of Figure 5 , and thus a detailed description thereof will be omitted. When the channel arbitration module 500 is implemented as hardware or partially as hardware, the job scheduler 530 and / or the state checker 540 can each be implemented by a logic circuit.

[0103] According to one embodiment of the inventive concept, the memory I / F can transmit request signals Req 1 to Req n for commands queued for a plurality of channels corresponding to n memory chips, respectively, to the channel arbitration module 500. When the operation of each of the n memory chips has ended, the memory I / F can transmit end signals End 1 to End n to the channel arbitration module 500. Each of the request signals and the end signals can include information about a number (or an identifier) of the corresponding memory chip or information about a command (or a memory operation) of the corresponding memory chip. For example, the identifier can uniquely identify a specific memory chip among the memory chips. For example, the information about the command can indicate a type of the completed operation (such as whether the operation is a read operation RD, a first program operation PG, etc.).

[0104] When the job scheduler 530 receives the request signals Req 1 to Req n or the end signals End 1 to End n for the n memory chips from the memory I / F, the job scheduler 530 can generate a job schedule by using the received request signals Req 1 to Req n or the received end signals End 1 to End n.

[0105] For example, when the job scheduler 530 receives a plurality of request signals from the memory I / F, the job scheduler 530 can generate a job schedule of jobs corresponding to the plurality of request signals according to an order in which the request signals are received. When the job scheduler 530 receives at least one end signal from the memory I / F, the job scheduler 530 can delete a job corresponding to the received end signal from the job schedule. Details of a method of generating a job schedule performed by the job scheduler 530 will be described later with reference to FIGS. 6 to 8. Figure 8A and Figure 8B Details of a method of generating a job schedule performed by the job scheduler 530.

[0106] The state checker 540 can generate operation state information of each of the n memory chips. For example, the state checker 540 can receive signals Status 1 to Status n representing respective operation states of the n memory chips from the memory I / F via a specific hardware component, and can generate information about the operation states by using the received signals Status 1 to Status n. The state checker 540 can provide the generated information about the operation states to the arbitration core 520.

[0107] The arbitration core 520 can determine which of the plurality of channels will be approved to perform transmission or reception. For example, when the arbitration core 520 receives a job schedule from the job scheduler 530, the arbitration core 520 can identify that it is necessary to determine which of the plurality of channels will be approved to perform transmission or reception, and thus the arbitration core 520 can receive information about the operating state from the state checker 540. The arbitration core 520 can receive a parameter corresponding to the operating state from the parameter 510 based on the received information about the operating state. The arbitration core 520 can check the number of channels corresponding to the received parameter according to the order of the job schedule. For example, each job in the job schedule can correspond to a different operation scheduled to be performed using a specific channel. When there is a channel that has not received a grant signal Grant among the checked channels, the arbitration core 520 can transmit the grant signal Grant to the channel.

[0108] For example, when the arbitration core 520 determines that the operation that the current memory chip is currently performing is a first programming operation based on the information about the operating state, the arbitration core 520 can check a parameter table of Figure 2A to determine a parameter X1 corresponding to the first programming operation. The arbitration core 520 can sequentially check X1 channels performing the first programming operation according to the order of the job schedule. When there is a channel that has not received a grant signal Grant among the checked X1 channels, the arbitration core 520 can transmit the grant signal Grant to the channel.

[0109] In Figure 7 , the channel arbitration module 500 includes the state checker 540. However, according to another embodiment, the state checker 540 is omitted. In this case, the channel arbitration module 500 can indirectly check the operating state of the memory chip. For example, the channel arbitration module 500 can infer the operating state of the memory chip determined to be included in the job schedule and having received the grant signal Grant based on the command information included in the job schedule. The channel arbitration module 500 can also infer that the memory chip included in the job schedule but having not received the grant signal Grant is in an idle state. Alternatively, the channel arbitration module 500 can infer the operating state of the memory chip by using the state in which the job requested from the host HOST is queued.

[0110] According to an exemplary embodiment of the inventive concept, the channel arbitration module 500 generates a job schedule and determines to approve or disapprove transmission or reception of a channel in the order of the generated job schedule, thereby sequentially scheduling a plurality of channels even when operations of a plurality of memory chips are expected.

[0111] Figure 8A and Figure 8B A method of generating a job schedule according to an embodiment of the inventive concept is illustrated.

[0112] According to an embodiment of the inventive concept Figure 7 The job scheduler 530 can input the request signals to a first-in-first-out (FIFO) 531 according to the order in which the request signals are received from the memory I / F. The job scheduler 530 can input the end signals to a FIFO 533 according to the order in which the end signals are received from the memory I / F. The job scheduler 530 can generate the job schedule 535 by using the FIFO 531 for the request signals and the FIFO 533 for the end signals.

[0113] For ease of explanation, a method is described in which the job scheduler 530 generates the job schedule 535 by additionally receiving the request signals or the end signals on the premise that the plurality of request signals Req 1, Req 3, Req 8, and Req 4 have been input to the FIFO 531 and the job schedule has been generated in the order of Req 1, Req 3, Req 8, and Req 4.

[0114] Referring to Figure 8A , the job scheduler 530 receives the second request signal Req 2 from the memory I / F (①) and inputs the second request signal Req 2 to the FIFO 531 for the request signals (②). The job scheduler 530 can generate the job schedule 535 by using a method such as a linked list or a search tree. For example, the job scheduler 530 sequentially fetches the request signals from the FIFO 531 for the request signals, checks whether the fetched request signals are included in the existing job schedule 535, and creates a new request signal (or entry) in the job schedule 535 for each of the fetched request signals that is not in the existing job schedule 535. In other words, the job scheduler 530 inserts the second request signal Req 2 as a new request signal from the FIFO 531 for the request signals into the job schedule 535 (③). The job scheduler 530 can provide the job schedule 535 generated in this way to the channel arbitration module 500.

[0115] The channel arbitration module 500 can receive information about the operating state from the state checker 540 in response to receiving the job schedule 535 and can determine that the current memory chip is performing the first programming operation PG and the read operation RD based on the received information about the operating state. The channel arbitration module 500 can determine the above-mentioned parameters X4 and Z3 as parameters corresponding to the checked operations by checking the table of Figure 2A

[0116] ​For example, the parameters X4 and Z3 can each be 3. The channel arbitration module 500 can check that the memory chips corresponding to the first request Req 1, the third request Req 3, the eighth request Req 8, and the fourth request Req 4 have performed operations in response to the grant signal Grant based on the information on the operation status or the transmission history of the grant signal Grant. Accordingly, the channel arbitration module 500 can determine to approve or disapprove the transmission or reception of the channel corresponding to the second request Req 2 for which the permission signal Grant has not been received according to the order of the job schedule 535. Because three channels are currently performing the first programming operation PG, the channel arbitration module 500 determines to disapprove the transmission or reception of the channel corresponding to the second request Req 2.

[0117] Referring to Figure 8B , the job scheduler 530 receives the third end signal End 3 from the memory I / F (④) and inputs the third end signal End 3 to the FIFO 533 for end signals (⑤). The job scheduler 530 can sequentially fetch end signals from the FIFO 533 for end signals and can delete the request signal corresponding to the fetched end signal from the request signals included in the job schedule 535. For example, the job scheduler 530 can fetch the third end signal End 3 as a new end signal from the FIFO 533 for end signals and can delete the third request signal Req 3 (or an entry associated with the request signal) included in the job schedule 535 (⑥). Although not shown in Figure 8B , the job scheduler 530 can delete the third request signal Req 3 from the FIFO 531 for request signals and the third end signal End 3 from the FIFO 533 for end signals. The job scheduler 530 can provide the job schedule 535 generated in this manner to the channel arbitration module 500.

[0118] The channel arbitration module 500 can receive the information on the operation status from the state checker 540 in response to the job schedule 535 and can check that the current memory chips are performing the first programming operation PG and the read operation RD based on the received information on the operation status. The channel arbitration module 500 can determine the above-described parameters X4 and Z3 as parameters corresponding to the checked operations from the table of Figure 2A .

[0119] For example, the parameters X4 and Z3 can each be 3. The channel arbitration module 500 can check that the memory chips corresponding to the first request Req 1, the eighth request Req 8, and the fourth request Req 4 are performing operations in response to the grant signal Grant based on information about the operating state or a transmission history of the grant signal Grant. Accordingly, the channel arbitration module 500 can re-determine whether to approve or disapprove transmission or reception of the channel corresponding to the second request Req 2 for which the grant signal Grant has not been received according to the order of the job schedule 535. Because two channels are currently performing the first programming operation PG, the channel arbitration module 500 determines to approve transmission or reception of the channel corresponding to the second request Req 2.

[0120] Figure 9 is a block diagram illustrating a method of scheduling data transmission or reception of channels according to an example embodiment of the inventive concept.

[0121] Referring to Figures 1 to 9 The memory system 700 includes a memory controller 710 including a channel arbitration module 711 and a memory I / F 713, and a memory device 720. The memory device 720 can include n memory chips 721_1 to 721_n (i.e., a first memory chip 721_1 to an n-th memory chip 721_n). According to an embodiment, the memory I / F 713 includes n pins 715_1 to 715_n (i.e., a first pin 715_1 to an n-th pin 715_n) for connecting n channels of the n memory chips 721_1 to 721_n. According to an embodiment, the term "pin" can be referred to as a terminal or an output pin.

[0122] According to an example embodiment of the inventive concept, the channel arbitration module 711 determines a channel among the plurality of channels to be approved to perform transmission or reception, and determines whether there is a channel among the channels to be approved to perform transmission or reception for which a grant signal Grant has not been received. When there is a channel for which the grant signal Grant has not been received, the channel arbitration module 711 can transmit the grant signal Grant to the channel. When the memory I / F 713 receives the grant signal Grant from the channel arbitration module 711, the memory I / F 713 can transmit a queued command CMD for the channel corresponding to the grant signal Grant to the memory device 720 via the channel.

[0123] For example, when the channel arbitration module 711 determines that a second channel CH2 among the channels via which transmission or reception has been approved is a channel that has not received the grant signal Grant, the channel arbitration module 711 transmits the grant signal Grant to the second pin 715_2, and the memory I / F 713 transmits the queued command CMD for the second channel CH2 to the second memory chip 721_2 via the second pin 715_2. The second memory chip 721_2 can perform a memory operation corresponding to the received command, and can transmit data related to the performed memory operation to the memory controller 711 on the second channel CH2 via the second pin 715_2.

[0124] Figure 10 is a flowchart of a method of scheduling data transmission or reception of a plurality of channels according to an exemplary embodiment of the inventive concept.

[0125] The method of scheduling data transmission or reception of a plurality of channels according to the present embodiment can be performed in the memory system 200 of Figure 1 the memory system 300 of Figure 5 or the memory system 700 of Figure 9 Referring to the description given in Figures 1 to 9 the same applies to the present embodiment.

[0126] Referring to Figure 10 , the memory system sets a parameter based on information related to power consumption of each operation of the memory chip (S11). The information related to power consumption of each operation of the memory chip can include an amount of power consumption of at least one of a program operation, a read operation, an erase operation, and an idle state. The program operation can be divided into a plurality of detailed operations. For example, the program operation can be divided into a data I / O operation (referred to as a first program operation for convenience of explanation) and a data write operation (referred to as a second program operation for convenience of explanation). The first program operation corresponds to an operation in which a program command and data are input to the memory chip through a channel and are buffered (for example, in an I / O buffer included in the memory chip). The second program operation corresponds to an operation of programming or writing the buffered data (for example, buffered in the I / O buffer included in the memory chip) to a memory cell array.

[0127] The memory system can set, as the parameter, a number of memory chips that can perform each memory operation in parallel as long as the total power consumption does not exceed a preset amount of power (i.e., an allowed amount of power). The memory system can set the parameter for each operation of the memory chip or for each combination of operations of the memory chip.

[0128] For example, the memory system can set, as a parameter, the number of memory chips capable of performing a first programming operation in parallel as long as the total power consumption does not exceed the allowable power amount, the number of memory chips capable of performing a second programming operation in parallel as long as the total power consumption does not exceed the allowable power amount, the number of memory chips capable of performing a read operation in parallel as long as the total power consumption does not exceed the allowable power amount, and the number of memory chips capable of performing an erase operation in parallel as long as the total power consumption does not exceed the allowable power amount. The memory system can set, as a parameter, the number of memory chips capable of performing an operation included in a combination of the first programming operation, the second programming operation, the read operation, and the erase operation in parallel as long as the total power consumption does not exceed the allowable power amount.

[0129] The memory system can set different parameters according to different temperature ranges of the memory system. For example, when the temperature of the memory system is relatively high, the memory system can set the parameters based on a relatively low allowable power amount.

[0130] The memory system can receive specification information of the host from the host, and can set the parameters based on the received specification information and the power consumption of each operation of the memory chips. The specification information can include, for example, information about a device type, model number information, and information about a required power amount of the memory system. The information included in the specification information is not limited thereto.

[0131] The memory system obtains information about operation states of a plurality of memory chips (S12). The operation states of the memory chips can include at least one of a programming operation, a read operation, an erase operation, and an idle state. The memory system controls transmission or reception through a plurality of channels based on the set parameters and the information about the operation states of the plurality of memory chips (S13). For example, the memory system can approve transmission or reception through a number of channels corresponding to the parameters. For example, the memory system can approve data transmission or reception through a number of channels corresponding to the parameters based on the information about the operation states of the plurality of memory chips, the number of channels corresponding to the parameters including channels corresponding to memory chips considered to be currently performing an operation.

[0132] Figure 11 is a flowchart of a method of scheduling data transmission or reception of a plurality of channels according to an exemplary embodiment of the inventive concept. In detail, Figure 11 is Figure 10 is a flowchart of an embodiment of operations S12 and S13 of Figure 1 the channel arbitration module 211 of Figure 5 the channel arbitration module 311 of Figure 6 the channel arbitration module 431 of Figure 7 the channel arbitration module 500 of Figure 9 the channel arbitration module 711 of

[0133] Referring to Figure 11 , the channel arbitration module receives a request for approval of transmission or reception of data via the first channel (S21). The channel arbitration module obtains information about the operating states of the plurality of memory chips (S22). For example, the channel arbitration module can request the information about the operating states from the memory I / F in response to the request, and thus can receive the information about the operating states from the memory I / F. Alternatively, the channel arbitration module can continuously receive signals representing respective operating states of the plurality of memory chips from the memory I / F via a specific hardware component, and can generate the information about the operating states by using the received signals in response to the request. Alternatively, the channel arbitration module can periodically receive the information about the operating states from the memory I / F regardless of whether the request is received.

[0134] The channel arbitration module determines whether to approve the first channel based on the set parameters and the information about the operating states of the plurality of memory chips (S23). The channel arbitration module provides the memory I / F with a result of the determination about whether to approve the first channel (S24). When the transmission or reception of the first channel is approved, the memory I / F can transmit data to or receive data from the first memory chip via the first channel. When the transmission or reception of the first channel is not approved, the memory I / F delays the transmission or reception of data via the first channel. Operation S23 and S24 will now be described in more detail with reference to Figure 12 and Figure 13 .

[0135] Figure 12 is a flowchart of a method of determining whether to approve or disapprove a target channel according to an exemplary embodiment of the inventive concept.

[0136] In detail, Figure 12 is Figure 11 a flowchart of an embodiment of operation S23 of Figure 1 the channel arbitration module 211 of Figure 5 the channel arbitration module 311 of Figure 6 the channel arbitration module 431 of Figure 7 the channel arbitration module 500 of Figure 9 and the channel arbitration module 711 of

[0137] Referring to Figure 12The channel arbitration module checks a parameter corresponding to the checked operation (S31). For example, the channel arbitration module can check what operation is being currently performed by the plurality of memory chips based on information about the operation state of the plurality of memory chips. The channel arbitration module can check the parameter corresponding to the checked operation. For example, when the channel arbitration module determines that the plurality of memory chips are performing a first programming operation, the channel arbitration module can check a parameter corresponding to the first programming operation.

[0138] According to an exemplary embodiment, when the channel arbitration module has set different parameters according to different temperature ranges, the channel arbitration module can obtain temperature information of the memory system from the temperature sensor, and can check a parameter corresponding to the obtained temperature information.

[0139] The channel arbitration module checks whether the number of memory chips performing the checked operation is equal to the checked parameter (S32). When the number of memory chips performing the checked operation is equal to the checked parameter (S32-Y), this can indicate that the amount of power consumption of the memory chips currently performing the operation reaches the allowed amount of power. Accordingly, in order to prevent an excess amount of power consumption due to the performance of an additional operation of the memory chips, the channel arbitration module determines to disapprove the first channel (S34).

[0140] On the other hand, when the number of memory chips performing the checked operation is not equal to (e.g., less than) the checked parameter (S32-N), this can indicate that the amount of power consumption of the memory chips currently performing the operation does not reach the allowed amount of power. Accordingly, the channel arbitration module determines to approve the first channel (S33).

[0141] Figure 13 is a flowchart of a method of determining whether to approve or disapprove a target channel according to an exemplary embodiment of the inventive concept. In detail, Figure 13 is Figure 12 a modifiable embodiment of

[0142] Referring to Figure 13 The channel arbitration module obtains a job schedule of the plurality of memory chips (S41). The channel arbitration module can generate the job schedule by using a request signal from the memory I / F for requesting data transmission or reception via a channel corresponding to each of the plurality of memory chips, or an end signal indicating that the operation of each of the plurality of memory chips has ended.

[0143] For example, when the channel arbitration module receives a plurality of request signals from the memory I / F, the channel arbitration module can generate a job schedule of jobs corresponding to the request signals according to an order in which the request signals are received. When the channel arbitration module receives at least one end signal from the memory I / F, the channel arbitration module can delete a job (or an entry associated with the job) corresponding to the received end signal from the job schedule.

[0144] The channel arbitration module checks parameters corresponding to operations of the plurality of memory chips (S42).

[0145] The channel arbitration module checks a channel to be approved to perform data transmission or reception by using the checked parameters and the job schedule (S43). For example, the channel arbitration module can check the number of channels corresponding to the checked parameters in the order of the job schedule. For example, when the plurality of memory chips perform a first programming operation and a value of a parameter corresponding to the first programming operation is 3, the channel arbitration module can determine that 3 channels correspond to the first programming operation according to the order of the job schedule.

[0146] The channel arbitration module checks whether the first channel is included in the channels to be approved (S44). When the first channel is not included in the approved channels (S44-N), the channel arbitration module determines not to approve the first channel (S46). On the other hand, when the first channel is included in the approved channels (S44-Y), the channel arbitration module determines to approve the first channel (S45).

[0147] Even when it is determined that the first channel is not approved, the channel arbitration module can re-determine whether to approve data transmission or reception of the first channel when a preset event occurs. The preset event can be an event in which a new request is received from the host so that the channel arbitration module receives a request for data transmission or reception of a channel corresponding to the new request from the memory I / F. Alternatively, the preset event can be an event in which, when an operation of one of the plurality of memory chips has ended, the channel arbitration module receives an end signal from the memory I / F. In this case, the channel arbitration module can update the job schedule by considering the received request signal or the end signal, and can re-determine whether to approve data transmission or reception of the first channel based on the updated job schedule.

[0148] Figure 14 is a block diagram of a computing system 1000 according to an exemplary embodiment of the inventive concept.

[0149] Referring to Figure 14The computing system 1000 can include a host 1100 and a storage device 1200. For example, the host 1100 can include a host controller 1110 and a host memory 1120. The storage device 1200 can include a storage controller 1210 and a non-volatile memory 1220. The host memory 1120 can be used as a buffer memory for temporarily storing data to be transmitted to the storage device 1200 or data transmitted by the storage device 1200.

[0150] For example, the computing system 1000 can correspond to any one of various types of systems such as a server device, a computer, a netbook, a network tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a navigation device, a digital camera, a wearable device, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, a virtual reality (VR) device, and an augmented reality (AR) device.

[0151] The storage device 1200 can include a storage medium for storing data according to a request from the host 1100. For example, the storage device 1200 can include at least one of a Solid State Drive (SSD), an embedded memory, and a detachable external memory. According to the present embodiment, the storage device 1200 can be a memory system corresponding to one of the above-described embodiments. Accordingly, the computing system 1000 can control data transmission or reception through a plurality of channels based on information about operating states of a plurality of chips within the storage device 1200 and information about power consumption of each operation of each memory chip (or a set of parameters based on information about power consumption of each operation), thereby preventing a problem from occurring in the entire system when the overall power consumption exceeds an allowed power level.

[0152] The host controller 1110 can manage an operation of storing data (e.g., write data) of the host memory 1120 in the non-volatile memory 1220 or storing data (e.g., read data) of the non-volatile memory 1220 in the host memory 1120.

[0153] The storage controller 1210 can include a host I / F 1211, a memory I / F 1212, and a processor 1213. The storage controller 1210 can further include a flash translation layer (FTL) 1214, a packet manager 1215, a buffer memory 1216, an error correction code (ECC) engine 1217, an advanced encryption standard (AES) engine 1218, and a memory 1219. The memory 1219 can include a channel arbitration module. The storage controller 1210 can further include a working memory (not shown) in which the FTL 1214 is loaded, and the processor 1213 can control data writing and reading with respect to the nonvolatile memory 1220 by executing the FTL 1214. According to an embodiment, the storage controller 1210 can further include a modem (not shown), an I / O device (not shown), a power supply (not shown), etc.

[0154] The host I / F 1211 can transmit or receive a packet to or from the host 1100. The packet transmitted by the host 1100 to the host I / F 1211 can include, for example, a command or data to be written to the nonvolatile memory 1220, and the packet transmitted by the host I / F 1211 to the host 1100 can include, for example, a response to a command or data read from the nonvolatile memory 1220.

[0155] The FTL 1214 can perform several functions such as address mapping, wear leveling, and garbage collection. Address mapping is an operation of changing a logical address received from a host to a physical address used to actually store data in the nonvolatile memory 1220. Wear leveling is a technique of preventing over-deterioration of a specific block by allowing uniform use of blocks included in the nonvolatile memory 1220, and can be implemented, for example, by a firmware technique of leveling an erase count of physical blocks. Garbage collection is a technique of securing available capacity in the nonvolatile memory 1220 by copying valid data of a block to a new block and then erasing the existing block.

[0156] The packet manager 1215 can generate a packet according to a protocol of an I / F negotiated with the host 1100, or parse various information from a packet received from the host 1100. The buffer memory 1216 can temporarily store data to be written to the nonvolatile memory 1220 or data to be read from the nonvolatile memory 1220. The buffer memory 1216 can be a component included in the storage controller 1210, but can be disposed outside the storage controller 1210.

[0157] The ECC engine 1217 can perform error detection and correction with respect to read data read from the nonvolatile memory 1220. In more detail, the ECC engine 1217 can generate parity bits with respect to write data to be written to the nonvolatile memory 1220, and the generated parity bits can be stored in the nonvolatile memory 1220 together with the write data. During data is read from the nonvolatile memory 1220, the ECC engine 1217 can correct errors of the read data by using the parity bits read from the nonvolatile memory 1220 together with the read data, and can output the read data corrected.

[0158] The AES engine 1218 can perform at least one of encryption and decryption with respect to data input to the storage controller 1210 by using a symmetric key algorithm. In one exemplary embodiment, the symmetric key algorithm uses the same cryptographic key to encrypt plaintext and to decrypt ciphertext.

[0159] The storage device 1200 can be implemented according to the embodiments described above with reference to Figures 1 to 13 The storage controller 1210 can correspond to the memory controller described above with reference to Figures 1 to 13 The nonvolatile memory 1220 can correspond to the memory device described above with reference to Figures 1 to 13 The storage controller 1210 can correspond to the memory controller described above with reference to

[0160] For example, the storage controller 1210 can include a channel arbitration module, and can support a function of arbitrating a plurality of channels connected to the nonvolatile memory 1220 by using the channel arbitration module. For example, the storage controller 1210 can check operating states of a plurality of memory devices included in the nonvolatile memory 1220, and can arbitrate the plurality of channels based on the checked operating states and information about power consumption of each operation. Detailed descriptions thereof can be substantially the same as given above with reference to Figures 1 to 13 The storage controller 1210 can correspond to the memory controller described above with reference to

[0161] Thus, the computing system 1000 can control data transmission or reception through a plurality of channels based on information about operating states of a plurality of chips within the storage device 1200 and information about power consumption of each operation of each memory chip (or a set of parameters based on information about power consumption of each operation), thereby preventing a problem from occurring in the entire system when the overall power consumption exceeds the allowed power level.

[0162] Figure 15 is a block diagram of a memory system 800 according to an embodiment of the inventive concept. Refer to Figure 15The memory system 800 can include a memory device 820 and a memory controller 810. The memory system 800 can support a plurality of channels CH1 to CHm, and the memory device 820 and the memory controller 810 can be connected to each other through the plurality of channels CH1 to CHm (where m denotes the number of channels and is a positive integer).

[0163] The memory device 820 can include a plurality of non-volatile memories NVM11 to NVMmn (where n denotes the number of memory devices connected to one channel and is a positive integer). Each of the non-volatile memories NVM11 to NVMmn can be connected to one of the plurality of channels CH1 to CHm through a path corresponding to each of the non-volatile memories NVM11 to NVMmn. For example, the non-volatile memories NVM11 to NVM1n can be connected to the first channel CH1 through paths W11 to W1n, and the non-volatile memories NVM21 to NVM2n can be connected to the second channel CH2 through paths W21 to W2n.

[0164] The memory controller 810 can transmit or receive a signal to or from the memory device 820 via the plurality of channels CH1 to CHm. For example, the memory controller 810 can transmit or receive data DATAa to DATAm to or from the memory device 820 through the plurality of channels CH1 to CHm.

[0165] The memory controller 810 can select one non-volatile memory from among the non-volatile memories connected to each channel through the channel, and can transmit or receive a signal to or from the selected non-volatile memory. For example, the memory controller 810 can select the non-volatile memory device NVM11 from among the non-volatile memories NVM11 to NVM1n connected to the first channel CH1. The memory controller 810 can transmit or receive data DATAa to or from the selected non-volatile memory device NVM11 through the first channel CH1.

[0166] The memory controller 810 can transmit or receive a signal to or from the memory device 820 in parallel via different channels. For example, while transmitting a command CMDa to the memory device 820 through the first channel CH1, the memory controller 810 can transmit a command CMDb to the memory device 820 through the second channel CH2.

[0167] Each of the non-volatile memory devices NVM11 to NVMmn can be operated under the control of the memory controller 810. For example, the non-volatile memory device NVM11 can program data DATAa according to the command CMDa, the address ADDRa, and the data DATAa provided through the first channel CH1.

[0168] In Figure 15 , the memory device 820 communicates with the memory controller 810 through m channels, and includes n non-volatile memory devices for each channel. However, the number of channels and the number of non-volatile memory devices connected to one channel can vary.

[0169] According to embodiments of the inventive concept, the memory system 800 can be implemented according to the above-described embodiments with reference to Figures 1 to 14 . For example, the memory controller 810 can include a channel arbitration module, and can support a function of arbitrating a plurality of channels CH1 to CHm connected to the non-volatile memory 820 by using the channel arbitration module. For example, the memory controller 810 can check the operating states of a plurality of memory devices NVM11 to NVMmn of the non-volatile memory 820, and can arbitrate the plurality of channels CH1 to CHm based on the checked operating states and information on power consumption for each operation. The detailed description thereof can be substantially the same as that given above with reference to Figures 1 to 14 , and thus will be omitted.

[0170] Figure 16 is a block diagram of a memory system 900 according to embodiments of the inventive concept. With reference to Figure 16 , the memory system 900 can include a memory device 920 and a memory controller 910. The memory device 920 can correspond to one of the non-volatile memories NVM11 to NVMmn of the memory system 800 based on one of a plurality of channels CH1 to CHm communicating with the memory controller 810. The memory controller 910 can correspond to the memory controller 810 of Figure 15 . Figure 15

[0171] The memory device 920 can include first to eighth pins P11 to P18, a memory I / F circuit 921, a control logic circuit 923, and a memory cell array 925.

[0172] ​The memory I / F circuit 921 can receive a chip enable signal nCE from the memory controller 910 through a first pin P11. The memory I / F circuit 921 can transmit or receive a signal to or from the memory controller 910 through second to eighth pins P12 to P18 according to the chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (e.g., low level), the memory I / F 921 can transmit or receive a signal to or from the memory controller 910 through the second to eighth pins P12 to P18.

[0173] The memory I / F circuit 921 can receive a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE from the memory controller 910 through second to fourth pins P12 to P14. The memory I / F circuit 921 can receive or transmit a data signal DQ to or from the memory controller 910 through a seventh pin P17. A command CMD, an address ADDR, and data DATA can be transferred through the data signal DQ. For example, the data signal DQ can be transferred through a plurality of data signal lines. In this case, the seventh pin P17 can include a plurality of pins corresponding to a plurality of data signals.

[0174] The memory I / F circuit 921 can obtain a command CMD from the data signal DQ received in an enabled interval (e.g., high level state) of the command latch enable signal CLE based on toggle timing of the write enable signal nWE. The memory I / F circuit 921 can obtain an address ADDR from the data signal DQ received in an enabled interval (e.g., high level state) of the address latch enable signal ALE based on toggle timing of the write enable signal nWE.

[0175] According to an embodiment, the write enable signal nWE is maintained in a static (or constant) state (e.g., high level or low level) for a period of time and then toggled between high level and low level. For example, the write enable signal nWE can be toggled in an interval in which the command CMD or the address ADDR is transmitted. Accordingly, the memory I / F 921 can obtain the command CMD or the address ADDR based on toggle timing of the write enable signal nWE.

[0176] The memory I / F circuit 921 can receive a read enable signal nRE from the memory controller 910 through a fifth pin P15. The memory I / F circuit 921 can receive or transmit a data strobe signal DQS to or from the memory controller 910 through a sixth pin P16.

[0177] In an operation of outputting data DATA of the memory device 920, the memory I / F 921 can receive the toggled read enable signal nRE through the fifth pin P15 before outputting the data DATA. The memory I / F circuit 921 can generate the data strobe signal DQS toggled based on the toggling of the read enable signal nRE. For example, the memory I / F circuit 921 can generate the data strobe signal DQS toggled starting after a predetermined delay (e.g., tDQSRE) from a toggling start point of the read enable signal nRE. The memory I / F circuit 921 can transmit the data signal DQ including the data DATA based on the toggling timing of the data strobe signal DQS. Accordingly, the data DATA can be aligned with the toggling timing of the data strobe signal DQS and transmitted to the memory controller 910.

[0178] In an operation of inputting data DATA of the memory device 920, the memory I / F circuit 921 can receive the toggled data strobe signal DQS as well as the data DATA from the memory controller 910 when the data signal DQ including the data DATA is received from the memory controller 910. The memory I / F circuit 921 can obtain the data DATA from the data signal DQ based on the toggling timing of the data strobe signal DQS. For example, the memory I / F circuit 921 can obtain the data DATA by sampling the data signal DQ at rising and falling edges of the data strobe signal DQS.

[0179] The memory I / F circuit 921 can transmit the ready / busy output signal nR / B to the memory controller 910 through the eighth pin P18. The memory I / F circuit 921 can transmit the status information of the memory device 920 to the memory controller 910 through the ready / busy output signal nR / B. When the memory device 920 is in a busy state (i.e., when an internal operation of the memory device 920 is being performed), the memory I / F circuit 921 can transmit the ready / busy output signal nR / B indicating the busy state to the memory controller 910. When the memory device 920 is in a ready state (i.e., when an internal operation of the memory device 920 is not performed or completed), the memory I / F circuit 921 can transmit the ready / busy output signal nR / B indicating the ready state to the memory controller 910. For example, when the memory device 920 reads the data DATA from the memory cell array 925 in response to a page read command, the memory I / F circuit 921 can transmit the ready / busy output signal nR / B indicating the busy state (e.g., a low level) to the memory controller 910. For example, when the memory device 920 programs the data DATA to the memory cell array 925 in response to a program command, the memory I / F circuit 921 can transmit the ready / busy output signal nR / B indicating the busy state to the memory controller 910.

[0180] The control logic circuit 923 can control various overall operations of the memory device 920. The control logic circuit 923 can receive the obtained command CMD / address ADDR from the memory I / F circuit 921. The control logic circuit 923 can generate a control signal for controlling other components of the memory device 920 according to the received command CMD / address ADDR. For example, the control logic circuit 923 can generate various control signals for programming or reading data DATA to or from the memory cell array 925.

[0181] The memory cell array 925 can store the data DATA obtained from the memory I / F circuit 921 under the control of the control logic circuit 923. The memory cell array 925 can output the stored data DATA to the memory I / F circuit 921 under the control of the control logic circuit 923. The memory controller 910 can include first to eighth pins P21 to P28 and a controller I / F circuit 911. The first to eighth pins P21 to P28 can correspond to the first to eighth pins P11 to P18 of the memory device 920.

[0182] The controller I / F circuit 911 can transmit a chip enable signal nCE to the memory controller 920 through the first pin P21. The controller I / F 911 can transmit or receive a signal to or from the memory device 920 selected by the chip enable signal nCE through the second to eighth pins P22 to P28.

[0183] The controller I / F circuit 911 can transmit a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE to the memory device 920 through the second to fourth pins P22 to P24, respectively. The controller I / F circuit 911 can transmit or receive a data signal DQ to or from the memory device 920 through the seventh pin P27.

[0184] The controller I / F circuit 911 can transmit a data signal DQ including a command CMD or an address ADDR to the memory device 920 along with a toggled write enable signal nWE. The controller I / F circuit 911 can transmit a data signal DQ including a command CMD to the memory device 920 while transmitting a command latch enable signal CLE having an enable state, and can transmit a data signal DQ including an address ADDR to the memory device 920 while transmitting an address latch enable signal ALE having an enable state.

[0185] The controller I / F circuit 911 can transmit a read enable signal nRE to the memory device 920 through a fifth pin P25. The controller I / F circuit 911 can receive or transmit a data strobe signal DQS from or to the memory device 920 through a sixth pin P26.

[0186] In an operation of outputting data DATA of the memory device 920, the controller I / F circuit 911 can generate a toggled read enable signal nRE, and can transmit the read enable signal nRE to the memory device 920. For example, the controller I / F circuit 911 can generate the read enable signal nRE that changes from a static (e.g., a high level or a low level) to a toggled state before outputting the data DATA. Accordingly, a data strobe signal DQS that is toggled based on the read enable signal nRE can be generated in the memory device 920. The controller I / F circuit 911 can receive a data signal DQ including the data DATA and the toggled data strobe signal DQS from the memory device 920. The controller I / F circuit 911 can obtain the data DATA from the data signal DQ based on a toggle timing of the data strobe signal DQS.

[0187] In an operation of inputting data DATA of the memory device 920, the controller I / F 911 can generate a toggled data strobe signal DQS. For example, the controller I / F circuit 911 can generate the data strobe signal DQS that changes from a static (e.g., a high level or a low level) to a toggled state before outputting the data DATA. The controller I / F circuit 911 can transmit a data signal DQ including the data DATA to the memory device 920 based on a toggle timing of the data strobe signal DQS.

[0188] The controller I / F circuit 911 can receive a ready / busy output signal nR / B from the memory device 920 through an eighth pin P28. The controller I / F circuit 911 can determine state information of the memory device 920 based on the ready / busy output signal nR / B.

[0189] Figure 17 is a block diagram of a memory device 600 according to embodiments of the inventive concepts. Referring to Figure 17 , the memory device 600 can include a control logic circuit 620, a memory cell array 630, a page buffer unit 640, a voltage generator 650, and a row decoder 660. Although not shown in Figure 17 , the memory device 600 can further include Figure 16 a memory I / F circuit 921, and can further include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, etc. According to embodiments of the inventive concepts, the memory device 600 can correspond to the memory device described above with reference to Figures 1 to 16 .

[0190] The control logic circuit 620 can control various overall operations of the memory device 600. The control logic circuit 620 can output various control signals in response to a command CMD and / or an address ADDR from the memory I / F circuit 921. For example, the control logic circuit 620 can output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.

[0191] The memory cell array 630 can include a plurality of memory blocks BLK1 to BLKz (where z is a positive integer), and each of the plurality of memory blocks BLK1 to BLKz can include a plurality of memory cells. The memory cell array 630 can be connected to the page buffer unit 640 via bit lines BL, and can be connected to the row decoder 660 via word lines WL, string selection lines SSL, and ground selection lines GSL.

[0192] According to an embodiment, the memory cell array 630 can include a three-dimensional (3D) memory cell array, and the 3D memory cell array can include a plurality of NAND strings. Each NAND string can include memory cells connected to word lines vertically stacked on a substrate, respectively. According to an embodiment, the memory cell array 630 can include a two-dimensional (2D) memory cell array, and the 2D memory cell array can include a plurality of NAND strings arranged in a column direction and a row direction.

[0193] The page buffer unit 640 can include a plurality of page buffers PB1 to PBn (where n is an integer equal to or greater than 3), and the plurality of page buffers PB1 to PBn can be connected to memory cells via a plurality of bit lines BL, respectively. The page buffer unit 640 can select at least one bit line from the plurality of bit lines BL in response to a column address Y-ADDR. The page buffer circuit 640 can operate as a write driver or a sense amplifier according to an operation mode. For example, during a program operation, the page buffer circuit 640 can apply a bit line voltage corresponding to data to be programmed to a selected bit line. During a read operation, the page buffer circuit 640 can sense a current or a voltage of a selected bit line to sense data stored in a memory cell. In an alternative embodiment, the page buffer unit 640 can include fewer page buffers.

[0194] The voltage generator 650 can generate various types of voltages for performing program, read, and erase operations based on the voltage control signal CTRL_vol. For example, the voltage generator 650 can generate a word line voltage VWL (e.g., a program voltage, a read voltage, a program verify voltage, and an erase voltage).

[0195] The row decoder 660 can select one word line from among a plurality of word lines WL in response to a row address X-ADDR, and can select one string selection line from among a plurality of string selection lines SSL. For example, during a program operation, the row decoder 660 can apply a program voltage and a program verify voltage to the selected word line, and during a read operation, the row decoder 660 can apply a read voltage to the selected word line.

[0196] Figure 18 is a view for explaining a 3D V-NAND structure according to an embodiment of the inventive concept. When the above-described memory device is implemented using a 3D V-NAND type flash memory, each of a plurality of memory blocks included in the memory device can be represented as an equivalent circuit as shown in Figures 1 to 17 Figure 18

[0197] Figure 18 The memory block BLKi represents a 3D memory block formed on a substrate to have a 3D structure. For example, a plurality of memory NAND strings included in the memory block BLKi can be formed in a direction perpendicular to the substrate (where i is a positive integer).

[0198] Referring to Figure 18 , the memory block BLKi can include a plurality of memory NAND strings NS11 to NS33 connected between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the plurality of memory NAND strings NS11 to NS33 can include a string selection transistor SST, a plurality of memory cells MC1, MC2 to MC8, and a ground selection transistor GST. Although each of the plurality of memory NAND strings NS11 to NS33 includes eight memory cells MC1, MC2 to MC8 in Figure 18 , embodiments are not limited thereto.

[0199] The string selection transistor SST can be connected to a corresponding one of string selection lines SSL1, SSL2, and SSL3. The plurality of memory cells MC1, MC2 to MC8 can be connected to gate lines, respectively. The gate lines can correspond to word lines, and some of the gate lines can correspond to dummy word lines. The ground selection transistor GST can be connected to a corresponding one of ground selection lines GSL1, GSL2, and GSL3. The string selection transistor SST can be connected to a corresponding one of bit lines BL1, BL2, and BL3, and the ground selection transistor GST can be connected to the common source line CSL.

[0200] A plurality of word lines (e.g., WL1) at the same level can be commonly connected to each other, and the ground selection lines GSL1, GSL2, and GSL3 and the string selection lines SSL1, SSL2, and SSL3 can be separated from each other. Although the plurality of word lines (e.g., WL1) at the same level are commonly connected to each other in Figure 18 ​​In the middle, the memory block BLKi is connected to eight gate lines and three bit lines BL1, BL2, and BL3, but embodiments are not limited thereto.

[0201] Figure 19 is a view for explaining a BVNAND structure according to an embodiment of the inventive concept. Referring to Figure 19 The memory device 1200 can be a chip-to-chip (C2C) structure. The C2C structure can mean that an upper chip including a cell region CELL is manufactured on a first wafer, a lower chip including a peripheral circuit region PERI is manufactured on a second wafer, and then the upper chip is connected to the lower chip through bonding. For example, the bonding can mean a method of electrically connecting a bonding metal formed on a topmost metal layer of the upper chip to a bonding metal formed on a topmost metal layer of the lower chip. For example, when the bonding metal is formed of copper (Cu), the bonding can be Cu-Cu bonding, and the bonding metal can be formed of aluminum or tungsten. The above-described C2C structure can be applied to at least one of the memory devices described above with reference to Figures 1 to 17 Figure 19

[0202] Each of the peripheral circuit region PERI and the cell region CELL of the memory device 1200 can include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0203] The peripheral circuit region PERI can include a first base 1210, an interlayer insulating layer 1215, a plurality of circuit devices 1220a, 1220b, and 1220c formed on the first base 1210, first metal layers 1230a, 1230b, and 1230c connected to the plurality of circuit devices 1220a, 1220b, and 1220c, respectively, and second metal layers 1240a, 1240b, and 1240c formed on the first metal layers 1230a, 1230b, and 1230c. According to an embodiment, the first metal layers 1230a, 1230b, and 1230c can be formed of tungsten having a relatively high resistance, and the second metal layers 1240a, 1240b, and 1240c can be formed of copper having a relatively low resistance.

[0204] ​​In the present specification, only the first metal layers 1230a, 1230b, and 1230c and the second metal layers 1240a, 1240b, and 1240c are illustrated and described. However, embodiments are not limited thereto, and one or more metal layers can also be formed on the second metal layers 1240a, 1240b, and 1240c. At least some of the one or more metal layers formed above the second metal layers 1240a, 1240b, and 1240c can be formed of copper or the like having a lower resistance than aluminum used to form the second metal layers 1240a, 1240b, and 1240c.

[0205] The interlayer insulating layer 1215 can be disposed on the first substrate 1210 to cover the plurality of circuit devices 1220a, 1220b, and 1220c, the first metal layers 1230a, 1230b, and 1230c, and the second metal layers 1240a, 1240b, and 1240c, and can include an insulating material such as silicon oxide or silicon nitride.

[0206] The lower bonding metals 1271b and 1272b can be formed on the second metal layer 1240b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 1271b and 1272b of the peripheral circuit area PERI can be electrically connected to the upper bonding metals 1371b and 1372b of the cell area CELL via bonding, and the lower bonding metals 1271b and 1272b and the upper bonding metals 1371b and 1372b can be formed of aluminum, copper, tungsten, or the like.

[0207] The cell area CELL can provide at least one memory block. The cell area CELL can include a second substrate 1310 and a common source line 1320. On the second substrate 1310, a plurality of word lines 1331 to 1338 (1330) can be stacked in a direction (Z-axis direction) perpendicular to an upper surface of the second substrate 1310. A string selection line and a ground selection line can be arranged above and below the plurality of word lines 1330, respectively, and the plurality of word lines 1330 can be arranged between the string selection line and the ground selection line.

[0208] In the bit line bonding area BLBA, a channel structure CH can extend in a direction perpendicular to an upper surface of the second substrate 1310 and can penetrate the word lines 1330, the string selection line, and the ground selection line. The channel structure CH can include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer can be electrically connected to the first metal layer 1350c and the second metal layer 1360c. For example, the first metal layer 1350c can be a bit line contact, and the second metal layer 1360c can be a bit line 1360c. According to an embodiment, the bit line 1360c can extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 1310.

[0209] According to Figure 19In embodiments, the region in which the channel structures CH, the bit lines 1360c, etc. are arranged can be defined as a bit line bonding area BLBA. The bit lines 1360c can be electrically connected to the circuit devices 1220c, which provide a page buffer 1393 in the peripheral circuit region PERI in the bit line bonding area BLBA. For example, the bit lines 1360c can be connected to the upper bonding metals 1371c and 1372c in the peripheral circuit region PERI, and the upper bonding metals 1371c and 1372c can be connected to the lower bonding metals 1271c and 1272c, which are connected to the circuit devices 1220c of the page buffer 1393.

[0210] In the word line bonding area WLBA, the word lines 1330 can each extend in a second direction (X-axis direction) parallel to an upper surface of the second base 1310, and can be connected to the plurality of cell contact plugs 1341 to 1347 (1340). The word lines 1330 can be connected to the cell contact plugs 1340 in the pads, wherein at least some of the word lines 1330 extend and are disposed at different lengths in the second direction. The first metal layer 1350b and the second metal layer 1360b can be sequentially connected to upper ends of the cell contact plugs 1340 connected to the word lines 1330. In the word line bonding area WLBA, the cell contact plugs 1340 can be connected to the peripheral circuit region PERI through the upper bonding metals 1371b and 1372b of the cell region CELL and the lower bonding metals 1271b and 1272b of the peripheral circuit region PERI.

[0211] The cell contact plugs 1340 can be electrically connected to the circuit devices 1220b, which provide a row decoder 1394 in the peripheral circuit region PERI. According to embodiments, the operating voltage of the circuit devices 1220b providing the row decoder 1394 can be different from the operating voltage of the circuit devices 1220c providing the page buffer 1393. For example, the operating voltage of the circuit devices 1220c providing the page buffer 1393 can be greater than the operating voltage of the circuit devices 1220b providing the row decoder 1394.

[0212] In the external pad bonding area PA, a common source line contact plug 1380 can be disposed. The common source line contact plug 1380 can be formed of an electrically conductive material, such as a metal, a metal compound, or polysilicon, and can be electrically connected to the common source line 1320. The first metal layer 1350a and the second metal layer 1360a can be sequentially stacked over the common source line contact plug 1380. For example, the region in which the common source line contact plug 1380, the first metal layer 1350a, and the second metal layer 1360a are arranged can be defined as the external pad bonding area PA.

[0213] In the external pad bonding region PA, the first I / O pad 1205 and the second I / O pad 1305 can be disposed. Referring to Figure 19 , a lower insulating layer 1201 covering a lower surface of the first substrate 1210 can be formed under the first substrate 1210, and the first I / O pad 1205 can be formed on the lower insulating layer 1201. The first I / O pad 1205 can be connected to at least one of the plurality of circuit devices 1220a, 1220b, and 1220c disposed in the peripheral circuit region PERI through the first I / O contact plug 1203, and can be separated from the first substrate 1210 by the lower insulating layer 1201. A lateral surface insulating layer can be disposed between the first I / O contact plug 1203 and the first substrate 1210, and can electrically separate the first I / O contact plug 1203 from the first substrate 1210.

[0214] Referring to Figure 19 , an upper insulating layer 1301 covering an upper surface of the second substrate 1310 can be formed over the second substrate 1310, and the second I / O pad 1305 can be disposed on the upper insulating layer 1301. The second I / O pad 1305 can be connected to at least one of the plurality of circuit devices 1220a, 1220b, and 1220c disposed in the peripheral circuit region PERI through the second I / O contact plug 1303. For example, referring to Figure 19 , the lower bonding metals 1271a and 1272a can be provided on the second metal layer 1240a connected to the circuit device 1220a via the first metal layer 1230a, and the second input / output contact plug 1303 connected to the second input / output pad 1305 can be electrically connected to the lower bonding metals 1271a and 1272a via the upper metal pattern provided in the uppermost metal layer of the cell region CELL, and thereby connected to, for example, the circuit device 1220a.

[0215] According to an embodiment, the second substrate 1310, the common source line 1320, etc. are not disposed in a region in which the second I / O contact plug 1303 is disposed. In one embodiment, the second I / O pad 1305 does not overlap the word line 1330 in the third direction (Z-axis direction). Referring to Figure 19 , the second I / O contact plug 1303 can be separated from the second substrate 1310 in a direction parallel to the upper surface of the second substrate 1310, and can be connected to the second I / O pad 1305 by penetrating the interlayer insulating layer 1315 of the cell region CELL.

[0216] According to embodiments, the first I / O pad 1205 and the second I / O pad 1305 can be selectively formed. For example, the memory device 1200 can include only the first I / O pad 1205 arranged over the first base 1201, or can include only the second I / O pad 1305 arranged over the second base 1301. Alternatively, the memory device 1200 can include both the first I / O pad 1205 and the second I / O pad 1305.

[0217] In the external pad bonding area PA and the bit line bonding area BLBA included in each of the cell region CELL and the peripheral circuit region PERI, a metal pattern of the topmost metal layer can exist as a dummy pattern, or the topmost metal layer can be empty.

[0218] In the external pad bonding area PA, the memory device 1200 can form a lower metal pattern 1273a on the topmost metal layer of the peripheral circuit region PERI corresponding to the upper metal pattern 1372a formed on the topmost metal layer of the cell region CELL, the lower metal pattern 1273a having the same shape as the upper metal pattern 1372a of the cell region CELL. In one embodiment, the lower metal pattern 1273a formed in the topmost metal layer of the peripheral circuit region PERI is not connected to a separate contact in the peripheral circuit region PERI. Similarly, in the external pad bonding area PA, the memory device 1200 can form an upper metal pattern on the topmost metal layer of the cell region CELL corresponding to the lower metal pattern formed on the topmost metal layer of the peripheral circuit region PERI, the upper metal pattern having the same shape as the lower metal pattern of the peripheral circuit region PERI. In the external pad bonding area PA, a contact 1371a can be disposed on the upper metal pattern 1372a, which can be electrically connected to the common source line contact plug 1380 via the contact 1371a, a portion of the second metal layer 1360a, and a portion of the first metal layer 1350a.

[0219] Lower bonding metals 1271b and 1272b can be formed on the second metal layer 1240b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 1271b and 1272b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 1371b and 1372b of the cell region CELL via bonding.

[0220] In the bit line bonding area BLBA, the memory device 1200 can form an upper metal pattern 1392 corresponding to the lower metal pattern 1252 formed on the topmost metal layer of the peripheral circuit area PERI on the topmost metal layer of the cell area CELL, the upper metal pattern 1392 having the same shape as the lower metal pattern 1252 of the peripheral circuit area PERI. In one exemplary embodiment, no contact is formed on the upper metal pattern 1392 formed on the topmost metal layer of the cell area CELL. In the bit line bonding area BLBA, the contact 1251 can be disposed on the lower metal pattern 1252, which can be connected to at least a portion of the second metal layer 1240c of the peripheral circuit area PERI through the contact 1251.

[0221] Figure 20 FIG. 1 is a block diagram of a system 2000 to which a storage device according to an embodiment of the inventive concept is applied. Figure 20 The system 2000 of FIG. 1 can be, for example, a mobile system such as a mobile phone, a smart phone, a tablet personal computer (PC), a wearable device, a health care device, or an Internet of Things (IOT) device. However, the system 2000 of FIG. 1 is not limited to a mobile system, but can be a PC, a laptop computer, a server, a media player, or a car device such as a navigation device. Figure 20 The system 2000 of FIG. 1 is not limited to a mobile system, but can be a PC, a laptop computer, a server, a media player, or a car device such as a navigation device.

[0222] Referring to FIG. 1, Figure 20 The system 2000 can include a main processor 2100, memories 2200a and 2200b, and storage devices 2300a and 2300b, and can further include one or more of an image capture device (or an optical input device) 2410, a user input device 2420, a sensor 2430, a communication device 2440, a display 2450, a speaker 2460, a power device 2470, and a connection interface 2480.

[0223] The main processor 2100 can control overall operations of the system 2000, and more particularly, operations of other components of the system 2000. The main processor 2100 can be implemented using a general-purpose processor, a special-purpose processor, an application processor (AP), or the like.

[0224] The main processor 2100 can include one or more CPU cores 2110, and can further include a controller 2120 for controlling the memories 2200a and 2200b and / or the storage devices 2300a and 2300b. According to an embodiment, the main processor 2100 can further include an accelerator 2130 as a special circuit for performing a high-speed data operation such as an artificial intelligence (AI) data operation. The accelerator 2130 can include a graphic processor (GPU), a neural processor (NPU), and / or a data processor (DPU), and can be implemented using a separate chip physically independent of other components of the main processor 2100.

[0225] The memories 2200a and 2200b can serve as main memory devices of the system 2000, and can each include a non-volatile memory such as SRAM and / or DRAM, but can also include a non-volatile memory such as a flash memory, a PRAM, and / or a RRAM. The memories 2200a and 2200b can be implemented within the same package as the main processor 2100.

[0226] The storage devices 2300a and 2300b can serve as non-volatile storage devices that store data regardless of whether power is supplied. The storage devices 2300a and 2300b can each include a storage controller 2310a and 2310b, and a non-volatile memory (NVM) storage device (or a flash memory) 2320a and 2320b that stores data under the control of the storage controller 2310a and 2310b, respectively.

[0227] For example, each of the storage controllers 2310a and 2310b can correspond to the memory controller described above with reference to Figures 1 to 19 For example, each of the storage controllers 2310a and 2310b can correspond to the memory controller described above with reference to Figures 1 to 19 For example, each of the storage controllers 2310a and 2310b can include a channel arbitration module, and can support a function of arbitrating a plurality of channels connected to each of the NVM storage devices 2320a and 2320b by using the channel arbitration module. A detailed description thereof can be substantially the same as the detailed description given above with reference to Figures 1 to 19 For example, each of the storage controllers 2310a and 2310b can include a channel arbitration module, and can support a function of arbitrating a plurality of channels connected to each of the NVM storage devices 2320a and 2320b by using the channel arbitration module. A detailed description thereof can be substantially the same as the detailed description given above with reference to

[0228] The storage 2300a and 2300b can be included in the system 2000 while being physically separated from the main processor 2100, and can be implemented within the same package as the main processor 2100. The storage 2300a and 2300b can be of a type such as a memory card, so as to be detachably combined with other components of the system 2000 through an interface such as a connection interface 2480 to be described later. Each of the storage 2300a and 2300b can be an application standard rules device (such as a universal flash storage (UFS)), but the embodiments are not limited thereto.

[0229] The image capture device 2410 can capture still images or moving pictures, and can be a camera, a camcorder, and / or a webcam.

[0230] The user input device 2420 can receive various types of data input by a user of the system 2000, and can be a touchpad, a keypad, a keyboard, a mouse, and / or a microphone.

[0231] The sensor 2430 can sense various types of physical quantities obtainable from the outside of the system 2000, and convert the sensed physical quantities into electrical signals. The sensor 2430 can be a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biological sensor, and / or a gyroscope.

[0232] The communication device 2440 can transmit and receive signals to and from other devices outside the system 2000 according to various communication protocols. The communication device 2440 can be implemented by including an antenna, a transceiver, and / or a modem.

[0233] The display 2450 and the speaker 2460 can serve as output devices that output visual information and auditory information, respectively, to a user of the system 2000.

[0234] The power supply device 2470 can appropriately convert power supplied from a battery (not shown) and / or an external power source built in the system 2000, and supply the converted power to each component of the system 2000.

[0235] The connection interface 2480 can provide a connection between the system 2000 and an external device connected to the system 2000 and capable of exchanging data with the system 2000. The connection interface 2480 can be implemented as various interface types such as an advanced technology attachment (ATA), a serial ATA (SATA), an external SATA (e-SATA), a small computer small interface (SCSI), a serial attached SCSI (SAS), a peripheral component interconnect (PCI), a PCI express (PCIe), an NVM express (NVMe), IEEE 1394, a universal serial bus (USB), a secure digital (SD) card, a multimedia card (MMC), an embedded multimedia card (eMMC), a universal flash memory (UFS), an embedded universal flash memory (eUFS), and a compact flash (CF) card interface.

[0236] Figure 21 is a block diagram for explaining a UFS system 3000 according to an embodiment of the inventive concept. The UFS system 3000 can be a system that complies with a UFS standard published by the Joint Electron Device Engineering Council (JEDEC), and thus can include a UFS host 3100, a UFS device 3200, and a UFS I / F 3300. The description of the system 2000 given above applies to the UFS system 3000, without conflicting with the following description of the UFS system 3000. Figure 20 Figure 21 Figure 21

[0237] Referring to Figure 21 , the UFS host 3100 and the UFS device 3200 can be connected to each other via the UFS I / F 3300. When the main processor 2100 of the system 2000 is an AP, the UFS host 3100 can be implemented as a part of the AP. The UFS host controller 3110 and the host memory 3140 can correspond to the controller 2120 of the main processor 2100 and the memories 2200a and 2200b of the system 2000, respectively. Figure 20 Figure 20 Figure 20 Figure 20 Figure 20

[0238] ​​​​​​​​The UFS host 3100 can include a UFS host controller 3110, an application 3120, a UFS driver 3130, a host memory 3140, and a UFS interconnect (UIC) layer 3150. The UFS device 3200 can include a UFS device controller 3210, an NVM storage 3220, a storage I / F 3230, a device memory 3240, a UIC layer 3250, and a regulator 3260. The UFS device controller 3210 and the NVM storage 3220 can be connected to each other via the storage I / F 3230. The storage I / F 3230 can be implemented to comply with a standard protocol such as toggle or ONFI.

[0239] The application 3120 can represent a program that desires to communicate with the UFS device 3200 in order to use a function of the UFS device 3200. The application 3120 can send an input-output request (IOR) to the UFS driver 3130 to complete input and output with respect to the UFS device 3200. The IOR can represent a request to read data, a request to write data, and / or a request to discard data, but is not limited thereto.

[0240] The UFS driver 3130 can manage the UFS host controller 3110 through a UFS-HCI (host controller interface). The UFS driver 3130 can convert an IOR generated by the application 3120 into a UFS command defined in a UFS standard, and can send the UFS command to the UFS host controller 3110. One IOR can be converted into a plurality of UFS commands. The UFS command can be substantially a command defined by a SCSI standard, but can also be a UFS standard dedicated command.

[0241] The UFS host controller 3110 can send a UFS command obtained by the UFS driver 3130 to the UIC layer 3250 of the UFS device 3200 through the UIC layer 3150 and the UFS I / F 3300. In this process, the UFS host register 3111 of the UFS host controller 3110 can function as a command queue (CQ).

[0242] The UIC layer 3150 on the UFS host 3100 side can include a MIPI M-PHY 3151 and a MIPI UniPro 3152, and the UIC layer 3250 on the UFS device 3200 side can include a MIPI M-PHY 3251 and a MIPI UniPro 3252.

[0243] The UFS I / F 3300 can include a line for transmitting a reference clock REF_CLK, a line for transmitting a hardware reset signal RESET_n of the UFS device 3200, a pair of lines for transmitting a pair of differential input signals DIN_T and DIN_C, and a pair of lines for transmitting a pair of differential output signals DOUT_T and DOUT_C.

[0244] The UFS device 3200 can generate clocks of various frequencies from the reference clock received from the UFS host 3100 by using a phase-locked loop (PLL) or the like. The UFS host 3100 can set a value of a data rate between the UFS host 3100 and the UFS device 3200 by a frequency value of the reference clock REF_CLK. In other words, the value of the data rate can depend on the frequency value of the reference clock REF_CLK.

[0245] The UFS I / F 3300 can support a plurality of lanes, and each of the plurality of lanes can be implemented as a differential pair. For example, in Figure 21 , a pair of lines for transmitting two differential input signals DIN_T and DIN_C can constitute a receive lane, and a pair of lines for transmitting two differential output signals DOUT_T and DOUT_C can constitute a transmit lane. Although one transmit lane and one receive lane are shown in Figure 21 , the number of transmit lanes and the number of receive lanes can vary.

[0246] The receive lane and the transmit lane can transmit data in a serial communication method, and a structure in which the receive lane and the transmit lane are separated from each other enables full-duplex type communication between the UFS host 3100 and the UFS device 3200. In other words, the UFS device 3200 can transmit data to the UFS host 3100 through the transmit lane while receiving data from the UFS host 3100 through the receive lane. Control data such as a command from the UFS host 3100 to the UFS device 3200, and user data that the UFS host 3100 desires to store in or read from the NVM storage 3220 of the UFS device 3200 can be transmitted to the same lane.

[0247] The UFS device controller 3210 of the UFS device 3200 can control the overall operation of the UFS device 3200. The UFS device controller 3210 can manage the NVM storage 3220 through a logical unit (LU) 3211 that is a logical data storage unit. The number of LUs 3211 can be, but is not limited to, eight. The UFS device controller 3210 can include a flash translation layer.

[0248] When a command from the UFS host 3100 is input to the UFS device 3200 through the UIC layer 3250, the UFS device controller 3210 can perform an operation according to the input command, and when the operation is completed, the UFS device controller 3210 can transmit a completion response to the UFS host 3100.

[0249] For example, when the UFS host 3100 desires to store user data in the UFS device 3200, the UFS host 3100 can transmit a data storage command to the UFS device 3200. When the UFS host 3100 receives a response from the UFS device 3200 indicating that the UFS device 3200 is ready to transfer user data, the UFS host 3100 can transmit user data to the UFS device 3200. The UFS device controller 3210 can temporarily store the received user data in the device memory 3240, and can store the user data temporarily stored in the device memory 3240 in selected locations of the NVM storage 3220 based on the address mapping information of the FTL.

[0250] As another example, when the UFS host 3100 intends to read user data from the UFS device 3200, the UFS host 3100 can transmit a data read command to the UFS device 3200. The UFS device controller 3210 can read user data from the NVM storage 3220 based on the data read command, and can temporarily store the read user data in the device memory 3240. In this read process, the UFS device controller 3210 can detect and correct errors of the read user data by using an embedded ECC circuit (not shown). The UFS device controller 3210 can transmit the user data temporarily stored in the device memory 3240 to the UFS host 3100. The UFS device controller 3210 can further include an AES circuit (not shown).

[0251] The UFS host 3100 can sequentially store commands to be transmitted to the UFS device 3200 in the UFS host register 3111 capable of being used as a command queue, and sequentially transmit the commands to the UFS device 3200. At this time, even when a previously transmitted command is still being processed by the UFS device 3200 (i.e., even before being notified that the previously transmitted command has been completely processed by the UFS device 3200), the UFS host 3100 can transmit a command waiting on the command queue to the UFS device 3200, and accordingly, the UFS device 3200 can receive the next command from the UFS host 3100 even while processing the previously transmitted command.

[0252] A power supply voltage such as VCC, VCCQ1, or VCCQ2 can be input to the UFS device 3200. VCC is a main power supply voltage of the UFS device 3200, VCCQ1 is a power supply voltage for supplying a voltage in a low range and is mainly used for a UFS device controller 321, and VCCQ2 is a power supply voltage for supplying a voltage in a range lower than VCC and higher than VCCQ1 and is mainly used for an I / O interface such as a MIPI M-PHY 3251. The power supply voltage can be supplied to components of the UFS device 3200 through a regulator 3260. The regulator 3260 can be implemented as a set of unit regulators connected to different voltages among the above-described power supply voltages, respectively.

[0253] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details can be made therein without departing from the spirit and scope of the disclosure.

Claims

1. A method of operating a memory system including a memory device including a plurality of memory chips, the method comprising: setting, for each of a plurality of operating states of a memory chip among the plurality of memory chips and / or each combination of the plurality of operating states, a parameter indicating a number of memory chips that are allowed to operate in parallel, based on information related to power consumption of each of the plurality of operating states of the memory chip; obtaining information related to an operating state of each of the plurality of memory chips; and scheduling data accesses through a plurality of channels corresponding to the plurality of memory chips based on the parameter and the information related to the operating state of each of the plurality of memory chips, wherein the scheduling of the data accesses through the plurality of channels comprises: checking an operation currently being performed by the plurality of memory chips based on the information related to the operating state of each of the plurality of memory chips; determining a value of the parameter corresponding to the checked operation from the parameter; determining whether a number of memory chips performing the checked operation is equal to the determined value of the parameter.

2. The operating method of claim 1, wherein, The step of setting the parameter comprises setting, for each of the plurality of operating states of a memory chip among the plurality of memory chips and / or each combination of the plurality of operating states, a maximum number of memory chips that are allowed to operate in parallel as the parameter by using the information related to power consumption of each of the plurality of operating states of the memory chip such that a total power consumption does not exceed a preset amount of power.

3. The method of operating according to claim 1 or 2, wherein, The step of setting the parameter comprises setting different parameters for each of the plurality of operating states or each combination of the plurality of operating states.

4. The operating method of claim 3, wherein, The scheduling of the data accesses through the plurality of channels further comprises: receiving a request for approval of data transmission or reception via a first channel; determining not to approve the data transmission or reception via the first channel when the number of memory chips performing the checked operation is equal to the determined value of the parameter, determining to approve the data transmission or reception via the first channel when the number of memory chips performing the checked operation is less than the determined value of the parameter.

5. The method of operating according to claim 1 or 2, wherein, The plurality of operating states includes at least one of a program operation, a read operation, an erase operation, and an idle state.

6. The method of operating according to claim 1 or 2, wherein, The step of setting the parameter comprises setting a parameter table including parameters indicating a number of memory chips that are allowed to operate in parallel for each of the plurality of operating states and / or each combination of the plurality of operating states in each of a plurality of temperature ranges, the parameter table being set for each of the plurality of temperature ranges.

7. The method of operation of claim 6, wherein, The scheduling of the data accesses through the plurality of channels comprises: sensing a temperature of the memory system; checking a parameter table corresponding to the sensed temperature; and scheduling the data accesses through the plurality of channels based on the checked parameter table and the information related to respective operating states of the plurality of memory chips.

8. The method of operation of claim 1 or 2, wherein, The step of setting the parameter comprises: receiving specification information from a host; and setting the parameter based on the received specification information and information related to power consumption of each of the plurality of operating states.

9. A memory system comprising: a memory device including a plurality of memory chips; a memory controller configured to control operations of the memory device; and a plurality of channels configured to connect each of the plurality of memory chips to the memory controller, wherein the memory controller is configured to check operating states of each of the plurality of memory chips, and schedule data accesses through the plurality of channels by using a parameter and the checked operating states of each of the plurality of memory chips, the parameter being set based on information related to power consumption of each of a plurality of operating states of a memory chip among the plurality of memory chips, and indicating a number of memory chips that are allowed to operate in parallel for each of the plurality of operating states and / or each combination of the plurality of operating states, wherein the memory controller is configured to: check operations that the plurality of memory chips are currently performing based on the operating states of each of the plurality of memory chips; determine a number of channels that are to be approved to perform data transmission or reception by using the parameter and the checked operating states of each of the plurality of memory chips; determine whether the number of memory chips that are performing the checked operations is equal to the number of channels that are to be approved to perform data transmission or reception.

10. The memory system of claim 9, wherein, the memory controller is configured to approve transmission or reception of the determined number of channels so that total power consumption does not exceed a preset amount of power.

11. The memory system of claim 10, wherein, the memory controller is configured to determine a number of channels as many as the parameter among the plurality of channels according to an order of jobs of the memory system.

12. The memory system of claim 11, wherein, the memory controller is configured to delay a job corresponding to one of the channels that are not approved to perform transmission or reception.

13. The memory system of claim 9, wherein, the memory controller is configured to re-determine channels that are to be approved to perform transmission or reception when a new request is received from a host or an operation of at least one of the plurality of memory chips has ended.

14. The memory system according to any one of claims 9 to 13, further comprising: a temperature sensor configured to sense a temperature of the memory system, wherein the parameter includes a plurality of sub-parameters defining a number of memory chips that are allowed to operate in parallel for each of the plurality of operating states and / or each combination of the plurality of operating states in each of a plurality of temperature ranges, and the memory controller is configured to check a sub-parameter corresponding to the sensed temperature, and schedule data transmission or reception of the plurality of channels based on the checked sub-parameter and the checked operating states of each of the plurality of memory chips.

15. A memory controller for controlling operations of a memory device including a plurality of memory chips, the memory controller comprising: a memory interface configured to transmit or receive data via a plurality of channels connecting each of the plurality of memory chips to the memory controller; and a channel arbitration module configured to, when a request for approval of transmission or reception of data via a first channel has been received from the memory interface, obtain information about an operating state of each of the plurality of memory chips, determine whether to approve the first channel based on a parameter set based on power consumption of each of a plurality of operating states of the memory chips and indicating a number of memory chips allowed to operate in parallel for each of the plurality of operating states and / or each combination of the plurality of operating states and the information about the operating state of each of the plurality of memory chips, and provide a result of the determination to the memory interface, wherein the channel arbitration module is configured to: check an operation currently being performed by the plurality of memory chips based on the information about the operating state of each of the plurality of memory chips; determine a number of memory chips corresponding to the checked operation from the parameter; determine whether the number of memory chips currently being operated has reached the number of memory chips corresponding to the checked operation.

16. The memory controller of claim 15, wherein, the channel arbitration module is configured to: determine not to approve the first channel when the number of memory chips currently being operated has reached the number of memory chips corresponding to the checked operation, and determine to approve the first channel when the number of memory chips currently being operated has not reached the number of memory chips corresponding to the checked operation.

17. The memory controller of claim 15, wherein, the channel arbitration module includes a state checker configured to check the operating state of each of the plurality of memory chips, and the state checker is configured to receive information about a command corresponding to the plurality of channels from the memory interface and check the operating state of each of the plurality of memory chips.

18. The memory controller of claim 16, wherein, the channel arbitration module includes a job scheduler configured to manage job scheduling of the plurality of memory chips, and the job scheduler updates the job scheduling when a new request for approval is received from the memory interface or information about an end of an operation of a memory chip corresponding to a second channel among the plurality of channels is received.

19. The memory controller of claim 18, wherein, the channel arbitration module is further configured to, when the job scheduling is updated, check a number of channels corresponding to the checked operation according to an order in the updated job scheduling, and determine whether to approve the first channel according to whether the first channel is included in the checked channels.

20. The memory controller of claim 15, wherein, the memory interface is configured to: transmit data to or receive data from a first memory chip corresponding to the first channel among the plurality of memory chips via the first channel when the first channel is approved, delay transmission of data to or reception of data from the first memory chip via the first channel when the first channel is not approved.

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