Switching control circuit

Abstract

The present application provides a kind of switch control circuit, even when the voltage of high voltage side has occurred variation, can export proper control signal.Switch control circuit is the switch control circuit of the switch of bridge circuit for driving load, comprising: control circuit, for making the switch element conductive set signal based on the control signal of the first logic level for making the switch element conductive is exported to the signal line, and for making the switch element cut-off reset signal based on the control signal of the second logic level for making the switch element cut-off is exported to the signal line;Setting circuit, after the reset signal is input to the control circuit, the logic level of the signal line is set to the second logic level in the period before the set signal is input to the control circuit;And drive circuit, based on the control signal to drive the switch element.

Description

TECHNICAL FIELD

[0001] The present application relates to a switching control circuit. BACKGROUND

[0002] There is a control circuit that controls switching of a switching element of an upper arm based on a signal output from a microcomputer (for example, Patent Literature 1).

[0003] PRIOR ART DOCUMENTS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: Japanese Patent Laid-Open No. 9-172358 SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] However, when a variation occurs in the power supply on the high voltage side, the control circuit sometimes erroneously generates a control signal that turns on the switching element when a control signal that turns off the switching element is to be generated.

[0008] The present application has been achieved in view of the above-described conventional problems, and aims to provide a switching control circuit that can output an appropriate control signal even when a variation occurs in the voltage on the high voltage side.

[0009] TECHNICAL SOLUTION

[0010] The switching control circuit according to the present application that solves the above-described problems is a switching control circuit that controls switching of a switching element of a bridge circuit for driving a load, including: a control circuit that outputs a control signal of a first logic level for turning on the switching element to a signal line based on a set signal for turning on the switching element, and outputs the control signal of a second logic level for turning off the switching element to the signal line based on a reset signal for turning off the switching element; a setting circuit that sets a logic level of the signal line to the second logic level during a period from when the reset signal is input to the control circuit to when the set signal is input to the control circuit; and a drive circuit that drives the switching element based on the control signal.

[0011] EFFECT OF THE INVENTION

[0012] According to the present application, it is possible to provide a switching control circuit that can output an appropriate control signal even when a variation occurs in the voltage on the high voltage side. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 is a diagram showing one example of the structure of the power module 10.

[0014] Figure 2 Fig. 1 is a diagram showing one example of the structure of the switching control circuit 20.

[0015] Figure 3 Fig. 2 is a diagram showing one example of the waveforms of the main signals of the switching control circuit 20.

[0016] Figure 4 Fig. 3 is a diagram showing a truth table that explains the logic action of the signal output circuit 60 based on the signals set, reset.

[0017] Figure 5 Fig. 4 is a diagram showing the action of the signals LTIN, ZLTIN, LTOT when the voltage Vb is restored after fluctuation.

[0018] Figure 6 Fig. 5 is a diagram showing one example of the structure of a variation of the circuit for controlling the NMOS transistor 112.

[0019] Figure 7 Fig. 6 is a diagram showing one example of the structure of the switching control circuit 20a. DETAILED DESCRIPTION

[0020] According to the description and the drawings of the present specification, at least the following matters are clear.

[0021] === This Embodiment ===

[0022] Figure 1 Fig. 7 is a diagram showing one example of the structure of the power module 10 as one embodiment of the present application.

[0023] << Power Module 10 >>

[0024] The power module 10 is a semiconductor device for driving a load 11 based on an instruction from a microcomputer (not shown), and includes a capacitor 14, a switching control circuit 20, a half-bridge circuit 30, and terminals D, P, S, N, COM.

[0025] The switching control circuit 20 is a high-voltage integrated circuit (HVIC), and controls the action of the half-bridge circuit 30 based on an input signal IN input from the microcomputer (not shown). The details of the switching control circuit 20 will be described later, and the switching control circuit 20 is configured to include terminals DS, VB, H, VS, L, G.

[0026] The half-bridge circuit 30 is a circuit that drives the load 11, and includes NMOS transistors 31, 32.

[0027] The NMOS transistor 31 is a high-side switching element, and the gate electrode is connected to the terminal H, and the source electrode is connected to the terminal S. In addition, the drain electrode of the NMOS transistor 31 is applied with a prescribed voltage Vdc (for example, "400 V") via the terminal P.

[0028] The NMOS transistor 32 is a low-side switching element, and the gate electrode is connected to the terminal L, and the drain electrode is connected to the terminal S. In addition, the source electrode of the NMOS transistor 32 is grounded.

[0029] The capacitor 12 is an element for stabilizing the power supply 13 that generates the prescribed voltage Vdc, and one end of the capacitor 12 is connected to the terminal P, and the other end is connected to the terminal N.

[0030] The capacitor 14 is an element to which a bootstrap voltage Vb that makes the high-side circuit operate is applied, and one end of the capacitor 14 is connected to the terminal VB, and the other end is connected to the terminal VS. The bootstrap voltage Vb from the charge pump circuit 101 described later is applied to the terminal VB, and thereby the capacitor 14 is charged. As a result, the bootstrap voltage Vb is generated across the capacitor 14.

[0031] For example, in the case where the voltage Vs of the terminal VS is "0 V", if the voltage of the gate electrode of the NMOS transistor 31 is higher than the threshold voltage of the NMOS transistor 31, the NMOS transistor 31 is turned on. However, if the NMOS transistor 31 is turned on, the voltage Vs of the terminal VS approaches the voltage Vdc (for example, "400 V"), and therefore, in order to keep the NMOS transistor 31 turned on, the NMOS transistor 31 needs to be driven so that the voltage of the gate electrode is higher than the threshold voltage of the NMOS transistor 31, with the voltage Vs of the terminal VS to which the source electrode of the NMOS transistor 31 is connected as a reference.

[0032] In the present embodiment, the voltage higher than the voltage Vs by the bootstrap voltage Vb is generated at the terminal VB with the power supply line L1 (refer to Figure 2 ) to which the voltage Vs of the terminal VS is applied as a reference. Therefore, although the details are described later, the switching control circuit 20 can use the bootstrap voltage Vb to turn on the NMOS transistor 31.

[0033] In addition, the NMOS transistors 31, 32 correspond to "switching elements", and in particular, the NMOS transistor 31 corresponds to an "upper arm switching element".

[0034] << Switching Control Circuit 20 >>

[0035] Figure 2is a diagram showing one example of the structure of the switching control circuit 20. In addition, the switching control circuit 20 is configured to include a high-side drive circuit 21 (hereinafter, referred to as "HDRV") (described later) that drives the NMOS transistor 31 of the upper arm, and a low-side drive circuit 22 (hereinafter, referred to as "LDRV") (described later) that drives the NMOS transistor 32 of the lower arm. Furthermore, Figure 2 In the figure, the terminal DS is omitted for convenience of illustration.

[0036] <<HDRV 21>>

[0037] The HDRV 21 is a circuit that drives the NMOS transistor 31 based on the input signal IN. The HDRV 21 is configured to include an input circuit 41, a pulse generation circuit 42, a level shift circuit 50, a signal output circuit 60, a latch circuit 70, a buffer 80, a bootstrap circuit 100, and a pull-down circuit 110.

[0038] <<Input Circuit 41>>

[0039] The input circuit 41 detects the level of the input signal IN, and outputs a signal HIN of the same logic level as the logic level of the input signal IN. Specifically, when the input signal IN is a high level (hereinafter, referred to as "H" level), the input circuit 41 outputs a signal HIN of the "H" level, and when the input signal IN is a low level (hereinafter, referred to as "L" level), the input circuit 41 outputs a signal HIN of the "L" level. Furthermore, the input circuit 41 is configured to include, for example, a comparator (not shown), and a low-pass filter (not shown) that removes high-frequency noise of the output of the comparator.

[0040] <<Pulse Generation Circuit 42>>

[0041] The pulse generation circuit 42 outputs a set signal set for turning on the NMOS transistor 31 of the high side, and a reset signal reset for turning off the NMOS transistor 31 of the high side, based on the signal HIN from the input circuit 41. Specifically, when the signal HIN is the "H" level, the pulse generation circuit 42 outputs the set signal set of the "H" level, and when the signal HIN is the "L" level, the pulse generation circuit 42 outputs the reset signal reset of the "H" level. In addition, the set signal set and the reset signal reset of the present embodiment are each a pulse signal whose amplitude level changes from 0 V to a low voltage Vcc (for example, 5 V).

[0042] <<Level Shift Circuit 50>>

[0043] The level shift circuit 50 is a circuit that shifts the level of the set signal set and the reset signal reset each generated by the pulse generation circuit 42 operating with a low voltage Vcc to a level at which the signal output circuit 60 (described later) of the high voltage Vb of the HDRV 21 can operate. Specifically, the level shift circuit 50 shifts the level of the set signal set and outputs a level shift completed set signal setdrn having an amplitude level of, for example, 10 V. In addition, the level shift circuit 50 shifts the level of the reset signal reset and outputs a level shift completed reset signal resdrn having an amplitude level of, for example, 10 V.

[0044] The level shift circuit 50 is configured to include NMOS transistors 51, 52, resistors 53, 54, 56, 57, an inverter 55, and diodes 58, 59.

[0045] The drain electrode of the NMOS transistor 51 is connected to a resistor circuit CI formed by the resistors 53, 56. Then, if a positive pulse, that is, the set signal set is input to the gate electrode, the NMOS transistor 51 is in an on state, and the level shift completed set signal setdrn is set to an "L" level.

[0046] The drain electrode of the NMOS transistor 52 is also connected to a resistor circuit C2 formed by the resistors 54, 57. Then, if a positive pulse, that is, the reset signal reset is input to the gate electrode, the NMOS transistor 52 is in an on state, and the level shift completed reset signal resdrn is set to an "L" level.

[0047] In addition, the resistor circuit CI formed by the resistors 53, 56 is changed based on an output signal LTOT of a latch circuit 70 (described later). Similarly, the resistor circuit C2 formed by the resistors 54, 57 is also changed based on the output signal LTOT of the latch circuit 70 (described later).

[0048] The relationship between the change in the combined resistance of the resistor circuits CI, C2 and the operation of the level shift completed set signal setdrn and the level shift completed reset signal resdrn is described later.

[0049] In addition, as one example, the resistors 53, 54 have a resistance value of 10 kΩ, and the resistors 56, 57 have a resistance value of 45 kΩ.

[0050] The diodes 58, 59 clamp the drain electrodes of the NMOS transistors 51, 52 with the voltage Vs of the power supply line LI. The anodes of the diodes 58, 59 are connected to the power supply line LI, and the cathodes are connected to the drain electrodes of the NMOS transistors 51, 52. Thus, the case where an overvoltage is applied to the signal output circuit 60 can be prevented.

[0051] Further, the voltage Vb of the power supply line L2 corresponds to "a prescribed voltage". In addition, either one of the power supply line LI and the power supply line L2 corresponds to "a first line", and the other one corresponds to "a second line". Further, the circuit obtained by combining the resistor circuits CI, C2 corresponds to "an adjustment circuit".

[0052] << Signal output circuit 60 > > >>

[0053] The signal output circuit 60 is a circuit that generates a signal LTIN that controls the signal LTOT output to the latch circuit 70 (described later). The signal output circuit 60 is configured to include inverters 61, 62, 63, and NMOS transistors 64, 65. The operation of the signal output circuit 60 will be described later.

[0054] << Latch circuit 70 > > >>

[0055] The latch circuit 70 is a circuit that holds the signal LTIN output from the signal output circuit 60 and outputs it as the signal LTOT. The latch circuit 70 is configured to include inverters 71, 72 and a resistor 73.

[0056] In the latch circuit 70, when the signal LTIN is at the "L" level, the output of the inverter 71 is at the "H" level, and the output of the inverter 72 is at the "L" level. At this time, the latch circuit 70 pulls down the signal line outputting the signal LTIN using the resistor 73. As a result, even if the output of the signal output circuit 60 is in a high impedance state, the latch circuit 70 can hold the signal LTOT at the "L" level.

[0057] On the other hand, when the signal LTIN is at the "H" level, the output of the inverter 71 is at the "L" level, and the output of the inverter 72 is at the "H" level. At this time, the latch circuit 70 pulls up the signal line outputting the signal LTIN using the resistor 73. As a result, even if the output of the signal output circuit 60 is in a high impedance state, the latch circuit 70 can hold the signal LTOT at the "H" level.

[0058] In addition, as one example, an example in which the latch circuit 70 includes two inverters is shown, but the latch circuit 70 can include an even number of inverters more than two.

[0059] Further, the latch circuit 70 corresponds to a "holding circuit", the signal line of the output signal LTIN corresponds to a "signal line". In addition, the inverters 71, 72 correspond to a "first inverting circuit", a "second inverting circuit", and the "first inverting circuit" and the "second inverting circuit" can each include more than one odd number of inverters. In addition, the resistor 73 corresponds to a "second resistor".

[0060] <<Buffer 80>>

[0061] The buffer 80 is a circuit that outputs a signal HO based on the signal LTOT, that is, a control signal from the latch circuit 70, and drives the NMOS transistor 31.

[0062] <<Pull-down circuit 110>>

[0063] The pull-down circuit 110 is a circuit that, when the voltage Vb recovers after fluctuation, prevents the signal LTIN from erroneously becoming an "H" level in a case where the signal LTOT should be an "L" level. The pull-down circuit 110 is configured to include a resistor 111 and an NMOS transistor 112.

[0064] One end of the resistor 111 is connected to the output, that is, the signal LTIN of the signal output circuit 60, and the other end is connected to the drain electrode of the NMOS transistor 112. Further, the source electrode of the NMOS transistor 112 is connected to the power supply line L1, and the gate electrode thereof is input with the output signal ZLTIN of the inverter 71 of the latch circuit 70.

[0065] As a result, when the signal LTIN is an "L" level and the output signal ZLTIN of the inverter 71 is an "H" level, the NMOS transistor 112 is turned on, and the output of the signal output circuit 60 is pulled down via the resistor 111.

[0066] Thus, the pull-down circuit 110 acts to set the signal LTIN to an "L" level in a case where the signal LTIN should be an "L" level.

[0067] In addition, the pull-down circuit 110 corresponds to a "setting circuit". The NMOS transistor 112 corresponds to a "switch". In addition, the resistor 111 corresponds to a "first resistor".

[0068] <<Boost circuit 100>>

[0069] The boost circuit 100 is a circuit that generates the voltage Vb for turning on the NMOS transistor 31 in the capacitor 14. The boost circuit 100 is configured to include a charge pump circuit 101 that operates with a low voltage Vcc and a boost diode 102.

[0070] The charge pump circuit 101 generates a voltage for supplying the voltage Vb to the capacitor 14 from a low voltage Vcc.

[0071] The bootstrap diode 102 is an element for preventing a flow of charge of the capacitor 14 into the charge pump circuit 101.

[0072] Thus, the bootstrap circuit 100 charges the capacitor 14 by using the low voltage Vcc, and thus even if the voltage Vs becomes a high voltage, the voltage Vb that enables the NMOS transistor 31 to be turned on can be supplied.

[0073] However, since the capacitor 14 is disposed outside the switch control circuit 20, the voltage Vb sometimes varies due to an influence of a parasitic inductance or the like generated on a wiring to the capacitor 14.

[0074] LDRV 22

[0075] The LDRV 22 is a circuit that drives the NMOS transistor 32 based on the signal HIN from the input circuit 41. Specifically, the LDRV 22 outputs a signal LO that inverts a logic level of the signal HIN, and controls the switch of the NMOS transistor 32. Further, the LDRV 22 operates based on a power supply voltage El.

[0076] Waveform of main signals of switch control circuit 20

[0077] Figure 3 is a drawing that shows one example of a waveform of main signals of the switch control circuit 20. Further, the set signal set and the reset signal reset are generated by the pulse generation circuit 42, and the level shift completed set signal setdrn and the level shift completed reset signal resdrn are generated by the level shift circuit 50.

[0078] The pulse generation circuit 42 generates the set signal set that is a positive pulse at a rising edge of the signal HIN from the input circuit 41. In addition, the pulse generation circuit 42 generates the reset signal reset that is a positive pulse at a falling edge of the signal HIN from the input circuit 41.

[0079] The level shift circuit 50 generates the level shift completed set signal setdrn and the level shift completed reset signal resdrn that are negative pulses based on the set signal set and the reset signal reset that are positive pulses.

[0080] When the level shift complete set signal setdrn at the "L" level is input to the signal output circuit 60, the signal output circuit 60 sets the signal LTIN to the "H" level. In addition, when the level shift complete reset signal resdrn at the "L" level is input to the signal output circuit 60, the signal output circuit 60 sets the signal LTIN to the "L" level. Further, when the level shift complete set signal setdrn and the level shift complete reset signal resdrn are at the "H" level, the signal LTIN is in a high impedance state.

[0081] The latch circuit 70 accepts the signal LTIN and outputs the signal LTOT as explained previously.

[0082] < Truth Table of the Signal Output Circuit 60 >

[0083] Figure 4 is a diagram showing a truth table for explaining the logic action of the signal output circuit 60 based on the set signal set and the reset signal reset. The level shift circuit 50 outputs the level shift complete set signal setdrn and the level shift complete reset signal resdrn based on the set signal set and the reset signal reset output from the pulse generation circuit 42. Then, the level shift complete set signal setdrn and the level shift complete reset signal resdrn are input to the signal output circuit 60.

[0084] In the case where both the set signal set and the reset signal reset are at the "L" level, both the level shift complete set signal setdrn and the level shift complete reset signal resdrn are at the "H" level. At this time, the PMOS transistor 63 and the NMOS transistor 64 are turned on, and the PMOS transistor 62 and the NMOS transistor 65 are turned off. Therefore, the output of the signal output circuit 60 is in a high impedance output state. Further, the state in which the output of the signal output circuit 60 is in a high impedance output state in the case where both the set signal set and the reset signal reset are at the "L" level is referred to as a "default state".

[0085] In the case where the signal set is at the "L" level and the signal reset is at the "H" level, the level shift complete set signal setdrn is at the "H" level and the level shift complete reset signal resdrn is at the "L" level. At this time, the NMOS transistors 64 and 65 are turned on, and the PMOS transistors 62 and 63 are turned off. Therefore, the output of the signal output circuit 60 is at the "L" level. Further, the state in which the output of the signal output circuit 60 is at the "L" level in the case where the signal set is at the "L" level and the signal reset is at the "H" level is referred to as a "reset state".

[0086] When the signal set is at the "H" level and the signal reset is at the "L" level, the level shift completion set signal setdrn is at the "L" level and the level shift completion reset signal resdrn is at the "H" level. At this time, the PMOS transistors 62, 63 are turned on and the NMOS transistors 64, 65 are turned off. Therefore, the output of the signal output circuit 60 is at the "H" level. Further, the state in which the output of the signal output circuit 60 is at the "H" level when the signal set is at the "H" level and the signal reset is at the "L" level is referred to as a "set state".

[0087] There is no state in which both the set signal set and the reset signal reset are at the "H" level, and there is no state in which both the level shift completion set signal setdrn and the level shift completion reset signal resdrn are at the "L" level. Therefore, this state is referred to as a "prohibited state".

[0088] As described above, when the signal set from the pulse generation circuit 42 is at the "H" level, the signal output circuit 60 is in the set state, and when the signal reset is at the "H" level, the signal output circuit 60 is in the reset state. In addition, when both the signals set and reset are at the "L" level, the signal output circuit 60 is in the default state. Further, in the present embodiment, the "H" level corresponds to the "first logic level" and the "L" level corresponds to the "second logic level". In addition, depending on the situation, sometimes the "L" level corresponds to the "first logic level" and the "H" level corresponds to the "second logic level".

[0089] <<Operation of the Switch Control Circuit 20>>

[0090] == Case in which the signal LTOT is at the "L" level ==

[0091] Figure 5 is a view showing the operation of the signals LTIN, ZLTIN, and LTOT when the voltage Vb has changed in the case in which the signal LTOT is at the "L" level.

[0092] First, at time tO, when the reset signal reset is at the "H" level, the level shift completion reset signal resdrn is at the "L" level. As a result, the signal output circuit 60 is in the "reset state" and the signal LTOT is at the "L" level. Thereby, the resistors 53, 56 of the resistance circuit C1, which is connected at one end to the power supply line L2, are connected in parallel, and the node at which the level shift completion set signal setdrn is output is connected to the other end of the resistors 53, 56. Therefore, the impedance between the power supply line L2 of the resistance circuit C1 and the node at which the level shift completion set signal setdrn is output decreases.

[0093] On the other hand, the resistance circuit C2 includes a resistance 54 connected to the power supply line L2, and a resistance 57 connected between the resistance 54 and the power supply line Ll, and the level-shifted completion reset signal resdrn is output from a connection node of the resistances 54, 57. Therefore, the impedance between the power supply line L2 of the resistance circuit C2 and the node outputting the level-shifted completion reset signal resdrn is increased.

[0094] Then, at time t1, when the reset signal reset is at the "H" level, the signal output circuit 60 is at the "default state".

[0095] Further, at time t2 to time t3, a fluctuation in the voltage Vb occurs due to noise or the like. Here, the impedance of the resistance circuit Cl is smaller than that of the resistance circuit C2. As a result, the level-shifted completion set signal setdrn rises earlier than the level-shifted completion reset signal resdrn. Therefore, when the voltage Vb recovers, normally, the signal output circuit 60 outputs the signal LTOT at the "L" level.

[0096] However, when the level of the voltage Vb greatly decreases, the on-resistance of the PMOS transistors 62, 63 sometimes becomes small at the time of recovery of the voltage Vb. As a result, the signal output circuit 60 sometimes outputs the signal LTOT at the "H" level. Therefore, the switch control circuit 20 of the present embodiment is provided with the pull-down circuit 110 which prevents the case where the signal LTOT at the "H" level is erroneously output.

[0097] Specifically, at time t3, the signal LTOT is originally at the "L" level, and the NMOS transistor 112 is turned on. Therefore, even if the output signal LTIN of the signal output circuit 60 fluctuates to be smaller than the threshold voltage of the inverter 71 of the latch circuit 70, it is pulled down by the pull-down circuit 110, and the signal LTOT remains at the "L" level.

[0098] As a result, the signals LTIN, LTOT, HO are at the "L" level, and the NMOS transistor 31 is turned off. Therefore, the switch control circuit 20 controls the NMOS transistor 31 to be in the safe state. That is, in the present embodiment, even in the case where the fluctuation in the voltage Vb occurs, the signal output circuit 60 can maintain the "reset state" because the NMOS transistor 112 is turned on.

[0099] == Case where the signal LTOT is at the "H" level ==

[0100] In the case where the signal output circuit 60 is at the "set state", the signal LTOT is at the "H" level. Thus, Figure 2The resistance circuit C1 includes a resistance 53 connected to the power supply line L2, and a resistance 56 connected between the resistance 53 and the power supply line Ll, and the level shift completion set signal setdrn is output from a connection node of the resistances 53, 56. Therefore, the impedance between the power supply line L2 of the resistance circuit C1 and the node outputting the level shift completion set signal setdrn is increased.

[0101] On the other hand, in the resistance circuit C2, resistances 54, 57 connected at one end to the power supply line L2 are connected in parallel, and the node outputting the level shift completion reset signal resdrn is connected to the other end of the resistances 54, 57. Therefore, the impedance between the power supply line L2 of the resistance circuit C2 and the node outputting the level shift completion reset signal resdrn is decreased.

[0102] After that, in the case where the signal output circuit 60 is in the default state, when a variation in the voltage Vb occurs, since the impedance of the resistance circuit C2 is smaller than the impedance of the resistance circuit C1, as a result, the level shift completion reset signal resdrn rises earlier than the level shift completion set signal setdrn. Therefore, at the time of recovery after the variation in the voltage Vb, the signal output circuit 60 operates so that the signal LTOT is at the "H" level.

[0103] In addition, in this case, the NMOS transistor 112 is turned off, and therefore the signal LTIN is not pulled down. Therefore, in the present embodiment, in the case where a variation in the voltage Vb occurs, the signal LTIN can be reliably set to the "H" level. Therefore, even in the case where a variation in the voltage Vb occurs, since the NMOS transistor 112 is turned off, the signal output circuit 60 can maintain the "set state".

[0104] Further, the signal line outputting the signal LTIN corresponds to the "signal line". In addition, the node outputting the level shift completion set signal setdrn corresponds to the "first node", and the node outputting the level shift completion reset signal resdrn corresponds to the "second node". In addition, the NMOS transistor 51 corresponds to the "first NMOS transistor", and the NMOS transistor 52 corresponds to the "second NMOS transistor".

[0105] == Modified Example ==

[0106] In the present embodiment, the circuit outputting the output signal ZLTIN of the inverter 71 of the latch circuit 70 to the gate electrode of the NMOS transistor 112 of the pull-down circuit 110 is provided.

[0107] In addition, the NMOS transistor 112 is turned off when the output signal ZLTIN of the inverter 71 of the latch circuit 70 is at the "H" level. Figure 2As shown, it can be controlled by the signal ZLTIN or by the output of inverter 55. Furthermore, a buffer 80 can be installed using two stages of inverters, and the NMOS transistor 112 can be controlled using the output of the first stage inverter. That is, depending on the design of the circuit following the signal output circuit 60, even... Figure 2 Signals other than ZLTIN and the output of inverter 55 can also control NMOS transistor 112.

[0108] In addition, as an alternative structure, such as Figure 6 As shown, a circuit that detects changes in voltage Vb can be used to output the signal ZLTIN. This circuit is configured to include a comparator 121, a counter 122, and a switch control circuit 123. The comparator 121 compares the power supply Vb with a reference voltage VREF. If Vb is lower than the reference voltage VREF, it outputs an "L" level signal. If the comparator 121 receives an "L" level signal (the detection result), the counter 122 starts counting and continues counting for a specified period. The switch control circuit 123 outputs an "H" level signal ZLTIN for the specified period. Additionally, the switch control circuit 123 outputs an "L" level signal ZLTIN when the level shift completion setdrn signal recovers from the change. The comparator 121 acts as a "detection circuit," and the counter 122 acts as a "counter."

[0109] In this embodiment, the circuit is configured such that NMOS transistor 31 is turned off when the signal LTIN is at the "L" level and turned on when the signal LTIN is at the "H" level. However, as an alternative structure, the circuit can be configured such that NMOS transistor 31 is turned off when the signal LTIN is at the "H" level and turned on when the signal LTIN is at the "L" level. In this case, a pull-up circuit 110a can be used for the power supply line L2 instead of the pull-down circuit 110.

[0110] Specifically, Figure 7One example of the above-described modification, i.e., the switch control circuit 20a, is shown. The switch control circuit 20a includes a pull-up circuit 110a in place of the pull-down circuit 110. The pull-up circuit 110a includes at least a PMOS transistor 112a. In addition, the pull-up circuit 110a can also include a resistor 111a. In addition, the switch control circuit 20a includes a signal output circuit 60a in place of the signal output circuit 60, the signal output circuit 60a including PMOS transistors 62, 63, NMOS transistors 64, 65, and an inverter 66 that inverts the signal setdrn. In addition, the switch control circuit 20a includes a latch circuit 70a in place of the latch circuit 70, the latch circuit 70a including inverters 71, 72, a resistor 73, and an inverter 74.

[0111] The PMOS transistor 112a can be controlled by the signal ZLTIN as shown, or can be controlled using the signal LTOT or the signal HO. That is, depending on the design of the circuit that is the subsequent stage of the signal output circuit 60a, a signal other than the signals ZLTIN, LTOT, and HO as shown can also control the PMOS transistor 112a. Figure 7 Figure 7 The PMOS transistor 112a can be controlled by the signal ZLTIN as shown, or can be controlled using the signal LTOT or the signal HO. That is, depending on the design of the circuit that is the subsequent stage of the signal output circuit 60a, a signal other than the signals ZLTIN, LTOT, and HO as shown can also control the PMOS transistor 112a.

[0112] SUMMARY

[0113] The power module 10 of the present embodiment has been described above. For example, in the case where the voltage Vb is restored after fluctuation, depending on the relationship between the level shift completion set signal setdrn or the level shift completion reset signal resdrn and the signal output circuit 60, the output of the signal output circuit 60 sometimes becomes indeterminate. However, when fluctuation of the voltage Vb occurs, by setting the output signal LTIN of the signal output circuit 60 to the "L" level, a signal of an appropriate logic level can be output, and the case where the NMOS transistor 31 is inadvertently turned on can be prevented.

[0114] In addition, in order to set the output signal LTIN of the signal output circuit 60 to the "L" level, the NMOS transistor 112 that is turned on based on the logic level of the signal LTIN is used, and a signal of an appropriate logic level can be output without a large circuit scale.

[0115] In addition, by providing the resistor 111 in series with the NMOS transistor 112, the pull-down circuit 110 also does not have an effect on the operation in the case where the signal LTIN is at the "H" level.

[0116] In addition, by providing the latch circuit 70 at the output of the signal output circuit 60, a signal of an appropriate logic level can be output even if the output of the signal output circuit 60 is high impedance.

[0117] ​Further, the latch circuit 70 is configured to include inverters 71, 72 and a resistor 73, and is small in circuit scale. Further, the output of the inverter 71 is input to the NMOS transistor 112, and thus the logic level of the signal LTIN can be appropriately controlled in accordance with the logic level of the signal LTIN.

[0118] Further, the resistor circuits Cl, C2 that change the circuit configuration based on the signal LTOT are used. This can adjust the recovery timing of the set signal setdrn and the level shift completion reset signal resdrn after the level shift of the voltage Vb, and can set the logic level of the signal LTOT to be the same as before the variation even in the case where the voltage Vb has varied.

[0119] Further, when the variation of the voltage Vb is detected, the logic level of the signal LTIN can be appropriately controlled, and thus the variation of the voltage Vb can be directly reflected in the control of the logic level of the signal LTIN.

[0120] Further, the counter 122 counts for a prescribed period based on the detection of the variation of the voltage Vb by the comparator 121, and turns on the NMOS transistor 112 for the period, and thus the period for controlling the logic level of the signal LTIN can be appropriately determined.

[0121] Further, the latch circuit 70 is provided at the output of the signal output circuit 60, and thus even if the output of the signal output circuit 60 is high impedance, a signal of an appropriate logic level can be output.

[0122] Further, the switch control circuit 20 can be used to control the NMOS transistor 31 on the high side.

[0123] Further, when the switch control circuit 20 is used on the high side, the NMOS transistor 31 can be normally turned on using the capacitor 14, the charge pump circuit 101, and the bootstrap diode 102.

[0124] Further, in the present embodiment, as the "bridge circuit", although it is configured to drive the load 11 by the half-bridge circuit 30, it is not limited to driving the load 11 by only the half-bridge circuit 30. As the "bridge circuit", it can be a circuit that uses switching elements in upper and lower arms, such as an H-bridge circuit, a three-phase inverter circuit, and the like.

[0125] The above-described embodiments are for facilitating understanding of the present application, and are not used to limit and explain the present application. Further, the present application can be changed or modified without departing from the gist thereof, and equivalent contents thereof are of course included in the present application.

[0126] Explanation of Reference Numerals

[0127] 10 power module,

[0128] 11 load,

[0129] 12, 14 capacitor,

[0130] 13 power supply,

[0131] 20 switch control circuit,

[0132] 21 HDRV,

[0133] 22 LDRV,

[0134] 30 half bridge circuit,

[0135] 31, 32, 51, 52, 64, 65, 112 NMOS transistor,

[0136] 41 input circuit,

[0137] 42 pulse generation circuit,

[0138] 50 level shift circuit,

[0139] 53, 54, 56, 57, 73, 111 resistor,

[0140] 58, 59 diode,

[0141] 55, 61, 71, 72 inverter,

[0142] 60 signal output circuit,

[0143] 62, 63 PMOS transistor,

[0144] 80, 90 buffer,

[0145] 101 charge pump circuit,

[0146] 102 bootstrap diode,

[0147] 110 pull-down circuit,

[0148] 121 comparator,

[0149] 122 counter,

[0150] 123 switch control circuit.

Claims

1. A switching control circuit, The switch control circuit controls switching of switching elements of a bridge circuit for driving a load, characterized by comprising: a control circuit that outputs a control signal for turning on a switching element to a signal line based on a set signal for turning on the switching element, and outputs the control signal for turning off the switching element to the signal line based on a reset signal for turning off the switching element; a setting circuit that sets a logic level of the signal line to a second logic level during a period in which the reset signal is input to the control circuit before the set signal is input to the control circuit; a holding circuit that holds the logic level of the signal line; and a drive circuit that drives the switching element based on an output of the holding circuit, the setting circuit includes: a switch that is provided between a first line to which a voltage corresponding to the second logic level is applied and the signal line, and is turned on during the period in which the reset signal is input to the control circuit before the set signal is input to the control circuit; and a first resistor that is provided between the first line and the signal line, and is connected in series to the switch.

2. The switching control circuit according to claim 1, wherein the holding circuit includes: a first inverting circuit that inverts the logic level of the signal line; a second inverting circuit that inverts a logic level output from the first inverting circuit; and a second resistor that connects the signal line and an output of the second inverting circuit, an output of the first inverting circuit is input to the switch.

3. The switching control circuit according to claim 1, wherein the control circuit includes: a level shift circuit that outputs a signal in which the set signal is level-shifted from a first node, and outputs a signal in which the reset signal is level-shifted from a second node; a signal output circuit that outputs the control signal of the first logic level to the signal line based on the set signal of which the level shift is completed from the first node, and outputs the control signal of the second logic level to the signal line based on the reset signal of which the level shift is completed from the second node; and an adjustment circuit that makes an impedance of the first node smaller than an impedance of the second node when the control signal of the second logic level is output to the signal line, and makes the impedance of the second node smaller than the impedance of the first node when the control signal of the first logic level is output to the signal line.

4. The switching control circuit according to claim 2, wherein the control circuit includes: a level shift circuit that outputs a signal in which the set signal is level-shifted from a first node, and outputs a signal in which the reset signal is level-shifted from a second node; ​ ​ a signal output circuit that outputs the control signal of the first logic level to the signal line based on a level shift completion set signal output from the first node and outputs the control signal of the second logic level to the signal line based on a level shift completion reset signal output from the second node; and an adjustment circuit that makes the impedance of the first node smaller than the impedance of the second node when the control signal of the second logic level is output to the signal line and makes the impedance of the second node smaller than the impedance of the first node when the control signal of the first logic level is output to the signal line.

5. The switch control circuit of claim 1, wherein comprising: a detection circuit that detects a variation in a voltage of a second line to which a voltage corresponding to the first logic level is applied; and a switch control circuit that makes the switch conductive based on a detection result indicating that the detection circuit has detected a variation in the voltage of the second line.

6. The switch control circuit according to claim 5, further comprising: a counter that counts within a prescribed period based on the detection result indicating that the detection circuit has detected a variation in the voltage of the second line, the switch control circuit making the switch conductive within the prescribed period.

7. The switch control circuit according to any one of claims 1 to 6, wherein: the switching element is a switching element of an upper side arm of the bridge circuit.

8. The switch control circuit of claim 7, wherein, comprising: a charge pump circuit that generates a voltage that becomes a voltage of a second line to which a voltage corresponding to the first logic level is applied; and a bootstrap diode connected between the charge pump circuit and the second line, the voltage of the second line being supplied by a capacitor connected between the second line and a first line to which a voltage corresponding to the second logic level is applied.

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