Protocol-aware oscilloscope for buses with sideband and control signals for error detection

Abstract

The present invention relates to a test and measurement instrument with error detection, and more particularly, to a test and measurement instrument that employs sideband signals for error detection. The test and measurement instrument comprises an input port for receiving bus-conducted data from a device under test, and a processing element coupled to the input port. The processing element is configured to execute instructions that cause the processing element to determine a data sequence from a bus signal received on a primary channel of the device, and to adjust parameters for performing error detection on the data sequence using information from at least one other signal of the bus on an auxiliary channel of the device based on a protocol associated with the bus. A method for performing error detection in a test instrument comprises: receiving a data sequence conducted by a bus from a device under test at an input port of the test instrument; determining the data sequence based on the bus signal received on the primary channel of the test instrument; and performing error detection on the data sequence using information from at least one other signal of the bus received on the auxiliary channel of the test instrument.

Description

[0001] Related Applications

[0002] This disclosure claims the benefit of U.S. Provisional Patent Application Serial No. 62 / 936,354, filed on November 15, 2019, entitled “PROTOCOL ANALYSIS FOR A BUSHAVING SIDEBAND AND CONTROL SIGNALS NECESSARY FOR ERROR DETECTION,” which is incorporated herein in its entirety. Technical Field

[0003] The present disclosure relates to test and measurement instruments with error detection, and more particularly, to test and measurement instruments that employ sideband signals for error detection. Background Art

[0004] Some test and measurement equipment, such as oscilloscopes, include error detectors that can look at a signal on a single channel input, such as a signal that conforms to a specific protocol in the device under test (DUT), and lock onto a pattern. The oscilloscope or other equipment can check the data for errors. This method works well for protocols that have a continuous pattern on a single channel that does not depend on other signals. However, some protocols have sideband signals that affect how the pattern is tracked.

[0005] Furthermore, many of these methods use a clock extracted from the data and do not allow for the measurement of the bit error rate (BER) during specific events on the device under test, such as the occurrence of crosstalk or high power consumption.

[0006] Embodiments of the disclosed apparatus and methods address shortcomings in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 An example of a conventional analog trigger system with error detection is shown;

[0008] Figure 2 An example of a conventional digital trigger system with error detection is shown;

[0009] Figure 3 An embodiment of a digital trigger system with error detection is shown;

[0010] Figure 4 An embodiment of a mode qualification logic block is shown. DETAILED DESCRIPTION

[0011] Embodiments herein enable the use of sideband signals that affect how a mode needs to be tracked, including gating a measurement, altering bit rate, changing mode, or adjusting timing. These embodiments also allow the use of a discrete clock or gating pulse, rather than a clock extracted from the data. These embodiments also allow the bit error rate (BER) to be measured during specific events on a device under test (DUT), such as crosstalk or greater power consumption.

[0012] Figure 1 An oscilloscope architecture with an analog trigger system having an error detector is shown. As an example, the discussion here will focus on an oscilloscope, but it should be noted that the embodiments used here can be applied to any test and measurement equipment that receives a data pattern over a channel.

[0013] Typically, error detection occurs by the device receiving a single channel input and locking the pattern in. The user can then check the pattern for errors. Figure 1 An acquisition channel 10 is shown acquiring an input analog data signal. The signal may undergo signal conditioning, including amplification provided by a preamplifier 12. The acquisition channel then converts the analog signal into a digital signal using an analog-to-digital converter (ADC) 14. The signal is then demultiplexed by a demultiplexer 16 and may then be stored in an acquisition memory 18.

[0014] The trigger system 20 also receives an input analog data signal, or Figure 1 As shown in , the input analog data signal after signal conditioning is received via the second analog signal path. One or more trigger comparators 22 receive the input signal. The trigger comparator 22 may include multiple comparators to handle multi-level logic. The trigger comparator may also receive other input signals, such as one or more external "trigger input" signals. The trigger comparator 22 typically detects different trigger conditions and sends them as inputs to the trigger state machine 30. The trigger state machine 30 generates an output signal that associates a portion of the input signal with a trigger event. The demultiplexer 16 receives the output signal. Examples of these trigger events include edges, pulse widths, dwarf pulses, glitches, timeouts, etc.

[0015] The signal from the trigger comparator 22 to the pattern lock logic block 24 is the beginning of the error detector. This block can align the matching pattern with the input data at a known bit rate and pattern. The pattern lock logic block 24 can also have a learning capability to learn short patterns and lock them. Once locking is achieved, the pattern comparison block 26 compares the matching pattern with the collected pattern, and the error counter 28 counts errors.

[0016] Figure 2Another example of an error detector 40 implemented in a device with a digital trigger system is shown. In this example, the acquisition channel of the device again receives an analog input signal from the DUT through a preamplifier 42, but the digital input to the trigger system comes from the output of an ADC 44, which may also be connected to acquisition logic 46, which will also contain acquisition memory. Because this example device has a digital trigger system, a word recognizer such as word recognizer 48 replaces the word recognizer in the example. Figure 1 The comparator 22 used in the analog trigger system example shown in . The word recognizer compares the word pattern between the received word and the reference word, detects the level and edge of the digitized signal, or the pattern of the digital channel input. The word recognizer can be configured to output events about any of these. The trigger state machine 56 uses the results from the word recognizer, just like the pattern lock block 50, the pattern comparison block 52 and the error counter block 54. Figure 1 and Figure 2 Both systems require patterns with constant sequence and rate to achieve mode locking.

[0017] In contrast, Figure 3 Embodiments use input received from other channels on the bus (sometimes referred to as sideband channels) to define a sequence or control what sequence or bit rate is used for matching. As will be discussed below with respect to some specific scenarios, the information on the sideband channel can define a sequence. For example, the information can control what sequence or bit rate is used for matching during comparison to detect errors. The information ensures that the sequence that matches the expected pattern has the correct timing and bit rate, which can improve the accuracy of error detection.

[0018] The main channel of the instrument connected to the bus, the acquisition channel 60, has a preamplifier 64 and any other conditioning circuits, as well as an ADC 66. The output of the ADC is demultiplexed by logic 62 to an acquisition memory 71. The output of the word recognizer 63 is used by a trigger state machine 72 and an error detector. Figure 2 In the example of , the error detector includes a mode lock block 65 , a mode comparison block 68 , and an error counter block 70 .

[0019] Figure 3 The embodiment of the invention has a mode definition logic block 76 that uses information from at least one other sideband signal received on one or more channels other than the main channel (referred to herein as auxiliary channels or inputs). In one embodiment, the first auxiliary input 81 also has a preamplifier 82, an ADC 84, and a demultiplexer 88 with a word recognizer 86. The second auxiliary input 91 also has a preamplifier 90, an ADC 92, and a demultiplexer 96 with a word recognizer 94. The mode definition logic 76 uses the auxiliary inputs 81, 91.

[0020] Some embodiments may be implemented in a mixed signal oscilloscope (MSO). A mixed signal oscilloscope is a digital storage oscilloscope that displays and compares both analog and digital signals. In these embodiments, the MSO may also have a digital acquisition channel or input 101, such as a Figure 1 As shown in the comparator 98 and the digital sampler 100 in FIG.

[0021] It should be noted that the discussion herein may refer to logic 62 as a processing element. The various components may be various logic elements, such as comparators, word recognizers, pattern definition logic 76, etc. One or more of these various components may be included in a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.

[0022] exist Figure 3 In the embodiment of the present invention, the clock recovery block 78 recovers the clock signal from the signal output of the ADC 66. The multiplexer 74 uses the recovered clock and / or the external clock 102 (if provided). If the system uses the external clock 102, the external clock 102 can enter as a sideband signal through another channel of the bus, or it can be provided as an external clock source. As described above, the bus has sideband signals on channels other than the main channel 60.

[0023] The mode definition logic 76 receives one or more of the outputs of the auxiliary inputs 81 and 91 and the digital acquisition input 101 (if present). The mode definition logic 76 sends signals to the error counter 70 and the mode lock block 65.

[0024] Figure 4 An example embodiment of mode definition logic 76 is shown. Figure 4 The embodiment shown in is only one example of the pattern definition logic 76. As will be appreciated by one of ordinary skill in the art, there are a variety of ways to implement pattern matching logic in the pattern definition logic 76 that can operate simultaneously or sequentially.

[0025] Inputs from the main acquisition channel and the auxiliary channel(s) are used to input the captured sequence into the pattern matching circuit 110 in parallel or serially. The pattern matching circuit 110 may have several sets of memories 112 and timing delay elements 114, which may contain lookup tables. The timing delays may allow the timing of the input sequence to be coordinated with the pattern match, and the timing delays 114 may include multiple timing delays and logic circuit stages. The output of the pattern matching circuit 110 may be input to the sequence matching circuit 111. The sequence matching circuit 111 may be selected by the user between the non-protocol specific circuit 116 and the protocol tracking circuit 118. The input signal may be mapped to a sequence in one of the matching circuits 116 and 118. If the user has identified a bus with a specific protocol, and the protocol uses sideband signals, the pattern matching circuit will send an output signal to the protocol tracking sequence matching circuit 118. If the user has not identified a specific protocol, the system will use the non-protocol specific sequence matching circuit 116. The process may still involve a protocol, where the protocol here is a non-specific protocol. Circuits 116 and 118 may also include memory and delays. The result of either circuit is selected by MUX 120 and output to acquisition logic and memory to allow the BER to be determined.

[0026] The simplest instance of a mode qualification logic circuit is a single signal qualifier. An example of this is measuring BER during a power supply event. The auxiliary channel is assigned as a qualifier, and the mode qualification logic is configured to reject any errors counted when the power supply level does not meet the criteria. This enables BER testing during power optimization.

[0027] Another level of complexity is to allow for a known delay between the auxiliary signal and the signal under test. The logic that allows for a defined delay accounts for probing and DUT skew differences.

[0028] Figure 4 The logic shown in allows multiple auxiliary signals to be combined into patterns with different skews. The logic also allows for qualification based on complex pattern sequences on these auxiliary signals. The logic can be used to decode complex command buses, such as the command buses used in double data rate (DDR) memory devices such as DDR 5th generation synchronous dynamic random access memory (SDRAM). For example, the logic can be used to qualify and isolate data that is only read by DDR. The logic can also be used for other command buses or packetized sideband buses.

[0029] In an exemplary embodiment, the bus protocol may be a High Definition Multimedia Interface (HDMI). HDMI has a side channel, or auxiliary channel, called a Data Display Channel (DDC). DDC is based on an Inter-Integrated Circuit (I 2C) bus and is physically bundled with the main HDMI high-speed differential signal in the HDMI cable. The serial packets on the DDC bus determine the bit rate at which HDMI operates. Figure 3 The error detector can monitor the DDC channel and wait to receive a command that the main channel, the high-speed serial bus, is running at the desired data rate. The error detector will then run at that data rate until the user stops it or a command to change to a new data rate is received. When the error detector loses lock due to a bit range change, the stop or change command will prevent the BER result from failing. For HDMI, the use lies in the ability to change the data rate by detecting internal errors. Otherwise, the user will not be able to determine the number of errors because the system will simply shift to a lower speed, which makes debugging difficult.

[0030] The sideband communications of some buses are complex enough to require dedicated logic. This dedicated protocol logic can be implemented in an ASIC or FPGA as many different protocol tracking blocks. Alternatively, these blocks can be implemented as FPGA blocks that are reprogrammed to the desired current standard. A simple example of a unique sideband is the Peripheral Component Interconnect (PCI) Express (PCIe) 100MHz clock bursts used to change transmitter equalizer settings according to regulations. Tracking these clock bursts is unique to PCIe compliance. There is a requirement to track the BER separately for each transmitter equalization setting.

[0031] It should be noted that this constitutes merely an example of implementation of the embodiments and is not intended to limit the scope of the claims, and no such limitation should be implied.

[0032] Examples of the present disclosure may be operated on specially created hardware, firmware, a digital signal processor, or on a specially programmed general-purpose computer including a processor operating according to programming instructions. The terms "controller" or "processor" used herein are intended to include microprocessors, microcomputers, ASICs, and dedicated hardware controllers. One or more aspects of the present disclosure may be embodied in computer-usable data and computer-executable instructions, such as one or more program modules executed by one or more computers (including monitoring modules) or other devices. Typically, program modules include routines, programs, objects, components, data structures, etc., which perform specific tasks or implement specific abstract data types when executed by a processor in a computer or other device. Computer executable instructions may be stored on non-temporary computer-readable media, such as hard disks, optical disks, removable storage media, solid-state memory, electrically erasable programmable read-only memory (EEPROM), random access memory (RAM), etc. As will be appreciated by those skilled in the art, the functions of the program modules may be combined or distributed as desired in various examples. In addition, the functions may be embodied in firmware or hardware equivalents in whole or in part, such as in integrated circuits, field programmable gate arrays (FPGAs), etc. Certain data structures may be used to more efficiently implement one or more aspects of the present disclosure, and such data structures are contemplated to be within the scope of the computer-executable instructions and computer-usable data described herein.

[0033] The various aspects of the present disclosure operate in various modified and alternative forms. Specific aspects have been shown by way of example in the drawings and are described in detail below. However, it should be noted that the examples disclosed herein are presented for the purpose of clarity of discussion and are not intended to limit the scope of the general concepts disclosed to the specific examples described herein, unless expressly limited. As such, according to the attached drawings and claims, the present disclosure is intended to cover all modifications, equivalents and alternatives of the described aspects.

[0034] References to embodiments, aspects, examples, etc. in the specification indicate that the items described may include specific features, structures, or characteristics. However, each disclosed aspect may or may not include specific features, structures, or characteristics. In addition, unless otherwise specified, such phrases do not necessarily refer to the same aspect. Further, when specific features, structures, or characteristics are described in conjunction with specific aspects, such features, structures, or characteristics may be used in conjunction with other disclosed aspects, regardless of whether such features are explicitly described in conjunction with such other disclosed aspects.

[0035] In some cases, the disclosed aspects may be implemented in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried or stored on one or more non-transitory computer-readable media, which may be read and executed by one or more processors. Such instructions may be referred to as computer program products. As discussed herein, computer-readable media refers to any medium that can be accessed by a computing device. As an example and not limitation, computer-readable media may include computer storage media and communication media.

[0036] Computer storage media refers to any medium that can be used to store computer-readable information. By way of example and not limitation, computer storage media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital video disk (DVD) or other optical disk storage, cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, and any other volatile or non-volatile, removable or non-removable media implemented in any technology. Computer storage media does not include the signal itself and the temporary form of signal transmission.

[0037] Communication media refers to any medium that can be used for communication of computer-readable information. By way of example and not limitation, communication media may include coaxial cables, fiber optic cables, air, or any other medium suitable for communication of electrical, optical, radio frequency (RF), infrared, acoustic, or other types of signals.

[0038] Example

[0039] Illustrative examples of the disclosed technology are provided below. Implementations of the technology may include one or more of the examples described below and any combination of the examples.

[0040] Example 1 is a test and measurement device comprising: an input port for receiving bus-conducted data from a device under test; and a processing element coupled to the input port and configured to execute instructions, the instructions causing the processing element to: determine a data sequence from a bus signal received on a primary channel of the device; and adjust parameters for performing error detection on the data sequence using information from at least one other signal from the bus received on an auxiliary channel of the device based on a protocol associated with the bus.

[0041] Example 2 is the apparatus of Example 1, wherein the processing element includes a mode lock circuit, a mode comparator, and an error counter.

[0042] Example 3 is the apparatus of Example 2, wherein the processing element further includes a clock recovery circuit.

[0043] Example 4 is any of Examples 1 to 3, wherein the processing element includes a trigger state machine and mode definition logic.

[0044] Example 5 is the apparatus of Example 4, wherein the pattern qualification logic includes a pattern matching circuit and a sequence matching circuit.

[0045] Example 6 is the apparatus of Example 5, wherein the pattern matching circuit comprises at least one lookup table and a delay element.

[0046] Example 7 is the apparatus of Example 6, wherein the sequence matching circuit comprises a non-protocol specific sequence matching circuit and a protocol tracking sequence matching circuit.

[0047] Example 8 is the apparatus of any of Examples 1-7, wherein the auxiliary channel has a preamplifier, an analog-to-digital converter, and a word recognizer.

[0048] Example 9 is the apparatus of any of Examples 1-8, wherein the auxiliary channel has a comparator and a digital sampler.

[0049] Example 10 is the apparatus of any of Examples 1-9, wherein adjusting the parameter comprises at least one of gating of the measurement, adjusting the bit rate, changing the mode, and adjusting the timing.

[0050] Example 11 is the apparatus of any of Examples 1-12, wherein the processing element comprises one of a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

[0051] Example 12 is the apparatus of any of Examples 1-12, wherein the processing element is reprogrammable to a different bus protocol.

[0052] Example 13 is the apparatus of any of Examples 1-12, further comprising a user interface, wherein the processing element is further configured to execute instructions that cause the processing element to perform error detection on the data sequence when a protocol associated with the bus is identified by a user through the user interface.

[0053] Example 14 is the device of Example 13, wherein the processing element is further configured to execute instructions that cause the processing element to perform error detection on the data sequence when the protocol associated with the bus is not identified by the user through the user interface.

[0054] Example 15 is a method for performing error detection in a test instrument, comprising: receiving a data sequence from a device under test conducted by a bus at an input port of the test instrument; determining the data sequence from a bus signal on a main channel of the test instrument; and performing error detection on the data sequence using information from at least one other signal of the bus on an auxiliary channel of the device.

[0055] Example 16 is the method of Example 15, wherein using information from the at least one other signal comprises at least one of determining a bit rate, gating a measurement, changing a mode, and adjusting timing on the primary channel.

[0056] Example 17 is the method of any of Examples 15 and 16, wherein using information from the at least one other signal comprises using the signal in a mode definition circuit within a primary channel of the device.

[0057] Example 18 is the method of any of Examples 15-17, wherein using information from at least one other signal includes using, by a mode definition circuit within the processing element, a state signal from a trigger state machine.

[0058] Example 19 is the method of any of Example 17, further comprising generating at least one output signal from the mode definition circuit.

[0059] Example 20 is the method of Example 19, wherein the at least one output signal comprises at least one of an output to a mode lock block and an output to an error counter.

[0060] Although particular embodiments have been shown and described for purposes of illustration, it will be appreciated that various modifications may be made without departing from the spirit and scope of the present disclosure. Therefore, the present invention should not be limited, except as in the appended claims.

Claims

1. A test and measurement device comprising: An input port, used to receive data conducted by the bus from the device under test; and a processing element coupled to the input port and configured to execute instructions that cause the processing element to: determining a data sequence from a bus signal received on a primary channel of the device; and Information from at least one other signal of the bus received on an auxiliary channel of the device is used to adjust parameters for performing error detection on the data sequence, wherein the information on the auxiliary channel is based on a protocol associated with the bus.

2. The apparatus of claim 1, wherein the processing element comprises a mode lock circuit, a mode comparator, and an error counter.

3. The apparatus of claim 2, wherein the processing element further comprises a clock recovery circuit.

4. The apparatus of claim 1, wherein the processing element comprises a trigger state machine and mode definition logic.

5. The apparatus of claim 4, wherein the pattern qualification logic comprises a pattern matching circuit and a sequence matching circuit.

6. The apparatus of claim 5, wherein the pattern matching circuit comprises at least one lookup table and a delay element.

7. The apparatus of claim 5, wherein the sequence matching circuit comprises a non-protocol specific sequence matching circuit and a protocol tracking sequence matching circuit.

8. The apparatus of claim 1, wherein the auxiliary channel has a preamplifier, an analog-to-digital converter, and a word recognizer.

9. The apparatus of claim 1, wherein the auxiliary channel has a comparator and a digital sampler.

10. The apparatus of claim 1, wherein adjusting parameters comprises at least one of gating a measurement, adjusting a bit rate, changing a mode, and adjusting a timing.

11. The apparatus of claim 1, wherein the processing element comprises one of a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

12. The apparatus of claim 1, wherein the processing element is reprogrammable to a different bus protocol.

13. The device of claim 1 , further comprising a user interface, wherein the processing element is further configured to execute instructions that cause the processing element to perform error detection on the data sequence when a protocol associated with the bus is identified by a user through the user interface.

14. The apparatus of claim 13, wherein the processing element is further configured to execute instructions that cause the processing element to perform error detection on the data sequence when the protocol associated with the bus is not identified by the user through the user interface.

15. A method for performing error detection in a test instrument, comprising: At the input port of the test instrument, a data sequence from the device under test conducted by the bus is received; determining a data sequence from a bus signal received on a primary channel of the test instrument; and Error detection is performed on the data sequence using information from at least one other signal of the bus received on an auxiliary channel of the test instrument, wherein the information on the auxiliary channel is based on a protocol associated with the bus.

16. The method of claim 15, wherein using information from the at least one other signal comprises at least one of determining a bit rate, gating a measurement, changing a mode, and adjusting timing on a primary channel.

17. The method of claim 15, wherein using information from the at least one other signal comprises using the signal in a mode definition circuit within a primary channel of the device.

18. The method of claim 15, wherein using information from the at least one other signal comprises using, by a mode definition circuit within a processing element, a state signal from a trigger state machine.

19. The method of claim 17, further comprising generating at least one output signal from the mode defining circuit.

20. The method of claim 19, wherein the at least one output signal comprises at least one of an output to a mode lock block and an output to an error counter.

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