A pulse detection circuit and a pulse detection method

Abstract

The present application discloses a pulse detection circuit and a pulse detection method, which can measure higher-speed input pulses while reducing the power consumption of a microcontroller. The pulse detection circuit includes: an input module, an automatic trigger measurement module, and a data latch module. The input end of the input module receives an external input pulse, and the pulse signal is respectively transmitted to the clock pulse end of the automatic trigger detection module and the input end of the data latch module through the output end of the input module. When the pulse signal changes from a first level to a second level, the automatic trigger detection module is enabled, and the output end of the automatic trigger detection module sends a latch signal to the enable end of the data latch module, so that the data latch module latches the pulse signal according to the latch signal.

Description

Technical Field

[0001] This application relates to the field of electronic technologies, and particularly to a pulse detection circuit and a pulse detection method. Background Art

[0002] Currently, with the continuous increase in the frequency of pulse signals, high-speed pulses are widely used in the field of electronic research. The progress of high-speed pulse technology is inseparable from the development of pulse measurement technology. Therefore, researching new technologies for measuring high-speed pulses and understanding pulse width, phase, and shape information are very important research contents.

[0003] With the rise of the Internet of Things industry and wearable devices, low power consumption has also become a very important research direction. However, traditional high-speed pulse measurement methods require a high-speed clock for counting. If automatic detection of high-speed pulses is to be achieved, the participation of a synchronizer is required, which will generate relatively high power consumption. Currently, there are many methods to reduce the power consumption of microcontrollers. Generally, the overall power consumption of the chip is reduced by reducing the main frequency or improving the process. However, reducing the main frequency will reduce the performance of the microcontroller, and advanced processes will increase costs.

[0004] Asynchronous circuits have no clock and have the advantages of low power consumption, high speed, good compatibility, and high reliability. Therefore, how to provide an asynchronous circuit for measuring high-frequency pulses with low power consumption without changing the process and main frequency, thereby reducing the overall power consumption of the microcontroller, has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0005] Embodiments of this application provide a pulse detection circuit and a pulse detection method, which can measure higher-frequency pulses under the condition of lower power consumption and reduce the overall power consumption of the microcontroller.

[0006] In a first aspect, embodiments of this application provide a pulse detection circuit. The pulse detection circuit includes an input module, an automatic trigger detection module, and a data latch module. The output end of the input module is connected to the clock pulse end of the automatic trigger detection module and the input end of the data latch module. The output end of the automatic trigger detection module is connected to the enable end of the data latch module;

[0007] Receive an input pulse signal through the input end of the input module, and transmit the pulse signal to the clock pulse end of the automatic trigger detection module and the input end of the data latch module respectively through the output end of the input module;

[0008] Among them, when the pulse signal changes from the first level to the second level, the automatic trigger detection module is enabled to send a latch signal from the output end of the automatic trigger detection module to the enable end of the data latch module, and the data latch module latches the pulse signal according to the latch signal.

[0009] In a possible design, the data latch module includes a plurality of cascaded latches, and the pulse signal is serially input into the plurality of latches, and the pulse levels within one pulse period of the pulse signal are latched by the plurality of latches.

[0010] In a possible design, the automatic trigger detection module includes a first register and a second register. The clock pulse terminals of the first register and the second register are both connected to the output end of the input module. The output end of the first register is connected to a first inverter and then to the input end of the second register. The output end of the second register is connected to the enable end of each stage of latch in the data latch module, where:

[0011] When it is detected that the pulse signal changes from the first level to the second level, it triggers the output level of the first register to be equal to the input level of the first register, and triggers the output level of the second register to be equal to the input level of the second register. The input end of the second register receives the level after the output level of the first register passes through the first inverter. The data latch module receives the latch signal output from the output end of the second register, and the data latch module latches the pulse signal according to the latch signal.

[0012] In a possible design, the input module includes a multiplexer. The input end of the multiplexer receives the pulse signal, and the output end of the multiplexer is connected to the clock pulse terminal of the automatic trigger detection module and the input end of the data latch module, where:

[0013] The selection terminal of the multiplexer receives a selection signal, and the multiplexer enables the automatic trigger detection module to send the latch signal to the data latch module according to the selection signal. The selection signal is a high level or a low level.

[0014] In a possible design, the input module further includes a filter. The input end of the filter receives the pulse signal, and the output end of the filter is connected to the input end of the multiplexer.

[0015] In a possible design, the input module further includes a second inverter. The input end of the second inverter is connected to the output end of the filter, and the output end of the second inverter is connected to the input end of the multiplexer, where:

[0016] When the selection signal is at a low level, the pulse signal is input to the second inverter, and the multiplexer receives the pulse signal output by the second inverter.

[0017] In a possible design, the first register, the second register, and each stage of the latch all include a reset terminal, where:

[0018] The reset terminals of the first register, the reset terminal of the second register, and the reset terminals of each stage of the latch receive a reset signal, and the automatic trigger detection module and the data latch module are reset according to the reset signal.

[0019] In a possible design, the first level is a 0 level and the second level is a 1 level.

[0020] In a second aspect, an embodiment of the present application provides a device for detecting a pulse signal, including the pulse detection circuit according to the first aspect or any possible design of the first aspect.

[0021] In a third aspect, an embodiment of the present application provides a pulse detection method, which is applied to a pulse detection circuit. The pulse detection circuit includes: an input module, an automatic trigger detection module, and a data latch module. The output end of the input module is connected to the clock pulse end of the automatic trigger detection module and the input end of the data latch module. The output end of the automatic trigger detection module is connected to the enable end of the data latch module. The method includes:

[0022] The input module is configured to receive an input pulse signal and transmit the pulse signal to the clock pulse end of the automatic trigger detection module and the input end of the data latch module respectively;

[0023] The automatic trigger detection module is configured to send a latch signal to the enable end of the data latch module when the pulse signal changes from a first level to a second level;

[0024] The data latch module is configured to latch the pulse signal according to the latch signal.

[0025] The pulse detection circuit provided by this application can detect the input pulse signal. The input end of the input module receives the input pulse signal, and through the output end of the input module, the pulse signal is respectively transmitted to the clock pulse end of the automatic trigger detection module and the input end of the data latch module. When it is detected that the pulse signal changes from the first level to the second level, the automatic trigger detection module is enabled. The output end of the automatic trigger detection module sends a latch signal to the enable end of the data latch module, so that the data latch module latches the pulse signal according to the latch signal. When measuring high-speed pulses, the pulse detection circuit provided by this application adopts a pure asynchronous circuit design. Since the asynchronous circuit does not require clock drive, while reducing the power consumption of the microcontroller, it can measure higher-speed input pulses. Moreover, because it is a pure asynchronous circuit design, each module circuit can work independently, and there is no interference between module circuits. The module circuits have combinability and reusability, and the overall performance of the circuit is relatively good. In practical applications, the number of latches in the latch group can be determined according to its maximum delay and the synchronous pulse capture unit of the chip itself, which increases the flexibility of the pulse detection circuit for detecting pulses.

[0026] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0028] Figure 1 It is a schematic framework diagram of a pulse detection circuit provided by an embodiment of this application;

[0029] Figure 2 It is an equivalent circuit diagram of a pulse detection circuit provided by an embodiment of this application;

[0030] Figure 3 It is a schematic diagram of a D flip-flop provided by an embodiment of this application;

[0031] Figure 4 provided by an embodiment of this application Figure 3 It is a timing diagram of the input and output signals of the D flip-flop shown;

[0032] Figure 5 It is a timing diagram of the input and output signals of a D latch provided by an embodiment of this application;

[0033] Figure 6Schematic flowchart of a pulse detection method provided by an embodiment of this application. Detailed implementation manners

[0034] To make the objectives, technical solutions, and advantages of this application clearer and more understandable, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part rather than all of the embodiments of this application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in this application without creative efforts shall fall within the scope of protection of this application. Without conflict, the embodiments in this application and the features in the embodiments may be arbitrarily combined with each other. And although the logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than here.

[0035] The terms "first" and "second" in the specification and claims of this application and the above accompanying drawings are used to distinguish different objects rather than to describe a specific order. In addition, the term "including" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes unlisted steps or units, or optionally further includes other steps or units inherent to these processes, methods, products, or devices. "Multiple" in this application may represent at least two, for example, it may be two, three, or more, and there is no limitation in the embodiments of this application.

[0036] In addition, the term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article generally represents an "or" relationship between the associated objects before and after without special instructions.

[0037] The pulse detection circuit and the pulse detection method provided by the embodiments of this application will be introduced in detail below in conjunction with the accompanying drawings of the specification.

[0038] Please refer to Figure 1 , Figure 1 which is a schematic framework diagram of a pulse detection circuit provided by an embodiment of this application. The pulse detection circuit provided by the embodiment of this application includes an input module 101, an automatic trigger detection module 102, and a data latch module 103. The output end of the input module 101 is connected to the clock pulse end of the automatic trigger detection module 102 and the input end of the data latch module 103, and the output end of the automatic trigger detection module 102 is connected to the enable end of the data latch module 103.

[0039] The pulse detection circuit provided by the embodiments of the present application can be used to detect pulse signals. For the convenience of description, the pulse signal that needs to pass through this pulse detection circuit is called an input pulse signal, such as Figure 1 the pulse signal input in. This input pulse can be input to the input end of the pulse detection circuit. After passing through the pulse detection circuit, high-frequency pulse signals or low-frequency pulse signals can be detected. It should be noted that the pulse detection circuit provided in the embodiments of the present application can only detect the pulse signal of one cycle each time. That is to say, the data latch module can only latch the pulse level of the pulse signal within one pulse cycle each time. Moreover, before using this pulse detection circuit to detect the pulse signal each time, the entire circuit needs to be reset to clear the pulse signal detected last time.

[0040] In the embodiments of the present application, the input module 101 can be used to receive the input pulse signal. After the pulse signal is input to the input module 101, the input module 101 can perform simple filtering processing on the input pulse, and then determine the pulse detection method. The pulse detection method is to determine whether to perform pulse detection at the rising edge of one pulse cycle or at the falling edge of one pulse cycle. When performing pulse signal detection at the rising edge, it is to start pulse signal detection during the process of the input pulse signal changing from the 0 level to the 1 level. When performing pulse signal detection at the falling edge, it is to perform detection during the process of the input pulse signal changing from the 1 level to the 0 level. That is to say, when choosing to perform pulse detection at the rising edge of the pulse, after the pulse detection circuit is reset, when a pulse rising edge is detected, the pulse signal starts to be detected. Or, when choosing to perform pulse detection at the falling edge of the pulse, when a pulse falling edge is detected, the pulse signal starts to be detected. Correspondingly, when the rising edge or falling edge of the next pulse cycle is detected, the detection of the pulse signal stops to ensure that the detected is the pulse within one pulse cycle.

[0041] The automatic trigger detection module 102 can be used to generate a latch signal that enables the data latch module 103 to latch the pulse signal. After resetting the pulse detection circuit, the pulse signal detected last time is cleared, and then the automatic trigger detection module 102 is enabled to start normal operation. When the pulse signal changes from the first level to the second level, the automatic trigger detection module 102 can be enabled to generate a latch signal. After the automatic trigger detection module 102 generates the corresponding latch signal, the latch signal will be input to the enable terminal of the data latch module 103, so that the data latch module 103 starts to latch the input pulse. It should be noted that in the embodiments of the present application, the first level refers to the 0 level, and the second level refers to the 1 level, that is, corresponding to the rising edge transition. However, in the specific implementation process, it can also be that the first level is the 1 level and the second level is the 0 level.

[0042] The data latch module 103 can be used to latch the pulse signal according to the latch signal of the automatic trigger detection module 102. The input pulse signal is serially input to the input terminal of the data latch module 103. After the data latch module 103 receives the latch signal of the automatic trigger detection module 102, it starts to detect the input pulse signal and latches the pulse level within one pulse period of the pulse signal in each latch.

[0043] For ease of understanding, the following will introduce each of the above-provided module circuits in detail with reference to the accompanying drawings.

[0044] Please refer to Figure 2 , Figure 2 which is a schematic diagram of the specific logic circuit of a pulse detection circuit provided by the embodiments of the present application. The input module 101 includes a filter, a resetter, and an inverter. For ease of distinction, this inverter will be referred to as the second inverter in the following text. The multiplexer has two input terminals, namely the high-level input terminal and the low-level input terminal. The input terminal of the filter receives the input pulse signal. The high-level input terminal of the multiplexer is directly connected to the output terminal of the filter. The low-level input terminal of the multiplexer is first connected to the second inverter and then to the output terminal of the filter. The output terminal of the multiplexer is connected to the clock pulse terminal of the automatic trigger detection module 102 and the input terminal of the data latch module 103.

[0045] The filter is used to simply filter the input pulse signal to remove clutter and power frequency interference. The multiplexer is used to measure the pulse signal by selecting whether to switch the pulse rising edge or the pulse falling edge for measurement. The selection signal of the multiplexer is one of low level or high level. When the selection signal is high level, it proves that when detecting the pulse signal at the rising edge, the high-level input terminal of the multiplexer receives the pulse signal. When the selection signal is low level, it proves that when detecting the pulse signal at the falling edge, the low-level input terminal of the multiplexer receives the pulse signal. The second inverter is used to invert the input pulse signal when the selection signal of the multiplexer is low level. After inverting the pulse signal, when the input pulse signal is at the falling edge, the automatic trigger detection module 102 can be triggered by the inverted rising edge to generate a latch signal, thereby detecting the input pulse signal, achieving the purpose of normalization, making the circuit design simple and effective, and also reducing the cost of circuit design.

[0046] In the specific implementation process, the filter can be, for example, a Schmitt trigger, or it can also be other filters that can filter the input pulse signal. The type of the filter is not limited in the embodiments of this application.

[0047] The multiplexer can be used to measure the pulse signal by selecting whether to switch the pulse rising edge or the pulse falling edge for measurement. In the embodiments of this application, the following two pulse signal detection methods are provided.

[0048] The first pulse signal detection method

[0049] When the selection signal of the resetter is high level, it proves that it is necessary to start detecting the pulse signal at the rising edge of the input pulse signal. At this time, the pulse rising edge is selected to capture the pulse signal. After the input pulse signal is filtered by the filter, it is input into the multiplexer. When a rising edge is detected passing through, the automatic trigger detection module 102 is triggered to generate a latch signal that enables the data latch module 103 to latch the pulse signal. After the latch signal is input into the data latch module 103, the latch in it starts to latch the pulse signal. When the next rising edge arrives, the latch signal is inverted, thereby ending the latching of the pulse signal, ensuring that the latched pulse signal is a signal within one period.

[0050] The second pulse signal detection method

[0051] When the selection signal of the resetter is at a low level, it proves that it is necessary to start detecting the pulse signal at the falling edge of the input pulse signal. At this time, the falling edge of the pulse is selected to capture the pulse signal. After the input pulse signal is filtered by the filter, it needs to be inverted by the second inverter first and then input into the multiplexer. When a rising edge is detected, the automatic trigger detection module 102 is triggered to generate a latch signal that enables the data latch module 103 to latch the pulse signal. After the latch signal is input into the data latch module 103, the latch in it starts to latch the pulse signal. When the next rising edge arrives, the enable signal is inverted, thereby ending the latching of the pulse signal and ensuring that the latched pulse signal is a signal within one period.

[0052] The automatic trigger detection module 102 includes a first register and a second register. The clock pulse terminal of the first register is connected to the output terminal of the multiplexer. The output terminal of the first register is connected to the input terminal of the second register after passing through the first inverter. The output terminal of the second register is connected to the enable terminals of all latches in the data latch module 103. The enable flag marked before the first register is used to re-enable the automatic trigger detection module 102 to operate normally after each circuit reset. The start or end of counting the input pulse signal can be determined by the first register and the second register to ensure that the counted pulse level is within one period. During the enable period when the automatic trigger detection module 102 enables the data latch module 103 to latch the pulse signal, the latches in the data latch module 103 latch the input pulse signal step by step through their own transmission delays, thereby enabling the detection of high-speed pulses.

[0053] When it is detected that the pulse signal changes from the first level (0 level) to the second level (1 level), the output terminal level signal of the first register is triggered to be equal to its input terminal level signal, and the output terminal level signal of the second register is triggered to be equal to its input terminal level signal. The input terminal of the second register receives the level signal after the output terminal level signal of the first register is inverted by the first inverter. The data latch module receives the output terminal level signal of the second register. It should be noted that the output terminal level signal of the second register is the latch signal input to the data latch module 103. Therefore, after the data latch module receives the latch signal output from the output terminal of the second register, it latches the pulse signal according to the latch signal.

[0054] A flip-flop is an information storage device with a memory function and is the basic logic unit that constitutes various sequential circuits. The basic unit of a register is a D flip-flop (D type flip-flop, DFF). Therefore, the first register and the second register in the embodiments of the present application are equivalent to D flip-flops. The following combines Figure 3 andFigure 4 For further explanation of the D flip-flop, Figure 3 FIG. shows a schematic diagram of a D flip-flop provided in this embodiment. Among them, din represents the input data signal, clk represents the input clock signal, dout represents the output signal, and clr represents the reset signal. The D flip-flop provided in the embodiment of the present application is a rising-edge triggered D flip-flop. The rising edge of the clock signal will trigger the D flip-flop to latch the level state of the input signal, and then output the latched level through the Q pin.

[0055] Figure 4 is Figure 3 the timing diagram of the input and output signals of the D flip-flop shown. As described above, the D flip-flop is rising-edge triggered. When clk is a rising edge, it triggers the output Q to be equal to the input D. At any other time, there is no relationship between the input and output of the D flip-flop. That is, when clk is a falling edge, remains high level, or remains low level, the output Q maintains its own state. That is to say, when clk is a rising edge, if the output Q is equal to the input D, then the output Q does not need to change. If the output Q is not equal to the input D, then the output Q needs to change to the state of the input D. Taking Figure 6 the first rising edge of clk in as an example, before the first rising edge of clk arrives, the state of the input D is high level, and the state of the output Q is low level. When the rising edge arrives, the output Q becomes high level, which is consistent with the state of the input D.

[0056] In the automatic trigger detection module 102, after the pulse detection circuit is reset, the output terminals of the first register and the second register are both restored to "0". For example, this signal "0" is called the first signal. The first signal passes through an inverter and outputs the signal "1". For example, this output signal "1" is called the second signal. After the second signal is input to the second register, the input terminal of the second register is the second signal "1". When there is a rising edge in the input pulse, this rising edge will trigger the output terminal of the second register to be equal to its input terminal. That is to say, at this time, the output terminal of the second register is the signal "1". This signal can be understood as the aforementioned latch signal. After this latch signal is input to the data latch module 103, it causes the latch in it to start latching the input pulse signal. When the rising edge of the next input pulse signal arrives, the first signal becomes "1". After passing through the inverter, the second signal becomes "0", and then the enable signal becomes "0". At this time, the latch signal enables the data latch module 103 to end the latching of the input pulse. Furthermore, the pulse information within one period is latched.

[0057] The data latch module 103 can latch high-speed pulse signals and low-speed pulse signals. When the frequency of the input pulse signal is greater than the preset frequency, it can be regarded as a high-speed pulse signal. When the frequency of the input pulse signal is less than or equal to the preset frequency, it can be regarded as a low-speed pulse signal. However, when the frequency of the input pulse signal is less than or equal to the preset frequency, the data latch module 103 requires a large number of latches, which will lead to an increase in cost. Therefore, when the frequency of the input pulse signal is less than or equal to the preset frequency, the pulse signal can be detected by the synchronous pulse detection circuit. It should be noted that the preset frequency is used to enable the pulse detection circuit to distinguish whether it is a high-speed pulse. For example, if the preset frequency is determined to be 100 MHz according to the actual application, it means that pulses greater than 100 MHz are high-speed pulses, and pulses less than or equal to 100 MHz are low-speed pulses.

[0058] The data latch module 103 includes a number of cascaded latches. The pulse signal is serially input into these latches, and these latches latch the pulse levels within one pulse period of the pulse signal. When it is determined that the input pulse is a high-speed pulse, each stage of the latch in the data latch module 103 latches the input pulse signal according to the latch signal. It should be noted that in general, in circuit designs that require a clock, registers are used to latch pulse signals. However, the D latch still has a latching function when the transmission delay is relatively low and can accurately latch the pulse width information. Therefore, in the embodiments of the present application, the data latch module 103 can be composed of a number of D latches, but in specific application processes, other latches can also be used.

[0059] The following combines Figure 5 to make an appropriate description of the D latch first. Figure 5 FIG. is the timing diagram of the input and output signals of the D latch provided by the embodiments of the present application. This D latch is enabled by a high level. When the enable signal EN is at a high level, it triggers the output Q to be equal to the input D. When EN is at a low level, there is no relationship between the input and output of the D latch, and the output Q maintains its own state. That is to say, when EN is at a high level, if the output Q is equal to the input D, then the output Q does not need to change. If the output Q is not equal to the input D, then the output Q needs to change to the state of the input D. Taking Figure 6 the first high level of EN in as an example, before the first high level of EN arrives, the state of the input D is at a high level, and the state of the output Q is at a low level. When the high level arrives, the output Q becomes a high level, which is the same as the state of the input D. When the high level of EN is within a short time before the end, if the input D becomes a low level, then the output Q also becomes a high level.

[0060] The number of several latches in the latch in the data latch module 103 can be determined according to the maximum delay of the latch group and the synchronous pulse capture unit. First, the delay of the latch can be determined, and then the number of latches that meet the required delay can be judged. In the actual application process, the number of latches can be dynamically changed. When it is determined that the error when using the synchronous pulse detection circuit to measure the input pulse and the error when the pulse detection circuit measures the input pulse signal belong to the preset error range, then the synchronous pulse capture unit can be used to detect the input pulse, and there is no need to add an additional D latch, reducing the cost of circuit design.

[0061] It should be noted that the preset number of latches can be 500 or 000, depending on the actual situation. The embodiment of the present application does not limit the number of latches in the latch group, but this number is generally in the hundreds or thousands. The latches in the latch group are sorted in a cascaded manner. The enable terminal of each stage of the latch is connected to the input terminal of the automatic trigger detection module 102 to receive the latch signal and then latch the pulse signal. The output terminal of each stage of the latch is connected to the input terminal of the next stage of the latch. The input terminal of the first stage of the latch is connected to the output terminal of the input module 101. The input pulse is input into the latch group in a serial manner. After the latch group receives the enable signal, it starts to latch the input pulse signal.

[0062] The first register and the second register in the automatic trigger detection module 102, and each stage of the latch in the data latch module 103 all have a reset terminal for receiving a reset signal and then performing a reset process on the automatic trigger detection module 102 and the data latch module 103. The reset signal can be a reset signal obtained by manual reset or a reset signal obtained by power-on reset. The embodiment of the present application does not make a limitation.

[0063] When using the data latch module 103 to latch the input pulse signal, after the pulse signal latching is completed, a string of codes can be obtained by reading the outputs of each stage of latches, and then, based on the obtained codes and the delay of the latches, pulse information such as the width and duty cycle of the pulse can be calculated. For example, if a set of sequences is obtained now, since the pulse signal within one period is detected, it is possible to know how many latches latch the high level and low level of the pulse signal respectively. Then, by multiplying the propagation delay of the latch by the number of latches corresponding to the high level, the pulse width of the high level can be obtained. By multiplying the propagation delay of the latch by the number of latches corresponding to the low level, the pulse width of the low level can be obtained, and then the duty cycle information of the pulse signal can be obtained. It should be noted that even if there are deviations in the manufacturing process of the latches, resulting in possible differences in the propagation delays of each latch, the difference is not large, and the latch group can avoid process deviations through a certain order arrangement, such as Gaussian white noise. When the number of latches in the latch group is large enough, the mean value of the deviation approaches 0, that is, it can be directly ignored. Therefore, in the embodiments of the present application, the propagation delay of the latch can be regarded as fixed. Therefore, the pulse width information obtained by this pulse detection circuit has high accuracy.

[0064] Please refer to Figure 6 , based on the same inventive concept, the embodiments of the present application provide a pulse detection method, which is applied to a pulse detection circuit, and the process of this method is described as follows.

[0065] Step 601: The input module 101 is configured to receive the input pulse signal and transmit the pulse signal to the clock pulse terminal of the automatic trigger detection module 102 and the input terminal of the data latch module 103 respectively.

[0066] Step 602: The automatic trigger detection module 102 is configured to send a latch signal to the enable terminal of the data latch module 103 when the pulse signal changes from the first level to the second level.

[0067] Step 603: The data latch module 103 is configured to latch the pulse signal according to the latch signal.

[0068] The embodiments of the present application adopt a pure asynchronous circuit design, which can measure higher-speed input pulses while reducing the power consumption of the microcontroller. In practical applications, the number of latches in the latch group can be determined according to its maximum delay and the synchronous pulse capture unit of the chip itself, increasing the flexibility of the pulse detection circuit for detecting pulses. After the latch group latches the pulse signal, the pulse width and duty cycle information can be calculated according to the outputs of each stage of latches read.

[0069] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0070] The present application is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, as well as the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0071] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including instruction means that implement the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0072] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0073] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A pulse detection circuit, characterized in that, Comprising: An input module, an automatic trigger detection module, and a data latch module. The output end of the input module is connected to the clock pulse end of the automatic trigger detection module and the input end of the data latch module. The output end of the automatic trigger detection module is connected to the enable end of the data latch module; Receiving an input pulse signal through the input end of the input module, and transmitting the pulse signal to the clock pulse end of the automatic trigger detection module and the input end of the data latch module respectively through the output end of the input module; Wherein, when the pulse signal changes from a first level to a second level, the automatic trigger detection module is enabled to send a latch signal from the output end of the automatic trigger detection module to the enable end of the data latch module. The data latch module serially inputs the pulse signal into a plurality of cascaded latches included in the data latch module according to the latch signal, and latches the pulse levels within one pulse period of the pulse signal through the plurality of latches.

2. The circuit according to claim 1, characterized in that, The automatic trigger detection module includes a first register and a second register. The clock pulse ends of the first register and the second register are both connected to the output end of the input module. The output end of the first register is connected to a first inverter and then to the input end of the second register. The output end of the second register is connected to the enable end of each stage of latch in the data latch module, wherein: When it is detected that the pulse signal changes from a first level to a second level, triggering the output level of the first register to be equal to the input level of the first register, and triggering the output level of the second register to be equal to the input level of the second register. The input end of the second register receives the level after the output level of the first register passes through the first inverter. The data latch module receives the latch signal output from the output end of the second register, and the data latch module latches the pulse signal according to the latch signal.

3. The circuit according to claim 1, characterized in that, The input module includes a multiplexer. The input end of the multiplexer receives the pulse signal, and the output end of the multiplexer is connected to the clock pulse end of the automatic trigger detection module and the input end of the data latch module, wherein: The selection end of the multiplexer receives a selection signal, and the multiplexer enables the automatic trigger detection module to send the latch signal to the data latch module according to the selection signal. The selection signal is a high level or a low level.

4. The circuit according to claim 3, wherein The input module further includes a filter. The input end of the filter receives the pulse signal, and the output end of the filter is connected to the input end of the multiplexer.

5. The circuit according to claim 3, characterized in that, The input module further includes a second inverter. The input end of the second inverter is connected to the output end of the filter, and the output end of the second inverter is connected to the input end of the multiplexer, wherein: When the selection signal is at a low level, the pulse signal is input into the second inverter, and the multiplexer receives the pulse signal output from the second inverter.

6. The circuit according to any one of claims 1-5, characterized in that, The first register, the second register, and each latch stage include a reset terminal, where: The reset terminals of the first register, the reset terminal of the second register, and the reset terminal of each latch stage receive a reset signal, and the automatic trigger detection module and the data latch module are reset according to the reset signal.

7. The circuit according to claim 1, characterized in that, The first level is the 0 level, and the second level is the 1 level.

8. A device for detecting a pulse signal, characterized in that, It includes the pulse detection circuit according to any one of claims 1-7.

9. A pulse detection method, characterized in that, Applied to a pulse detection circuit, the pulse detection circuit includes: an input module, an automatic trigger detection module, and a data latch module. The output terminal of the input module is connected to the clock pulse terminal of the automatic trigger detection module and the input terminal of the data latch module. The output terminal of the automatic trigger detection module is connected to the enable terminal of the data latch module. The method includes: The input module is configured to receive an input pulse signal and transmit the pulse signal to the clock pulse terminal of the automatic trigger detection module and the input terminal of the data latch module respectively. The automatic trigger detection module is configured to send a latch signal to the enable terminal of the data latch module when the pulse signal changes from the first level to the second level. The data latch module is configured to serially input the pulse signal into a plurality of cascaded latches included in the data latch module according to the latch signal, and latch the pulse levels within one pulse period of the pulse signal through the plurality of latches.

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