Gate driving circuit and display device including the same

Abstract

The present application relates to a gate drive circuit and a display device including the same. The display device includes a display panel, a gate drive circuit including a plurality of stages, and a power supply circuit that outputs a clock signal, a clock bar signal, a first discharge voltage, and a second discharge voltage. Each stage includes: a charging unit that charges a clock signal having a first high voltage to a charging node; an output unit that charges the first high voltage to an output node in response to a first node voltage of the charging node, and outputs a second node voltage of the output node to a gate signal; a first discharge unit that discharges the second node voltage to a first discharge voltage in response to the clock bar signal having a second high voltage; and a second discharge unit that discharges the first node voltage to a second discharge voltage in response to a clock bar signal having a second high voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0150301 filed on November 21, 2019, in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments of the present disclosure relate to a display device, and more particularly, to a gate driving circuit and a display device including the gate driving circuit. Background Art

[0004] The display device includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels connected to the plurality of gate lines and the plurality of data lines. The display device includes a gate driving circuit for providing gate signals to the gate lines and a data driving circuit for outputting data signals to the data lines.

[0005] The gate driving circuit includes a shift register, which includes a plurality of driving stage circuits (hereinafter referred to as driving stages). Each driving stage outputs a gate signal to a gate line. Each driving stage includes a plurality of transistors for outputting a gate signal. Summary of the invention

[0006] One or more aspects of exemplary embodiments of the present disclosure are directed to a gate driving circuit capable of improving driving reliability and a display device including the gate driving circuit.

[0007] An embodiment of the present disclosure provides a gate driving circuit, including: a charging section connected to a charging node and configured to charge a clock signal having a first high voltage to the charging node during a first section; an output section connected to each of the charging node and the output node, and configured to charge the first high voltage to the output node in response to the first node voltage of the charging node during the first section, and output the second node voltage of the output node to a gate signal; a first discharging section configured to discharge the second node voltage to a first discharging voltage in response to a clock bar signal having a second high voltage during a second section continuous with the first section; and a second discharging section configured to discharge the first node voltage to a second discharging voltage during the second section. Here, the first section has one of a first subsection and a second subsection, during the first subsection, the second discharging section is turned off, and during the second subsection, the second discharging section alternates between a first mode in which the second discharging section is turned on and a second mode in which the second discharging section is turned off.

[0008] In an embodiment, the second discharge section may receive a clock bar signal having a first low voltage during a first section, and in the first mode, a first voltage level of the second discharge voltage may be lower than a second voltage level of the first low voltage.

[0009] In an embodiment, a first voltage level of the second discharge voltage may be substantially the same as a second voltage level of the first low voltage during the first subsection and in the second mode.

[0010] In an embodiment, the second discharge part may discharge the first node voltage to a second discharge voltage having a first voltage level in the first mode.

[0011] In an implementation, the second discharge section may include a first discharge transistor configured to discharge the first node voltage to a second discharge voltage having a first voltage level in response to a first low voltage of the clock bar signal during the second section.

[0012] In an implementation, the first discharge section may include a second discharge transistor configured to discharge the second node voltage to a first discharge voltage in response to a first low voltage of the clock bar signal during the second section.

[0013] In an embodiment, during the second subsection, a voltage level of the second discharge voltage according to the first mode at a first time and a voltage level of the second discharge voltage according to the first mode at a second time may be different from each other.

[0014] In an embodiment, during the second subsection, a voltage level of the second discharge voltage according to the first mode at a first time and a voltage level of the second discharge voltage according to the first mode at a second time may be substantially identical to each other.

[0015] In an embodiment, the first mode and the second mode may have time periods that are substantially the same in duration as each other.

[0016] In an embodiment, the first mode and the second mode may have time sections different in duration from each other, and the time section according to the first mode may be longer than the time section according to the second mode.

[0017] In an embodiment of the present disclosure, a display device includes: a display panel; a gate driving circuit including a plurality of stages configured to output a plurality of gate signals to the display panel, the plurality of stages including the i-th stage, wherein i is a natural number; a signal control circuit configured to output a power control signal; and a power supply circuit configured to output a clock signal, a clock bar signal, a first discharge voltage, and a second discharge voltage to the gate driving circuit in response to the power control signal. Here, the i-th stage of the plurality of stages includes: a charging section configured to charge a clock signal having a first high voltage to a charging node during a first segment; an output section connected to the charging section through a charging node, and configured to charge a first high voltage to an output node in response to a first node voltage of the charging node, and output a second node voltage of the output node to an i-th gate signal among the plurality of gate signals; a first discharge section connected to the output section through an output node, and configured to discharge a second node voltage to a first discharge voltage in response to a clock bar signal having a second high voltage during a second segment continuous with the first segment; and a second discharge section connected to the charging node and configured to discharge the first node voltage to a second discharge voltage during a second segment. Furthermore, the first section has one of a first subsection during which the second discharge section is turned off and a second subsection during which the second discharge section alternates between a first mode in which the second discharge section is turned on and a second mode in which the second discharge section is turned off.

[0018] In an embodiment, the display device may further include a temperature sensing unit configured to output a temperature control signal based on an external temperature, and the first segment may have one of the first sub-segment and the second sub-segment in response to the temperature control signal.

[0019] In an embodiment, the power supply circuit may include: a power generation unit configured to output a first discharge voltage and a second discharge voltage; a clock generation unit configured to output a clock signal and a clock bar signal; and a power control unit configured to receive the second discharge voltage and control a voltage level of the second discharge voltage based on an external temperature.

[0020] In an embodiment, the power control section may include: a frame selection part configured to output a selection signal in response to the temperature control signal and the power control signal; and a voltage adjustment part configured to adjust a voltage level of the second discharge voltage in response to the selection signal.

[0021] In an embodiment, the second discharge part may receive a first low voltage of the clock bar signal during the first section, and in the first mode, a first voltage level of the second discharge voltage may be lower than a second voltage level of the first low voltage.

[0022] In an embodiment, the power control signal may include a first pulse signal corresponding to the first mode and a second pulse signal corresponding to the second mode, and the first pulse signal and the second pulse signal are repeated alternately.

[0023] In an embodiment, the temperature control signal may include a first temperature signal and a second temperature signal, in which the external temperature is less than a reference temperature, in which the external temperature is equal to or greater than the reference temperature, and the first section may correspond to the first sub-section according to the first temperature signal and to the second sub-section according to the second temperature signal.

[0024] In an embodiment, the display device may further include a signal sensing unit configured to receive gate signals output from the gate driving circuit and analyze the gate signals, and the signal sensing unit may transmit an analysis control signal based on an analysis result of each of the gate signals to the power supply circuit.

[0025] In an embodiment, the power supply circuit may control the operation of the second discharge part in response to the analysis control signal.

[0026] In an embodiment of the present disclosure, a display device includes: a display panel; a gate driving circuit including a plurality of stages configured to output a plurality of gate signals to the display panel, the plurality of stages including the i-th stage, wherein i is a natural number; and a power supply circuit configured to output a clock signal, a clock bar signal, a first discharge voltage, and a second discharge voltage to the gate driving circuit. Here, the i-th stage of the plurality of stages includes: a charging section configured to charge a clock signal having a first high voltage to a charging node; an output section connected to the charging section through the charging node, and configured to charge the first high voltage to an output node in response to a first node voltage of the charging node, and output a second node voltage of the output node to the i-th gate signal in the gate signal; a first discharge section connected to the output section through the output node and configured to discharge the second node voltage to the first discharge voltage in response to a clock bar signal having a second high voltage; and a second discharge section connected to the charging node and configured to discharge the first node voltage to the second discharge voltage in response to a clock bar signal having a second high voltage. In addition, the second discharge part may alternate between a first mode in which the second discharge part discharges the first node voltage to the second discharge voltage in response to the clock bar signal and a second mode in which the second discharge part maintains the first node voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0028] Figure 1is a perspective view showing a display device according to an embodiment of the present disclosure;

[0029] Figure 2 is a plan view showing a display device according to an embodiment of the present disclosure;

[0030] Figure 3 is a block diagram showing a gate driving circuit according to an embodiment of the present disclosure;

[0031] Figure 4 It is shown Figure 3 A timing diagram of the operation of the stages in FIG.

[0032] Figure 5 is a circuit diagram showing a stage according to an embodiment of the present disclosure;

[0033] Figure 6 is a block diagram showing a display device according to an embodiment of the present disclosure;

[0034] Fig. 7A is a circuit diagram showing a temperature sensing unit according to an embodiment of the present disclosure;

[0035] Figure 7B is a block diagram showing a power supply circuit according to an embodiment of the present disclosure;

[0036] Figure 7C is a timing diagram showing clock signals according to an embodiment of the present disclosure;

[0037] Figure 8 is a block diagram showing a power control section according to an embodiment of the present disclosure;

[0038] Fig.9A The present invention is shown in the embodiment of the present invention. Figure 8 A table of operations in the frame selection part;

[0039] Fig. 9B The present invention is shown in the embodiment of the present invention. Figure 8 Circuit diagram of the voltage regulation part in;

[0040] Fig.10 is a timing chart showing the operation of the display device in a high temperature state according to an embodiment of the present disclosure;

[0041] Fig.11 is a timing chart showing the operation of a display device in a high temperature state according to another embodiment of the present disclosure;

[0042] Fig. 12A is a circuit diagram showing a stage according to an embodiment of the present disclosure;

[0043] Fig. 12Bis a circuit diagram showing a stage according to an embodiment of the present disclosure;

[0044] Fig.13 is a block diagram showing a display device according to another embodiment of the present disclosure; and

[0045] Fig.14 is a block diagram showing a power control section according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] In the present specification, it should also be understood that when a component (or region, layer, portion) is referred to as being on, connected to, or coupled to another component, it may be directly disposed on / connected to / coupled to the one component, or an intervening third component may also be present.

[0047] In the entire specification, the same reference numerals represent the same elements. In addition, in the drawings, the thickness, proportion and size of components are exaggerated for clarity of illustration.

[0048] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0049] Furthermore, when describing embodiments of the present disclosure, the use of “may” refers to “one or more embodiments of the present disclosure.”

[0050] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent variations in measurements or calculations that those of ordinary skill in the art would recognize.

[0051] Any numerical ranges cited herein are intended to include all subranges of the same numerical precision contained within the cited range. For example, the range of "1.0 to 10.0" is intended to include all subranges between the cited minimum value 1.0 and the cited maximum value 10.0 (and including 1.0 and 10.0), that is, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit cited herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit cited in this specification is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to modify this specification (including claims) to explicitly describe any subranges contained within the scope explicitly cited herein.

[0052] As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively.

[0053] As used herein, expressions such as “at least one of,” “one of,” and “selected from,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

[0054] The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0055] It should be understood that although terms such as "first" and "second" are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one component from other components. For example, a first element referred to as a first element in one embodiment may be referred to as a second element in another embodiment without departing from the scope of the appended claims. Unless otherwise mentioned, terms in the singular may include plural forms.

[0056] In addition, “under”, “below”, “above”, “upper”, etc. are used to describe the relationship between components shown in the drawings. These terms may be relative concepts and described based on the directions expressed in the drawings.

[0057] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art. Terms defined in commonly used dictionaries should be interpreted as having the same meaning as in the context of the relevant technology, and unless clearly defined in the specification, these terms are not ideally or excessively interpreted as having formal meanings.

[0058] The meaning of “include” or “comprise” specifies a property, a fixed number, a step, an operation, an element, a component or a combination thereof, but does not exclude other properties, fixed numbers, steps, operations, elements, components or a combination thereof.

[0059] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0060] Figure 1 is a perspective view showing a display device according to an embodiment of the present disclosure. Figure 2 is a plan view showing a display device according to an embodiment of the present disclosure.

[0061] In one or more embodiments, a display device DD applicable to a mobile phone terminal is exemplarily shown. In one or more embodiments, the mobile phone terminal may be configured such that an electronic module, a camera module, and a power module mounted on a mainboard are located in a bracket / housing together with the display device DD. The display device DD according to an embodiment of the present disclosure may be used for large electronic devices such as televisions and monitors, and small and medium-sized electronic devices such as tablet PCs, navigation units for vehicles, game consoles, and smart watches.

[0062] like Figure 1 As shown in , the display device DD may display an image IM through the display surface DD-IS (eg, the display area DD-DA of the display surface DD-IS). Figure 1 An icon image is shown as an example of an image IM. The display surface DD-IS is parallel to a surface or plane defined by a first direction DR1 and a second direction DR2. The normal direction of the display surface DD-IS (i.e., the thickness direction of the display device DD) refers to a third direction DR3. As used herein, the expression "plan view" may refer to observing features in the third direction DR3. In the following, the front surface (or top surface) and the rear surface (or bottom surface) of each layer or each unit are distinguished by the third direction DR3. However, the directions indicated by the first direction, the second direction, and the third direction (e.g., DR1, DR2, and DR3, respectively) may be related to each other and may change relative to each other.

[0063] In addition, the display surface DD-IS includes a display area DD-DA in which the image IM is displayed and a non-display area DD-NDA disposed adjacent to the display area DD-DA. The non-display area DD-NDA may be an area in which (or through which) the image IM is not displayed. In one or more embodiments, the non-display area DD-NDA surrounds the display area DD-DA. However, one or more embodiments of the present disclosure are not limited thereto. For example, the non-display area DD-NDA may be adjacent to one side of the display area DD-DA, and in one or more embodiments, the non-display area DD-NDA may be omitted.

[0064] Reference Figure 2 The display device DD includes a display panel DP, a signal control circuit 100, a gate driving circuit 200, a data driving circuit 300 and a driving circuit board MCB.

[0065] Although the display panel DP according to the embodiment of the present disclosure may be a light-emitting display panel, one or more embodiments of the present disclosure are not limited thereto. For example, the display panel DP may be an organic light-emitting display panel and a quantum dot light-emitting display panel. The organic light-emitting display panel may include a light-emitting layer containing an organic light-emitting material. The quantum dot light-emitting display panel may include a light-emitting layer containing quantum dots and quantum rods. For example, the display panel DP may be a liquid crystal display panel. The liquid crystal display panel may include a liquid crystal layer and display an image by using external light.

[0066] The display panel DP includes a first substrate DS1 and a second substrate DS2 facing each other in the third direction DR3. In addition, the display panel DP includes a display area DA for displaying an image and a non-display area NDA adjacent to the display area DA. The display area DA and the non-display area NDA of the display panel DP may correspond to Figure 1 The display device DD in FIG. 2 includes a display area DD-DA and a non-display area DD-NDA.

[0067] The display panel DP includes a plurality of gate lines GL1 to GLn, a plurality of data lines DL1 to DLm, and a plurality of pixels PX. 11 To PX nm The gate lines GL1 to GLn each extend in the first direction DR1 and are arranged in the second direction DR2. The data lines DL1 to DLm each extend in the second direction DR2 and are arranged in the first direction DR1. The data lines DL1 to DLm cross the gate lines GL1 to GLn in an insulated manner. The gate lines GL1 to GLn are connected to the gate driving circuit 200, and the data lines DL1 to DLm are connected to the data driving circuit 300. The pixel PX 11 To PX nm Connected to the gate lines GL1 to GLn and the data lines DL1 to DLm.

[0068] In one or more embodiments, a plurality of gate lines GL1 to GLn, a plurality of data lines DL1 to DLm, and a plurality of pixels PX 11 To PX nm It can be set on the first substrate DS1.

[0069] The signal control circuit 100 may be mounted on the driving circuit board MCB. The signal control circuit 100 receives image data and control signals from an external graphics control unit. The signal control circuit 100 outputs a gate control signal to the gate driving circuit 200 and a data control signal to the data driving circuit 300 in response to the control signal.

[0070] For example, the control signal may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a clock signal. The vertical synchronization signal is a signal for distinguishing frame segments adjacent to each other, the horizontal synchronization signal is a signal for distinguishing horizontal segments (i.e., a row distinction signal), and the data enable signal has a high level only during a period of outputting data to display a data input segment.

[0071] The gate driving circuit 200 generates a gate signal based on a gate control signal received from the signal control circuit 100 through the signal line GSL. The gate control signal may include a vertical start signal that starts the operation of the gate driving circuit 200. The gate driving circuit 200 outputs the gate signal to the corresponding gate line. The gate signal may be sequentially output corresponding to the corresponding horizontal segment.

[0072] According to an embodiment of the present disclosure, the gate driving circuit 200 can be connected to the pixel PX by thin film process. 11 To PX nm The gate driving circuit 200 is arranged in parallel (e.g., simultaneously). For example, the gate driving circuit 200 may be mounted on the first substrate DS1 in the form of an amorphous silicon TFT gate driver circuit (ASG) to overlap with the non-display area NDA. As another example, the gate driving circuit 200 may be mounted on the first substrate DS1 in the form of an oxide semiconductor TFT gate driver circuit (OSG) to overlap with the non-display area NDA.

[0073] However, one or more embodiments of the present disclosure are not limited thereto. For example, the display device DD may include two gate drive circuits 200. One of the two gate drive circuits 200 may be connected to the left end of the plurality of gate lines GL1 to GLn, and the other of the two gate drive circuits 200 may be connected to the right end of the plurality of gate lines GL1 to GLn. In addition, one of the two gate drive circuits 200 may be connected to an odd-numbered gate line, and the other of the two gate drive circuits 200 may be connected to an even-numbered gate line.

[0074] The data driving circuit 300 receives a data control signal and an image signal from the signal control circuit 100. The data driving circuit 300 converts the image signal into a plurality of data voltages and supplies the converted data voltages to the data lines DL1 to DLm in response to the data control signal. For example, the data control signal may include a horizontal start signal for starting the operation of the data driving circuit 300, an inversion signal for inverting the polarity of the data voltage, and an output command signal for determining the time for outputting the data voltage from the data driving circuit 300.

[0075] The data driving circuit 300 may include a driving chip 310 and a flexible circuit board 320 on which the driving chip 310 is mounted. The flexible circuit board 320 connects (eg, electrically connects) the driving circuit board MCB and the first substrate DS1. The plurality of driving chips 310 provide corresponding data signals to corresponding data lines among the plurality of data lines DL1 to DLm.

[0076] Despite Figure 2 exemplarily illustrates a tape carrier package (TCP) type data driving circuit 300, but one or more embodiments of the present disclosure are not limited thereto. For example, a chip on glass (COF) type data driving circuit 300 may be mounted in the non-display area NDA of the first substrate DS1.

[0077] Figure 3 is a block diagram showing a gate driving circuit according to an embodiment of the present disclosure. Figure 4 It is shown Figure 3 Timing diagram of the operation of the stages in FIG.

[0078] The gate driving circuit 200 may include a plurality of stages connected independently of each other. The plurality of stages may include a driving stage and a dummy stage. The driving stage may be connected to Figure 1 The plurality of driving stages may output gate signals to the gate lines GL1 to GLn, respectively.

[0079] Hereinafter, a first stage SRC1 to a seventh stage SRC7 (a first stage SRC1, a second stage SRC2, a third stage SRC3, a fourth stage SRC4, a fifth stage SRC5, a sixth stage SRC6, and a seventh stage SRC7) corresponding to a driving stage among a plurality of stages are described in detail. Figure 3 Although the first to seventh stages SRC1 to SRC7 are shown as examples, the driver stages and dummy stages may have the same Figure 3 Basically the same structure as shown in .

[0080] Each of the first to seventh stages SRC1 to SRC7 (hereinafter referred to as “stage”) includes a first input terminal IN1, a second input terminal IN2, a first clock terminal CK1, a first clock terminal CK2, a first discharge terminal V1, a second discharge terminal V2, an output terminal OUT, and a carry terminal CR.

[0081] The carry terminal CR of each of the stages SRC1 to SRC7 is connected (e.g., electrically connected) to the first input terminal IN1 of the next stage. The i-th stage can output the i-th carry signal through the carry terminal CR. Here, i is a natural number. The first input terminal IN1 of the first stage SRC1 receives the vertical start signal STV output from the signal control circuit 100 without receiving the carry signal of the previous stage, and the vertical start signal STV starts the drive of the gate drive circuit 200. The first input terminal IN1 of each of the stages SRC2 to SRC7 after the first stage SRC1 receives the carry signal of the previous stage. The first input terminal IN1 of the i-th stage is connected (e.g., electrically connected) to the carry terminal CR of the i-1-th stage. The first input terminals IN1 of the second stage SRC2 and the third stage SRC3 receive the carry signals of the first stage SRC1 and the second stage SRC2, respectively.

[0082] However, one or more embodiments of the present disclosure are not limited thereto. For example, the first input terminal IN1 of the i-th stage may be connected (eg, electrically connected) to the carry terminal CR of any suitable previous stage (eg, the i-1th stage, the i-2th stage, or the i-3th stage).

[0083] The second input terminal IN2 of the i-1th stage is connected (e.g., electrically connected) to the carry terminal CR of the i+6th stage and receives the carry signal of the i+6th stage. For example, the second input terminal IN2 of the first stage SRC1 receives the carry signal of the seventh stage SRC7, and the second input terminal IN2 of the second stage SRC2 receives the carry signal of the eighth stage.

[0084] At least one driver stage in the stage can receive a carry signal through a dummy stage. In other words, a second input terminal IN2 of at least one driver stage can receive a carry signal output from a dummy stage. The dummy stages are sequentially connected from the rear end of the last driver stage in the driver stage. However, the number and position of the dummy stages in one or more embodiments can be appropriately changed according to the design purpose.

[0085] The first clock terminal CK1 and the second clock terminal CK2 of the i-th stage may respectively receive signals having opposite phases. In other words, the first clock terminal CK1 of the first stage SRC1 may receive a clock signal having a high voltage, and the second clock terminal CK2 may receive a low voltage clock bar signal.

[0086] For more details, refer to Figure 3 and Figure 4, the first section P1 is a section where each of the clock signals CKV1 to CKV6 (clock signals CKV1, CKV2, CKV3, CKV4, CKV5, and CKV6) is a high voltage, and the second section P2 is a section where each of the clock signals CKV1 to CKV6 is a low voltage. The first section P1 may be a section where each of the clock bar signals CKVB1 to CKVB6 (clock bar signals CKVB1, CKVB2, CKVB3, CKVB4, CKVB5, and CKVB6) is a low voltage, and the second section P2 may be a section where each of the clock bar signals CKVB1 to CKVB6 is a high voltage.

[0087] According to an embodiment of the present disclosure, the first to sixth stages SRC1 to SRC6 may sequentially output the first to sixth gate signals G1 to G6 (the first gate signal G1, the second gate signal G2, the third gate signal G3, the fourth gate signal G4, the fifth gate signal G5, and the sixth gate signal G6) in response to the first to sixth clock signals CKV1 to CKV6. Thereafter, the seventh to twelfth stages may sequentially output the seventh to twelfth gate signals in response to the first to sixth clock bar signals CKVB1 to CKVB6. The above-mentioned operation method may be repeatedly performed.

[0088] First, the operation method of the first stage SRC1 to the sixth stage SRC6 will be described.

[0089] During the first section P1, the first clock terminal CK1 of the first stage SRC1 receives the first high voltage of the first clock signal CKV1, and the second clock terminal CK2 of the first stage SRC1 receives the second low voltage of the first clock bar signal CKVB1. The output terminal OUT of the first stage SRC1 may output the first gate signal G1 during the first section P1 in response to the first high voltage of the first clock signal CKV1. The phase difference between the first clock signal CKV1 and the first clock bar signal CKVB1 may be about 180°.

[0090] During the first section P1, the first clock terminal CK1 of the second stage SRC2 receives the first high voltage of the second clock signal CKV2, and the second clock terminal CK2 of the second stage SRC2 receives the second low voltage of the second clock bar signal CKVB2. The output terminal OUT of the second stage SRC2 may output the second gate signal G2 during the first section P1 in response to the first high voltage of the second clock signal CKV2. The phase difference between the second clock signal CKV2 and the second clock bar signal CKVB2 may be about 180°.

[0091] During the first section P1, the first clock terminal CK1 of the third stage SRC3 receives the first high voltage of the third clock signal CKV3, and the second clock terminal CK2 of the third stage SRC3 receives the second low voltage of the third clock bar signal CKVB3. The output terminal OUT of the third stage SRC3 may output the third gate signal G3 during the first section P1 in response to the first high voltage of the third clock signal CKV3. The phase difference between the third clock signal CKV3 and the third clock bar signal CKVB3 may be about 180°.

[0092] As described above, the fourth to sixth stages SRC4 to SRC6 may sequentially output the fourth to sixth gate signals G4 to G6 in response to the first high voltages of the fourth to sixth clock signals CKV4 to CKV6 , respectively.

[0093] In addition, according to an embodiment of the present disclosure, the first high voltage sections of the first to sixth clock signals CKV1 to CKV6 may overlap with each other (e.g., overlap in time). In other words, one or more of the first to sixth clock signals CKV1 to CKV6 may be simultaneously (e.g., in the case of Figure 4 1 to 6) is at a high level (high signal level) during the first segment P1 shown in FIG. 1 . For example, the first high voltage segment of the sixth clock signal CKV6 may overlap with the first high voltage segment of the first clock signal CKV1 to the fifth clock signal CKV5. In the same manner, the second low voltage segments of the first clock bar signal CKVB1 to the sixth clock bar signal CKVB6 may overlap with each other (e.g., overlap in time). In other words, one or more of the first clock bar signal CKVB1 to the sixth clock bar signal CKVB6 may be simultaneously (e.g., during the period shown in FIG. 1 ). Figure 4 For example, the second low voltage section of the sixth clock bar signal CKVB6 may overlap with the second low voltage sections of the first to fifth clock bar signals CKVB1 to CKVB5.

[0094] Hereinafter, an operation method of the seventh to twelfth stages will be described. Each of the seventh to twelfth stages may output seventh to twelfth gate signals in response to the second high voltage of the first to sixth clock bar signals CKVB1 to CKVB6.

[0095] In more detail, during the second section P2, the first clock terminal CK1 of the seventh stage SRC7 receives the second high voltage of the first clock bar signal CKVB1, and the second clock terminal CK2 of the seventh stage SRC7 receives the first low voltage of the first clock signal CKV1. The output terminal OUT of the seventh stage SRC7 may output the seventh gate signal G7 during the second section P2 in response to the second high voltage of the first clock bar signal CKVB1. The carry signal output from the carry terminal CR of the seventh stage SRC7 may be received through the second input terminal IN2 of the first stage SRC1.

[0096] In one or more embodiments, during the second section P2 , each of the eighth to twelfth stages may output the eighth to twelfth gate signals in response to the second high voltage of the second to sixth clock bar signals CKVB2 to CKVB6 .

[0097] In addition, the first discharge voltage VSS1 may be output to the first discharge terminal V1 of each of the stages SRC1 to SRC7, and the second discharge voltage VSS2 may be output to the second discharge terminal V2 of each of the stages SRC1 to SRC7. For example, each of the first discharge voltage VSS1 and the second discharge voltage VSS2 may have a level equal to or less than a ground voltage.

[0098] For example, the first discharge voltage VSS1 may have a voltage level greater than that of the second discharge voltage VSS2. The first discharge voltage VSS1 may be set within a range from about -10 V to about -5 V, and the second discharge voltage VSS2 may be set within a range from about -16 V to about -10 V. In one or more embodiments, the first discharge voltage VSS1 and the second discharge voltage VSS2 may have substantially the same voltage level as each other.

[0099] Figure 5 is a circuit diagram showing a stage according to an embodiment of the present disclosure.

[0100] Figure 5 Level SRC i It is one of the levels according to an embodiment of the present disclosure.

[0101] Reference Figure 5 , Level SRC i The device includes a pre-charging unit 10 , a charging unit 20 , an output unit 30 , a first discharging unit 40 and a second discharging unit 50 .

[0102] The precharge unit 10 may increase the voltage level of the charge node QP in advance. In other words, the precharge unit 10 may receive a carry signal before receiving the clock signal CKV through the first clock terminal CK1. For example, in the case of the i-th stage, the i-1-th carry signal CR may be received through the first input terminal IN1.i-1 .

[0103] The pre-charging unit 10 includes a first transistor TR1 and is connected (e.g., electrically connected) to the first input terminal IN1. The first transistor TR1 includes a control electrode and a first electrode connected to the first input terminal IN1 and a second electrode connected to the charging node QP. The voltage level of the charging node QP may increase in response to a carry signal received through the first input terminal IN1. As a result, a voltage may be charged to the capacitor C.

[0104] The charging unit 20 may charge the voltage of the charging node QP based on the voltage received from the first clock terminal CK1. As the charging unit 20 increases the voltage level of the charging node QP, the gate signal G may be output from the output unit 30. i .

[0105] The charging unit 20 includes a second transistor TR2 and a third transistor TR3. The second transistor TR2 includes a control electrode connected to the charging node QP, a first electrode connected to the first clock terminal CK1, and a second electrode connected to the carry terminal CR. The carry signal CR i The third transistor TR3 includes a control electrode connected to the first clock terminal CK1, a first electrode connected to the charge node QP, and a second electrode connected to the carry terminal CR.

[0106] The second transistor TR2 transmits the clock signal CKV having a high voltage received through the first clock terminal CK1 to the third transistor TR3 in response to the first node voltage of the charging node QP. The third transistor TR3 transmits the clock signal CKV having a high voltage transmitted from the second transistor TR2 to the charging node QP in response to the clock signal CKV having a high voltage. As a result, the first node voltage level of the charging node QP can be increased.

[0107] The output unit 30 may transmit the clock signal CKV having a high voltage to the output node OP in response to the first node voltage level of the charging node QP. The output unit 30 includes a fourth transistor TR4, and the fourth transistor TR4 includes a control electrode connected to the charging node QP, a first electrode connected to the first clock terminal CK1, and a second electrode connected to the output node OP. The output node OP is connected (e.g., electrically connected) to the output terminal OUT.

[0108] According to an embodiment, the first node voltage level of the charging node QP may be boosted by the voltage charged to the capacitor C and the high voltage of the clock signal CKV transmitted through the third transistor TR3. The boosted voltage level of the charging node QP may be transmitted to the control electrode of the fourth transistor TR4. The fourth transistor TR4 transmits the gate signal G corresponding to the high voltage of the clock signal CKV through the output node OP. iOutput to the output terminal OUT.

[0109] Thereafter, when the high voltage of the clock signal CKV is switched to a low voltage, the first and second discharge sections 40 and 50 may discharge the second node voltage level of the output node OP and the first node voltage level of the charging node QP, respectively.

[0110] The first discharge unit 40 includes a fifth transistor TR5. In one or more embodiments, the fifth transistor TR5 may be a discharge transistor. The fifth transistor TR5 includes a control electrode connected to the second clock terminal CK2, a first electrode connected to the output node OP, and a second electrode connected to the first discharge terminal V1. The fifth transistor TR5 may be turned on in response to a high voltage of the clock bar signal CKVB received through the second clock terminal CK2. In another embodiment, the fifth transistor TR5 may be turned on in response to a low voltage of the clock bar signal CKVB received through the second clock terminal CK2. When the fifth transistor TR5 is turned on, the second node voltage level of the output node OP may be reduced to the first discharge voltage VSS1 (i.e., discharged).

[0111] As used herein, the expression "transistor off" means that current does not flow between the first electrode and the second electrode of the transistor according to the control electrode. In addition, the expression "transistor on" means that current flows between the first electrode and the second electrode of the transistor according to the control electrode.

[0112] The second discharge unit 50 includes a sixth transistor TR6 and a seventh transistor TR7. In one or more embodiments, each of the sixth transistor TR6 and the seventh transistor TR7 may be a discharge transistor. The sixth transistor TR6 includes a control electrode connected to the second clock terminal CK2, a first electrode connected to each of the carry terminal CR and the charge node QP (e.g., via the third transistor TR3), and a second electrode connected to the second discharge terminal V2. The sixth transistor TR6 may be turned on in response to a high voltage of the clock bar signal CKVB received through the second clock terminal CK2. When the sixth transistor TR6 is turned on, the voltage level of the carry terminal CR is reduced to the second discharge voltage VSS2. When the clock bar signal CKVB switches from a low voltage to a high voltage, the clock signal CKV switches from a high voltage to a low voltage.

[0113] The seventh transistor TR7 includes a control electrode connected to the second input terminal IN2, a first electrode connected to the charge node QP, and a second electrode connected to the second discharge terminal V2. The seventh transistor TR7 responds to the carry signal CR output from the i+6th stage. i+6 When the seventh transistor TR7 is turned on, the first node voltage level of the charging node QP decreases to the second discharge voltage VSS2.

[0114] As mentioned above, the output gate signal G i Thereafter, the first and second discharge sections 40 and 50 may reduce the voltage level of each of the charge node QP, the output node OP, and the carry terminal CR to the first discharge voltage VSS1 or the second discharge voltage VSS2 .

[0115] like Figure 3 and Figure 4 As shown in FIG. 1 , the first gate signal G1 may be output through the first stage SRC1 in response to the first clock signal CKV1 having a high voltage. The data voltage may be charged to the pixel connected to the first gate line GL1 in response to the first gate signal G1.

[0116] After charging the data voltage to the pixel connected to the first gate line GL1 in response to the first gate signal G1, the first node voltage of the charging node QP may be reduced. In other words, when the i-1th carry signal is switched from a high voltage to a low voltage, the first transistor TR1 of the pre-charging unit 10 is turned off. As a result, as the first node voltage level of the charging node QP gradually decreases, the second transistor TR2 of the charging unit 20 and the fourth transistor TR4 of the output unit 30 are turned off.

[0117] Thereafter, the second gate signal G2 may be output through the second stage SRC2 in response to the second clock signal CKV2. The data voltage may be charged to the pixel connected to the second gate line in response to the second gate signal G2.

[0118] like Figure 4 As shown in , the first section P1 of the first clock signal CKV1 and the second section P2 of the second clock signal CKV2 may overlap each other (e.g., overlap in time). For example, the first gate signal G1 may be output from the first stage SRC1 in response to the high voltage of the first clock signal CKV1, and at the same time, the charging node QP of the second stage SRC2 may be precharged in response to the high voltage of the second clock signal CKV2. When the second transistor TR2 and the fourth transistor TR4 of the first stage SRC1 are turned off, the voltage level of the first gate signal G1 may be reduced. Thereafter, the second gate signal G2 may be output from the second stage SRC2.

[0119] Even when the second gate signal G2 is output from the second stage SRC2, the first clock signal CKV1 maintains a high voltage. As a result, due to the high voltage of the first clock signal CKV1, a coupling between the first electrode of the fourth transistor TR4 and the control electrode of the second transistor TR2 may be generated. In particular, when the display device DD is exposed to a high temperature, the strength of the coupling may be increased, and thus, the first node voltage of the charging node QP may be increased. As a result, the second transistor TR2 and the fourth transistor TR4 may be turned on to re-output the first gate signal G1 from the first stage SRC1 while outputting the second gate signal G2 from the second stage SRC2.

[0120] According to an embodiment of the present disclosure, when the voltage level of the second discharge voltage VSS2 is controlled, the operation of the sixth transistor TR6 included in the second discharge part 50 may be controlled.

[0121] For example, when the display device DD is in the high temperature mode, the first node voltage of the charging node QP may be discharged through the sixth transistor TR6 connected (e.g., electrically connected) to the charging node QP (e.g., via the third transistor TR3). When it is detected that the display device DD is in the high temperature state, the voltage level of the second discharge voltage VSS2 may be controlled to a first voltage level lower than the low voltage of the first clock bar signal CKVB1. The first voltage level of the second discharge voltage VSS2 may be set in a range from about -20V to about -30V.

[0122] In this case, the second voltage level of the low voltage of the first clock bar signal CKVB1 received from the control electrode of the sixth transistor TR6 may be higher than the first voltage level of the second discharge voltage VSS2 received from the second electrode of the sixth transistor TR6. Therefore, the sixth transistor TR6 may be turned on, and the first node voltage of the charge node QP connected (e.g., electrically connected) to the first electrode of the sixth transistor TR6 (e.g., via the third transistor TR3) may be discharged to the second discharge voltage VSS2.

[0123] For example, when the display device DD is in the low temperature mode, the sixth transistor TR6 may maintain a cut-off state. The operation method of the display device DD in the low temperature mode or the high temperature mode will be described in more detail below.

[0124] Figure 6 is a block diagram illustrating a display device according to an embodiment of the present disclosure. Fig. 7A is a circuit diagram illustrating a temperature sensing unit according to an embodiment of the present disclosure. Figure 7B is a block diagram showing a power supply circuit according to an embodiment of the present disclosure. Figure 7C is a timing diagram showing clock signals according to an embodiment of the present disclosure.

[0125] Reference Figure 6 ,Apart from Figure 2 In addition to the signal control circuit 100 and the gate driving circuit 200 shown in FIG. 8 , the display device DD may further include a temperature sensing unit (eg, a temperature sensor or a temperature sensing circuit) 400 and a power supply circuit 500 .

[0126] The temperature sensing unit 400 may detect an external temperature and output a temperature control signal NC based on the detected temperature. Fig. 7A , the temperature sensing unit 400 includes a temperature sensor NTC, a first resistor R1 , a second resistor R2 , and a temperature selection part 410 .

[0127] The first resistor R1 and the second resistor R2 are connected in series (connected in series), and the node ND is located between the first resistor R1 and the second resistor R2. Each of the first resistor R1 and the second resistor R2 may have a fixed value. The temperature sensor NTC may be a resistor and is connected in parallel (connected in parallel) with the first resistor R1 and connected in series (connected in series) with the second resistor R2. The temperature sensor NTC may be a variable resistor. The temperature sensor NTC may have a resistance value that varies according to the external temperature.

[0128] The temperature selection section 410 may output a temperature control signal NC that distinguishes whether the external temperature is in a high temperature mode or a low temperature mode by detecting a voltage level of a node ND, and the voltage level of the node ND varies based on a reference voltage VT1. For example, when the voltage level of the node ND is equal to or greater than the reference level, the temperature selection section 410 outputs a temperature control signal NC according to the high temperature mode. When the voltage level of the node ND is less than the reference level, the temperature selection section 410 outputs a temperature control signal NC indicating a low temperature mode. In one or more embodiments, the reference level may be room temperature.

[0129] Reference Figure 6 , the temperature sensing unit 400 may output the temperature control signal NC to each of the signal control circuit 100 and the power supply circuit 500 .

[0130] The signal control circuit 100 may output a power control signal P-CS to the power supply circuit 500. The signal control circuit 100 may output a power control signal P-CS that alternately repeats the first signal and the second signal to the power supply circuit 500. This will be described later in Fig.9A Described in more detail in .

[0131] The power supply circuit 500 may generate a clock signal CKV, a clock bar signal CKVB, a first discharge voltage VSS1, and a second discharge voltage VSS2 and output the clock signal CKV, the clock bar signal CKVB, the first discharge voltage VSS1, and the second discharge voltage VSS2 to the gate driving circuit 200.

[0132] According to an embodiment of the present disclosure, the power supply circuit 500 receives the power control signal P-CS from the signal control circuit 100 and receives the temperature control signal NC from the temperature sensing unit 400. The power supply circuit 500 may adjust the voltage level of the second discharge voltage VSS2 based on the power control signal P-CS and the temperature control signal NC.

[0133] For more details, refer to Figure 7B , the power supply circuit 500 includes a power generation section 510 , a power control section 520 , and a clock generation section 530 .

[0134] The power generation unit 510 may generate a first discharge voltage VSS1 and a second discharge voltage VSS2. The power generation unit 510 outputs the first discharge voltage VSS1 to the gate driving circuit 200, and outputs the second discharge voltage VSS2 to the power control unit 520. In addition, the power generation unit 510 outputs the gate-on voltage VON to the clock generation unit 530. In one or more embodiments, the power generation unit 510 outputs the gate-off voltage VOFF to the clock generation unit 530.

[0135] The power control unit 520 receives the temperature control signal NC, the power control signal P-CS, and the second discharge voltage VSS2. According to an embodiment of the present disclosure, the power control unit 520 may adjust the voltage level of the second discharge voltage VSS2 in response to the temperature control signal NC and the power control signal P-CS.

[0136] In one or more embodiments, the power control unit 520 may output a second discharge voltage VSS2 having a first voltage level according to the temperature control signal NC in the high temperature mode. The first voltage level of the second discharge voltage VSS2 may be lower than the first discharge voltage VSS1 and the low voltage of the clock bar signal CKVB.

[0137] In one or more embodiments, the power control unit 520 may output a second discharge voltage VSS2 having a second voltage level according to the temperature control signal NC in the low temperature mode. The second voltage level of the second discharge voltage VSS2 may be equal to or substantially equal to the first discharge voltage VSS1 and a low voltage of the clock bar signal CKVB.

[0138] According to an embodiment of the present disclosure, in the high temperature mode, the power control unit 520 may output the second discharge voltage VSS2 in response to the power control signal P-CS. The power control signal P-CS may include a first pulse signal corresponding to the first mode and a second pulse signal corresponding to the second mode, and the first pulse signal and the second pulse signal are repeated alternately.

[0139] For example, the power control part 520 outputs the second discharge voltage VSS2 having the first voltage level in the first mode and outputs the second discharge voltage VSS2 having the second voltage level in the second mode.

[0140] In more detail, Figure 5 The sixth transistor TR6 of the second discharge part 50 in the embodiment may be turned on in response to the second discharge voltage VSS2 having the first voltage level. Therefore, the sixth transistor TR6 may be turned on, and the first node voltage of the charge node QP connected (e.g., electrically connected) to the first electrode of the sixth transistor TR6 may be discharged to the second discharge voltage VSS2.

[0141] When the sixth transistor TR6 is continuously turned on, degradation of the sixth transistor TR6 may occur.

[0142] According to an embodiment of the present disclosure, in the second mode, the sixth transistor TR6 of the second discharge unit 50 is turned off in response to the second discharge voltage VSS2 having the second voltage level. In other words, in the high temperature mode, the power control unit 520 may alternately and repeatedly output the second discharge voltage VSS2 having the first voltage level and the second discharge voltage VSS2 having the second voltage level. In other words, in the high temperature mode, the power control unit 520 may output the second discharge voltage VSS2 such that the second discharge voltage VSS2 alternates between the first voltage level and the second voltage level. Therefore, in the high temperature mode, the sixth transistor TR6 may repeat the on operation and the off operation.

[0143] In addition, in the low temperature mode, the power control unit 520 may continuously output the second discharge voltage VSS2 having the second voltage level according to the temperature control signal NC and the power control signal P-CS. Figure 5 The sixth transistor TR6 of the second discharge part 50 may be turned off.

[0144] The clock generating section 530 receives the gate-on voltage VON and the gate-off voltage VOFF, and generates a clock signal CKV and a clock bar signal CKVB in response to the gate-on voltage VON and the gate-off voltage VOFF. Figure 7C, the horizontal axis represents time TS, and the vertical axis represents voltage level VL. The clock signal CKV includes a high voltage corresponding to the gate-on voltage VON and a low voltage corresponding to the gate-off voltage VOFF. In one or more embodiments, the clock bar signal CKVB includes a high voltage corresponding to the gate-on voltage VON and a low voltage corresponding to the gate-off voltage VOFF. The clock generation unit 530 outputs the clock signal CKV and the clock bar signal CKVB to the gate driving circuit 200.

[0145] According to an embodiment of the present disclosure, the first segment P1 of each clock signal CKV may correspond to the first sub-segment T-VL (eg, Fig.10 ) and a second sub-segment T-VH (e.g., as Fig.10 In more detail, the first sub-section T-VL represents a section in which the sixth transistor TR6 is turned off. In the low temperature mode, the first section P1 of each clock signal CKV may maintain the first sub-section T-VL.

[0146] The second subsection T-VH represents a section in which a first mode in which the sixth transistor TR6 is turned on and a second mode in which the sixth transistor TR6 is turned off are alternately repeated. In the high temperature mode, the first section P1 of each clock signal CKV may maintain the second subsection T-VH.

[0147] Figure 8 is a block diagram showing a power control section according to an embodiment of the present disclosure. Fig.9A The present invention is shown in the embodiment of the present invention. Figure 8 Table of operations in the frame selection section. Fig. 9B The present invention is shown in the embodiment of the present invention. Figure 8 Circuit diagram of the voltage control section.

[0148] Reference Figure 7B and Figure 8 , the power control section 520 includes a frame selection section 521 and a voltage adjustment section 522 .

[0149] The frame selection part 521 receives the temperature control signal NC and the power control signal P-CS. The frame selection part 521 may output a selection signal SC selecting a voltage level of the second discharge voltage VSS2 in response to the temperature control signal NC and the power control signal P-CS.

[0150] For more details, refer to Fig.9A , the power control signal P-CS may include a first signal having 0 bit and a second signal having 1 bit. The signal control circuit 100 may output the power control signal P-CS that alternately repeats the first signal and the second signal to the power supply circuit 500 .

[0151] The temperature control signal NC may include a first temperature signal having a bit of 0 and a second temperature signal having a bit of 1. The first temperature signal may correspond to a low temperature mode, and the second temperature signal may correspond to a high temperature mode.

[0152] The frame selection part 521 may output the selection signal SC having the first level VS1 according to the power control signal P-CS corresponding to the first signal and the temperature control signal NC corresponding to the first temperature signal.

[0153] The frame selection part 521 may output the selection signal SC having the first level VS1 according to the power control signal P-CS corresponding to the second signal and the temperature control signal NC corresponding to the first temperature signal. In one or more embodiments, the frame selection part 521 may output the selection signal SC having the first level VS1 in response to the temperature control signal NC corresponding to the first temperature signal regardless of the power control signal P-CS.

[0154] The frame selection part 521 may output the selection signal SC having the first level VS1 according to the power control signal P-CS corresponding to the first signal and the temperature control signal NC corresponding to the second temperature signal.

[0155] The frame selection part 521 may output the selection signal SC having the second level VS2 according to the power control signal P-CS corresponding to the second signal and the temperature control signal NC corresponding to the second temperature signal.

[0156] Reference Figure 8 , the voltage regulating part 522 may regulate the voltage level of the second discharging voltage VSS2 in response to the selection signal SC.

[0157] For more details, refer to Fig. 9B The voltage regulating part 522 includes a first voltage generator VGP1, a second voltage generator VGP2, a first selection transistor TR11, and a second selection transistor TR12. A selection signal SC is output to each of a control electrode of the first selection transistor TR11 and a control electrode of the second selection transistor TR12.

[0158] According to an embodiment of the present disclosure, one of the first selection transistor TR11 and the second selection transistor TR12 may be turned on and the other may be turned off according to the selection signal SC. In other words, the first selection transistor TR11 and the second selection transistor TR12 may be switched on and off inversely according to the selection signal SC. For example, the first selection transistor TR11 may be a P-MOS transistor, and the second selection transistor TR12 may be an N-MOS transistor. In one or more embodiments, with appropriate changes to the selection signal SC, the first voltage generator VGP1, and / or the second voltage generator VGP2, the first selection transistor TR11 may be an N-MOS transistor, and the second selection transistor TR12 may be a P-MOS transistor.

[0159] The frame selection part 521 outputs the selection signal SC having the first level VS1 according to the first signal of the power control signal P-CS and the first temperature signal of the temperature control signal NC. The feature that the selection signal SC has the first level VS1 indicates that the sixth transistor TR6 is turned off. In other words, when the selection signal SC having the first level VS1 is output, the voltage level of the second discharge voltage VSS2 corresponds to the low voltage of the clock signal CKV or the clock bar signal CKVB corresponding to the gate-off voltage VOFF (for example, Figure 7C ).

[0160] According to the selection signal SC having the first level VS1, the first selection transistor TR11 may be turned on, and the second selection transistor TR12 may be turned off. As a result, the second discharge voltage VSS2 having the second voltage level may be output from the first voltage generator VGP1.

[0161] The frame selection part 521 outputs the selection signal SC having the second level VS2 according to the second signal of the power control signal P-CS and the second temperature signal of the temperature control signal NC. The feature that the selection signal SC has the second level VS2 indicates that the sixth transistor TR6 is turned on. In other words, when the selection signal SC having the second level VS2 is output, the voltage level of the second discharge voltage VSS2 corresponds to a lower voltage (for example, as shown in FIG. 1 ) than the gate-off voltage VOFF of the clock signal CKV or the clock bar signal CKVB. Figure 7C ) a low first voltage level.

[0162] According to the selection signal SC having the second level VS2, the first selection transistor TR11 may be turned off, and the second selection transistor TR12 may be turned on. As a result, the second discharge voltage VSS2 having the first voltage level may be output from the second voltage generator VGP2.

[0163] When the first signal and the second signal are alternately repeated, in the high temperature mode, the power control signal P-CS may be output such that the second discharge voltage VSS2 having the first voltage level and the second discharge voltage VSS2 having the second voltage level are alternately repeated.

[0164] Fig.10 is a timing chart showing the operation of the display device in a high temperature state according to an embodiment of the present disclosure. Fig.11 is a timing chart showing the operation of a display device in a high temperature state according to another embodiment of the present disclosure. Fig. 12A is a circuit diagram of a stage device according to an embodiment of the present disclosure. Fig. 12B is a circuit diagram of a stage device according to an embodiment of the present disclosure.

[0165] Reference Figure 6 , Fig. 9B and Fig.10 , the horizontal axis represents time TS, and the vertical axis represents voltage level VL. As described above, when the temperature control signal NC is the first temperature signal corresponding to the low temperature mode, the first section P1 (eg, Figure 4 ) may correspond to the first sub-section T-VL. The power supply circuit 500 may output a second discharge voltage VSS2 corresponding to the voltage level of the clock bar signal CKVB having a low voltage. As a result, Figure 5 The sixth transistor TR6 in is kept in the off state.

[0166] When the temperature control signal NC is the second temperature signal corresponding to the high temperature mode, the first section P1 having a high voltage of each clock signal CKV may correspond to the second subsection T-VH The second subsection T-VH includes a variable section THa and a fixed section THb.

[0167] In addition, each of the variable section THa and the fixed section THb includes an alternately repeated on section TON and an off section TOFF, which may be controlled in accordance with the first and second signals of the power control signal P-CS.

[0168] The on section TON represents a section in which the second discharge voltage VSS2 having a first voltage level is output from the second voltage generator VGP2, and the first voltage level is less than the low voltage of the clock signal CKV. The off section TOFF represents a section in which the second discharge voltage VSS2 having a second voltage level is output from the second voltage generator VGP2, and the second voltage level corresponds to the low voltage of the clock bar signal CKVB.

[0169] For example, Fig.10As shown in FIG. 1 , in the variable section THa, the second voltage generator VGP2 may output a second discharge voltage VSS2 having a different first voltage level compared to the plurality of conduction sections TON. For example, the first voltage level V-1 of the second discharge voltage according to the first conduction section TON may be greater than the first voltage level V-2 of the second discharge voltage according to the second conduction section TON.

[0170] For example, in the fixed section THb, the second voltage generator VGP2 may be Output in multiple conduction sections TON The second discharge voltage VSS2 has the same first voltage level.

[0171] According to an embodiment of the present disclosure, the on section TON and the off section TOFF (eg, such as Fig.10 The two adjacent sections of the on section TON and the off section TOFF shown in FIG. 1 may have the same or substantially the same time sections in duration. For example, the on section TON has a first time T1, and the off section TOFF has a second time T2. Fig.10 As shown in , the first time T1 and the second time T2 may be identical in duration to each other.

[0172] According to another embodiment of the present disclosure, the on section TON and the off section TOFF (eg, such as Fig.11 The two adjacent sections of the on section TON and the off section TOFF shown in FIG. 3 may have time sections different from each other in duration. For example, the on section TON may be maintained for a longer time than the off section TOFF.

[0173] Reference Fig. 12A , the clock signal CKV may correspond to a first section P1 having a high voltage (eg, Figure 4 ). In the high temperature mode, a coupling CTL may be generated between the first electrode of the fourth transistor TR4 and the control electrode of the second transistor TR2. In this case, the first node voltage level of the charging node QP may increase.

[0174] According to an embodiment of the present disclosure, Fig.10 In the conduction section TON of the sixth transistor TR6, the power supply circuit 500 may output the second discharge voltage VSS2 having the first voltage level to the second discharge terminal V2 in response to the temperature control signal NC corresponding to the second temperature signal. Since the first voltage level of the second discharge voltage VSS2 is set to a voltage level lower than the low voltage of the clock bar signal CKVB received from the control electrode of the sixth transistor TR6, the sixth transistor TR6 may be turned on. Therefore, the first node voltage of the charging node QP charged by the coupling CTL may be discharged to the second discharge voltage VSS2.

[0175] Reference Fig. 12B ,exist Fig.10 In the off section TOFF of the sixth transistor TR6, the power supply circuit 500 may output the second discharge voltage VSS2 having the second voltage level to the second discharge terminal V2. Since the second voltage level of the second discharge voltage VSS2 is substantially the same as the low voltage of the clock bar signal CKVB received from the control electrode of the sixth transistor TR6, the sixth transistor TR6 may be turned off. Therefore, the degradation of the sixth transistor TR6 may be prevented or substantially prevented.

[0176] Fig.13 is a block diagram illustrating a display device according to another embodiment of the present disclosure. Fig.14 is a block diagram showing a power control section according to another embodiment of the present disclosure.

[0177] When with Figure 6 When comparing the display device DD, Fig.13 The display device DD in the embodiment further includes a signal sensing unit (eg, a signal analyzing unit or circuit) 600 and omits the temperature sensing unit 400. The operations of the remaining components are substantially the same as each other, and descriptions thereof will be omitted (ie, not repeated) for convenience.

[0178] Reference Fig.13 , the signal sensing unit 600 may be connected (eg, electrically connected) to Figure 2 The signal sensing unit 600 receives gate signals output through the gate lines GL1 to GLn from the gate driving circuit 200 and analyzes whether each gate signal is output at a normal timing or a set timing.

[0179] According to an embodiment of the present disclosure, the signal sensing unit 600 outputs an analysis control signal VCS to the power supply circuit 500 , and the analysis control signal VCS analyzes whether each gate signal is output at a normal timing or a set timing.

[0180] For example, when the gate signal is output to the k-1th gate line and the gate signal is output to the kth gate line, the signal sensing unit 600 outputs the analysis control signal VCS according to the error mode. In this case, the power supply circuit 500 outputs the second discharge voltage VSS2 having a first voltage level less than the low voltage of the clock bar signal CKVB.

[0181] For example, when the gate signal is normally output to the gate line, the signal sensing unit 600 outputs the analysis control signal VCS according to the normal mode. In this case, the power supply circuit 500 outputs the second discharge voltage VSS2 having a second voltage level corresponding to the low voltage of the clock bar signal CKVB.

[0182] Reference Fig.14The power control section 520a includes a frame selection part 521a and a voltage control part 522a. The frame selection part 521a may output a selection signal SC in response to the analysis control signal VCS and the power control signal P-CS. Fig.10 The first sub-segment T-VL and the second sub-segment T-VH in the power control signal VCS can be determined by analyzing the normal mode and the error mode of the power control signal VCS. Fig.9A The power control signal P-CS in the described operation method is basically the same.

[0183] According to an embodiment of the present disclosure, the operation of the discharge transistor connected to the charging node can be controlled by controlling the voltage level of the discharge voltage. In particular, when the display device detects a high temperature state, the voltage level of the discharge voltage can be controlled to be less than the low voltage of the clock bar signal. As a result, the discharge transistor can be turned on and the node voltage of the charging node can be discharged to the discharge voltage.

[0184] As a result, the overall driving reliability of the display device can be enhanced.

[0185] Although the exemplary embodiments of the present disclosure have been described, it should be understood that the present disclosure should not be limited to these exemplary embodiments, but various changes and modifications can be made by ordinary technicians in the art within the spirit and scope of the present disclosure to be protected. Therefore, the actual protection scope of the present disclosure should be determined by the technical scope of the attached claims and their equivalents.

Claims

1. Gate drive circuit, including: a charging section connected to a charging node and configured to charge a clock signal having a first high voltage to the charging node during a first section; an output section connected to each of the charging node and the output node and configured to charge the first high voltage to the output node in response to a first node voltage of the charging node during the first section and output a second node voltage of the output node to a gate signal; a first discharging section configured to discharge the second node voltage to a first discharging voltage in response to a clock bar signal having a second high voltage during a second section continuous with the first section; as well as a second discharge unit configured to discharge the first node voltage to a second discharge voltage in response to the clock bar signal during the second section, The first section has one of a first subsection and a second subsection, during the first subsection, the second discharge section is turned off, and during the second subsection, the second discharge section alternates between a first mode in which the second discharge section is turned on and a second mode in which the second discharge section is turned off, wherein the clock bar signal has a first low voltage during the first section, and Wherein, in the first mode, a first voltage level of the second discharge voltage is lower than a second voltage level of the first low voltage.

2. The gate drive circuit according to claim 1, wherein: The first voltage level of the second discharge voltage is the same as the second voltage level of the first low voltage during the first sub-section and in the second mode.

3. The gate driving circuit according to claim 1, wherein: The second discharge section is configured to discharge the first node voltage to the second discharge voltage having the first voltage level in the first mode.

4. The gate driving circuit according to claim 1, wherein: The second discharge section includes a first discharge transistor configured to discharge the first node voltage to a second discharge voltage having the first voltage level in response to the first low voltage of the clock bar signal during the second section.

5. The gate driving circuit according to claim 4, wherein: The first discharge section includes a second discharge transistor configured to discharge the second node voltage to the first discharge voltage in response to the first low voltage of the clock bar signal during the second section.

6. The gate driving circuit according to claim 1, wherein: During the second subsection, a voltage level of the second discharge voltage according to the first mode at a first time and a voltage level of the second discharge voltage according to the first mode at a second time are different from each other.

7. The gate driving circuit according to claim 1, wherein: During the second sub-section, a voltage level of the second discharge voltage according to the first mode at a first time and a voltage level of the second discharge voltage according to the first mode at a second time are identical to each other.

8. The gate driving circuit according to claim 1, wherein: The first mode and the second mode have time sections that are identical in duration to each other.

9. Gate drive circuit, including: a charging section connected to a charging node and configured to charge a clock signal having a first high voltage to the charging node during a first section; an output section connected to each of the charging node and the output node and configured to charge the first high voltage to the output node in response to a first node voltage of the charging node during the first section and output a second node voltage of the output node to a gate signal; a first discharging section configured to discharge the second node voltage to a first discharging voltage in response to a clock bar signal having a second high voltage during a second section continuous with the first section; as well as a second discharge unit configured to discharge the first node voltage to a second discharge voltage during the second section; wherein the first section has one of a first subsection and a second subsection, during the first subsection, the second discharge section is turned off, and during the second subsection, the second discharge section alternates between a first mode in which the second discharge section is turned on and a second mode in which the second discharge section is turned off, and in, The first mode and the second mode have time sections that are different in duration from each other, and The time period according to the first mode is longer than the time period according to the second mode.

10. A display device comprising: Display panel; a gate driving circuit, comprising a plurality of stages configured to output a plurality of gate signals to the display panel, the plurality of stages including an i-th stage, wherein i is a natural number; a temperature sensing unit configured to output a temperature control signal based on an external temperature; a signal control circuit configured to output a power control signal; and a power supply circuit configured to output a clock signal, a clock bar signal, a first discharge voltage and a second discharge voltage to the gate drive circuit in response to the power control signal, Wherein, the i-th level among the multiple levels includes: a charging unit configured to charge the clock signal having a first high voltage to a charging node during a first section; an output section connected to the charging section through the charging node and configured to charge the first high voltage to an output node in response to a first node voltage of the charging node, and output a second node voltage of the output node to an i-th gate signal among the plurality of gate signals; a first discharge section connected to the output section through the output node and configured to discharge the second node voltage to the first discharge voltage in response to the clock bar signal having a second high voltage during a second section continuous with the first section; and a second discharging section connected to the charging node and configured to discharge the first node voltage to the second discharging voltage during the second section, wherein the first section has one of a first subsection and a second subsection, during the first subsection, the second discharge section is turned off, and during the second subsection, the second discharge section alternates between a first mode in which the second discharge section is turned on and a second mode in which the second discharge section is turned off, and The first section has one of the first sub-section and the second sub-section in response to the temperature control signal.

11. The display device according to claim 10, wherein: The power supply circuit comprises: a power generation unit configured to output the first discharge voltage and the second discharge voltage; a clock generating unit configured to output the clock signal and the clock bar signal; and The power control unit is configured to receive the second discharge voltage and control a voltage level of the second discharge voltage based on the external temperature.

12. The display device according to claim 11, wherein: The power control unit includes: a frame selection section configured to output a selection signal in response to the temperature control signal and the power control signal; and A voltage regulating section is configured to regulate the voltage level of the second discharge voltage in response to the selection signal.

13. The display device according to claim 12, wherein: The second discharge section is configured to receive a first low voltage of the clock bar signal during the first section, and Wherein, in the first mode, a first voltage level of the second discharge voltage is lower than a second voltage level of the first low voltage.

14. The display device according to claim 12, wherein: The power control signal includes a first pulse signal corresponding to the first mode and a second pulse signal corresponding to the second mode, and the first pulse signal and the second pulse signal are repeated alternately.

15. The display device according to claim 10, in, The temperature control signal includes a first temperature signal and a second temperature signal, in which the first temperature signal the external temperature is less than a reference temperature, and in which the second temperature signal the external temperature is equal to or greater than the reference temperature, and The first section corresponds to the first subsection according to the first temperature signal and corresponds to the second subsection according to the second temperature signal.

16. A display device comprising: Display panel; a gate driving circuit, comprising a plurality of stages configured to output a plurality of gate signals to the display panel, the plurality of stages including an i-th stage, wherein i is a natural number; a signal sensing unit configured to receive the plurality of gate signals output from the gate driving circuit and analyze the plurality of gate signals; a signal control circuit configured to output a power control signal; and a power supply circuit configured to output a clock signal, a clock bar signal, a first discharge voltage and a second discharge voltage to the gate drive circuit in response to the power control signal, Wherein, the i-th level among the multiple levels includes: a charging unit configured to charge the clock signal having a first high voltage to a charging node during a first section; an output section connected to the charging section through the charging node and configured to charge the first high voltage to an output node in response to a first node voltage of the charging node, and output a second node voltage of the output node to an i-th gate signal among the plurality of gate signals; a first discharge section connected to the output section through the output node and configured to discharge the second node voltage to the first discharge voltage in response to the clock bar signal having a second high voltage during a second section continuous with the first section; and a second discharging section connected to the charging node and configured to discharge the first node voltage to the second discharging voltage during the second section, wherein the first section has one of a first subsection and a second subsection, during the first subsection, the second discharge section is turned off, and during the second subsection, the second discharge section alternates between a first mode in which the second discharge section is turned on and a second mode in which the second discharge section is turned off, and The signal sensing unit is configured to transmit an analysis control signal based on an analysis result of each of the plurality of gate signals to the power supply circuit.

17. The display device according to claim 16, wherein: The power supply circuit is configured to control an operation of the second discharge section in response to the analysis control signal.

18. A display device comprising: Display panel; a gate driving circuit comprising a plurality of stages configured to output a plurality of gate signals to the display panel, the plurality of stages including an i-th stage, wherein i is a natural number; and a power supply circuit configured to output a clock signal, a clock bar signal, a first discharge voltage and a second discharge voltage to the gate drive circuit, Wherein, the i-th level of the plurality of levels comprises: a charging unit configured to charge the clock signal having a first high voltage to a charging node; an output section connected to the charging section through the charging node and configured to charge the first high voltage to an output node in response to a first node voltage of the charging node, and output a second node voltage of the output node to an i-th gate signal among the plurality of gate signals; a first discharge section connected to the output section through the output node and configured to discharge the second node voltage to the first discharge voltage in response to the clock bar signal having a second high voltage; and a second discharging section connected to the charging node and configured to discharge the first node voltage to the second discharging voltage in response to the clock bar signal having the second high voltage; wherein the second discharge section is configured to alternate between a first mode in which the second discharge section discharges the first node voltage to the second discharge voltage in response to the clock bar signal and a second mode in which the second discharge section maintains the first node voltage, wherein the first mode and the second mode have time periods that are different from each other in duration, and The time period according to the first mode is longer than the time period according to the second mode.

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