Alignment method for backside lithography process

Abstract

This application provides an alignment method for back-side photolithography on wafers. The method includes: dicing the wafer and using at least two edges formed by the dicing as first alignment marks; bonding the front side of the wafer to a spacer to form a composite wafer; and aligning the first alignment marks with corresponding second alignment marks on a photomask for back-side photolithography. This method is not limited by wafer thickness or material, and reduces the need for secondary investment in photolithography equipment. It also reduces the probability of fragmentation on thin wafers during photolithography, effectively improving product yield.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to an alignment method for back-side photolithography processes. Background Technology

[0002] In the wafer fabrication process, it is often necessary to perform back-side lithography on the wafer, but before performing back-side lithography, it is necessary to align it with the pattern on the front side of the wafer.

[0003] Currently, to achieve precise alignment between the front and back patterns of a wafer, infrared double-sided alignment technology is generally used. This involves placing the patterned front side of the wafer downwards and the opposite back side upwards. An infrared light source is placed at the bottom of the wafer, and an infrared microscope is placed above it. Infrared light can penetrate the wafer, and because the pattern on the front side has different shapes and transmittance, the infrared light can project the pattern onto the back side of the wafer. The projected pattern can then be observed through the infrared microscope. Finally, the positions of the wafer and the photomask are adjusted to achieve alignment between the front and back patterns. However, this technology is only suitable for thinner wafers. When the wafer thickness exceeds a certain value, it is difficult to observe a clear pattern, and some wafer materials cannot transmit infrared light. To address this, a new bottom alignment technology has been adopted to align the patterns on the front and back of the wafer. Specifically, a set of microscopes is placed under the photomask, and the microscopes image the data to a computer system via a camera. In the specific operation, the bottom camera first takes a picture of the pattern on the photomask and records the position information of the pattern on the photomask on the computer. Then, the wafer is moved in with the front side facing down. Similarly, the bottom camera can observe the pattern on the front of the wafer. Then, by adjusting the position of the wafer, the pattern on the front of the wafer is aligned with the pattern on the saved photomask, thus completing the back-side photolithography alignment.

[0004] However, the equipment required for this bottom alignment technology is expensive, and it is prone to breakage during the processing of thin wafers, resulting in a low product yield. Summary of the Invention

[0005] This application provides an alignment method for back-side photolithography, which is not limited by wafer thickness and material, and reduces the secondary investment in photolithography equipment; at the same time, it can reduce the probability of thin wafers breaking during photolithography, effectively improving the product yield.

[0006] To solve the above-mentioned technical problems, one technical solution adopted in this application is: to provide an alignment method for back-side photolithography processes on wafers, the alignment method comprising:

[0007] The wafer is diced, and at least two edges formed by the dicing are used as the first alignment markers;

[0008] The front side of the wafer is bonded to the spacer to form a composite wafer;

[0009] Align the first alignment mark on the composite wafer with the corresponding second alignment mark on the photomask for back-side lithography.

[0010] Specifically, the process of dicing the wafer and using at least two edges formed by the dicing as first alignment marks includes: providing a wafer; setting at least two preset dicing lines on one side surface of the wafer with a pattern; dicing along the preset dicing lines and using at least two edges formed by the dicing as first alignment marks.

[0011] Specifically, at least two preset dicing lines are set on the side surface of the wafer on which the pattern is etched. This includes: obtaining several distance reference values, where the distance reference values ​​are the vertical distance values ​​from the first preset position of the pattern on the photomask to the second alignment mark; starting from the second preset position, determining several dicing points on the wafer based on the several distance reference values, and then connecting the several dicing points to form at least two preset dicing lines; wherein the second preset position is the position on the wafer corresponding to the first preset position of the pattern.

[0012] There are two preset cutting lines; the two preset cutting lines are either continuous straight lines or discontinuous straight lines, and the two preset cutting lines are perpendicular to each other.

[0013] The second alignment mark is set around the graphic on the photomask, and the preset cutting line is set according to the outer edge of the second alignment mark.

[0014] The size of the spacer shall not be smaller than the size of the standard wafer.

[0015] The wafer is made of silicon, germanium, gallium arsenide or indium phosphide; the pad is made of silicon substrate, sapphire substrate or gallium arsenide substrate.

[0016] The thickness of the wafer does not exceed 150 micrometers.

[0017] The wafer is bonded to the spacer using temporary bonding adhesive.

[0018] The process of aligning the first alignment mark on the composite wafer with the corresponding second alignment mark on the photomask for back-side photolithography also includes: detaching the wafer from the pad.

[0019] The alignment method for back-side lithography provided in this application involves dicing the wafer to create at least two edges as first alignment markers; then bonding the front side of the wafer to a spacer to form a composite wafer; finally, aligning the first alignment markers on the composite wafer with corresponding second alignment markers on the photomask for back-side lithography. Since this method uses at least two edges as first alignment markers, in practice, only the first alignment markers need to be aligned with the corresponding second alignment markers on the photomask. Compared to existing methods using infrared double-sided alignment and bottom alignment techniques, this application eliminates the need for infrared light to penetrate the wafer to map the pattern on the front side onto the back side, and also eliminates the need for a camera under the photomask to capture the patterns on the photomask and the front side of the wafer. Therefore, this alignment method is not limited by wafer thickness or material, has a wide range of applications, and effectively reduces the investment in back-side lithography equipment. Furthermore, by bonding the diced wafer to the spacer, the probability of thin wafer fragments during lithography is effectively reduced, significantly improving the product yield. Attached Figure Description

[0020] Figure 1 A schematic flowchart of an alignment method for back-side lithography on a wafer provided in an embodiment of this application;

[0021] Figure 2 for Figure 1 A schematic diagram of the product structure corresponding to step S11;

[0022] Figure 3 for Figure 1 A detailed flowchart of step S10 is shown below;

[0023] Figure 4 A schematic diagram of the front structure of a wafer provided for a specific embodiment of this application;

[0024] Figure 5 A schematic diagram of the front structure of a wafer after it has been cut, provided for a specific embodiment of this application;

[0025] Figure 6 for Figure 5 A schematic diagram of the back structure of the intermediate wafer;

[0026] Figure 7 for Figure 4 A schematic diagram of the structure of the back side of the corresponding wafer after photolithography;

[0027] Figure 8 for Figure 3 A detailed flowchart of step S101 is shown below;

[0028] Figure 9This is a schematic flowchart of an alignment method for back-side photolithography on a wafer, provided as another embodiment of this application. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0030] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0031] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0032] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0033] See also Figures 1 to 2 ,in, Figure 1 A schematic flowchart of an alignment method for back-side lithography on a wafer provided in an embodiment of this application; Figure 2 for Figure 1 A schematic diagram of the product structure corresponding to step S11.

[0034] In this embodiment, an alignment method for back-side lithography on wafers is provided. This alignment method can be operated on a conventional front-side alignment lithography machine, enabling back-side alignment lithography on wafers and reducing the need for secondary investment in lithography equipment. Specifically, the alignment method includes:

[0035] Step S10: Cut the wafer and use at least two edges formed by the cutting as the first alignment mark.

[0036] Optionally, the material of wafer 10 may be silicon; of course, in other embodiments, wafer 10 may also be made of germanium, gallium arsenide or indium phosphide, etc., and this embodiment does not limit this.

[0037] Optionally, the thickness of wafer 10 does not exceed 150 micrometers; of course, in other embodiments, the thickness of wafer 10 may be greater than 150 micrometers, and this embodiment does not limit this.

[0038] It is understood that the alignment method provided in this application uses at least two edges formed by cutting as the first alignment mark. In the specific implementation process, it is only necessary to align the first alignment mark with the corresponding second alignment mark on the photomask. Compared with the prior art methods of alignment by infrared double-sided alignment technology and bottom alignment technology, this application does not require infrared light to penetrate the wafer 10 to map the pattern on the front side of the wafer 10 to the back side of the wafer 10, nor does it require setting a camera under the photomask to collect the pattern on the photomask and the pattern on the front side of the wafer 10. Therefore, the above-mentioned alignment method of this application is not only not limited by the thickness and material of the wafer 10, but also has a wide range of applications and effectively reduces the investment in back-side photolithography equipment.

[0039] Step S11: Bond the front side of the wafer to the spacer to form a composite wafer.

[0040] It should be noted that in this application, the side surface of wafer 10 with the pattern engraved on it is the front side of wafer 10, and the side surface of wafer 10 without the pattern engraved on it, that is, the side surface of wafer 10 to be processed, is the back side of wafer 10.

[0041] Specifically, in step S11, the surface of wafer 10 with the pattern etched on it is bonded to spacer 12 with adhesive to form composite wafer 1. The specific structure of composite wafer 1 can be found in [reference needed]. Figure 2 Specifically, the composite wafer 1 includes a wafer 10, an adhesive layer 11, and a spacer 12.

[0042] Optionally, the pad 12 may be a silicon substrate, a sapphire substrate, or a gallium arsenide substrate.

[0043] Optionally, in one embodiment, the wafer 10 is bonded to the spacer 12 with temporary bonding adhesive, and the size of the spacer 12 is not smaller than the size of the standard wafer. It is understood that fully automated lithography equipment can only recognize industry-standard wafers and cannot recognize non-circular wafer products with parts of their structure cut off. This application, by bonding the cut wafer 10 to a circular spacer 12 of the same size as the standard wafer or a larger spacer 12, compensates for the cut-off portion of the wafer 10. Therefore, the wafer 10 provided in this method not only meets the size requirements of the fully automated equipment for standard wafers, enabling the fully automated equipment to correctly recognize and process the wafer 10, but also effectively reduces the probability of thin wafer fragments during lithography, greatly improving the product yield.

[0044] Step S12: Align the first alignment mark on the composite wafer with the corresponding second alignment mark on the photomask for back-side photolithography.

[0045] Specifically, a photomask is set on a conventional front-side alignment lithography machine, and a pattern is set on the photomask. A second alignment mark is set around the pattern on the photomask so that the first alignment mark is also set around the pattern on the wafer 10, thereby avoiding damage to the pattern on the front side of the wafer 10 during the dicing process.

[0046] Specifically, the second alignment mark can be a multi-edged or edged letter pattern. This embodiment does not limit this, as long as the first alignment mark and the second alignment mark can be aligned.

[0047] The alignment method for back-side photolithography provided in this embodiment involves dicing a wafer 10 to create at least two edges as first alignment markers; then bonding the front side of the wafer 10 to a spacer 12 to form a composite wafer 1; finally aligning the first alignment markers on the composite wafer 1 with corresponding second alignment markers on the photomask for back-side photolithography. Since this method uses at least two edges as first alignment markers, in practice, it is only necessary to align these first alignment markers with the corresponding second alignment markers on the photomask, unlike the prior art which uses red... Compared with the alignment methods of external double-sided alignment and bottom alignment, this application does not require infrared light to penetrate the wafer 10 to map the pattern on the front side of the wafer 10 onto the back side of the wafer 10, nor does it require setting up a camera under the photomask to capture the pattern on the photomask and the pattern on the front side of the wafer 10. Therefore, the alignment method of this application is not only not limited by the thickness and material of the wafer 10, but also has a wider range of applications and effectively reduces the investment in back-side photolithography equipment. In addition, by bonding the diced wafer 10 to the spacer 12, the probability of thin wafer fragments during the photolithography process is effectively reduced, and the product yield is greatly improved.

[0048] See also Figures 3 to 4 ,in, Figure 3 for Figure 1 A detailed flowchart of step S10 is shown below; Figure 4 A schematic diagram of the front structure of a wafer provided for a specific embodiment of this application; Figure 5 A schematic diagram of the front structure of a wafer after it has been cut, provided for a specific embodiment of this application; Figure 6 for Figure 5 A schematic diagram of the back structure of the wafer.

[0049] In this embodiment, unlike the first embodiment described above, step S10 specifically includes:

[0050] Step S100: Provide a wafer.

[0051] Specifically, wafer 10 has a circular structure, and the front side of wafer 10 is engraved with a pattern, while the back side of wafer 10 is not decorated with a pattern.

[0052] Step S101: Set at least two preset dicing lines on the side surface of the wafer on which the pattern is etched.

[0053] Specifically, the front structure of wafer 10 after step S101 can be found in [reference needed]. Figure 4 .

[0054] Optionally, in order to facilitate the dicing of wafer 10 while forming the first alignment mark, in one embodiment, there may be two preset dicing lines, and the two preset dicing lines are perpendicular to each other; specifically, in order to improve the dicing accuracy, the two preset dicing lines may be continuous straight lines; of course, in other embodiments, the two preset dicing lines may also be discontinuous straight lines, or the two dicing lines may not be perpendicular to each other.

[0055] Step S102: Cut along the preset cutting line and use at least two edges formed by the cut as the first alignment mark.

[0056] Specifically, in one embodiment, the structure of the front and back sides of the wafer 10 after step S102 can be found in [reference needed]. Figure 5 and Figure 6 In this embodiment, after alignment using the alignment method provided in this application, photolithography is then performed. The specific structure of the resulting product can be found in [reference needed]. Figure 7 , Figure 7 for Figure 4 A schematic diagram of the structure of the back side of the corresponding wafer after photolithography.

[0057] Optionally, in the specific cutting process, a dicing machine is generally used to first make a cleaving cut along the preset cutting line, and then a splitting machine is used to split it to form at least two edges as the first alignment mark; of course, in other embodiments, a rotating grinding wheel blade can be used to cut directly or a laser can be used to cut, depending on the wafer material to be processed, and this embodiment does not limit this.

[0058] See also Figure 8 ,for Figure 3 A detailed flowchart of step S101 is provided below. In this embodiment, unlike the second embodiment described above, step S101 specifically includes:

[0059] Step S200: Obtain several distance reference values, which are the vertical distance values ​​from the first preset position of the graphic on the photomask to the second alignment mark.

[0060] Specifically, several distance reference values ​​can be the vertical distance from the first preset position of the graphic on the photomask to the second alignment mark in different directions.

[0061] In one embodiment, there may be three distance reference values, which are the vertical distances from three points on the edge of the pattern on the photomask in different directions to the second alignment mark.

[0062] Specifically, in one embodiment, the pattern on the photomask and the second alignment mark can be mapped onto a plane first, and then a distance reference value can be obtained by measuring the vertical distance from the edge of the pattern on the photomask to the second alignment mark on the plane.

[0063] Step S201: Starting from the second preset position, determine several cutting points on the wafer based on several distance reference values, and then connect the several cutting points to form at least two preset cutting lines; wherein, the second preset position is the position on the wafer corresponding to the pattern and the first preset position.

[0064] It should be noted that when selecting the position of the preset cutting line, it is necessary to avoid the pattern area and it is best to set it in the edge area.

[0065] The steps S200 to S201 will be illustrated below with reference to a specific embodiment.

[0066] If positions A, B, and C on the photomask are selected as the first preset positions, then the vertical distances from A, B, and C to the second alignment mark are measured to obtain three distance reference values ​​m, n, and k. Then, positions A', B', and C' on the wafer 10 corresponding to positions A, B, and C are selected as the second preset positions. When A' is the starting point, the cutting point corresponding to A' is determined according to the distance reference value m. When B' is the starting point, the cutting point corresponding to B' is determined according to the distance reference value n. When C' is the starting point, the cutting point corresponding to C' is determined according to the distance reference value k. Then, the three cutting points are connected together by a continuous straight line or a discontinuous straight line to form at least two cutting lines.

[0067] Specifically, the preset cutting line can be set using conventional adhesive coating and developing processes.

[0068] Please see Figure 9 This is a schematic flowchart of an alignment method for a wafer backside photolithography process provided in another embodiment of this application. In this embodiment, unlike the third embodiment described above, after step S12, the method includes:

[0069] Step S13: Remove the wafer from the pad.

[0070] Understandably, in the specific implementation process, the wafer 10 can be separated from the composite wafer 1 according to the needs of the later process; specifically, the composite wafer 1 can be heated to liquefy the adhesive layer 11 and thus separate the wafer 10 from the pad 12.

[0071] It is understood that in other embodiments, the composite wafer can be placed in a dissociation solution to soften the adhesive and thereby dissociate the wafer 10 from the pad 12. In this method, care should be taken to ensure that the dissociation solution does not react with the wafer body and the pad.

[0072] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. An alignment method for back-side photolithography processes on wafers, characterized in that, include: The wafer is diced, and at least two edges formed by the dicing are used as the first alignment markers; The front side of the wafer is bonded to the spacer to form a composite wafer; Align the first alignment mark on the composite wafer with the corresponding second alignment mark on the photomask for back-side photolithography; The process of dicing the wafer and using at least two edges formed by the dicing as the first alignment marker specifically includes: Provide wafers; At least two preset cutting lines are provided on the side surface of the wafer where the pattern is etched; Cut along the preset cutting line, and use at least two edges formed by the cut as the first alignment mark; The provision of at least two preset dicing lines on the surface of the wafer on the side where the pattern is etched specifically includes: Acquire several distance reference values, wherein the distance reference values ​​are the vertical distance values ​​from the first preset position of the graphic on the photomask to the second alignment mark; Starting from a second preset position, several cutting points on the wafer are determined based on several distance reference values, and then the several cutting points are connected to form at least two preset cutting lines; wherein, the second preset position is the position on the wafer corresponding to the pattern and the first preset position.

2. The alignment method for back-side photolithography process of wafers according to claim 1, characterized in that, The preset cutting lines are two; The two preset cutting lines are either continuous straight lines or discontinuous straight lines, and the two preset cutting lines are perpendicular to each other.

3. The alignment method for back-side photolithography process of wafers according to claim 1, characterized in that, The second alignment mark is positioned around the pattern on the photomask, and the preset cutting line is positioned according to the outer edge of the second alignment mark.

4. The alignment method for back-side photolithography process of a wafer according to claim 1, characterized in that, The size of the gasket is not smaller than the size of a standard wafer.

5. The alignment method for back-side photolithography process of a wafer according to claim 1, characterized in that, The wafer is made of silicon, germanium, gallium arsenide, or indium phosphide. The pad is a silicon substrate, a sapphire substrate, or a gallium arsenide substrate.

6. The alignment method for back-side photolithography process of a wafer according to claim 1, characterized in that, The thickness of the wafer does not exceed 150 micrometers.

7. The alignment method for back-side photolithography process of a wafer according to claim 1, characterized in that, The wafer is bonded to the gasket using temporary bonding adhesive.

8. The alignment method for back-side photolithography process of a wafer according to claim 1, characterized in that, After aligning the first alignment mark on the composite wafer with the corresponding second alignment mark on the photomask for back-side photolithography, the process further includes: The wafer is detached from the pad.

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