Reverse body biasing of transistors using photovoltaic source

Abstract

Embodiments of the present disclosure relate to reverse body biasing of a transistor using a photovoltaic source. A metal-oxide-semiconductor (MOS) transistor has a source terminal, a drain terminal, a gate terminal, and a body terminal. The source terminal is connected to receive a supply voltage, and the body terminal is connected to receive a reverse body bias voltage. A photovoltaic circuit has a first terminal connected to the source terminal of the MOS transistor and a second terminal connected to the body terminal of the MOS transistor. The photovoltaic circuit converts photons received from the environment to generate the reverse body bias voltage.

Description

Technical Field

[0001] This invention relates to the body bias of transistors in digital circuits, and more particularly to the implementation of reverse body bias of transistors in digital circuits, wherein the reverse body bias voltage is generated using an energy harvesting source (such as a photovoltaic circuit). Background Technology

[0002] It is well known in the art that body bias is applied to the well (body) region of a metal-oxide-semiconductor field-effect transistor (MOSFET) to influence the characteristics of the transistor channel. For example, a forward body bias (FBB) applied to the well effectively affects device operation by lowering the transistor's threshold voltage (Vt). This results in faster device operation due to the increased channel current at the expense of increased leakage current. Conversely, a reverse body bias (RBB) applied to the well effectively affects device operation by increasing the transistor's threshold voltage (Vt). This results in lower leakage current at the expense of reduced speed. Therefore, it is clear that circuit designers can use body bias selection to modulate the transistor's threshold voltage, thereby achieving a tradeoff between power and speed in circuit operation.

[0003] There is a growing interest in circuits that operate at ultra-low voltage levels. For example, voltage levels equal to or less than 0.5V for digital circuits are now common in many applications, such as devices for the Internet of Things (IoT). For digital circuits, operation in pause modes (such as sleep or deep sleep) is common, and when in this mode, reducing the leakage current of transistors in the digital circuit is important.

[0004] To address this issue, circuit designers can choose to use a reverse body bias (RBB) applied to the transistor well (body). In these schemes, the body of the p-channel transistor (pMOS) is connected to a voltage source that generates a voltage (e.g., Vdds) greater than (i.e., corrected) the supply voltage (e.g., Vdd) at the transistor power supply, and the body of the n-channel transistor (nMOS) is connected to a voltage source that generates a voltage (e.g., Gnds) less than (i.e., more negative) the supply voltage (e.g., Gnd) at the transistor power supply.

[0005] As in Figure 1As shown, an example of a CMOS digital logic inverter gate 10 of a digital circuit device using a pMOS transistor 12 and an nMOS transistor 14 with series coupling, an n-well bias generator circuit 16 is used to generate a reverse body bias voltage Vdds to be applied to the well of the pMOS transistor 12, the source of the pMOS transistor 12 is connected to a power supply voltage Vdd (where Vdds > Vdd), and a p-well bias generator circuit 18 is used to generate a reverse body bias voltage Gnds to be applied to the well of the nMOS transistor 14, the source of the nMOS transistor 14 is connected to a ground voltage Gnd (where Gnds < Gnd). The n-well bias generator circuit 16 is typically a positive charge pump circuit, and the p-well bias generator circuit 18 is typically a negative charge pump circuit. A problem with this implementation is that the charge pump circuits of the bias generator circuits 16 and 18 consume a certain amount of power overhead from the power supply voltage Vdd.

[0006] There is a need in the art to address the drawbacks of the prior art reverse body bias schemes. Summary of the Invention

[0007] In an embodiment, a circuit includes: a metal-oxide-semiconductor (MOS) transistor having a source terminal, a drain terminal, a gate terminal, and a body terminal; wherein the source terminal is connected to receive a power supply voltage; and a photovoltaic circuit having a first terminal connected to the source terminal of the MOS transistor and a second terminal connected to the body terminal of the MOS transistor, wherein the photovoltaic circuit converts received photons to generate a reverse body bias voltage applied to the body terminal of the MOS transistor.

[0008] In an embodiment, a circuit includes: a metal-oxide-semiconductor (MOS) transistor having a source terminal, a drain terminal, a gate terminal, and a body terminal; wherein the source terminal is connected to receive a power supply voltage; and an energy harvesting circuit having a first terminal connected to the source terminal of the MOS transistor and a second terminal connected to the body terminal of the MOS transistor, wherein the energy harvesting circuit harvests energy to generate a reverse body bias voltage applied to the body terminal of the MOS transistor. Brief Description of the Drawings

[0009] To better understand the embodiments, reference will now be made only by way of example to the accompanying drawings, in which:

[0010] Figure 1 is a block diagram of a digital circuit with reverse body bias of a transistor well using a charge pump circuit;

[0011] Figure 2 is a block diagram of a digital circuit with reverse body bias of a transistor well using a photovoltaic circuit;

[0012] Figure 3 It is a block diagram of an integrated circuit device;

[0013] Figure 4 This is a block diagram of an imaging integrated circuit device;

[0014] Figure 5 The general layout of the imaging circuitry within an imaging integrated circuit device is shown;

[0015] Figure 6 This is a cross-sectional view of a pixel photovoltaic cell in a photovoltaic circuit that generates a reverse body bias voltage.

[0016] Figure 7 This is a cross-sectional view of an nMOS transistor and a pMOS transistor in a digital circuit, where the transistor body is reverse biased.

[0017] Figures 8A to 8B The circuit implementation for photovoltaic circuits is shown; and

[0018] Figure 9 It is a block diagram of a digital circuit with a reverse body bias using a transistor well employing an energy harvesting circuit. Detailed Implementation

[0019] Now for reference Figure 2 This diagram illustrates a block diagram of a digital circuit with a transistor well and an inverted body bias (RBB). The digital circuit is powered by a power supply circuit 20 configured to provide a power domain with a positive supply voltage Vdd and a ground voltage Gnd. In ultra-low voltage circuit applications, Vdd can be equal to 0.5V. Here, the digital circuit is represented in a simplified form by a single CMOS digital logic inverter gate 10, which includes a pMOS transistor 12 and an nMOS transistor 14 coupled in series with each other. The source terminal of the pMOS transistor 12 is coupled to a power node 22 receiving the positive supply voltage Vdd. The source terminal of the nMOS transistor 14 is coupled to a power node 24 receiving the ground voltage Gnd. The gate terminals of the pMOS transistor 12 and the nMOS transistor 14 are commonly coupled to a signal input node 26. The drain terminals of the pMOS transistor 12 and the nMOS transistor 14 are commonly coupled to a signal output node 28.

[0020] The n-well bias generator circuit 16' is used to generate a reverse body bias voltage Vdds (where Vdds > Vdd) to be applied to the wells of the pMOS transistors 12. The n-well bias generator circuit 16' is formed by at least one photovoltaic cell PVpos (such as a diode operating in a photovoltaic mode) to generate a voltage from the received photons 30 from the environment. The diode of the photovoltaic cell PVpos has a cathode and an anode, the cathode of which is coupled to a power supply node 22 receiving a positive power supply voltage Vdd, and the anode of which is coupled to a more positive power supply node 32 generating the reverse body bias voltage Vdds. The reverse body bias voltage Vdds is applied to the wells of the (one or more) pMOS transistors 12. The p-well bias generator circuit 18' is used to generate a reverse body bias voltage Gnds (where Gnds < Gnd) to be applied to the wells of the nMOS transistors 14. The p-well bias generator circuit 18' is formed by at least one photovoltaic cell PVneg (such as a diode operating in a photovoltaic mode) to generate a voltage from the received photons 30 from the environment. The diode for the photovoltaic cell PVneg has an anode and a cathode, the anode of which is coupled to a power supply node 24 receiving a ground power supply voltage Gnd, and the cathode of which is coupled to a more negative power supply node 34 generating the reverse body bias voltage Gnds. The reverse body bias voltage Gnds is applied to the wells of the (one or more) nMOS transistors 14.

[0021] Now refer to Figure 3, which shows a block diagram of an integrated circuit device 40. The integrated circuit device 40 includes digital logic circuitry 42, which is powered by a power domain having a positive supply voltage Vdd and a ground voltage Gnd. The digital logic circuitry 42 includes CMOS digital circuits such as digital logic gates (logic AND, OR, NAND, NOR, etc.) and other digital signal handling and processing circuits (such as flip - flops, latches, multiplexers, processors, controllers, etc.). These digital circuits are formed by interconnected pMOS transistors 44 and nMOS transistors 46. Each pMOS transistor 44 includes a source terminal, a drain terminal, a gate terminal, and a body (well) terminal. Each nMOS transistor 46 includes a source terminal, a drain terminal, a gate terminal, and a body (well) terminal. The integrated circuit device 40 also includes a photovoltaic (PV) circuitry 50 having a positive PV (PVpos) circuit 52, the positive PV (PVpos) circuit 52 generating a reverse body bias voltage Vdds (where Vdds > Vdd) in response to received photons 30 for application to the (one or more) wells of the (one or more) pMOS transistors 44 within the digital logic circuitry 42. The photovoltaic (PV) circuitry 50 also includes a negative PV (PVneg) circuit 54, the negative PV (PVneg) circuit 54 generating a reverse body bias voltage Gnds (where Gnds < Gnd) in response to received photons 30 for application to the (one or more) wells of the (one or more) nMOS transistors 46 within the digital logic circuitry 42.

[0022] The positive PV circuit 52 may include one photovoltaic cell PVpos (see Figure 2 , label 16’) or multiple photovoltaic cells PVpos interconnected with each other between a power node receiving the positive supply voltage Vdd and a more positive power node generating the reverse body bias voltage Vdds (see Figures 8A to 8B ).

[0023] The negative PV circuit 54 may include one photovoltaic cell PVneg (see Figure 2 , label 18’) or multiple photovoltaic cells PVneg interconnected with each other between a power node receiving the ground voltage Gnd and a more negative power node generating the reverse body bias voltage Gnds (see Figures 8A to 8B ).

[0024] The power domain having the positive supply voltage Vdd and the ground voltage Gnd may be provided “off - chip” by a power supply external to the integrated circuit device 40 or “on - chip” by a power supply within the integrated circuit device 40 (such as a voltage regulator circuit receiving power from an off - chip power supply).

[0025] Now refer to Figure 4, which shows a block diagram of an imaging integrated circuit device 70. The integrated circuit device 70 includes a digital logic circuit device 42 and an imaging circuit 80 powered by a power supply domain having a positive power supply voltage Vdd and a ground voltage Gnd. The imaging circuit 80 includes an array 82 of photodetectors (such as photodiodes) for receiving photons 30. A sensing and conversion circuit 84 senses signals generated by the photodetectors in the array 82 and performs a conversion to generate a digital image signal 86 for processing by the digital logic circuit device 42. The digital logic circuit device 42 includes CMOS digital circuits such as digital logic gates (logical AND, OR, NAND, NOR, etc.) and other digital signal handling and processing circuits (such as flip-flops, latches, multiplexers, processors, controllers, etc.). These digital circuits are formed by interconnected pMOS transistors 44 and nMOS transistors 46. Each pMOS transistor 44 includes a source terminal, a drain terminal, a gate terminal, and a body (well) terminal. Each nMOS transistor 46 includes a source terminal, a drain terminal, a gate terminal, and a body (well) terminal.

[0026] The imaging circuit 80 further includes a photovoltaic (PV) circuit device, and the photovoltaic (PV) circuit device includes a positive PV (PVpos unit) circuit 52 that generates a reverse body bias voltage Vdds (where Vdds > Vdd) in response to the received photons 30 for application to the (one or more) wells of the (one or more) pMOS transistors 44 within the digital logic circuit device 42. The photovoltaic (PV) circuit device further includes a negative PV (PVneg unit) circuit 54 that generates a reverse body bias voltage Gnds (where Gnds < Gnd) in response to the received photons 30 for application to the (one or more) wells of the (one or more) nMOS transistors 44 within the digital logic circuit device 42.

[0027] Figure 5 Shows a general layout of the photosensitive portion 90 of the imaging circuit 80. The photosensitive portion 90 is formed by an array of pixels, where each pixel includes a diode structure. The first pixel of the array of pixels is arranged in a sub-array 92 to form the array 82 of photodetectors. The second pixel of the array of pixels is arranged in a ring 94 that provides an area surrounding the array of the first pixels. A first portion 96 of the second pixel provides one or more photovoltaic cells PVpos of the positive PV circuit 52 that generate a reverse body bias voltage Vdds > Vdd. A second portion 98 of the second pixel provides one or more photovoltaic cells PVneg of the negative PV circuit 54 that generate a reverse body bias voltage Gnds < Gnd.

[0028] Now refer to Figure 6It shows an example cross-section of the photosensitive portion 90, where the cross-section is in Figure 5 In the annular region 94, indicated by the dashed line 100, the photosensitive portion 90 is formed in a lightly p-type doped semiconductor substrate 102. In the annular region 94, a deep trench separator 101 is formed in the semiconductor substrate 102, substantially surrounding a subarray 92 providing the photodetector array 82. Each pixel in the second pixel is formed within a p-type doped well 104, which is separated from other pixels and the substrate 100 by the deep trench separator 101. The p-type doped well 104 forms the anode of the photovoltaic cell PV. Electrical contact is made with the p-type doped well 104 through a more heavily p-type doped contact region 106. An n-type doped region 108 is embedded in the p-type doped well 104 to form the cathode of the photovoltaic cell PV.

[0029] For the second pixel in the first portion 96 of the annular region 94, which is part of the positive PV circuit 52, the n-type doped region 108 of the cathode of the photovoltaic cell PVpos is electrically connected to the positive power supply voltage Vdd, and the p-type doped contact region 106 of the anode of the photovoltaic cell PVpos is electrically connected to provide a reverse body bias voltage Vdds to the well (body) of the pMOS transistor.

[0030] For the second pixel in the second portion 98 of the annular region 94, which is part of the negative PV circuit 54, the p-type doped contact region 106 of the anode of the photovoltaic cell PVneg is electrically connected to the ground voltage Gnd, and the n-type doped region 108 of the cathode of the photovoltaic cell PVneg is electrically connected to provide a reverse body bias voltage Gnds to the well (body) of the nMOS transistor.

[0031] The nMOS transistors and pMOS transistors of the digital logic circuit device 42 can be as follows: Figure 7The cross-section shown illustrates a p-type doped substrate 100 supported using a well-known triple-well process. A pMOS transistor 44 is formed within an n-well 126 supported within the substrate 100. The n-well 126 provides the body of the pMOS transistor 44, which is a reverse body biased by a positive PV circuit 52 having a reverse body bias voltage Vdds. A further n-type doped contact region 146 is provided in the n-well 126 for applying the reverse body bias voltage Vdds to the body of the pMOS transistor 44. The pMOS transistor 44 includes p-type conductive source and drain regions 142 provided in the n-well 126. The source and drain regions 142 are separated by a channel region (of the well 126), and an insulated gate 144 is provided on this channel region. An nMOS transistor 46 is formed within a p-well 122 supported within the n-well 126. The p-well 122 is laterally separated from the n-well 126 using a shallow trench separator 128. The p-well 122 provides the body of the nMOS transistor 46, which is a reverse body biased by a negative PV circuit 54 having a reverse body bias voltage Gnds. A p-type, more p-doped contact region 136 is provided in the p-well 122 for applying the reverse body bias voltage Gnds to the body of the nMOS transistor 46. The nMOS transistor 46 includes n-type conductive source and drain regions 132 provided in the p-well 122. The source and drain regions 132 are separated by a channel region (of the well 122), and an insulated gate 134 is provided on this channel region.

[0032] like Figure 8A As shown, each PV circuit 52, 54 can be formed by multiple photovoltaic units PV1 to PV2 connected in parallel. Alternatively, as... Figure 8B As shown, each PV circuit 52, 54 can be formed by multiple photovoltaic units PV1 to PVz connected in series. Furthermore, each PV circuit 52, 54 can be formed by multiple photovoltaic units PV1 to PVz electrically connected in a circuit network that includes both parallel and series connections of diodes. The selection of the electrical interconnections for the multiple photovoltaic units PV1 to PVz is made by the circuit designer based on the desired amplitude of the voltage and current driven by the reverse body bias of the transistors used in the digital circuit, which needs to be generated by the PV circuits 52, 54.

[0033] It should be understood that the voltage and current drive depend on the illumination provided by the received photons 30. In this context, the illumination is ambient illumination, e.g., for the scene imaged by the imaging circuit 80 or the environment in which the PV circuit device 50 is exposed. Changes in the ambient light level will change the magnitudes of both the voltage and current generated by the PV circuit device 50. The generated voltage will increase proportionally to the logarithm of the light level, and the generated voltage is considered suitable for providing the RBB voltage at all light levels. The achieved leakage current reduction and power savings will vary with the light level, but the leakage current reduction and power savings will be present at all light levels.

[0034] Although the embodiments discussed above consider using a photovoltaic circuit to generate a reverse body bias voltage, it should be noted that other forms of harvesting energy from the environment can alternatively be used in appropriate situations. For example, in an operating scenario where the integrated circuit is not exposed to ambient light, a photovoltaic solution is inoperable. However, if other energy sources are available in that operating scenario, then different forms of energy harvesting can alternatively be used. Energy sources such as thermal energy or vibrational energy can be harvested by appropriate energy harvesting (EH) circuits known to those skilled in the art to generate the required reverse body bias voltage. Such an implementation is shown in Figure 9 which the same reference numerals indicate Figure 3 the same components as shown in and previously described herein.

[0035] The integrated circuit 40’ includes an energy harvesting (EH) circuit device 50’ having a positive EH circuit 52’ that generates a reverse body bias voltage Vdds (where Vdds > Vdd) in response to the received energy 30’ (such as thermal energy or vibrational energy) for application to the wells of the pMOS transistors 44 within the digital logic circuit device 42. The energy harvesting (EH) circuit device 50’ further includes a negative EH circuit 54’ that generates a reverse body bias voltage Gnds (where Gnds < Gnd) in response to the received energy 30’ for application to the wells of the nMOS transistors 46 within the digital logic circuit device 42. It should be noted that the EH circuit device 50’ can be formed by a combination of harvesting circuits. For example, photovoltaic harvesting can be combined with one or more of a thermal harvesting circuit or a vibration harvesting circuit. The advantage of photovoltaic harvesting is that the required circuitry is compatible with standard CMOS technology and can be supported on a common die.

[0036] Although the invention has been described and illustrated in detail in the accompanying drawings and the foregoing description, such description and illustration are to be considered illustrative or exemplary rather than restrictive; the invention is not limited to the disclosed embodiments. Other variations of the disclosed embodiments can be understood and practiced by those skilled in the art through study of the drawings, this disclosure and the appended claims in the practice of the invention.

Claims

1. A circuit comprising: a metal oxide semiconductor (MOS) transistor having a source terminal, a drain terminal, a gate terminal, and a body terminal; wherein the source terminal is connected to receive a supply voltage; a photovoltaic circuit having a first terminal connected to the source terminal of the MOS transistor and a second terminal connected to the body terminal of the MOS transistor, wherein the photovoltaic circuit converts received photons to generate a reverse body bias voltage applied to the body terminal of the MOS transistor; and an imaging circuit comprising an array of pixels, wherein a first pixel of the array forms an array of photodetectors, and wherein a second pixel of the array forms the photovoltaic circuit.

2. The circuit of claim 1, wherein the MOS transistor is a p-channel MOS transistor, the supply voltage is a positive voltage Vdd, and the reverse body bias voltage is a more positive voltage Vdds > Vdd.

3. The circuit of claim 2, wherein the p-channel MOS transistor is a circuit component of a digital logic gate.

4. The circuit of claim 1, wherein the MOS transistor is an n-channel MOS transistor, the supply voltage is a ground voltage Gnd, and the reverse body bias voltage is a more negative voltage Gnds < Gnd.

5. The circuit of claim 4, wherein the n-channel MOS transistor is a circuit component of a digital logic gate.

6. The circuit of claim 1, wherein the photovoltaic circuit comprises a photovoltaic diode, wherein the first terminal is a cathode of the photovoltaic diode and the second terminal is an anode of the photovoltaic diode.

7. The circuit of claim 1, wherein the photovoltaic circuit comprises a photovoltaic diode, wherein the first terminal is an anode of the photovoltaic diode and the second terminal is a cathode of the photovoltaic diode.

8. The circuit of claim 1, wherein the photovoltaic circuit comprises a plurality of photovoltaic diodes electrically connected in a circuit network, wherein the first terminal is a cathode of at least one photovoltaic diode of the plurality of photovoltaic diodes and the second terminal is an anode of the at least one photovoltaic diode.

9. The circuit of claim 8, wherein the circuit network is a parallel electrical connection of the plurality of photovoltaic diodes.

10. The circuit of claim 8, wherein the circuit network is a series electrical connection of the plurality of photovoltaic diodes.

11. The circuit of claim 1, wherein the photovoltaic circuit comprises a plurality of photovoltaic diodes electrically connected in a circuit network, wherein the first terminal is an anode of at least one photovoltaic diode of the plurality of photovoltaic diodes and the second terminal is a cathode of the at least one photovoltaic diode.

12. The circuit of claim 11, wherein the circuit network is a parallel electrical connection of the plurality of photovoltaic diodes.

13. The circuit of claim 11, wherein the circuit network is a series electrical connection of the plurality of photovoltaic diodes. ​ 14. The circuit of claim 1, wherein the second pixels are arranged in an annular region, the annular region surrounding the first pixels forming the array of photodetectors.

15. The circuit of claim 1, wherein each second pixel is formed by a photovoltaic diode, wherein the first terminal is a cathode of the photovoltaic diode and the second terminal is an anode of the photovoltaic diode.

16. The circuit of claim 1, wherein each second pixel is formed by a photovoltaic diode, wherein the first terminal is an anode of the photovoltaic diode and the second terminal is a cathode of the photovoltaic diode.

17. The circuit of claim 1, implemented as an integrated circuit.

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