Luminous display panel

Abstract

A light-emitting display panel includes a plurality of pixels. Each of the plurality of pixels includes: a first pixel circuit layer, which includes a first pixel circuit constituting a pixel driving circuit; a second pixel circuit layer, which is arranged on the first pixel circuit layer, the second pixel circuit layer includes a second pixel circuit constituting the pixel driving circuit; a third pixel circuit layer, which is arranged on the second pixel circuit layer, the third pixel circuit layer includes a third pixel circuit constituting the pixel driving circuit; a fourth pixel circuit layer, which is arranged on the third pixel circuit layer, the fourth pixel circuit layer includes a fourth pixel circuit constituting the pixel driving circuit; and a light-emitting device layer, which is arranged on the fourth pixel circuit layer, the light-emitting device layer includes a light-emitting device electrically connected to the fourth pixel circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0144210, filed on November 12, 2019, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a light-emitting display panel. Background Art

[0004] Since the light-emitting display apparatus displays an image by using a self-luminous device, the light-emitting display apparatus has a fast response time, low power consumption, and a good viewing angle, and thus has received more attention as a next-generation apparatus.

[0005] Each of the plurality of pixels constituting the light-emitting display panel of the light-emitting display device includes a pixel driving circuit. The pixel driving circuit controls the level of current flowing from the driving power supply to the light-emitting device based on the switching of the driving transistor based on the data voltage, thereby allowing the light-emitting device to emit light. Therefore, the light-emitting display device displays a specific image.

[0006] In a light-emitting display panel, the current flowing in the light-emitting device of each pixel may vary based on the deviation of the threshold voltage of the driving transistor caused by the process deviation. Therefore, even when the same data voltage is supplied to the pixel driving circuit of the light-emitting display panel, the current output from the driving transistor may vary for each pixel, and due to this, uniform image quality may not be achieved. Therefore, an internal compensation circuit for compensating the threshold voltage of the driving transistor is included in each pixel driving circuit.

[0007] Recently, the resolution of a light-emitting display panel applied to a mobile electronic device, a virtual image display device, or a head-mounted display device has gradually increased. As the resolution of the light-emitting display panel gradually increases, the size of each pixel gradually decreases. Therefore, it is difficult to form (or place) a pixel driving circuit including an internal compensation circuit in a pixel, and due to this, it is difficult to manufacture a high-resolution light-emitting display panel. Summary of the invention

[0008] Accordingly, the present disclosure is directed to a light emitting display panel that substantially obviates one or more problems due to limitations and disadvantages of the related art.

[0009] An aspect of the present disclosure is directed to providing a light-emitting display panel in which a plurality of transistors constituting a pixel driving circuit are separately disposed in different layers.

[0010] Additional advantages and features of the present disclosure will be partially described in the following description and will become apparent to those of ordinary skill in the art after reading the following, or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained through the structures particularly pointed out in the written description and claims and the accompanying drawings.

[0011] To achieve these and other technical advantages and in accordance with the purposes of the present disclosure, as specifically embodied and broadly described herein, a light-emitting display panel including a plurality of pixels is provided, wherein each of the plurality of pixels includes: a first pixel circuit layer including a first pixel circuit constituting a pixel driving circuit; a second pixel circuit layer disposed on the first pixel circuit layer, the second pixel circuit layer including a second pixel circuit constituting the pixel driving circuit; a third pixel circuit layer disposed on the second pixel circuit layer, the third pixel circuit layer including a third pixel circuit constituting the pixel driving circuit; a fourth pixel circuit layer disposed on the third pixel circuit layer, the fourth pixel circuit layer including a fourth pixel circuit constituting the pixel driving circuit; and a light-emitting device layer disposed on the fourth pixel circuit layer, the light-emitting device layer including a light-emitting device electrically connected to the fourth pixel circuit. A driving transistor for controlling the amount of current flowing to the light-emitting device is included in the first pixel circuit layer, and a capacitor for storing a threshold voltage of the driving transistor is included in the third pixel circuit layer.

[0012] It is to be understood that both the foregoing summary and the following detailed description of the present disclosure are illustrative and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application. The accompanying drawings illustrate embodiments of the present disclosure and together with the description are used to explain the principles of the present disclosure. In the drawings:

[0014] Figure 1 is a diagram schematically showing a light-emitting display device to which a light-emitting display panel according to an embodiment of the present disclosure is applied;

[0015] Figure 2 is a circuit diagram of an embodiment of a pixel applied to a light-emitting display panel according to the present disclosure;

[0016] Figure 3 It is shown Figure 2 A cross-sectional view of the layer structure of the pixel shown;

[0017] Figure 4 It is shown Figure 3 A diagram of the circuit configuration of each layer shown;

[0018] Figure 5is a cross-sectional view showing an example in which a first pixel circuit layer, a second pixel circuit layer, a third pixel circuit layer, and a fourth pixel circuit layer applied to the present disclosure are coupled to each other;

[0019] Figure 6 It is shown Figure 2 A diagram of a first pixel circuit shown;

[0020] Figure 7 It is shown that Figure 6 A diagram of a layout of a first pixel circuit layer of a first pixel circuit shown;

[0021] Figure 8 is along Figure 7 A cross-sectional view taken along line AA' shown;

[0022] Fig. 9 It is shown Figure 2 A diagram of a second pixel circuit shown;

[0023] Fig.10 It is shown that Fig. 9 A diagram of a layout of a second pixel circuit layer of a second pixel circuit shown;

[0024] Fig.11 is along Fig.10 A cross-sectional view taken along line BB' shown;

[0025] Fig.12 It is shown Figure 2 A diagram of a third pixel circuit shown;

[0026] Fig.13 It is shown that Fig.12 A diagram of a layout of a third pixel circuit layer of the third pixel circuit shown;

[0027] Fig.14 is along Fig.13 A cross-sectional view taken along line CC' shown;

[0028] Fig.15 It is shown Figure 2 A diagram of a fourth pixel circuit shown;

[0029] Fig.16 It is shown that Fig.15 A diagram of a layout of a fourth pixel circuit layer of a fourth pixel circuit shown; and

[0030] Fig.17 is along Fig.16 A cross-sectional view taken along line DD' is shown. DETAILED DESCRIPTION

[0031] Reference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Throughout the drawings, the same reference numerals will be used wherever possible to refer to the same or like parts.

[0032] The advantages and features of the present disclosure and its implementation methods will be clarified by the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0033] The shapes, sizes, ratios, angles and quantities disclosed in the accompanying drawings for describing the embodiments of the present disclosure are merely examples, and therefore, the present disclosure is not limited to the details shown. Throughout the text, similar reference numerals refer to similar elements. In the following description, when it is determined that the detailed description of the relevant known functions or structures makes it unnecessary to understand the main points of the present disclosure, the detailed description will be omitted. In the case of using "including", "having" and "comprising" described in this specification, another part may be added unless "only" is used. Unless otherwise indicated, terms in the singular may include plural forms.

[0034] In interpreting an element, although there is no explicit description, the element is interpreted as including an error range.

[0035] When describing a positional relationship, for example, when the positional relationship between two parts is described as "on," "over," "under," and "beside," one or more other parts may be disposed between the two parts unless "only" or "directly" is used.

[0036] When describing a time relationship, for example, when a time sequence is described as "after," "afterwards," "next," and "before," discontinuous cases may be included unless "only" or "directly" is used.

[0037] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.

[0038] When describing the elements of the present disclosure, terms such as first, second, A, B, (a), (b), etc. may be used. Such terms are only used to distinguish the corresponding elements from other elements, and the corresponding elements are not limited by these terms in terms of their essence, order or priority. It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it may be directly on or directly connected to another element or layer, or there may be an intermediate element or layer. Moreover, it should be understood that when an element is arranged on or under another element, this may represent a situation in which the elements are arranged to be in direct contact with each other, but may also represent that the elements are arranged not to be in direct contact with each other.

[0039] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed elements. For example, the meaning of "at least one of a first element, a second element, and a third element" represents the combination of all elements proposed from two or more of the first element, the second element, and the third element, as well as the first element, the second element, or the third element.

[0040] Those skilled in the art can fully understand that the features of the various embodiments of the present disclosure can be coupled or combined with each other in part or in whole, and can interoperate with each other in various ways and be driven technically. The embodiments of the present disclosure can be performed independently of each other, or can be performed together in a mutually dependent relationship.

[0041] Figure 1 is a diagram schematically showing a light-emitting display device to which a light-emitting display panel according to an embodiment of the present disclosure is applied.

[0042] like Figure 1 As shown, a light-emitting display device to which the light-emitting display panel according to an embodiment of the present disclosure is applied may include a light-emitting display panel 100 , a gate driver 200 , a data driver 300 , and a timing controller 400 .

[0043] The light emitting display panel 100 may include a substrate, a display area AA defined on the substrate, and a non-display area IA adjacent to the display area AA.

[0044] The substrate may be a base substrate (or base layer) and may include a plastic or glass material. The substrate according to the embodiment may have a flat quadrilateral shape, a quadrilateral shape in which each corner portion is rounded with a certain radius of curvature, or a non-quadrilateral shape including at least seven sides. Here, the substrate having a non-quadrilateral shape may include at least one protruding portion or at least one notched portion.

[0045] The substrate according to an embodiment may include a colored polyimide material. For example, the substrate including the polyimide material may be formed by curing a polyimide resin, which is coated to have a certain thickness on the front surface of a peeling layer provided in a relatively thick carrier substrate. In this case, the carrier substrate may be separated from the substrate by peeling off the peeling layer through a laser peeling process. The substrate according to an embodiment may also include a backplane coupled to the rear surface of the substrate relative to the thickness direction Z. The backplane may maintain the substrate in a flat state. The backplane according to an embodiment may include a plastic material, and may include, for example, polyethylene terephthalate. The backplane may be laminated on the rear surface of the substrate separated from the carrier substrate.

[0046] According to another embodiment, the substrate may be a flexible glass substrate. For example, the substrate including the glass material may be a thin glass substrate having a thickness of 100 μm or less, or may be a carrier glass substrate etched to have a thickness of 100 μm or less by a substrate etching process performed after the manufacturing process is completed.

[0047] A plurality of initialization voltage lines IVL, a plurality of scan control lines SCL, a plurality of emission control lines ECL, a plurality of data lines DL, a plurality of pixel driving voltage lines PL, a common electrode layer, and a plurality of pixels P may be provided in the display area AA.

[0048] The plurality of initialization voltage lines IVL may extend in length in a second direction Y intersecting the first direction X, and may be separated from each other in the first direction X. Here, the first direction X may be a direction parallel to the width direction of the substrate, and the second direction Y may be a direction parallel to the length direction of the substrate. However, the present disclosure is not limited thereto, and the first direction X may be a direction parallel to the length direction of the substrate, and the second direction Y may be a direction parallel to the width direction of the substrate. Each of the plurality of initialization voltage lines IVL may transmit an initialization voltage supplied from the data driver 300 or the power supply circuit to a corresponding pixel among the plurality of pixels.

[0049] The plurality of scan control lines SCL may extend in length in the first direction X and may be respectively disposed adjacent to the plurality of emission control lines ECL. Each of the plurality of scan control lines SCL may transmit a scan control signal supplied from the gate driver 200 to a corresponding pixel among the plurality of pixels.

[0050] The plurality of emission control lines ECL may extend a length in the first direction X and may be disposed parallel to the plurality of scan control lines SCL. Each of the plurality of emission control lines ECL may transmit an emission control signal supplied from the gate driver 200 to a corresponding pixel among the plurality of pixels.

[0051] The plurality of data lines DL may extend a length in the second direction Y, and may be separated from each other in the first direction X. Each of the plurality of data lines DL may transmit a data voltage supplied from the data driver 300 to a corresponding pixel among the plurality of pixels.

[0052] The plurality of pixel driving voltage lines PL may be respectively disposed in parallel with the plurality of data lines DL. Each of the plurality of pixel driving voltage lines PL may transmit a pixel driving voltage supplied from the data driver 300 or a power supply circuit to a corresponding pixel among the plurality of pixels.

[0053] Each of the plurality of pixel driving voltage lines PL according to the embodiment may be provided to correspond to two pixels disposed adjacent to each other in the first direction X. That is, one pixel driving voltage line PL may be provided to be shared by two pixels disposed adjacent to each other in the first direction X.

[0054] The common electrode layer may be disposed in the entire display area AA. The common electrode layer may transmit a common voltage Vss supplied from the data driver 300 or a power circuit to a plurality of pixels. At least one common power line electrically connected to the common electrode layer may be disposed in the display area AA.

[0055] Each of the plurality of pixels P may be disposed in a pixel area defined in the display area AA, and may be electrically connected to a corresponding initialization voltage line IVL, a corresponding scan control line SCL, a corresponding emission control line ECL, a corresponding data line DL, a pixel driving voltage line PL, and a common electrode layer, which pass through the pixel area or are disposed near the pixel area.

[0056] In this case, in order to implement the light-emitting display panel 100 with high resolution, each of the scan control line SCL and the emission control line ECL may be disposed to pass through or through the pixel region, and each of the initialization voltage line IVL, the data line DL, and the pixel driving voltage line PL may be disposed at an outer portion of the pixel region. Moreover, two pixels disposed adjacent to each other in the first direction X may have a symmetrical structure with respect to the pixel driving voltage line PL.

[0057] The pixel P according to the embodiment may be arranged in a stripe structure in the display area AA. In this case, one unit pixel may include a red pixel, a green pixel, and a blue pixel, and further, may further include a white pixel.

[0058] According to another embodiment, the pixel P may be arranged to have a pentile structure in the display area AA. In this case, one unit pixel may include at least one red pixel, at least two green pixels, and at least one blue pixel, which are arranged to have a polygonal shape one-dimensionally. For example, a unit pixel having a pentile structure may be arranged so that one red pixel, two green pixels, and one blue pixel are arranged to have an octagonal shape one-dimensionally, and in this case, the blue pixel may include an opening area (or emission area) having a relatively maximum size, and the green pixel may include an opening area having a relatively minimum size.

[0059] Each of the plurality of pixels P may operate in the order of an initialization period, a sampling period, and an emission period to emit light having brightness corresponding to a data voltage supplied through a corresponding data line DL.

[0060] In some embodiments, the non-display area IA may be disposed along an edge of the substrate to surround the display area AA. One non-display area of ​​the non-display area IA may include a pad portion.

[0061] The pad portion may be disposed in one non-display area of ​​the substrate, and may be electrically connected to a line disposed in the display area AA in the second direction Y. Also, the pad portion may be electrically connected to the data driver 300 .

[0062] The timing controller 400 may align input video data Idata to generate pixel data Pdata based on driving of the light-emitting display panel 100 , generate a data control signal DCS based on the timing synchronization signal TSS, and provide the pixel data Pdata and the data control signal DCS to the data driver 300 .

[0063] The timing controller 400 may generate a gate control signal GCS including a gate start signal and a plurality of gate shift clocks based on the timing synchronization signal TSS, and may provide the gate control signal GCS to the gate driver 200. The gate control signal GCS may be provided to the gate driver 200 via a pad portion.

[0064] The data driver 300 may be connected to a plurality of data lines DL provided in the light-emitting display panel 100 via a pad portion. The data driver 300 may convert pixel data Pdata into analog data voltages by using a data control signal DCS and a plurality of reference gamma voltages provided from the timing controller 400, and may provide the converted data voltages to corresponding data lines DL.

[0065] The gate driver 200 can generate an initialization control signal, a scanning control signal, and an emission control signal corresponding to an initialization period, a sampling period, and an emission period of each of a plurality of pixels P, respectively, based on a gate control signal GCS provided from the controller 400, and can provide the initialization control signal, the scanning control signal, and the emission control signal to the plurality of pixels P.

[0066] The gate driver 200 according to the embodiment may generate emission control signals having the same cycle and sequentially shifted phases, and may supply the emission control signals to a plurality of emission control lines ECL.

[0067] The gate driver 200 according to an embodiment may be disposed in the left non-display area and / or the right non-display area of ​​the substrate through a process of manufacturing a thin film transistor (TFT) of each pixel P.

[0068] For example, the gate driver 200 may be disposed in a left non-display area of ​​the substrate, and may supply an emission control signal to one end of each emission control line ECL based on a single feeding method.

[0069] As another example, the gate driver 200 may be disposed in each of the left and right non-display areas of the substrate, and may supply the emission control signal to both ends of each emission control line ECL based on a dual feeding method.

[0070] Figure 2 is a circuit diagram of an embodiment of a pixel applied to a light-emitting display panel according to the present disclosure, Figure 3 It is shown Figure 2 A cross-sectional view of the layer structure of a pixel is shown, and Figure 4 It is shown Figure 3 A diagram showing the circuit configuration of each layer.

[0071] like Figures 2 to 4 As shown, a pixel P applied to a light-emitting display panel according to the present disclosure may include: a pixel driving circuit layer 150 including a pixel driving circuit PDC; and a light-emitting device layer 170 including a light-emitting device ED electrically connected to the pixel driving circuit PDC.

[0072] The pixel driving circuit layer 150 may include: a first pixel circuit layer 110, which includes a first pixel circuit PC1; a second pixel circuit layer 120, which includes a second pixel circuit PC2; a third pixel circuit layer 130, which includes a third pixel circuit PC3; and a fourth pixel circuit layer 140, which includes a fourth pixel circuit PC4.

[0073] First, the first pixel circuit layer 110 according to the embodiment may include a substrate 10, a first pixel circuit PC1, a data line DL for transmitting a data voltage to the first pixel circuit PC1, and an nth scan control line SCL(n) for transmitting an nth scan control signal to the first pixel circuit PC1.

[0074] As described above, the substrate 10 may include a plastic or glass material.

[0075] The data line DL may be disposed at one edge of the pixel P in parallel with the second direction Y. The data line DL according to the embodiment may be disposed at one edge of the pixel P to overlap or not overlap with the n-th scan control line SCL(n) disposed one-dimensionally in the first pixel circuit layer 110. For example, the data line DL may be disposed at one edge of the pixel P to overlap with the n-th scan control line SCL(n) disposed in the first pixel circuit layer 110.

[0076] The nth scan control line SCL(n) may be disposed in the pixel P and may be separated from and parallel to the emission control line ECL. The nth scan control line SCL(n) according to an embodiment may be disposed in the pixel P to overlap or not overlap with the emission control line ECL one-dimensionally disposed in the second pixel circuit layer 120.

[0077] The first pixel circuit PC1 may control the amount of current flowing to the light emitting device ED by using the data voltage supplied through the data line DL.

[0078] The first pixel circuit PC1 according to an embodiment may include a third transistor T3 including a gate connected to an nth scan control line SCL(n) and a first terminal connected to a data line DL, and a driving transistor Tdr including a first terminal connected to a second terminal of the third transistor T3.

[0079] The third transistor T3 may be turned on or off based on the nth scan control signal supplied through the nth scan control line SCL(n). When the third transistor T3 is turned on, the data voltage supplied through the data line DL may be charged into the capacitor C.

[0080] The third transistor T3 according to the embodiment may include a gate connected to the nth scan control line SCL (n), a second terminal connected to the first terminal of the driving transistor Tdr through the first node n1, and a first terminal connected to the data line DL. In the following description, in the case where the gates of the first transistor T1 to the sixth transistor T6 should be distinguished from each other, these gates may be referred to as the first gate electrode to the sixth gate electrode. Moreover, the gate of the driving transistor Tdr may be referred to as the driving gate electrode. However, in the case where it is not necessary to distinguish the gates, each of the gates of the first transistor T1 to the sixth transistor T6 may be referred to as a gate.

[0081] The driving transistor Tdr may transmit a current corresponding to a gate-source voltage to the light emitting device ED based on a data voltage supplied through the data line DL.

[0082] The driving transistor Tdr according to an embodiment may include a first terminal connected to the second terminal of the third transistor T3 through the first node n1, a second terminal connected to the fourth transistor T4 included in the second pixel circuit layer 120 and the second transistor T2 included in the fourth pixel circuit layer 140, and a gate connected to the sixth transistor T6 included in the third pixel circuit layer 130 and the capacitor C.

[0083] The first terminal of the driving transistor Tdr may be a source electrode, and the second terminal thereof may be a drain electrode. The driving transistor Tdr may be turned on based on its gate-source voltage, and thus a current corresponding to the gate-source voltage based on the data voltage may flow in the first transistor T1, the driving transistor Tdr, the second transistor T2, and the light emitting device ED.

[0084] Each of the third transistor T3 and the driving transistor Tdr may include a semiconductor layer including an amorphous silicon material, a polycrystalline silicon material, or an oxide semiconductor material, and each of the third transistor T3 and the driving transistor Tdr may be a P-type TFT including a semiconductor layer doped with a P-type impurity, but is not limited thereto, and may be an N-type TFT including a semiconductor layer doped with an N-type impurity. That is, in Figure 2 , a pixel driving circuit PDC including a plurality of P-type TFTs is shown, but the pixel driving circuit PDC may include a plurality of N-type TFTs.

[0085] Polysilicon material may have good reliability with respect to strong bias stress and may have high electron mobility. Therefore, each of the third transistor T3 and the driving transistor Tdr according to the embodiment may include a P-type TFT including a semiconductor layer including a polysilicon material doped with P-type impurities.

[0086] Characteristics of materials included in the third transistor T3 and the driving transistor Tdr may be applied to all of the first transistor T1 , the second transistor T2 , and the fourth to sixth transistors T4 to T6 .

[0087] Second, the second pixel circuit layer 120 may be disposed on the top surface (or surface) of the first pixel circuit layer 110. The second pixel circuit layer 120 according to an embodiment may include a second pixel circuit PC2, an emission control line ECL for transmitting an emission control signal to the second pixel circuit PC2, and an nth scan control line SCL(n) for transmitting an nth scan control signal to the second pixel circuit PC2.

[0088] The emission control line ECL may be disposed in the pixel P in parallel to the first direction X.

[0089] The nth scan control line SCL(n) may be arranged in the pixel P so as to be separated from and parallel to the emission control line ECL. In particular, the nth scan control line SCL(n) included in the second pixel circuit layer 120 may be electrically connected to the nth scan control line SCL(n) included in the first pixel circuit layer 110 through the first scan connection line. In this case, the first scan connection line may be arranged in the display area AA, and further, may be arranged in the non-display area IA. In addition, at least one first scan connection line may be arranged only in the non-display area IA, at least one first scan connection line may be arranged only in the display area AA, and at least two first scan connection lines may be arranged only in the display area AA and the non-display area IA.

[0090] The second pixel circuit PC2 may charge the capacitor C with a data voltage supplied through the data line DL.

[0091] According to the embodiment, the second pixel circuit PC2 may include: a first transistor Tl, which includes a first terminal connected to the pixel driving voltage line PL, a second terminal connected to the second terminal of the third transistor T3 and the first terminal of the driving transistor Tdr through the first node n1, and a gate connected to the emission control line ECL; and a fourth transistor T4, which includes a gate connected to the nth scanning control line SCL(n), a first terminal connected to the gate of the driving transistor Tdr and the second electrode of the capacitor C, and a second terminal connected to the second terminal of the driving transistor Tdr and the first terminal of the second transistor T2 through the second node n2.

[0092] The first transistor T1 may be turned on or off based on an emission control signal supplied through the emission control line ECL. When the first transistor T1 is turned on, current may be supplied to the driving transistor Tdr.

[0093] The first transistor T1 according to the embodiment may include a gate connected to the emission control line ECL, a first terminal connected to the pixel driving voltage line PL, and a second terminal connected to the first terminal of the driving transistor Tdr. The second terminal of the first transistor T1 may be connected to the second terminal of the third transistor T3.

[0094] The fourth transistor T4 may be turned on or off based on the nth scan control signal supplied through the nth scan control line SCL(n). When the fourth transistor T4 is turned on, the data voltage supplied through the data line DL, the third transistor T3 and the driving transistor Tdr may be charged into the capacitor C.

[0095] The fourth transistor T4 according to the embodiment may include a gate connected to the nth scan control line SCL(n), a first terminal connected to the gate of the driving transistor Tdr, and a second terminal connected to the second terminal of the driving transistor Tdr. The first terminal of the fourth transistor T4 may be connected to the second terminal of the sixth transistor T6 and the second electrode of the capacitor C. Moreover, the second terminal of the fourth transistor T4 may be connected to the first terminal of the second transistor T2.

[0096] Third, the third pixel circuit layer 130 may be disposed on a top surface (or surface) of the second pixel circuit layer 120 .

[0097] According to the embodiment, the third pixel circuit layer 130 may include a third pixel circuit PC3, an n-1th scan control line SCL(n-1) for transmitting an n-1th scan control signal to the third pixel circuit PC3, an initialization voltage line IVL for transmitting an initialization voltage to the third pixel circuit PC3, and an nth scan control line SCL(n) for transmitting an nth scan control signal to the third pixel circuit PC3.

[0098] The n-1th scan control line SCL(n-1) may be disposed in the pixel P to be separated from and parallel to the emission control line ECL and the n-th scan control line SCL(n). The n-1th scan control line SCL(n-1) according to the embodiment may be disposed in the pixel P to overlap or not overlap with the emission control line ECL one-dimensionally disposed in the second pixel circuit layer 120, and may be disposed in the pixel P to overlap with the n-th scan control line SCL(n) disposed in the first pixel circuit layer 110.

[0099] The initialization voltage line IVL may be disposed in parallel with the data line DL in the pixel P. The initialization voltage supplied through the initialization voltage line IVL may initialize the capacitor C, the gate of the driving transistor Tdr, and the light emitting device ED.

[0100] The n-th scan control line SCL(n) included in the third pixel circuit layer 130 may be electrically connected to the n-th scan control line SCL(n) included in the second pixel circuit layer 120 through the second scan connection line. In this case, the second scan connection line may be provided in the display area AA, and further, may be provided in the non-display area IA. In addition, at least one second scan connection line may be provided only in the non-display area IA, at least one second scan connection line may be provided only in the display area AA, and at least two second scan connection lines may be provided only in the display area AA and the non-display area IA.

[0101] The third pixel circuit PC3 may initialize the capacitor C and the gate of the driving transistor Tdr.

[0102] According to the embodiment, the third pixel circuit PC3 may include: a sixth transistor T6, the sixth transistor T6 includes a first terminal connected to the initialization voltage line IVL, a second terminal connected to the gate of the driving transistor Tdr, and a gate connected to the n-1th scanning control line SCL(n-1); a fifth transistor T5, the fifth transistor T5 includes a gate connected to the nth scanning control line SCL(n) and a first terminal connected to the initialization voltage line IVL; and a capacitor C, the capacitor C includes a first electrode connected to the pixel driving voltage line PL and a second electrode connected to the second terminal of the sixth transistor T6.

[0103] The sixth transistor T6 may be turned on or off based on the n-1th scan control signal supplied through the n-1th scan control line SCL(n-1). When the sixth transistor T6 is turned on, the third node n3 may be initialized by the initialization voltage supplied through the initialization voltage line IVL and the sixth transistor T6.

[0104] The sixth transistor T6 according to the embodiment may include a first terminal connected to the initialization voltage line IVL and the first terminal of the fifth transistor T5, a second terminal connected to the second electrode of the capacitor C, the first terminal of the fourth transistor T4, and the gate of the driving transistor Tdr, and a gate connected to the n-1th scanning control line SLC (n-1). The first terminal of the sixth transistor T6 may be connected to the initialization voltage line IVL and the first terminal of the fifth transistor T5. The second terminal of the sixth transistor T6 may be connected to the second electrode of the capacitor C, the first terminal of the fourth transistor T4, and the gate of the driving transistor Tdr.

[0105] The fifth transistor T5 may be turned on or off based on the nth scan control signal supplied through the nth scan control line SCL(n). When the fifth transistor T5 is turned on, the light emitting device ED may be initialized by the initialization voltage supplied through the initialization voltage line IVL and the fifth transistor T5.

[0106] The fifth transistor T5 according to the embodiment may include a gate connected to the nth scan control line SCL(n), a first terminal connected to the initialization voltage line IVL, and a second terminal connected to the light emitting device ED. The first terminal of the fifth transistor T5 may also be connected to the first terminal of the sixth transistor T6. The second terminal of the fifth transistor T5 may be connected to the second terminal of the second transistor T2 and the light emitting device ED.

[0107] As described above, the capacitor C can store the data voltage supplied through the data line DL. In addition, the capacitor C can store the initialization voltage supplied through the initialization voltage line IVL. In addition, the capacitor C can store the threshold voltage of the driving transistor Tdr. That is, the capacitor C can sense the change of the threshold voltage of the driving transistor Tdr and can store the threshold voltage for performing an internal compensation function of compensating for the change of the threshold voltage.

[0108] The first electrode of the capacitor C according to the embodiment may be connected to the first terminal of the first transistor T1 and the pixel driving voltage line PL.

[0109] The second electrode of the capacitor C may be connected to the third node n3. That is, the second electrode of the capacitor C may be connected to the gate of the driving transistor Tdr, the first terminal of the fourth transistor T4, and the second terminal of the sixth transistor T6.

[0110] Fourth, the fourth pixel circuit layer 140 may be disposed on a top surface (or surface) of the third pixel circuit layer 130 .

[0111] The fourth pixel circuit layer 140 according to an embodiment may include a fourth pixel circuit PC4 and an emission control line ECL for transmitting an emission control signal to the fourth pixel circuit PC4 .

[0112] The emission control line ECL may be disposed in the pixel P in parallel to the first direction X.

[0113] The emission control line ECL included in the second pixel circuit layer 120 may be electrically connected to the emission control line ECL included in the fourth pixel circuit layer 140 through the emission control signal connection line. In this case, the emission control signal connection line may be provided in the display area AA, and further, may be provided in the non-display area IA. In addition, at least one emission control signal connection line may be provided only in the non-display area IA, at least one emission control signal connection line may be provided only in the display area AA, and at least two emission control signal connection lines may be provided only in the display area AA and the non-display area IA.

[0114] The fourth pixel circuit PC4 may perform a function of supplying current to the light emitting device ED.

[0115] The fourth pixel circuit PC4 according to the embodiment may include a second transistor T2 including a gate connected to the emission control line ECL, a first terminal connected to the second terminal of the driving transistor Tdr, and a second terminal connected to the light emitting device ED.

[0116] The second transistor T2 may be turned on or off based on an emission control signal supplied through the emission control line ECL. When the second transistor T2 is turned on, current may be supplied to the light emitting device ED through the first transistor T1, the driving transistor Tdr, and the second transistor T2.

[0117] The second transistor T2 according to the embodiment may include a gate connected to the emission control line ECL, a first terminal connected to the second terminal of the driving transistor Tdr, and a second terminal connected to the light emitting device ED. The second terminal of the second transistor T2 may be connected to the second terminal of the fifth transistor T5.

[0118] The light emitting device layer 170 may include a light emitting device ED, which is electrically connected to the fourth pixel circuit PC4 and emits light based on a current supplied from the fourth pixel circuit PC4 , and a bank pattern BNK.

[0119] The light emitting device ED according to the embodiment may include a pixel driving electrode AE ​​(referred to as an anode electrode) connected to a pixel driving circuit PDC, a light emitting layer EL formed on the pixel driving electrode AE, and a common electrode layer CE (referred to as a cathode electrode) electrically connected to the light emitting layer EL.

[0120] The pixel driving electrode AE ​​may be disposed in an opening region of the pixel P, and may be electrically connected to a second terminal of the driving transistor Tdr included in the first pixel circuit PC1 through the second transistor T2.

[0121] The pixel driving electrode AE ​​according to the embodiment may include a metal material with high reflectivity. For example, the pixel driving electrode AE ​​may be formed in a multilayer structure such as a stacked structure of aluminum (Al) and titanium (Ti) (titanium / aluminum / titanium (Ti / Al / Ti)), a stacked structure of Al and indium tin oxide (ITO) (indium tin oxide / aluminum / indium tin oxide (ITO / Al / ITO)), an APC (silver / palladium / copper (Ag / Pd / Cu)) alloy, or a stacked structure of an APC alloy and ITO (ITO / APC / ITO), or may include a single-layer structure including one material or an alloy material of two or more materials selected from Ag, Al, molybdenum (Mo), gold (Au), magnesium (Mg), calcium (Ca) and barium (Ba).

[0122] The edge of the pixel driving electrode AE ​​may be at least partially covered by the bank pattern BNK. The bank pattern BNK may be disposed in a pixel region other than the opening region of the pixel P and may at least partially cover the edge of the pixel driving electrode AE. Thus, the opening region of the pixel P may be defined.

[0123] The bank pattern BNK according to the embodiment may define an opening region of the pixel P as a pentile structure or a stripe structure.

[0124] The light emitting layer EL according to the embodiment may be formed in the entire display area AA of the substrate 10 to at least partially cover the pixel driving electrode AE ​​and the bank pattern BNK.

[0125] The light-emitting layer EL according to the embodiment may include two or more light-emitting parts for emitting white light. For example, the light-emitting layer EL according to the embodiment may include a first light-emitting part and a second light-emitting part for emitting white light based on a combination of the first light and the second light. Here, the first light-emitting part may emit the first light, and may include one of a blue light-emitting part, a green light-emitting part, a red light-emitting part, a yellow light-emitting part, and a yellow-green light-emitting part. The second light-emitting part may include a light-emitting part that emits a second light having a complementary color relationship with the first light among the blue light-emitting part, the green light-emitting part, the red light-emitting part, the yellow light-emitting part, and the yellow-green light-emitting part.

[0126] According to another embodiment, the light emitting layer EL may include one of a blue light emitting portion, a green light emitting portion, and a red light emitting portion for emitting colored light corresponding to a color set in the pixel P. For example, the light emitting layer EL according to another embodiment may include one of an organic light emitting layer, an inorganic light emitting layer, and a quantum dot light emitting layer, or may include a stacked or combined structure of an organic light emitting layer (or an inorganic light emitting layer) and a quantum dot light emitting layer.

[0127] In addition, the light emitting device ED according to the embodiment may further include a functional layer for enhancing the emission efficiency and / or lifetime of the light emitting layer EL.

[0128] The common electrode layer CE may be formed to be electrically connected to the light emitting layer EL. The common electrode layer CE may be formed in the entire display area AA of the substrate 10, and may be commonly connected to the light emitting layer EL provided in each pixel area PA.

[0129] The common electrode layer CE according to the embodiment may include a transparent conductive material, a transparent metal or a semi-transmissive conductive material that can transmit light. When the common electrode layer CE includes a semi-transmissive conductive material, the emission efficiency of the light emitted from the light emitting device ED can be increased based on the microcavity. The semi-transmissive conductive material according to the embodiment may include Mg, Ag or an alloy of Mg and Ag. In addition, a cover layer for adjusting the refractive index of the light emitted from the light emitting device ED to enhance the emission efficiency of the light may be further formed on the common electrode layer CE.

[0130] According to another embodiment, the light emitting layer EL may include a micro light emitting diode device implemented as an integrated circuit (IC) type. The micro light emitting diode device may include a first terminal electrically connected to the pixel driving electrode AE ​​and a second terminal electrically connected to the common electrode layer CE.

[0131] The pixel P according to the embodiment may further include a planarization layer 160 at least partially covering the fourth pixel circuit layer 140 and an encapsulation layer 190 at least partially covering the light emitting device layer 170 .

[0132] The planarization layer 160 may be disposed on the substrate 10 to at least partially cover the fourth pixel circuit layer 140 , and may provide a flat surface on the fourth pixel circuit layer 140 .

[0133] The light emitting device layer 170 may be disposed on the planarization layer 160. In this case, the pixel driving electrode AE ​​of the light emitting device layer 170 may be connected to the second terminal of the second transistor T2 of the fourth pixel circuit PC4 through an electrode contact hole disposed in the planarization layer 160, and the first terminal of the second transistor T2 may be electrically connected to the second terminal of the driving transistor Tdr of the first pixel circuit PC1.

[0134] The encapsulation layer 190 may be formed on the substrate 10 to at least partially surround the light emitting device layer 170. The encapsulation layer 190 may prevent oxygen or water from penetrating into the light emitting device ED.

[0135] The encapsulation layer 190 according to the embodiment may include at least one inorganic layer for preventing or minimizing the penetration of oxygen or water and an organic layer for covering particles occurring during the manufacturing process. For example, the encapsulation layer 190 may include a first inorganic layer, an organic layer on the first inorganic layer, and a second inorganic layer on the organic layer.

[0136] In addition, the pixel P according to an embodiment of the present disclosure may further include a black matrix overlapping the bank pattern BNK and a wavelength conversion layer disposed in the opening region.

[0137] A black matrix may be disposed on the encapsulation layer 190 to overlap the bank pattern BNK.

[0138] The wavelength conversion layer according to the embodiment may include a color filter disposed on the encapsulation layer 190 at least partially overlapping the opening region of the pixel P to transmit only the color wavelength of white light incident from the light emitting device ED disposed in the pixel P. For example, the wavelength conversion layer may transmit only red, green, or blue wavelengths. When the light emitting layer EL of the light emitting device ED includes a light emitting layer emitting red, green, and blue light, the wavelength conversion layer may be omitted.

[0139] The pixel P according to an embodiment of the present disclosure may further include a blocking film and a light path control layer.

[0140] The barrier film may be attached on the encapsulation layer 190 by using an adhesive layer. The barrier film may mainly prevent the penetration of oxygen or water, and may include a material with a low water vapor transmission rate.

[0141] The light path control layer can control the path of incident light.

[0142] The light path control layer according to the embodiment may include a plurality of refractive layers. The plurality of refractive layers may have different refractive indices. The light path control layer may have a structure in which high refractive layers and low refractive layers are alternately stacked. The light path control layer according to the embodiment may change the path of the incident light to minimize the color shift phenomenon caused by the viewing angle.

[0143] According to another embodiment, the light path control layer may be a polarization layer. The polarization layer may change external light reflected by the TFT and / or wire provided in the pixel P into circularly polarized light, thereby enhancing visibility and contrast.

[0144] The operation of the pixel according to the embodiment of the present disclosure will be described below.

[0145] The pixel P according to the embodiment of the present disclosure may operate in an initialization period, a routing period, and an emission period. For example, one frame of a light-emitting display device to which the light-emitting display panel according to the embodiment of the present disclosure is applied may include an initialization period for initializing the gate of the driving transistor Tdr, a routing period for storing a sampling voltage and a data voltage each corresponding to a characteristic value (e.g., a threshold voltage) of the driving transistor Tdr, and an emission period for causing the light-emitting device ED to emit light using a current corresponding to the data voltage.

[0146] In the initialization period, a low voltage may be supplied to the n-1th scan control line SCL(n-1), and therefore, the sixth transistor T6 may be turned on. In this case, the voltage of the third node n3 may be the initialization voltage Vinit. The third node n3 may be a portion connected to the second electrode of the capacitor C, the gate of the driving transistor Tdr, the first terminal of the fourth transistor T4, and the second terminal of the sixth transistor T6.

[0147] In the routing cycle, a low voltage may be supplied to the nth scan control line SCL(n), and therefore, the third transistor T3 may be turned on. In this case, the voltage of the third node n3 may be the sum voltage of the data voltage Vdata supplied through the data line DL and the threshold voltage Vth of the driving transistor Tdr. That is, the voltage of the third node n3 may be changed from the initialization voltage Vinit to the sum voltage (=Vdata+Vth) of the data voltage Vdata and the threshold voltage Vth.

[0148] In the emission period, a low voltage may be supplied to the emission control line ECL, and thus, the first transistor T1 and the second transistor T2 may be turned on. In this case, the current supplied to the light emitting device ED may be proportional to the square of the difference voltage between the gate-source voltage Vgs and the threshold voltage Vth of the driving transistor Tdr. In the emission period, the gate voltage of the driving transistor Tdr (i.e., the voltage of the third node n3) may be the sum voltage (=Vdata+Vth) of the data voltage Vdata and the threshold voltage Vth, and the source voltage of the driving transistor Tdr may be the pixel driving voltage Vdd supplied through the pixel driving voltage line PL. Therefore, the difference voltage between the gate-source voltage Vgs and the threshold voltage Vth of the driving transistor Tdr may be [((Vdata+Vth)-Vdd)-Vth=Vdata-Vdd]. Therefore, the current supplied to the light emitting device ED may be proportional to the square of the difference voltage (=Vdata-Vdd) between the data voltage Vdata and the pixel driving voltage Vdd.

[0149] That is, according to the present disclosure, the current supplied to the light emitting device ED may be independent of the threshold voltage Vth of the driving transistor Tdr, and may be determined only by the pixel driving voltage Vdd and the data voltage Vdata.

[0150] Therefore, according to the present disclosure, even when the driving transistor Tdr degrades to cause a change in the threshold voltage Vth of the driving transistor Tdr, the current supplied to the light emitting device ED is not affected by the change in the threshold voltage Vth. Therefore, according to the present disclosure, the current can be controlled only by the data voltage Vdata regardless of the amount of change in the threshold voltage Vth of the driving transistor Tdr.

[0151] Figure 5 is a cross-sectional view showing an example in which a first pixel circuit layer, a second pixel circuit layer, a third pixel circuit layer, and a fourth pixel circuit layer applied to the present disclosure are coupled to each other, Figure 6 It is shown Figure 2 Schematic diagram of a first pixel circuit shown in FIG. Figure 7 It is shown that Figure 6A diagram of a layout of a first pixel circuit layer of a first pixel circuit shown in FIG. Figure 8 is along Figure 7 The cross-sectional view is taken along the line AA' shown. That is, Figure 6 A first pixel circuit included in a pixel is shown, Figure 7 shows the horizontal structure of the first pixel circuit layer in one pixel, and Figure 8 The vertical structure of the first pixel circuit layer in one pixel is shown.

[0152] In the pixel P of the light-emitting display panel 100 according to the embodiment of the present disclosure, as shown in FIG. Figures 6 to 8 As shown, the first pixel circuit layer 110 may include a substrate 10, a first buffer layer 111, a first semiconductor layer 112 formed in a region of the substrate 10 corresponding to the third transistor T3 and the driving transistor Tdr, a first gate insulating layer 113 at least partially covering the first semiconductor layer 112, a first gate electrode layer 114 formed in a region of the first gate insulating layer 113 corresponding to the third transistor T3 and the driving transistor Tdr, a first passivation layer 115 at least partially covering the first gate electrode layer 114, an a-th contact electrode CTa electrically connected to a region of the first semiconductor layer 112 disposed in the first node n1 through an a-th contact hole CHa formed in the first passivation layer 115, and a b-th contact hole CHb electrically connected to the first semiconductor layer 112 through a b-th contact hole CHb formed in the first passivation layer 115. a b-th contact electrode CTb of the layer 112 set in the second node n2 area, a second passivation layer 116 at least partially covering the first passivation layer 115, a first planarization layer 117 at least partially covering the second passivation layer 116, a first connection line CL1 electrically connected to the a-th contact electrode CTa through a first contact hole CH1 formed in the first planarization layer 117 and the second passivation layer 116, a 2-1 connection line CL2-1 electrically connected to the b-th contact electrode CTb through a 2-1 contact hole CH2-1 formed in the first planarization layer 117 and the second passivation layer 116, and a 3-1 connection line CL3-1 connected to the driving gate electrode (Gate dr) of the driving transistor Tdr through a 3-1 contact hole CH3-1 formed in the first planarization layer 117, the second passivation layer 116 and the first passivation layer 115.

[0153] First, the substrate 10 may include a display area AA and a non-display area IA, and a plurality of pixels P may be disposed in the display area AA. Figures 6 to 8 One pixel is shown.

[0154] The first buffer layer 111 may be disposed on the substrate 10 for preventing water penetration or increasing adhesion to the first semiconductor layer 112 .

[0155] The first buffer layer 111 may include an organic material or an inorganic material, and may be formed of at least two layers.

[0156] The first semiconductor layer 112 may be disposed in a region in which the third transistor T3 and the driving transistor Tdr are disposed. The first semiconductor layer 112 may include a polysilicon material.

[0157] The first semiconductor layer 112 according to the embodiment may include a plurality of channel regions and a plurality of high-concentration doped regions, the plurality of channel regions being disposed in a region overlapping with the third gate electrode (Gate3) of the third transistor T3 and the driving gate electrode (Gate dr) of the driving transistor Tdr, the plurality of high-concentration doped regions being disposed at portions other than the channel regions. The high-concentration doped regions may be disposed at both ends of the channel region.

[0158] Each of the plurality of channel regions may serve as a semiconductor layer of each of the third transistor T3 and the driving transistor Tdr.

[0159] The high-concentration doped region may include metal characteristics, and may function as a first terminal or a second terminal of each of the third transistor T3 and the driving transistor Tdr.

[0160] For example, in Figure 8 In the illustrated cross-sectional surface, the channel region corresponding to the third gate electrode (Gate 3) and the driving gate electrode (Gate dr) is not illustrated, and only the high-concentration doped region is illustrated.

[0161] Subsequently, a first gate insulating layer 113 may be formed over the entire substrate 10 to at least partially cover or completely cover the first semiconductor layer 112. The first gate insulating layer 113 according to an embodiment may include silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof.

[0162] Subsequently, a first gate electrode layer 114 may be disposed on the first gate insulating layer 113. The first gate electrode layer 114 may include a third gate electrode (Gate 3) and a driving gate electrode (Gate dr).

[0163] The first gate electrode layer 114 may include a single layer or multiple layers of one of metals such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0164] Subsequently, a first passivation layer 115 may be formed over the entire substrate 10 to at least partially cover or completely cover the first gate electrode layer 114. The first passivation layer 115 may include SiOx, SiNx, or a multilayer thereof.

[0165] Subsequently, the a-th contact electrode CTa may be electrically connected to a region of the first semiconductor layer 112 disposed in the first node n1 through the a-th contact hole CHa formed in the first passivation layer 115 .

[0166] like Figure 8 As shown, the a-th contact electrode CTa may be electrically connected to the first link electrode CL1.

[0167] That is to say, Figure 2 , Figure 4 and Figure 8 As shown, the first node n1 between the third transistor T3 and the driving transistor Tdr included in the first pixel circuit layer 110 may extend to the second pixel circuit layer 120 through the ath contact electrode CTa included in the first pixel circuit layer 110 and the first connection electrode CL1 included in the second pixel circuit layer 120 .

[0168] Subsequently, the b-th contact electrode CTb may be electrically connected to a region of the first semiconductor layer 112 disposed in the second node n2 through the b-th contact hole CHb formed in the first passivation layer 115 .

[0169] like Figure 8 As shown, the b-th contact electrode CTb may be connected to the 2-1-th connection electrode CL2-1.

[0170] That is to say, Figure 2 , Figure 4 and Figure 8 As shown, the second node n2 connected to the second terminal of the driving transistor Tdr included in the first pixel circuit layer 110 can extend to the second pixel circuit layer 120 through the bth contact electrode CTb included in the first pixel circuit layer 110 and the 2-1th connection electrode CL2-1 included in the second pixel circuit layer 120.

[0171] Subsequently, a second passivation layer 116 may be formed over the entire substrate 10 to cover the first contact electrode CTa and the second contact electrode CTb. The second passivation layer 116 may include SiOx, SiNx, or a multilayer thereof.

[0172] The data line DL may be disposed in the second passivation layer 116 .

[0173] Subsequently, a first planarization layer 117 may be formed over the entire substrate 10 to cover the data line DL. The first planarization layer 117 may include SiOx, SiNx, or a multi-layer thereof.

[0174] Subsequently, the first connection line CL1 may be connected to the a-th contact electrode CTa through the first contact hole CH1 formed in the first planarization layer 117 and the second passivation layer 116 .

[0175] The first connection line CL1 may be connected to a second terminal of the first transistor T1 included in the second pixel circuit layer 120 .

[0176] That is, the first connection line CL1 may connect the second terminal of the first transistor T1 included in the second pixel circuit layer 120 to the second terminal of the third transistor T3 and the first terminal of the driving transistor Tdr included in the first pixel circuit layer 110. The node connected to the first terminal of the driving transistor Tdr, the second terminal of the third transistor T3, and the second terminal of the first transistor T1 may be the first node n1. To provide additional description, the first connection line CL1 may connect the first node n1 included in the first pixel circuit layer 110 to the first node n1 included in the second pixel circuit layer 120.

[0177] Subsequently, the 2-1th connection line CL2 - 1 may be connected to the b-th contact electrode CTb through the 2-1th contact hole CH2 - 1 formed in the first planarization layer 117 and the second passivation layer 116 .

[0178] The 2-1th connection line CL2 - 1 may be connected to the second terminal of the fourth transistor T4 included in the second pixel circuit layer 120 .

[0179] That is, the 2-1st connecting line CL2-1 may connect the second terminal of the driving transistor Tdr included in the first pixel circuit layer 110 to the second terminal of the fourth transistor T4 included in the second pixel circuit layer 120. The node connected to the second terminal of the driving transistor Tdr and the second terminal of the fourth transistor T4 may be the second node n2. To provide additional description, the 2-1st connecting line CL2-1 may connect the second node n2 included in the first pixel circuit layer 110 to the second node n2 included in the second pixel circuit layer 120.

[0180] Finally, the 3-1st connection line CL3 - 1 may be connected to the driving gate electrode (Gate dr) of the driving transistor Tdr through the 3-1st contact hole CH3 - 1 formed in the first planarization layer 117 , the second passivation layer 116 , and the first passivation layer 115 .

[0181] The 3-1th connection line CL3 - 1 may be connected to a first terminal of the fourth transistor T4 included in the second pixel circuit layer 120 .

[0182] That is, the 3-1st connection line CL3-1 may connect the driving gate electrode (Gate dr) of the driving transistor Tdr included in the first pixel circuit layer 110 to the first terminal of the fourth transistor T4 included in the second pixel circuit layer 120. The node connected to the driving gate electrode (Gate dr) of the driving transistor Tdr and the first terminal of the fourth transistor T4 may be the third node n3. To provide additional description, the 3-1st connection line CL3-1 may connect the third node n3 included in the first pixel circuit layer 110 to the third node n3 included in the second pixel circuit layer 120. The third node n3 may be connected to the second electrode of the capacitor C included in the third pixel circuit layer 130.

[0183] Fig. 9 It is shown Figure 2 A diagram of a second pixel circuit shown in FIG. Fig.10 It is shown that Fig. 9 A diagram of a layout of a second pixel circuit layer of a second pixel circuit shown in FIG. Fig.11 is along Fig.10 The cross-sectional view taken along the line BB' shown. That is, Fig. 9 A second pixel circuit PC2 included in one pixel is shown, Fig.10 shows a horizontal structure of the second pixel circuit layer 120 in one pixel, and Fig.11 The vertical structure of the second pixel circuit layer 120 in one pixel is shown.

[0184] In the light-emitting display panel according to the embodiment of the present disclosure, as Figures 9 to 11As shown, the second pixel circuit layer 120 may include a second buffer layer 121 at least partially covering the first planarization layer 117, a second semiconductor layer 122 formed on the second buffer layer 121, a second gate insulating layer 123 at least partially covering the second semiconductor layer 122, a second gate electrode layer 124 formed on the second gate insulating layer 123, a third passivation layer 125 at least partially covering the second gate electrode layer 124, a 3-1 connecting line CL3-1 connected to the third node n3 through a 3-1 contact hole CH3-1 formed in the third passivation layer 125, the second gate insulating layer 123, the second buffer layer 121, the first planarization layer 117, the second passivation layer 116, and the first passivation layer 115, and a 3-1 connecting line CL3-1 connected to the third node n3 through a 3-1 contact hole CH3-1 formed in the third passivation layer 125, the second gate insulating layer 123, the second buffer layer 121, the first planarization layer 117, the second passivation layer 116, and the first passivation layer 115. The second gate insulating layer 123, the second buffer layer 121, the 2-1 connection line CL2-1 connected to the second node n2 through the 2-1 contact hole CH2-1 in the first planarization layer 117 and the second passivation layer 116, the fourth passivation layer 126 at least partially covering the third passivation layer 125, the second planarization layer 127 at least partially covering the fourth passivation layer 126, the 3-2 connection line CL3-2 connected to the 3-1 connection line CL3-1 through the 3-2 contact hole CH3-2 formed in the second planarization layer 127 and the fourth passivation layer 126, and the 2-2 connection line CL2-2 connected to the 2-1 connection line CL2-1 through the 2-2 contact hole CH2-2 formed in the second planarization layer 127 and the fourth passivation layer 126.

[0185] First, the second buffer layer 121 may be disposed on the substrate 10 for preventing water penetration or increasing adhesion to the second semiconductor layer 122 .

[0186] The second buffer layer 121 may include an organic material or an inorganic material, and may be formed of at least two layers.

[0187] A first contact hole CH1 may be formed in the second buffer layer 121, and a first connection line CL1 may be disposed in the first contact hole CH1. The first connection line CL1 disposed in the second buffer layer 121 may be connected to the second terminal of the first transistor T1.

[0188] In this case, the first connection line CL1 disposed in the first pixel circuit layer 110 and the first connection line CL2 disposed in the second pixel circuit layer 120 may be disposed as one body, or as shown in FIG. Figure 5 , Figure 8 and Fig.11 As shown, the first connection line CL1 disposed in the first pixel circuit layer 110 and the first connection line CL2 disposed in the second pixel circuit layer 120 may be disposed as two lines that are independently disposed and electrically connected to each other.

[0189] Subsequently, the second semiconductor layer 122 may be disposed in a region in which the first transistor T1 and the second transistor T2 are disposed. The second semiconductor layer 122 may include a polysilicon material.

[0190] The second semiconductor layer 122 according to the embodiment may include a plurality of channel regions and a plurality of high-concentration doped regions, the plurality of channel regions being arranged in a region overlapping with the first gate electrode (Gate 1) of the first transistor T1 and the fourth gate electrode (Gate 4) of the fourth transistor T4, the plurality of high-concentration doped regions being arranged at portions other than the channel regions. The high-concentration doped regions may be arranged at both ends of the channel region.

[0191] Each of the plurality of channel regions may be used as a semiconductor layer of each of the first transistor T1 and the fourth transistor T4.

[0192] The high-concentration doped region may include metal characteristics, and may function as a first terminal or a second terminal of each of the first transistor T1 and the fourth transistor T4 .

[0193] For example, in Fig.11 In the illustrated cross-sectional surface, channel regions corresponding to the first gate electrode (Gate 1) and the fourth gate electrode (Gate 4) are not illustrated, and only a high-concentration doped region is illustrated.

[0194] Subsequently, a second gate insulating layer 123 may be formed over the entire substrate 10 to cover the second semiconductor layer 122. The second gate insulating layer 123 according to an embodiment may include SiOx, SiNx, or a multilayer thereof.

[0195] Subsequently, the second gate electrode layer 124 may be disposed on the second gate insulating layer 123. The second gate electrode layer 124 may include a first gate electrode (Gate 1) and a fourth gate electrode (Gate 4).

[0196] The second gate electrode layer 124 may include a single layer or multiple layers of one of metals such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), etc., or an alloy thereof.

[0197] Subsequently, a third passivation layer 125 may be formed over the entire surface of the substrate 10 to cover the second gate electrode layer 124. The third passivation layer 125 may include SiOx, SiNx, or a multilayer thereof.

[0198] Subsequently, the 3-1st connection line CL3 - 1 may be connected to the third node n3 through the 3-1st contact hole CH3 - 1 formed in the third passivation layer 125 , the second gate insulating layer 123 , the second buffer layer 121 , the first planarization layer 117 , the second passivation layer 116 , and the first passivation layer 115 .

[0199] The 3-1th connection line CL3 - 1 may be connected to a first terminal of the fourth transistor T4 included in the second pixel circuit layer 120 .

[0200] Subsequently, the 2-1st connection line CL2 - 1 may be connected to the second node n2 through the 2-1st contact hole CH2 - 1 formed in the third passivation layer 125 , the second gate insulating layer 123 , the second buffer layer 121 , the first planarization layer 117 , and the second passivation layer 116 .

[0201] The 2-1th connection line CL2 - 1 may be connected to the second terminal of the fourth transistor T4 included in the second pixel circuit layer 120 .

[0202] Subsequently, a fourth passivation layer 126 may be formed over the entire substrate 10 to cover the 3-1st connection line CL3-1 and the 2-1st connection line CL2-1. The fourth passivation layer 126 may include SiOx, SiNx, or a multilayer thereof.

[0203] A source-drain electrode SD serving as a source or a drain of each of the first transistor T1 and the fourth transistor T4 may be provided in the fourth passivation layer 126.

[0204] Subsequently, a second planarization layer 127 may be formed over the entire substrate 10 to cover the three source-drain electrodes SD. The second planarization layer 127 may include SiOx, SiNx, or a multilayer thereof.

[0205] Subsequently, the 3-2nd connection line CL3 - 2 may be connected to the 3-1st connection line CL3 - 1 through the 3-2nd contact hole CH3 - 2 formed in the second planarization layer 127 and the fourth passivation layer 126 .

[0206] The 3-2 th connection line CL3 - 2 may be connected to the second electrode of the capacitor C included in the third pixel circuit layer 130 and the second terminal of the sixth transistor T6 .

[0207] That is, the 3-2 th connection line CL3 - 2 may connect the first terminal of the fourth transistor T4 included in the second pixel circuit layer 120 to the second electrode of the capacitor C included in the third pixel circuit layer 130 and the second terminal of the sixth transistor T6 .

[0208] To provide additional description, the driving gate electrode (Gate dr) of the driving transistor Tdr included in the first pixel circuit layer 110, the first terminal of the fourth transistor T4 included in the second pixel circuit layer 120, and the second electrode of the capacitor C included in the third pixel circuit layer 130 and the second terminal of the sixth transistor T6 can be connected to each other via the 3-1 connecting line CL3-1 and the 3-2 connecting line CL3-2.

[0209] A node connected to the driving gate electrode (Gate dr) of the driving transistor Tdr, the first terminal of the fourth transistor T4, the second terminal of the sixth transistor T6, and the second electrode of the capacitor C may be a third node n3.

[0210] Finally, the 2-2nd connection line CL2 - 2 may be connected to the 2-1st connection line CL2 - 1 through the 2-2nd contact hole CH2 - 2 formed in the second planarization layer 127 and the fourth passivation layer 126 .

[0211] The 2-2 th connection line CL2 - 2 may be connected to the first terminal of the second transistor T2 included in the fourth pixel circuit layer 140 .

[0212] That is, the 2-2 th connection line CL2 - 2 may connect the second terminal of the fourth transistor T4 included in the second pixel circuit layer 120 to the first terminal of the second transistor T2 included in the fourth pixel circuit layer 140 .

[0213] To provide additional description, the second terminal of the driving transistor Tdr included in the first pixel circuit layer 110, the second terminal of the fourth transistor T4 included in the second pixel circuit layer 120, and the first terminal of the second transistor T2 included in the fourth pixel circuit layer 140 can be connected to each other through the 2-1 connection line CL2-1 and the 2-2 connection line CL2-2.

[0214] A node connected to the second terminal of the driving transistor Tdr, the second terminal of the fourth transistor T4, and the first terminal of the second transistor T2 may be a second node n2.

[0215] Fig.12 It is shown Figure 2 A diagram of a third pixel circuit shown in FIG. Fig.13 It is shown that Fig.12 A diagram of a layout of a third pixel circuit layer of a third pixel circuit shown in FIG. Fig.14 is along Fig.13 The cross-sectional view is taken along the line CC' shown. That is, Fig.12 A third pixel circuit PC3 included in one pixel is shown, Fig.13shows a horizontal structure of the third pixel circuit layer 130 in one pixel, and Fig.14 The vertical structure of the third pixel circuit layer 130 in one pixel is shown.

[0216] In the light-emitting display panel according to the embodiment of the present disclosure, as Figure 12 to Figure 14 As shown, the third pixel circuit layer 130 may include a third buffer layer 131 at least partially covering the second planarization layer 127, a third semiconductor layer 132 formed on the third buffer layer 131, a third gate insulating layer 133 at least partially covering the third semiconductor layer 132, a third gate electrode layer 134 formed on the third gate insulating layer 133, a fifth passivation layer 135 at least partially covering the third gate electrode layer 134, a 3-2 connection line CL3-2 connected to the third node n3 through a 3-2 contact hole CH3-2 formed in the fifth passivation layer 135, the third gate insulating layer 133, the third buffer layer 131, the second planarization layer 127, and the fourth passivation layer 126, and a 3-2 connection line CL3-2 connected to the third node n3 through a 3-2 contact hole CH3-2 formed in the fifth passivation layer 135, the third gate insulating layer 133, the third buffer layer 131, the second planarization layer 127, and the fourth passivation layer 126. a 2-2 connection line CL2-2 connected to the node n2 through the 2-2 contact hole CH2-2 formed in the sixth passivation layer 136 at least partially covering the fifth passivation layer 135, a 4-1 connection line CL4-1 connected to the second terminal of the fifth transistor T5 through the 4-1 contact hole CH4-1 formed in the sixth passivation layer 136, the fifth passivation layer 135, and the third gate insulating layer 133, a third planarization layer 137 at least partially covering the 4-1 connection line CL4-1, a 2-3 connection line CL2-3 connected to the 2-2 connection line CL2-2 through the 2-3 contact hole CH2-3 formed in the third planarization layer 137 and the sixth passivation layer 136, and a 4-2 connection line CL4-2 connected to the 4-1 connection line CL4-1 through the 4-2 contact hole CH4 formed in the third planarization layer 137.

[0217] First, the third buffer layer 131 may be disposed on the substrate 10 for preventing water penetration or increasing adhesion to the third semiconductor layer 132 .

[0218] The third buffer layer 131 may include an organic material or an inorganic material, and may be formed of at least two layers.

[0219] A 3-2nd contact hole CH3-2 may be formed in the third buffer layer 131, and a 3-2nd connection line CL3-2 may be disposed in the 3-2nd contact hole CH3-2. The 3-2nd connection line CL3-2 disposed in the third buffer layer 131 may be connected to the driving gate electrode of the driving transistor Tdr.

[0220] The initialization voltage line IVL may be disposed between the third buffer layer 131 and the second planarization layer 127 .

[0221] Subsequently, a third semiconductor layer 132 may be disposed in a region in which the fifth transistor T5 and the sixth transistor T6 are disposed. The third semiconductor layer 132 may include a polysilicon material.

[0222] The third semiconductor layer 132 according to the embodiment may include a plurality of channel regions and a plurality of high-concentration doped regions, the plurality of channel regions being arranged in a region overlapping with a fifth gate electrode (Gate 5) of the fifth transistor T5 and a sixth gate electrode (Gate 6) of the sixth transistor T6, the plurality of high-concentration doped regions being arranged at portions other than the channel regions. The high-concentration doped regions may be arranged at both ends of the channel region.

[0223] Each of the plurality of channel regions may serve as a semiconductor layer of each of the fifth transistor T5 and the sixth transistor T6 .

[0224] The high-concentration doped region may include metal characteristics, and may function as a first terminal or a second terminal of each of the fifth transistor T5 and the sixth transistor T6 .

[0225] For example, in Fig.14 In the cross-sectional surface shown, channel regions corresponding to the fifth gate electrode (Gate 5) and the sixth gate electrode (Gate 6) and a high-concentration doped region connected only to the channel region are shown.

[0226] In particular, one end (i.e., the high-concentration doped region) of the third semiconductor layer 132 constituting the fifth transistor T5 may be connected to the initialization voltage line IVL to constitute the first terminal of the fifth transistor T5, and the other end (i.e., the other high-concentration doped region) of the third semiconductor layer 132 constituting the fifth transistor T5 may constitute the second terminal of the fifth transistor T5. The second terminal of the fifth transistor T5 may be connected to the second terminal of the second transistor T2 through the 4-1st connecting wire CL4-1 and the 4-2nd connecting wire CL4-2.

[0227] Subsequently, a third gate insulating layer 133 may be formed over the entire substrate 10 to cover the third semiconductor layer 132. The third gate insulating layer 133 according to an embodiment may include SiOx, SiNx, or a multilayer thereof.

[0228] Subsequently, a third gate electrode layer 134 may be disposed on the third gate insulating layer 133. The third gate electrode layer 134 may include a fifth gate electrode (Gate 5) and a sixth gate electrode (Gate 6).

[0229] The third gate electrode layer 134 may include a single layer or multiple layers of one of metals such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), etc., or an alloy thereof.

[0230] Subsequently, a fifth passivation layer 135 may be formed over the entire substrate 10 to cover the third gate electrode layer 134. The fifth passivation layer 135 may include SiOx, SiNx, or a multi-layer thereof.

[0231] Subsequently, the 3-2nd connection line CL3 - 2 may be connected to the third node n3 through the 3-2nd contact hole CH3 - 2 formed in the fifth passivation layer 135 , the third gate insulating layer 133 , the third buffer layer 131 , the second planarization layer 127 , and the fourth passivation layer 126 .

[0232] The 3-2 th connection line CL3 - 2 may be connected to the second electrode of the capacitor C included in the third pixel circuit layer 130 and the second terminal of the sixth transistor T6 .

[0233] That is, the 3-2 th connection line CL3 - 2 may connect the first terminal of the fourth transistor T4 included in the second pixel circuit layer 120 to the second electrode of the capacitor C included in the third pixel circuit layer 130 and the second terminal of the sixth transistor T6 .

[0234] To provide additional description, the driving gate electrode (Gate dr) of the driving transistor Tdr included in the first pixel circuit layer 110, the first terminal of the fourth transistor T4 included in the second pixel circuit layer 120, and the second electrode of the capacitor C included in the third pixel circuit layer 130 and the second terminal of the sixth transistor T6 can be connected to each other via the 3-1 connecting line CL3-1 and the 3-2 connecting line CL3-2.

[0235] A node connected to the driving gate electrode (Gate dr) of the driving transistor Tdr, the first terminal of the fourth transistor T4, the second terminal of the sixth transistor T6, and the second electrode of the capacitor C may be a third node n3.

[0236] Subsequently, the 2-2nd connection line CL2 - 2 may be connected to the second node n2 through the 2-2nd contact hole CH2 - 2 formed in the fifth passivation layer 135 , the third gate insulating layer 133 , the third buffer layer 131 , the second planarization layer 127 , and the fourth passivation layer 126 .

[0237] The 2-2 th connection line CL2 - 2 may be connected to the first terminal of the second transistor T2 included in the fourth pixel circuit layer 140 .

[0238] That is, the 2-2 th connection line CL2 - 2 may connect the second terminal of the fourth transistor T4 included in the second pixel circuit layer 120 to the first terminal of the second transistor T2 included in the fourth pixel circuit layer 140 .

[0239] To provide additional description, the second terminal of the driving transistor Tdr included in the first pixel circuit layer 110, the second terminal of the fourth transistor T4 included in the second pixel circuit layer 120, and the first terminal of the second transistor T2 included in the fourth pixel circuit layer 140 can be connected to each other through the 2-1 connection line CL2-1 and the 2-2 connection line CL2-2.

[0240] A node connected to the second terminal of the driving transistor Tdr, the second terminal of the fourth transistor T4, and the first terminal of the second transistor T2 may be a second node n2.

[0241] Subsequently, a sixth passivation layer 136 may be formed over the entire substrate 10 to cover the 3-2nd and 2-2nd connection lines CL3-2 and CL2-2. The sixth passivation layer 136 may include SiOx, SiNx, or a multilayer thereof.

[0242] Subsequently, the 4-1st connection line CL4 - 1 may be connected to the second terminal of the fifth transistor T5 through the 4-1st contact hole CH4 - 1 formed in the sixth passivation layer 136 , the fifth passivation layer 135 , and the third gate insulating layer 133 .

[0243] Subsequently, a third planarization layer 137 may be formed over the entire substrate 10 to cover the 4-1 th connection line CL4-1. The third planarization layer 137 may include SiOx, SiNx, or a multilayer thereof.

[0244] Subsequently, the 2-3rd connection line CL2 - 3 may be connected to the 2-2nd connection line CL2 - 2 through the 2-3rd contact hole CH2 - 3 formed in the third planarization layer 137 and the sixth passivation layer 136 .

[0245] The 2-3 th connection line CL2 - 3 may be connected to the first terminal of the second transistor T2 included in the fourth pixel circuit layer 140 .

[0246] That is, the 2-3rd connection line CL2 - 3 may connect the second terminal of the fourth transistor T4 included in the second pixel circuit layer 120 to the first terminal of the second transistor T2 included in the fourth pixel circuit layer 140 .

[0247] To provide additional description, the second terminal of the driving transistor Tdr included in the first pixel circuit layer 110, the second terminal of the fourth transistor T4 included in the second pixel circuit layer 120, and the first terminal of the second transistor T2 included in the fourth pixel circuit layer 140 can be connected to each other via the 2-1st connecting line CL2-1, the 2-2nd connecting line CL2-2, and the 2-3rd connecting line CL2-3.

[0248] A node connected to the second terminal of the driving transistor Tdr, the second terminal of the fourth transistor T4, and the first terminal of the second transistor T2 may be a second node n2.

[0249] Finally, the 4-2 th connection line CL4 - 2 may be connected to the 4-1 th connection line CL4 - 1 through the 4-2 th contact hole CH4 - 2 formed in the third planarization layer 137 .

[0250] The 4-2 th connection line CL4 - 2 may be connected to the second terminal of the second transistor T2 included in the fourth pixel circuit layer 140 .

[0251] That is, the 4-2 th connection line CL4 - 2 may connect the second terminal of the fifth transistor T5 included in the third pixel circuit layer 130 to the second terminal of the second transistor T2 included in the fourth pixel circuit layer 140 .

[0252] A node connected to the second terminal of the second transistor T2, the second terminal of the fifth transistor T5, and the pixel driving electrode AE ​​(anode electrode) of the light emitting device ED may be a fourth node n4.

[0253] The capacitor C included in the third pixel circuit layer 130 may include a metal formed in the fifth passivation layer 135 together with the second 2-2 connection line CL2-2, and a metal formed in the sixth passivation layer 136 together with the 4-1 connection line CL4-1. Here, the metal formed in the fifth passivation layer 135 may be the first metal (or the second metal), and the metal formed in the sixth passivation layer 136 may be the second metal (or the first metal).

[0254] A first electrode of the capacitor C may be connected to a first terminal of the first transistor T1 included in the first pixel circuit layer 110 through a capacitor connecting line, and a second electrode of the capacitor C may be connected to a second terminal of the sixth transistor T6.

[0255] Fig.15 It is shown Figure 2 Schematic diagram of a fourth pixel circuit shown in FIG. Fig.16 It is shown that Fig.15 A diagram of a layout of a fourth pixel circuit layer of a fourth pixel circuit shown in FIG. Fig.17 is along Fig.16 The cross-sectional view is taken along the line D-D' shown. That is, Fig.15 A fourth pixel circuit PC1 included in one pixel is shown, Fig.16 shows a horizontal structure of the fourth pixel circuit layer 140 in one pixel, and Fig.17 The vertical structure of the fourth pixel circuit layer 140 in one pixel is shown.

[0256] In the light-emitting display panel according to the embodiment of the present disclosure, as Figures 15 to 17 As shown, the fourth pixel circuit layer 140 may include a fourth buffer layer 141 at least partially covering the third planarization layer 137, a fourth semiconductor layer 142 formed on the fourth buffer layer 141, a fourth gate insulating layer 143 at least partially covering the fourth semiconductor layer 142, a fourth gate electrode layer 144 formed on the fourth gate insulating layer 143, a seventh passivation layer 145 at least partially covering the fourth gate electrode layer 144, and a fourth passivation layer 146 formed on the seventh passivation layer 145, the fourth gate insulating layer 143, the fourth buffer layer 141, the third planarization layer 137, and the fourth semiconductor layer 142. The 2-3 contact hole CH2-3 in the sixth passivation layer 136 is connected to the 2-3 connection line CL2-3 of the second node n2, the eighth passivation layer 146 at least partially covering the seventh passivation layer 145, the 4-2 connection line CL4-2 connected to the fourth node n4 through the 4-2 contact hole CH4-2 formed in the eighth passivation layer 146, the seventh passivation layer 145, the fourth gate insulating layer 143, the fourth buffer layer 141 and the third planarization layer 137, and the fourth planarization layer 147 at least partially covering the 4-2 connection line CL4-2.

[0257] First, the fourth buffer layer 141 may be disposed on the substrate 10 for preventing water penetration or increasing adhesion to the fourth semiconductor layer 142 .

[0258] The fourth buffer layer 141 may include an organic material or an inorganic material, and may be formed of at least two layers.

[0259] Subsequently, a fourth semiconductor layer 142 may be disposed in a region in which the second transistor T2 is disposed. The fourth semiconductor layer 142 may include a polysilicon material.

[0260] The fourth semiconductor layer 142 according to the embodiment may include a channel region and a plurality of high-concentration doped regions, the channel region being disposed in a region overlapping the second gate electrode (Gate 2) of the second transistor T2, and the plurality of high-concentration doped regions being disposed at portions other than the channel region. The high-concentration doped regions may be disposed at both ends of the channel region.

[0261] The channel region may serve as a semiconductor layer of the second transistor T2 .

[0262] The high-concentration doped region may include metallic characteristics and may function as a first terminal or a second terminal of the second transistor T2 .

[0263] For example, in Fig.17 In the cross-sectional surface shown, a channel region corresponding to the second gate electrode (Gate 2) and a high-concentration doped region connected only to the channel region are shown.

[0264] Subsequently, a fourth gate insulating layer 143 may be formed over the entire surface of the substrate 10 to cover the fourth semiconductor layer 142. The fourth gate insulating layer 143 according to an embodiment may include SiOx, SiNx, or a multilayer thereof.

[0265] Subsequently, a fourth gate electrode layer 144 may be disposed on the fourth gate insulating layer 143. The fourth gate electrode layer 144 may be connected to the emission control line ECL. The fourth gate electrode layer 144 may include a second gate electrode (Gate 2).

[0266] The fourth gate electrode layer 144 may include a single layer or multiple layers including one of metals such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), etc., or an alloy thereof.

[0267] Subsequently, a seventh passivation layer 145 may be formed over the entire substrate 10 to cover the fourth gate electrode layer 144. The seventh passivation layer 145 may include SiOx, SiNx, or a multi-layer thereof.

[0268] Subsequently, the 2-3rd connection line CL2 - 3 may be connected to the second node n2 through the 2-3rd contact hole CH2 - 3 formed in the seventh passivation layer 145 , the fourth gate insulating layer 143 , the fourth buffer layer 141 , the third planarization layer 137 , and the sixth passivation layer 136 .

[0269] The 2-3 th connection line CL2 - 3 may be connected to the first terminal of the second transistor T2 included in the fourth pixel circuit layer 140 .

[0270] That is, the second terminal of the driving transistor Tdr included in the first pixel circuit layer 110, the second terminal of the fourth transistor T4 included in the second pixel circuit layer 120, and the first terminal of the second transistor T2 included in the fourth pixel circuit layer 140 can be connected to each other through the 2-1st connecting line CL2-1 and the 2-2nd connecting line CL2-2.

[0271] A node connected to the second terminal of the driving transistor Tdr, the second terminal of the fourth transistor T4, and the first terminal of the second transistor T2 may be a second node n2.

[0272] Subsequently, an eighth passivation layer 146 may be formed over the entire substrate 10 to cover the 2-3 nd connection line CL2-3. The eighth passivation layer 146 may include SiOx, SiNx, or a multilayer thereof.

[0273] Subsequently, the 4-2 th connection line CL4 - 2 may be connected to the fourth node n4 through the 4-2 th contact hole CH4 - 2 formed in the eighth passivation layer 146 , the seventh passivation layer 145 , the fourth gate insulating layer 143 , and the fourth buffer layer 141 .

[0274] The 4-2nd connection line CL4 - 2 may be connected to the 4-1st connection line CL4 - 1 included in the third pixel circuit layer 130 , and the 4-1st connection line CL4 - 1 may be connected to a terminal of the fifth transistor T5 .

[0275] In addition, the 4-2 th connection line CL4 - 2 may be connected to the pixel driving electrode AE ​​(anode electrode) included in the light emitting device layer 170 .

[0276] That is, the second terminal of the fifth transistor T5 included in the third pixel circuit layer 130, the second terminal of the second transistor T2 included in the fourth pixel circuit layer 140, and the pixel driving electrode AE ​​(anode electrode) included in the light emitting device layer 170 can be connected to each other through the 4-2nd connecting line CL4-2 and the 4-1st connecting line CL4-1.

[0277] A node connected to the second terminal of the fifth transistor T5, the second terminal of the second transistor T2, and the pixel driving electrode AE ​​(anode electrode) included in the light emitting device layer 170 may be a fourth node n4.

[0278] Finally, a fourth planarization layer 147 may be formed over the entire substrate 10 to cover the 4-2 th connection line CL4-2. The fourth planarization layer 147 may include SiOx, SiNx, or a multi-layer thereof.

[0279] Reference above Figure 3 The planarization layer 160 may be disposed on the fourth planarization layer 147 , or the fourth planarization layer 147 may perform the function of the planarization layer 160 .

[0280] The features of the present disclosure described above will be briefly described below.

[0281] In the present disclosure, seven transistors and one capacitor may be separately disposed at four layers, and the circuits disposed in the four layers may be connected to each other by including contact holes in the four layers.

[0282] In this case, since the planarization layer is disposed on the top surface of each layer, each layer may be separated by the planarization layer.The planarization layer may include an organic material or an inorganic material, or may be formed of a combination of an organic material and an inorganic material.

[0283] At the outer portion of the pixel, the same lines separately provided in a plurality of layers may be connected to each other.

[0284] In this case, in each of the second pixel circuit layer 120, the third pixel circuit layer 130 and the fourth pixel circuit layer 140, a plurality of scan control lines for transmitting scan control signals may be formed to at least partially overlap with the semiconductor layer to prevent the semiconductor layer included in each layer from being affected by the signal transmitted from the layer therebelow.

[0285] That is, the semiconductor layer constituting the transistors included in each of the second pixel circuit layer 120, the third pixel circuit layer 130 and the fourth pixel circuit layer 140 can be formed to at least partially overlap with the multiple scanning control lines included in each of the second pixel circuit layer 120, the third pixel circuit layer 130 and the fourth pixel circuit layer 140.

[0286] In order to ensure an area for disposing circuits, the number of gate lines in the first pixel circuit layer 110 including the driving transistor Tdr may be minimized. That is, the first pixel circuit layer 110 may include only the n-th scan control line SCL(n).

[0287] The fifth transistor T5 and the sixth transistor T6 connected to the initialization voltage line Vini may be disposed on the same layer, and thus, use of space may be increased, and the capacitor C may be included in the third pixel circuit layer 130 .

[0288] Since the fourth node n4 should be connected to the anode electrode of the light emitting device ED, the fourth node n4 may be included in the uppermost layer (ie, the fourth pixel circuit layer 140 ) together with the second transistor T2 .

[0289] In order to prevent the driving transistor Tdr from being affected by the capacitor C, the driving transistor Tdr and the capacitor C may be separated from each other to the greatest extent. That is, in the present disclosure, the driving transistor Tdr may be included in the first pixel circuit layer 110 , and the capacitor C may be included in the third pixel circuit layer 130 .

[0290] To provide additional description, since the driving transistor Tdr occupies a larger area than each other transistor and the capacitor C preferably has a large area, the driving transistor Tdr and the capacitor C can be set on different layers, so that the area of ​​each of the driving transistor Tdr and the capacitor C can be ensured to the greatest extent.

[0291] In the present disclosure, in order to prevent interference caused by a layer disposed under each pixel circuit layer, in each of the second pixel circuit layer 120, the third pixel circuit layer 130 and the fourth pixel circuit layer 140, the semiconductor layers 112, 122, 132 and 142 may be under the gate electrode layers 114, 124, 134 and 144.

[0292] Furthermore, according to the present disclosure, in a high-resolution light-emitting display device, an internal compensation circuit including seven transistors and one capacitor may be implemented.

[0293] In the embodiment of the present disclosure, it is described that all transistors included in the pixel driving circuit PDC are implemented as P-type, but the present disclosure is not limited thereto. Therefore, without departing from the technical feature of the present disclosure in which an ultra-high resolution pixel is implemented by stacking two circuit layers, all transistors may be modified to N-type, or some transistors may be modified to N-type.

[0294] The light-emitting display device to which the present invention is applied can be applied to portable electronic devices requiring high resolution, such as smartphones, mobile communication terminals, mobile phones, tablet personal computers (PCs), smart watches, watch phones and wearable devices, home appliances such as televisions, notebook computers, monitors and refrigerators, and various products such as virtual image display devices and head-mounted display devices.

[0295] In the light-emitting display panel according to the present disclosure, a plurality of transistors constituting a pixel driving circuit can be separately arranged at four layers. Therefore, even in the case where the size of each pixel is reduced by achieving high resolution, a pixel driving circuit can be sufficiently provided in each pixel, thereby implementing a high-resolution light-emitting display panel.

[0296] The above-mentioned features, structures and effects of the present disclosure are included in at least one embodiment of the present disclosure, but are not limited to one embodiment. In addition, those skilled in the art can implement the features, structures and effects described in at least one embodiment of the present disclosure by combining or modifying other embodiments. Therefore, the contents associated with the combination and modification should be interpreted as being within the scope of the present disclosure.

[0297] It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, it is intended that the present disclosure cover modifications and variations of the present disclosure as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. A light-emitting display panel, comprising: Multiple pixels, in Each of the plurality of pixels comprises: A first pixel circuit layer, which includes a first pixel circuit constituting a pixel driving circuit; A second pixel circuit layer, which is disposed on the first pixel circuit layer, and the second pixel circuit layer includes a second pixel circuit constituting the pixel driving circuit; A third pixel circuit layer, which is disposed on the second pixel circuit layer, and the third pixel circuit layer includes a third pixel circuit constituting the pixel driving circuit; a fourth pixel circuit layer, which is disposed on the third pixel circuit layer, the fourth pixel circuit layer comprising a fourth pixel circuit constituting the pixel driving circuit; and a light emitting device layer disposed on the fourth pixel circuit layer, the light emitting device layer comprising a light emitting device electrically connected to the fourth pixel circuit, a driving transistor for controlling the amount of current flowing to the light emitting device, wherein the driving transistor is included in the first pixel circuit layer, and a capacitor for storing a threshold voltage of the driving transistor, wherein the capacitor is included in the third pixel circuit layer and is used to perform compensation for a change in the threshold voltage, wherein the first pixel circuit is configured to control the amount of current flowing to the light emitting device by using a data voltage supplied through a data line; wherein the second pixel circuit is configured to charge the data voltage supplied through the data line into the capacitor; wherein the third pixel circuit is configured to initialize the capacitor and the gate of the driving transistor; and The fourth pixel circuit is configured to perform a function of providing current to the light emitting device.

2. The light emitting display panel according to claim 1, wherein A first terminal of the driving transistor included in the first pixel circuit layer is connected to a first transistor included in the second pixel circuit layer through a first connecting line, A second terminal of the driving transistor is connected to a second terminal of a fourth transistor included in the second pixel circuit layer through a 2-1 connection line, and The gate of the driving transistor is connected to the first terminal of the fourth transistor through the 3-1 th connecting line.

3. The light emitting display panel according to claim 2, wherein The first terminal of the fourth transistor is connected to the second terminal of the sixth transistor included in the third pixel circuit layer through a 3-2 connection line, and The second terminal of the fourth transistor is connected to a first terminal of a second transistor included in the fourth pixel circuit layer through a 2-2 connecting line and a 2-3 connecting line.

4. The light emitting display panel according to claim 3, wherein: The 3-2 connection line is connected to the 3-1 connection line.

5. The light emitting display panel according to claim 3, wherein: The 2-2nd connecting line is connected to the 2-1st connecting line and the 2-3rd connecting line.

6. The light-emitting display panel according to claim 3, wherein: The third pixel circuit layer includes a fifth transistor including a first terminal connected to the first terminal of the sixth transistor and a second terminal connected to the second terminal of the second transistor included in the fourth pixel circuit layer through a 4-1 connection line.

7. The light-emitting display panel according to claim 1, wherein: The first pixel circuit comprises: a third transistor including a gate connected to an nth scan control line and a first terminal connected to a data line; and The drive transistor includes a first terminal connected to the second terminal of the third transistor.

8. The light emitting display panel according to claim 7, wherein: The second pixel circuit comprises: a first transistor including a first terminal connected to a pixel driving voltage line, a second terminal connected to the second terminal of the third transistor, and a gate connected to an emission control line; and A fourth transistor includes a gate connected to the nth scan control line, a first terminal connected to the gate of the driving transistor, and a second terminal connected to the second terminal of the driving transistor.

9. The light emitting display panel according to claim 8, wherein: The third pixel circuit comprises: a sixth transistor including a first terminal connected to an initialization voltage line, a second terminal connected to the gate of the driving transistor, and a gate connected to an n-1th scan control line; a fifth transistor including a gate connected to the nth scan control line and a first terminal connected to the initialization voltage line; and A capacitor includes a first electrode connected to the second terminal of the sixth transistor and a second electrode connected to the pixel driving voltage line.

10. The light emitting display panel according to claim 9, wherein: The fourth pixel circuit includes a second transistor including a gate connected to the emission control line, a first terminal connected to the second terminal of the driving transistor, and a second terminal connected to the light emitting device.

11. The light emitting display panel according to claim 1, wherein: The semiconductor layer constituting the transistors included in each of the second pixel circuit layer, the third pixel circuit layer, and the fourth pixel circuit layer is formed to overlap with a plurality of scanning control lines included in each of the second pixel circuit layer, the third pixel circuit layer, and the fourth pixel circuit layer.

12. A display device, comprising: A display panel comprising a plurality of pixels, wherein each of the plurality of pixels comprises: A first pixel circuit layer, which includes a first pixel circuit constituting a pixel driving circuit; A second pixel circuit layer, which is disposed on the first pixel circuit layer, and the second pixel circuit layer includes a second pixel circuit constituting the pixel driving circuit; A third pixel circuit layer, which is disposed on the second pixel circuit layer, and the third pixel circuit layer includes a third pixel circuit constituting the pixel driving circuit; a fourth pixel circuit layer, which is disposed on the third pixel circuit layer, the fourth pixel circuit layer comprising a fourth pixel circuit constituting the pixel driving circuit; and a light emitting device layer disposed on the fourth pixel circuit layer, the light emitting device layer comprising a light emitting device electrically connected to the fourth pixel circuit, a driving transistor for controlling the amount of current flowing to the light emitting device, wherein the driving transistor is included in the first pixel circuit layer, and a capacitor for storing a threshold voltage of the driving transistor, wherein the capacitor is included in the third pixel circuit layer and is used to perform compensation for a change in the threshold voltage, wherein the first pixel circuit is configured to control the amount of current flowing to the light emitting device by using a data voltage supplied through a data line; wherein the second pixel circuit is configured to charge the data voltage supplied through the data line into the capacitor; wherein the third pixel circuit is configured to initialize the capacitor and the gate of the driving transistor; and The fourth pixel circuit is configured to perform a function of providing current to the light emitting device.

13. The display device according to claim 12, wherein: A first terminal of the driving transistor included in the first pixel circuit layer is connected to a first transistor included in the second pixel circuit layer through a first connection line; A second terminal of the driving transistor is connected to a second terminal of a fourth transistor included in the second pixel circuit layer through a second connecting line; and The gate of the driving transistor is connected to the first terminal of the fourth transistor through a third connecting line.

14. The display device according to claim 13, wherein: The first terminal of the fourth transistor is connected to the second terminal of a sixth transistor included in the third pixel circuit layer through a fifth connection line; and The second terminal of the fourth transistor is connected to the first terminal of the second transistor included in the fourth pixel circuit layer through a sixth connection line and a seventh connection line.

15. The display device according to claim 14, wherein: The fifth connection line is connected to the third connection line.

16. The display device according to claim 14, wherein: The sixth connection line is connected to the second connection line and the seventh connection line.

17. The display device according to claim 14, wherein: The third pixel circuit layer includes a fifth transistor, and the fifth transistor includes: a first terminal connected to the first terminal of the sixth transistor; and a second terminal connected to the second terminal of the second transistor included in the fourth pixel circuit layer through an eighth connection line.

18. The display device according to claim 12, wherein: The first pixel circuit comprises: a third transistor including a gate connected to an nth scan control line and a first terminal connected to a data line; and the driving transistor including a first terminal connected to the second terminal of the third transistor, Wherein, the second pixel circuit comprises: a first transistor including a first terminal connected to a pixel driving voltage line, a second terminal connected to the second terminal of the third transistor, and a gate connected to an emission control line; and A fourth transistor includes a gate connected to the nth scan control line, a first terminal connected to the gate of the driving transistor, and a second terminal connected to the second terminal of the driving transistor.

19. The display device according to claim 18, wherein: The third pixel circuit comprises: a sixth transistor including a first terminal connected to an initialization voltage line, a second terminal connected to the gate of the driving transistor, and a gate connected to an n-1th scan control line; a fifth transistor including a gate connected to the nth scan control line and a first terminal connected to the initialization voltage line; and A capacitor includes a first electrode connected to the second terminal of the sixth transistor and a second electrode connected to the pixel driving voltage line.

20. The display device according to claim 19, wherein: The fourth pixel circuit includes a second transistor including a gate connected to the emission control line, a first terminal connected to the second terminal of the driving transistor, and a second terminal connected to the light emitting device.

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