Semiconductor structure manufacturing method and computer readable storage medium

Abstract

Embodiments of the present invention relate to a method for manufacturing a semiconductor structure and a computer-readable storage medium. The present disclosure relates to a method for manufacturing a semiconductor structure. The manufacturing method includes the following operations. Preset process parameters of the semiconductor structure are obtained. The semiconductor structure is divided into a plurality of units. A first parameter is assigned to a portion of the unit, and a second parameter is assigned to another portion of the unit. A first simulation event and a second simulation event are obtained respectively. A process simulation is performed, wherein the process simulation performs a first simulation event for the unit having the first parameter and a second simulation event for the unit having the second parameter. The preset process parameters are adjusted based on the simulation results. A process of the semiconductor structure is performed.

Description

Technical Field

[0001] The present disclosure relates to a manufacturing method, and more particularly to a manufacturing method of a semiconductor structure and a computer-readable storage medium. Background Art

[0002] Wafer fabrication facilities may use a variety of processing operations to manufacture or finish semiconductor wafers. These processing operations and associated fabrication tools may involve techniques such as deposition, polishing, lapping, thermal oxidation, diffusion, ion implantation, epitaxy, etching, and photolithography. Within each operation, metrology tools may be used to monitor the quality and yield of the product (e.g., semiconductor wafer). Summary of the Invention

[0003] An embodiment of the present disclosure discloses a method for manufacturing a semiconductor structure, comprising: obtaining preset process parameters of the semiconductor structure; dividing the semiconductor structure into a plurality of units; assigning a first parameter to a portion of the unit and a second parameter to another portion of the unit; respectively obtaining a first simulation event and a second simulation event; performing a process simulation, wherein the process simulation performs the first simulation event for the unit having the first parameter and the second simulation event for the unit having the second parameter; adjusting the preset process parameters based on the simulation results; and performing a process on the semiconductor structure.

[0004] Another embodiment of the present disclosure discloses a method for manufacturing a semiconductor structure, comprising: performing a process on the semiconductor structure according to preset process parameters; obtaining process parameters; dividing the semiconductor structure into a plurality of units; assigning a first parameter to a portion of the unit and a second parameter to another portion of the unit; obtaining a first simulation event and a second simulation event respectively according to the process parameters; performing a process simulation, wherein the process simulation performs the first simulation event on the unit having the first parameter and performs the second simulation event on the unit having the second parameter; obtaining simulation results; and adjusting the preset process parameters according to the simulation results.

[0005] Another embodiment of the present disclosure discloses a computer-readable storage medium storing at least one program. When a computer loads and executes the program, a semiconductor process simulation method can be completed. The simulation method includes: obtaining preset process parameters of a semiconductor structure; dividing the semiconductor structure into multiple units; assigning a first parameter to a part of the unit and assigning a second parameter to another part of the unit; obtaining a first simulation event and a second simulation event respectively according to the preset process parameters; performing a process simulation, wherein the process simulation performs the first simulation event for the unit having the first parameter and performs the second simulation event for the unit having the second parameter; and obtaining a simulation result. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 A flow chart illustrating a method for fabricating a semiconductor structure according to some embodiments of the present disclosure is shown.

[0008] Figure 2A FIG2 is a top view illustrating a certain stage of a semiconductor structure according to the present disclosure in some embodiments.

[0009] Figure 2B for Figure 2A The semiconductor structure shown in the dotted box is a schematic cross-sectional view along line AA.

[0010] Figure 3 To illustrate how the semiconductor structure according to the present disclosure may be configured in some embodiments, Figure 2B Schematic top view of the reaction surface.

[0011] Figure 4 To illustrate how the semiconductor structure according to the present disclosure may be configured in some embodiments, Figure 3 Schematic top view of the reaction surface.

[0012] Figure 5 To illustrate a certain stage of a semiconductor structure according to the present disclosure in some embodiments, Figure 2A Schematic diagram of the cross section of the AA line.

[0013] Figure 6 The flowchart is for illustrating a method for manufacturing a semiconductor structure according to other embodiments of the present disclosure. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing the different features of the provided theme. The specific examples of components and arrangements are described below to simplify this disclosure. These are merely examples and are not intended to be restrictive. For example, in the following description, a first component is formed above or on a second component and may include an embodiment in which the first component and the second component are formed as direct contacts, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not directly contact. In addition, this disclosure may repeat element symbols and / or letters in various examples. This repetition is for simple and clear purposes, and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0015] The following describes embodiments of the present disclosure in detail. However, it should be understood that the present disclosure provides many applicable inventive concepts that can be embodied in a variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the present disclosure.

[0016] In addition, for ease of description, spatially relative terms (e.g., "below," "below," "down," "above," "up," "down," "left," "right," etc.) may be used herein to describe the relationship of one element or component to another element or components, as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be oriented in other ways (rotated 90 degrees or into other orientations), and therefore the spatially relative descriptors used herein should be interpreted similarly. It will be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected or coupled to the other element, or intervening elements may be present.

[0017] Semiconductor device fabrication methods may include multiple operations. These operations and associated fabrication tools or equipment may involve techniques such as deposition, polishing, lapping, thermal oxidation, diffusion, ion implantation, epitaxy, etching, and photolithography. During each of these technically related operations, structural parameter deviations may occur due to varying conditions. For example, during deposition, epitaxy, or etching processes, random deviations in the resulting structure (e.g., shape) may occur due to material properties, process conditions, or other factors.

[0018] The present disclosure provides a method for fabricating a semiconductor structure to address the aforementioned issues. The disclosed method can divide the semiconductor structure into multiple units and assign different or identical parameters to each unit. Process simulations are then performed on each unit using different simulation events corresponding to the different parameters. The simulation results can be used to predict the shape of the semiconductor structure, thereby adjusting and correcting process parameters to mitigate parameter deviations (e.g., geometric parameters (shape)).

[0019] Figure 1FIG. 1 is a flow chart illustrating a method 100 for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0020] Please refer to Figure 1 As shown, in some embodiments, the method 100 for fabricating a semiconductor structure includes operation 102 , operation 104 , operation 106 , operation 108 , operation 110 , operation 112 , and operation 114 .

[0021] Figure 2A The figure illustrates a top view of a semiconductor structure 200 at a certain stage according to the present disclosure in some embodiments. The semiconductor structure 200 may include, but is not limited to, a silicon substrate, for example. In the case of a silicon substrate, the semiconductor structure 200 may further include other semiconductor materials, such as silicon germanium, silicon carbide, or gallium arsenide. In the present embodiment, the semiconductor structure 200 comprises a p-type semiconductor substrate (P-substrate) or an n-type semiconductor substrate (N-substrate) of silicon. Alternatively, the semiconductor structure 200 includes another elemental semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. In other alternative embodiments, the semiconductor structure 200 may include a doped epitaxial layer, a gradient semiconductor layer, and / or a semiconductor layer above another semiconductor layer of a different type, such as a silicon layer on a silicon germanium layer.

[0022] Figure 2B for Figure 2A The cross-sectional view of the semiconductor structure 200 along the line AA is shown in the dotted box. Figure 1 、 2A As shown in Figures 2B and 2B, in operation 102, preset process parameters of the semiconductor structure 200 may be obtained. In the semiconductor structure 200, for example, but not limited to, a semiconductor material may form a reaction surface 204. The semiconductor material may include, for example, a crystalline phase material grown during an epitaxial growth process or a thin film deposition process of the semiconductor structure 200, or a semiconductor material etched during an etching process of the semiconductor structure 200. In some embodiments, the semiconductor material may include, for example, silicon, germanium, or other materials with a matching lattice structure. In some embodiments, the reaction surface 204 may be formed by molecules 202 of the semiconductor material. It is worth mentioning that the reaction surface 204 may be formed using atoms, lattice units, or other basic units that undergo reactions.

[0023] In some embodiments, a computer or server may be used to execute Figure 1 Some or all of the operations of the method shown. For example, but not limited to, using a simulator to perform Figure 1Multiple simulation methods can be used to perform some or all of the operations of the method shown. Figure 1 Part or all of the operations of the method shown may be performed using, for example but not limited to, a Lattice Kinetic Monte Carlo model, in which each molecule 202 on the reaction surface 204 of the semiconductor structure 200 may be displayed in a spherical manner.

[0024] In some embodiments, processes that can be simulated include, but are not limited to, epitaxial processes, thin film deposition processes, and etching processes. Therefore, the preset process parameters of the semiconductor structure 200 include, but are not limited to, preset parameters of deposition, epitaxy, or etching processes. For example, preset parameters include the growth rate of a deposition process, the growth rate of an epitaxy process, the gas concentration of an epitaxy process, and the etching rate of an etching process.

[0025] Figure 3 To illustrate how the semiconductor structure 200 according to the present disclosure may be configured in some embodiments, Figure 2B Please refer to the top view of the reaction surface 204. Figure 1 and Figure 3 As shown, in operation 104, the semiconductor structure 200 is divided into a plurality of units 2021. In some embodiments, the units 2021 are, for example, Figure 2B The molecules 202 are shown as units for differentiation. In other embodiments, the units 2021 may also be differentiated by atoms, lattice units, or other basic units for reactions, which are not intended to limit the present disclosure.

[0026] Figure 4 To illustrate how the semiconductor structure 200 according to the present disclosure may be configured in some embodiments, Figure 3 Please refer to the top view of the reaction surface 204. Figure 1 and Figure 4 As shown, in operation 106, parameter 1 is assigned to a portion of the unit 2021, parameter 2 is assigned to a portion of the unit 2021, parameter 3 is assigned to a portion of the unit 2021, and parameter 4 is assigned to another portion of the unit 2021. It is worth noting that this embodiment uses parameter 1, parameter 2, parameter 3, and parameter 4 as examples for illustration, but this is not limiting. In some embodiments, more or fewer parameters may be included.

[0027] The parameter allocation may be performed by, for example but not limited to, allocating or assigning attributes related to the parameters to different locations of the reaction surface 204 of the semiconductor structure 200 .

[0028] It should be noted that the number of parameters is related to the simulation events of the semiconductor structure and can be set by the user. For example, if the number of subsystems containing parameters is K, then the selection of parameter i is 1≦i≦K. That is, the parameters assigned to the unit 2021 may be 1, 2...K. In some embodiments, the number of parameters may correspond to the number of groups that are calculated (parallel operations) simultaneously preset by the user. For example, if the unit 2021 is preset to be divided into 4 groups for parallel operation, then the number of parameters is 4. If the unit 2021 is preset to be divided into K groups for parallel operation, then the number of parameters is K. It is non-limiting. Furthermore, the allocation of parameters can be uniformly generated from a parameter set containing all subsystems via a uniform random number generation (RNG) equation.

[0029] On the other hand, since the number of parameters is related to the number of simulation events, if the number of parameters is small (i.e., K is small), then the simulation events assigned to each parameter are more; if the number of parameters is large (i.e., K is large), then the simulation events assigned to each parameter are fewer, which will be explained below.

[0030] In operation 108, a first simulation event and a second simulation event are obtained. The first simulation event and the second simulation event each include, for example, one of a plurality of possible simulation events. The first simulation event and the second simulation event may include, for example, an atomic adsorption event, a surface passivation event, or an atomic desorption event, which are non-limiting.

[0031] It should be noted that the selection of the first and second simulated events is determined, for example, by probability. For example, each possible simulated event has its own probability of occurrence. Therefore, when selecting possible simulated events, simulated events with a higher probability of occurrence may be prioritized for selection as the first or second simulated event. In certain embodiments, the probability of a simulated event can be calculated using the following formula, which is non-limiting.

[0032]

[0033] p is a parameter related to the reaction gas pressure, molecular weight or viscosity coefficient, E a is the activation barrier of the reaction of the reactants, k is the Boltzmann constant, and T is the temperature.

[0034] In some embodiments, the first and second simulated events can be obtained simultaneously. In other words, the probability of occurrence of the possible simulated events can be calculated simultaneously, and the first and second simulated events can be obtained. Furthermore, this embodiment uses the first and second simulated events as examples for illustration, but this is not intended to be limiting. In some embodiments, more or fewer simulated events may be included.

[0035] In operation 110, a process simulation is performed. The process simulation performs a first simulation event for the cell 2021 with parameter 1, and a second simulation event for the cell 2021 with parameter 2. In some embodiments, a third simulation event is performed for the cell 2021 with parameter 3, and a fourth simulation event is performed for the cell 2021 with parameter 4. In some embodiments, the simulation events are different simulation events. Furthermore, as described above, the number of parameters is related to the number of simulation events. If the number of parameters is small (i.e., there are fewer groups of parallel operations), and each parameter is assigned a large number of simulation events, the calculation time may be longer due to the large number of simulation events assigned to each cell 2021. However, the accuracy of the process simulation may be improved due to the large number of simulation events available for selection. On the other hand, if the number of parameters is large (i.e., there are more groups of parallel operations), and each parameter is assigned a small number of simulation events, the calculation time may be shorter due to the small number of simulation events assigned to each cell 2021. However, the accuracy of the process simulation may be reduced due to the small number of simulation events available for selection (i.e., system distortion). It should be noted that the number of parameters is related to the number of simulation events that need to be performed, but the accuracy of process simulation is not solely determined by the number of parameters. For example, the probability of occurrence of different simulation events can also be adjusted based on their importance.

[0036] In certain embodiments, before performing a process simulation, it may be determined whether the process simulation has a conflicting event. A conflicting event, for example, includes a specific distance between one of the units 2021 performing a first simulation event and one of the units 2021 performing a second simulation event. The specific distance is, for example, greater than 0 and less than 10 times the minimum distance between the units 2021, which is non-limiting. A specific distance of 0, for example, indicates that the two units 2021 are connected to each other. A minimum distance between units 2021, for example, indicates that the two units 2021 are not connected but are adjacent to each other within the reaction influence range.

[0037] In some embodiments, if a process simulation is determined to involve a conflicting event, the first simulation event or the second simulation event for one of the units 2021 located within a specific distance is canceled. In other words, if the first simulation event and the second simulation event cannot be performed simultaneously within the specific distance or if performing them simultaneously would result in an error, then one of the first simulation event or the second simulation event is canceled, and a new simulation event is selected to replace the canceled first simulation event or the second simulation event.

[0038] In some embodiments, the process simulation may be performed simultaneously on the unit 2021 having parameters 1, 2, 3, and 4 to respectively perform a first simulation event, a second simulation event, a third simulation event, and a fourth simulation event.

[0039] Figure 5 To illustrate a certain stage of the semiconductor structure 200 according to the present disclosure in some embodiments, Figure 2A In some embodiments, after process simulation, the cross-sectional view of the AA line is shown. Figure 4 After the unit 2021 performs various simulation events, an intermediate simulation result of the semiconductor structure 200 after a preset simulation time can be obtained. The preset simulation time can be determined by the user and is not restrictive. Figure 5 As shown, the intermediate simulation result is, for example, that new molecules 206 are formed on the semiconductor structure 200 to form a new reaction surface 208 .

[0040] In some embodiments, the occurrence probabilities of the first simulation event and the second simulation event can be respectively corrected based on the intermediate simulation results. In some embodiments, the correction of the occurrence probabilities of the simulation events can be performed simultaneously. For example, in the case of a new reaction surface 208, a new simulation event may be generated between the molecule 202 and the molecule 206, or the occurrence probability of the simulation event of the molecule 202 may also need to be adjusted and corrected due to the molecule 206. In other words, if the semiconductor structure 200 of the intermediate simulation result is different from the expected result or the actual result, the occurrence probabilities of the first simulation event and the second simulation event can be adjusted, for example, the occurrence probability of the first simulation event or the second simulation event can be increased or decreased. Furthermore, the first simulation event and the second simulation event are determined by the probability of each possible simulation event. Therefore, based on the simulation results, the occurrence probability of the simulation event obtained as the first simulation event or the second simulation event can be corrected so that the type of simulation event obtained is more in line with the requirements.

[0041] In some embodiments, based on the revised probabilities of occurrence of the first and second simulation events, the process simulation may be repeated for the next predetermined simulation time. Specifically, as the semiconductor structure 200 changes during the process (e.g., from the reaction surface 204 to the reaction surface 208), the probabilities of occurrence of different simulation events may also change. Therefore, operations 108 and 110 are repeated until a predetermined termination condition (e.g., a predetermined number of simulations or a predetermined end time) is met to obtain simulation results.

[0042] Please refer to Figure 1 As shown, in operation 112, the preset process parameters are adjusted based on the simulation results. In some embodiments, if the semiconductor structure 200 of the simulation results differs from the expected results or the actual results, the preset process parameters can be adjusted to make the actual process results more consistent with the requirements.

[0043] In operation 114 , a semiconductor structure process is performed. In some embodiments, based on the adjusted preset process parameters, actual semiconductor structure processes such as, but not limited to, epitaxial growth, thin film deposition, and etching processes may be performed.

[0044] For example, in some embodiments, when forming source / drain regions in a semiconductor structure, the source / drain regions may be grown via a selective epitaxial process. The source or drain material may include, for example, but not limited to, silicon, silicon germanium, or other suitable materials (e.g., materials having a different lattice constant than the channel region). The epitaxial growth process may utilize precursors such as, but not limited to, silane, dichlorosilane, germanium, and the like.

[0045] Therefore, the disclosed semiconductor structure fabrication method can divide the source / drain region to be grown into multiple units, assign different or identical parameters to each unit, and perform process simulations on each unit using different simulation events corresponding to the different parameters. The simulation results can predict the shape of the source / drain region, thereby adjusting and correcting process parameters (such as growth time) to mitigate shape deviation issues (such as geometric parameters (shape)).

[0046] Furthermore, in some embodiments, such as in chemical vapor deposition processes, multiple gases are mixed before entering a reactor to cause a chemical reaction in the reactor and, as a result of the reaction, to deposit a solid material on a substrate. Alternatively, in some embodiments, such as in physical vapor deposition, plasma sputtering is used to eject atoms or molecules from a target material by bombardment with high-energy particles, so that the ejected atoms or molecules can condense on the substrate to form a thin film. Alternatively, in some embodiments, such as in atomic layer deposition, which is a vapor-phase chemical process, a surface-controlled growth mechanism is used to provide a dense film with few (or no) pores.

[0047] Similarly, the disclosed semiconductor structure fabrication method can divide the substrate where deposition is to be performed into multiple cells, assigning different or identical parameters to each cell. Process simulations are then performed on each cell using different simulation events corresponding to the different parameters. The simulation results can be used to predict the shape of the deposition area, thereby adjusting and correcting process parameters (e.g., material concentration) to mitigate shape deviations (e.g., geometric parameters (shape)).

[0048] In addition, in certain embodiments, such as in an etching process, the method for manufacturing a semiconductor structure disclosed herein can divide the area to be etched on the substrate into a plurality of units, and assign different or identical parameters to each unit. Corresponding to different parameters, process simulation is performed on each unit with different simulation events. Based on the simulation results, the shape of the area to be etched can be predicted, thereby adjusting and correcting process parameters (such as etchant concentration, etc.) to alleviate the problem of shape deviation of parameters (such as geometric parameters (shape)). The etching process can include a dry etching process, a wet etching process, or other etching processes.

[0049] In summary, the disclosed semiconductor structure manufacturing method can divide a semiconductor structure (e.g., a reaction surface) into multiple units, assign different or identical parameters to each unit, and perform process simulations on each unit using different simulation events corresponding to the different parameters. The simulation results can be used to predict the shape of the semiconductor structure, thereby adjusting and correcting process parameters to mitigate shape deviations (e.g., geometric parameters (shape)).

[0050] Furthermore, the disclosed method for fabricating a semiconductor structure can simultaneously perform the following operations on multiple cells on a reaction surface: obtaining simulation events, executing simulation events, and correcting the probability of occurrence of the simulation events. This can reduce the time consumption and computing resource requirements of process simulations. Furthermore, in certain embodiments, conflicting events at a specific distance can be eliminated, thereby alleviating problems such as buffer zones between adjacent cells, which can lead to errors in simulation results due to overlap, uncalculated or duplicated calculations.

[0051] Figure 6 This is a flow chart illustrating a method 600 for manufacturing a semiconductor structure according to another embodiment of the present disclosure. Figure 6 As shown, in some embodiments, the method 600 for fabricating a semiconductor structure includes operation 602 , operation 604 , operation 606 , operation 608 , operation 610 , operation 612 , operation 614 , and operation 616 .

[0052] In operation 602, a semiconductor structure is processed according to preset process parameters. In operation 604, the process parameters are obtained. In operation 606, the semiconductor structure is divided into a plurality of units. In operation 608, a first parameter is assigned to a portion of the units, and a second parameter is assigned to another portion of the units. In operation 610, a first simulation event and a second simulation event are obtained based on the process parameters. In operation 612, a process simulation is performed, wherein the first simulation event is performed for the units having the first parameters, and the second simulation event is performed for the units having the second parameters. In operation 614, simulation results are obtained. In operation 616, the preset process parameters are adjusted based on the simulation results.

[0053] Figure 6 The manufacturing method 600 and Figure 1 The difference between the manufacturing method 100 and the manufacturing method 600 is that the manufacturing method 600 first performs a process of the semiconductor structure according to the preset process parameters, then obtains the process parameters of the semiconductor structure during or after the process, and then performs simulation according to the process parameters during or after the actual process. Figure 2A 、 Figure 2B 、 Figure 3 、 Figure 4 and Figure 5 The details are described in detail in the text, so I will not repeat them here.

[0054] Therefore, the manufacturing method 600 can be simulated by using process parameters during or after the process, so that the preset process parameters can be adjusted and modified according to actual conditions to alleviate the problem of parameter (eg, geometric parameter (shape)) shape deviation.

[0055] In some embodiments of the present disclosure, a computer-readable storage medium can be used to store at least one program. When the computer loads and executes the program, a simulation method for a semiconductor process can be completed. Figure 1 、 Figure 2A 、 Figure 2B 、 Figure 3 、 Figure 4 、 Figure 5 and Figure 6 The manufacturing method 100 and the manufacturing method 600 are the same and are not described again herein.

[0056] In certain embodiments, a method for manufacturing a semiconductor structure is provided, comprising: obtaining preset process parameters of the semiconductor structure; dividing the semiconductor structure into a plurality of units; assigning a first parameter to a portion of the unit and a second parameter to another portion of the unit; obtaining a first simulation event and a second simulation event respectively according to the preset process parameters; performing a process simulation, wherein the process simulation performs the first simulation event for the unit having the first parameter and the second simulation event for the unit having the second parameter; obtaining simulation results; and performing a process of the semiconductor structure based on the simulation results.

[0057] In other embodiments, a method for manufacturing a semiconductor structure is provided, comprising: performing a process on the semiconductor structure according to preset process parameters; obtaining the process parameters; dividing the semiconductor structure into a plurality of units; assigning a first parameter to a portion of the unit, and assigning a second parameter to another portion of the unit; obtaining a first simulation event and a second simulation event respectively according to the process parameters; performing a process simulation, wherein the process simulation performs a first simulation event on the unit having the first parameter, and performs a second simulation event on the unit having the second parameter; obtaining simulation results; and adjusting the preset process parameters based on the simulation results.

[0058] In other embodiments, a computer-readable storage medium is provided, storing at least one program. When a computer loads and executes the program, a semiconductor process simulation method can be completed. The simulation method includes: obtaining preset process parameters of a semiconductor structure; dividing the semiconductor structure into multiple units; assigning a first parameter to a part of the unit, and assigning a second parameter to another part of the unit; obtaining a first simulation event and a second simulation event respectively according to the preset process parameters; performing a process simulation, wherein the process simulation is to perform the first simulation event for the unit having the first parameter, and to perform the second simulation event for the unit having the second parameter; and obtaining a simulation result.

[0059] The above summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same objectives and / or achieve the same advantages of the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

[0060] Explanation of symbols

[0061] 100, 600 Manufacturing Method

[0062] 102, 104, 106, 108, 110, 112, 114, 602, Operation 604, 606, 608, 610, 612, 614, 616

[0064] 200 Semiconductor Structure

[0065] 202, 206 molecules

[0066] 204, 208 reaction surface

[0067] 2021 Unit

Claims

1. A method for manufacturing a semiconductor structure, comprising: Obtaining preset process parameters of a semiconductor structure; The semiconductor structure is divided into a plurality of units, wherein: The unit of each of the units is a molecule, an atom or a lattice unit; assigning a first parameter to a portion of the unit and assigning a second parameter to another portion of the unit; obtaining a first simulation event and a second simulation event respectively, wherein the first simulation event and the second simulation event comprise an atomic adsorption event, a surface passivation event, or an atomic desorption event; performing a process simulation, wherein the process simulation is to perform the first simulation event on the unit having the first parameters, and to perform the second simulation event on the unit having the second parameters, wherein the first simulation event and the second simulation event are performed simultaneously; determining whether the process simulation has a conflict event, wherein the conflict event includes that a distance between one of the units performing the first simulation event and one of the units performing the second simulation event is a specific distance, and the specific distance is greater than or equal to 0 and less than or equal to 10 times a minimum distance between the units; If the answer is yes, canceling the first simulation event or the second simulation event of one of the units within the specific distance; Adjusting the preset process parameters according to the simulation results; and A process for forming the semiconductor structure is performed, wherein the process includes an epitaxial process, a thin film deposition process, and an etching process. 2 . The manufacturing method according to claim 1 , wherein the first simulation event and the second simulation event each have an occurrence probability.

3. The manufacturing method according to claim 2, further comprising: The occurrence probabilities of the first simulated event and the second simulated event are respectively revised.

4. A method for manufacturing a semiconductor structure, comprising: Performing a process for the semiconductor structure according to preset process parameters, wherein the process includes an epitaxial process, a thin film deposition process, and an etching process; Obtain process parameters; Dividing the semiconductor structure into a plurality of units, wherein the unit of each unit is a molecule, an atom or a lattice unit; assigning a first parameter to a portion of the unit and assigning a second parameter to another portion of the unit; According to the process parameters, a first simulation event and a second simulation event are respectively obtained, wherein the first simulation event and the second simulation event include an atomic adsorption event, a surface passivation event or an atomic desorption event; performing a process simulation, wherein the process simulation is to perform the first simulation event on the unit having the first parameters, and to perform the second simulation event on the unit having the second parameters, wherein the first simulation event and the second simulation event are performed simultaneously; determining whether the process simulation has a conflict event, wherein the conflict event includes that a distance between one of the units performing the first simulation event and one of the units performing the second simulation event is a specific distance, and the specific distance is greater than or equal to 0 and less than or equal to 10 times a minimum distance between the units; If the answer is yes, canceling the first simulation event or the second simulation event of one of the cells within the specific distance; obtaining a simulation result; and The preset process parameters are adjusted according to the simulation results. The manufacturing method according to claim 4 , wherein the first simulation event and the second simulation event each have an occurrence probability.

6. The manufacturing method according to claim 4, further comprising: The process of the semiconductor structure is performed according to the adjusted preset process parameters.

7. A computer-readable storage medium storing at least one program, wherein when a computer loads and executes the program, the computer can perform a semiconductor process simulation method, the simulation method comprising: Obtaining preset process parameters of a semiconductor structure; Dividing the semiconductor structure into a plurality of units, wherein the unit of each unit is a molecule, an atom or a lattice unit; assigning a first parameter to a portion of the unit and assigning a second parameter to another portion of the unit; obtaining a first simulation event and a second simulation event respectively, wherein the first simulation event and the second simulation event comprise an atomic adsorption event, a surface passivation event, or an atomic desorption event; performing a process simulation, wherein the process simulation is to perform the first simulation event on the unit having the first parameters, and to perform the second simulation event on the unit having the second parameters, wherein the first simulation event and the second simulation event are performed simultaneously; Determining whether the process simulation has a conflict event; wherein the conflict event includes a specific distance between one of the units performing the first simulation event and one of the units performing the second simulation event, and the specific distance is greater than or equal to 0 and less than or equal to 10 times the minimum distance between the units; If the answer is yes, canceling the first simulation event or the second simulation event of one of the units within the specific distance; and Get simulation results.

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