Image Sensor

Abstract

An image sensor includes: a substrate; a photoelectric conversion element disposed in the substrate and configured to generate photocharges in response to incident light; a first floating diffusion node and a second floating diffusion node disposed in the substrate to be spaced apart on opposite sides of the photoelectric conversion element; a first transfer gate disposed on the substrate to at least partially overlap the photoelectric conversion element and the first floating diffusion node; and a second transfer gate disposed on the substrate to at least partially overlap the photoelectric conversion element and the second floating diffusion node. Each of the first transfer gate and the second transfer gate includes a first gate dielectric layer at least partially overlapping the photoelectric conversion element and a second gate dielectric layer at least partially overlapping the first floating diffusion node or the second floating diffusion node. The thickness of the first gate dielectric layer is greater than the thickness of the second gate dielectric layer.

Description

Technical Field

[0001] The techniques and implementations disclosed in this patent document generally relate to an image sensor for sensing a distance to a target object. Background Art

[0002] An image sensor is a semiconductor device that captures images by utilizing the property of semiconductors to react to light. With the development of the computer industry and the communications industry, the demand for high-performance image sensing devices (e.g., smart phones, digital cameras, game consoles, the Internet of Things, robots, surveillance cameras, medical micro cameras, etc.) is increasing.

[0003] Image sensors can generally be divided into CCD (charge coupled device) image sensors and CMOS (complementary metal oxide semiconductor) image sensors. Compared with CMOS image sensors, CCD image sensors have less noise and better image quality. However, CMOS image sensors have a simpler and more convenient driving scheme, and therefore may be preferred in some applications. In addition, CMOS image sensors can integrate signal processing circuits in a single chip, so that CMOS image sensors for implementation in products can be easily miniaturized and have the additional benefit of extremely low power consumption. CMOS image sensors can be manufactured using CMOS manufacturing technology, thereby obtaining low manufacturing costs. CMOS image sensing devices are widely used because they are suitable for implementation in mobile devices. Summary of the invention

[0004] Various embodiments of the disclosed technology relate to an image sensor capable of efficiently performing a sensing operation to measure a distance. In various implementations, the time of the sensing operation of the image sensor can also be reduced.

[0005] Various objects to be achieved by the present disclosure are not limited to the above-mentioned objects, and other objects can be clearly understood from the following description by those skilled in the art to which the present disclosure belongs.

[0006] In one embodiment, an image sensor may include: a substrate; a photoelectric conversion element disposed in the substrate and configured to generate photocharges in response to incident light; a first floating diffusion node and a second floating diffusion node disposed in the substrate to be spaced apart on opposite sides of the photoelectric conversion element; a first transfer gate disposed on the substrate to at least partially overlap the photoelectric conversion element and the first floating diffusion node; and a second transfer gate disposed on the substrate to at least partially overlap the photoelectric conversion element and the second floating diffusion node. Each of the first transfer gate and the second transfer gate includes a first gate dielectric layer at least partially overlapping the photoelectric conversion element and a second gate dielectric layer at least partially overlapping the first floating diffusion node or the second floating diffusion node. The thickness of the first gate dielectric layer is greater than the thickness of the second gate dielectric layer.

[0007] In one embodiment, an image sensor may include: a substrate; a photoelectric conversion element disposed in the substrate and configured to generate photocharges in response to incident light; a first transfer gate disposed on the substrate to at least partially overlap one side of the photoelectric conversion element; a second transfer gate disposed on the substrate to at least partially overlap the other side of the photoelectric conversion element; and a photoelectric conversion gate disposed between the first transfer gate and the second transfer gate. Each of the first transfer gate and the second transfer gate includes a first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer at least partially overlaps the photoelectric conversion element and has a first thickness, and the second gate dielectric layer has a second thickness less than the first thickness. The first transfer gate is configured to receive a first transfer signal corresponding to a logic high level, the first transfer signal providing a potential distribution that increases from a lower side of the second transfer gate to a lower side of the first transfer gate.

[0008] According to the embodiments disclosed in this document, photocharge transfer efficiency and photocharge transfer speed may be improved in high-speed operation of a time-of-flight (ToF) image sensor.

[0009] Furthermore, various effects directly or indirectly understood through this document can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a diagram schematically showing a representation of an example of a configuration of an image sensor according to an embodiment of the disclosed technology.

[0011] Figure 2A It is shown Figure 1 A cross-sectional view of an embodiment of a unit pixel is shown.

[0012] Figure 2B It is shown Figure 1 FIG. 1 is a cross-sectional view of another embodiment of a unit pixel.

[0013] Figure 3A It is shown Figure 2A Cross-sectional view showing an exemplary representation of a partial region.

[0014] Figure 3B It is shown Figure 2B Cross-sectional view showing an exemplary representation of a partial region.

[0015] Figure 4 is a diagram showing an example of a potential distribution in a unit pixel during a first period.

[0016] Figure 5 is a diagram showing an example of potential distribution in a unit pixel during the second period.

[0017] Figure 6 is a diagram showing an example of potential distribution in a unit pixel during the third period.

[0018] Figure 7 is a diagram showing an example of potential distribution in a unit pixel during a fourth period. DETAILED DESCRIPTION

[0019] Hereinafter, various embodiments of the disclosed technology are described with reference to the accompanying drawings. However, this description is not intended to limit the present disclosure to a specific embodiment, and it should be construed as including various modifications, equivalents and / or replacements according to the embodiments of the present disclosure.

[0020] Figure 1 is a diagram schematically showing a representation of an example of a configuration of an image sensor according to an embodiment of the present disclosure.

[0021] Reference Figure 1 , the image sensor may measure the distance to the target object 1 by using a time-of-flight (ToF) method. Such an image sensor may include a light source 100 , a lens module 200 , a pixel array 300 , and a control circuit 400 .

[0022] The light source 100 irradiates light toward the target object 1 in response to the clock signal MLS from the control circuit 400. The light source 100 may be a laser diode (LD), a light emitting diode (LED), a near infrared laser (NIR), a point light source, a monochromatic illumination source combining a white light and a monochromator, or a combination of other laser light sources that emit light of a specific wavelength band (e.g., near infrared light, infrared light, or visible light). For example, the light source 100 may emit infrared light having a wavelength of 800 nm to 1000 nm. The light irradiated from the light source 100 may be modulated to a predetermined frequency. Although for ease of explanation, Figure 1 Only one light source 100 is shown, but it should be noted that a plurality of light sources may be arranged around the lens module 200 .

[0023] The lens module 200 may collect light reflected from the target object 1 and may focus the collected light on the pixel PX of the pixel array 300. For example, the lens module 200 may include a focusing lens or other cylindrical optical elements having a glass surface or a plastic surface. The lens module 200 may include a plurality of lenses aligned about an optical axis.

[0024] The pixel array 300 may include a plurality of unit pixels PX, and the plurality of unit pixels PX are continuously arranged in a two-dimensional matrix structure (for example, continuously arranged in the column direction and the row direction). The unit pixels PX may be formed on a semiconductor substrate. Each unit pixel PX may convert light reflected from the target object 1 and then received through the lens module 200 into an electrical signal corresponding to the intensity of the light, thereby outputting a pixel signal. The pixel signal may indicate the distance between the image sensor and the target object 1, rather than the color of the target object 1. Each unit pixel PX may be a pixel having a pinned photodiode (PPD) structure. This will be referred to later. Figure 2A A detailed structure and operation of each unit pixel PX are described.

[0025] The control circuit 400 may irradiate light to the target object 1 by controlling the light source 100 , and may process a pixel signal corresponding to the light reflected from the target object 1 by driving the unit pixel PX of the pixel array 300 to measure a distance to the surface of the target object 1 .

[0026] Such a control circuit 400 may include a row decoder 410 , a light source driver 420 , a timing controller 430 , a photogate controller 440 , and a logic circuit 450 .

[0027] The row decoder 410 may drive the unit pixel PX of the pixel array 300 in response to the timing signal output from the timing controller 430. For example, the row decoder 410 may generate a control signal capable of selecting at least one row line among a plurality of row lines. Such control signals may include a reset signal for controlling a reset transistor, a selection signal for controlling a selection transistor, and a transfer signal for controlling the operation of a transfer transistor.

[0028] The light source driver 420 may generate a clock signal MLS capable of driving the light source 100 under the control of the timing controller 430. The clock signal MLS may be a signal modulated to a predetermined frequency.

[0029] The timing controller 430 may generate timing signals for controlling operations of the row decoder 410 , the light source driver 420 , the photo gate controller 440 , and the logic circuit 450 .

[0030] The photo gate controller 440 may generate a photo gate control signal and provide the photo gate control signal to the pixel array 300 under the control of the timing controller 430. Figure 1 Only the photo gate controller 440 is described, but it should be noted that the control circuit 400 may include a photodiode controller that generates a plurality of photodiode control signals and provides the photodiode control signals to the pixel array 300 under the control of the timing controller 430 .

[0031] The logic circuit 450 may generate digital signal type pixel data by processing the pixel signal output from the pixel array 300 under the control of the timing controller 430. The logic circuit 450 may include a correlated double sampler (CDS) for performing correlated double sampling on the pixel signal output from the pixel array 300. In addition, the logic circuit 450 may include an analog-to-digital converter for converting the output signal from the correlated double sampler into a digital signal. In addition, the logic circuit 450 may include a buffer circuit for temporarily storing the pixel data output from the analog-to-digital converter and outputting the pixel data to the outside under the control of the timing controller 430.

[0032] The light source 100 may emit modulated light modulated to a predetermined frequency to a scene to be captured by the image sensor. In response to receiving the modulated light (i.e., incident light) reflected from the target object 1, the image sensor may generate depth information about each unit pixel. For example, the image sensor may measure the time taken from the emission of light from the light source to the generation of a pixel signal. The light emitted from the light source 100 is reflected from the target object 1 and reaches the photoelectric conversion element of the unit pixel, and a pixel signal is generated when the light reaches the photoelectric conversion element. In some implementations, depending on the distance between the image sensor and the target object 1, a time delay between the modulated light and the incident light may occur. This time delay is represented by a phase difference between a signal generated by the image sensor and a clock signal MLS for controlling the light source 100. An image processor (not shown) may generate a depth image including depth information about each unit pixel by calculating the phase difference represented by the signal output from the image sensor.

[0033] Figure 2A It is shown Figure 1 A view of an embodiment of a unit pixel is shown.

[0034] Reference Figure 2A , the unit pixel 500 may correspond to Figure 1Any unit pixel PX in the pixel array 300 shown.

[0035] The unit pixel 500 may include one photodiode 520 and may include two sensing circuits including a first sensing circuit and a second sensing circuit, each of which is capable of outputting an electrical signal obtained by sensing and amplifying photocharges generated at different timings to a corresponding column line. Figure 2A , a photodiode 520 is shown, but the unit pixel 500 may include other photoelectric conversion elements, such as a phototransistor, a photogate, or other photosensitive circuits capable of converting incident light into a pixel signal (e.g., charge, voltage, or current). The first sensing circuit may include a first transfer transistor, a first reset transistor, a first source follower, and a first selection transistor. Similarly, the second sensing circuit may include a second transfer transistor, a second reset transistor, a second source follower, and a second selection transistor.

[0036] The unit pixel 500 may include a substrate 510, a photodiode 520, a first floating diffusion node 530 and a second floating diffusion node 540, a first drain node 550 and a second drain node 560, a photodiode gate TD, a first transfer gate TX1 and a second transfer gate TX2, a first reset gate RST1 and a second reset gate RST2, a first source follower SF1 and a second source follower SF2, and a first selection transistor SX1 and a second selection transistor SX2. Figure 2A The structure of the unit pixel 500 shown in FIG. 5 is for illustration purposes only. In some implementations, some components may be omitted or any additional components may be added.

[0037] The first transmission transistor and the first reset transistor of the above-mentioned first sensing circuit can be configured by the first transmission gate TX1 and the first reset gate RST1, respectively, and the first source follower and the first selection transistor of the above-mentioned first sensing circuit can correspond to the first source follower SF1 and the first selection transistor SX1, respectively. The second transmission transistor and the second reset transistor of the above-mentioned second sensing circuit can be configured by the second transmission gate TX2 and the second reset gate RST2, respectively, and the second source follower and the second selection transistor of the above-mentioned second sensing circuit can correspond to the second source follower SF2 and the second selection transistor SX2, respectively.

[0038] The substrate 510 may have a front surface and a back surface facing away from each other at opposite sides of the substrate 510 . Figure 2A The top surface of the substrate 510 shown may represent the front surface, while Figure 2AThe bottom surface of the illustrated substrate 510 may represent a back surface. The unit pixel 500 may have a backside illumination type structure receiving incident light through a back surface, or may have a frontside illumination type structure receiving incident light through a front surface.

[0039] The substrate 510 may be formed as or include a p-type epitaxial layer p-epi. The substrate 510 may include a photodiode 520 that may be configured as a doped impurity layer, floating diffusion nodes 530 and 540, and drain nodes 550 and 560.

[0040] The photodiode 520 can absorb incident light and accumulate photocharges corresponding to the amount of incident light. In this implementation, the photodiode 520 can be implemented by a pinned photodiode (PPD) including a pinning layer 522 and a photoelectric conversion layer 524. Although the photodiode 520 is described as a pinned photodiode in this example, other implementations are possible.

[0041] The pinning layer 522 may be disposed along the surface of the substrate 510 and be doped with p+ type impurities. The pinning layer 522 may suppress the generation of dark current.

[0042] The photoelectric conversion layer 524 may be disposed under the pinned layer 522 and doped with n-type impurities. The photoelectric conversion layer 524 may generate and accumulate photocharges corresponding to the amount of incident light.

[0043] like Figure 2AAs shown, the width of the photoelectric conversion layer 524 may be greater than the width of the pinning layer 522. Therefore, the photoelectric conversion layer 524 may have a shape extending beyond the pinning layer 522 along the surface of the substrate 510. For example, the photoelectric conversion layer 524 may include an extension portion located on both sides (e.g., the left and right sides) of the pinning layer 522. The extension portion of the photoelectric conversion layer 524 is located on the surface of the substrate, and the photoelectric conversion layer 524 may be directly connected to the channel region below the first transfer gate TX1 and the second transfer gate TX2 through the extension portion of the photoelectric conversion layer 524. Therefore, a potential barrier that may be formed in the region between the photodiode 520 and the first transfer transistor or between the photodiode 520 and the second transfer transistor may be removed. In the case where there is no or only a small potential barrier between the photodiode 520 and the first transfer transistor or the second transfer transistor, when the transfer transistor is turned on, the transmission of photocharges may be performed more smoothly. Generally, the impurity concentration of the photoelectric conversion layer 524 is higher near the edge of the photoelectric conversion layer 524. Due to the high impurity concentration, the potential around the edge of the photoelectric conversion layer 524 may increase, thereby forming a potential barrier. Since the proposed implementation provides the photoelectric conversion layer 524 having extensions on both sides of the pinned layer 522, the photoelectric conversion layer 524 can be directly connected to the channel region under the first and second transfer gates TX1 and TX2. Therefore, the potential barrier around the edge of the photoelectric conversion layer 524 can be removed.

[0044] Each of the first floating diffusion node 530 and the second floating diffusion node 540 may be provided as an n+ doping region and accumulate photocharges transmitted from the photodiode 520 through each of the first transfer transistor and the second transfer transistor. The first floating diffusion node 530 and the second floating diffusion node 540 may be provided to be spaced apart from the photodiode 520 by a predetermined distance along the surface of the substrate 510, respectively.

[0045] The first drain node 550 and the second drain node 560 may be provided as n+ doping regions and may receive photo charges from the first floating diffusion node 530 and the second floating diffusion node 540 through the first reset transistor and the second reset transistor, respectively, and drain the photo charges to the power supply voltage VDD.

[0046] The photodiode gate TD may be disposed between the first transfer gate TX1 and the second transfer gate TX2 on a region corresponding to a central portion of the photodiode 520 , and may receive a photodiode signal and control a potential under the photodiode gate TD.

[0047] The first transmission gate TX1 may be disposed on a region between the photodiode 520 and the first floating diffusion node 530 while at least partially overlapping the photodiode 520 and the first floating diffusion node 530. The first transmission gate TX1 may receive a first transmission signal V_TX1 (see Figure 3A ), and controls the on and off of the first transfer transistor. If the first transfer transistor is turned on, a channel may be formed in the region between the photodiode 520 and the first floating diffusion node 530, so that the photocharge accumulated in the photodiode 520 may be transferred to the first floating diffusion node 530. On the contrary, if the first transfer transistor is turned off, a channel may not be formed in the region between the photodiode 520 and the first floating diffusion node 530, so that photocharge transfer does not occur between the photodiode 520 and the first floating diffusion node 530.

[0048] The second transmission gate TX2 may be disposed on a region between the photodiode 520 and the second floating diffusion node 540 while at least partially overlapping the photodiode 520 and the second floating diffusion node 540. The second transmission gate TX2 may receive a second transmission signal V_TX2 (see Figure 3A ), and controls the turning on and off of the second transfer transistor. If the second transfer transistor is turned on, a channel may be formed in the region between the photodiode 520 and the second floating diffusion node 540, so that the photocharge accumulated in the photodiode 520 may be transferred to the second floating diffusion node 540. On the contrary, if the second transfer transistor is turned off, a channel may not be formed in the region between the photodiode 520 and the second floating diffusion node 540, so that photocharge transfer does not occur between the photodiode 520 and the second floating diffusion node 540.

[0049] The first reset gate RST1 may be disposed on a region between the first floating diffusion node 530 and the first drain node 550 while at least partially overlapping the first floating diffusion node 530 and the first drain node 550. The first reset gate RST1 may receive a first reset signal and control the turning on and off of the first reset transistor. If the first reset transistor is turned on, a channel may be formed in a region between the first floating diffusion node 530 and the first drain node 550, so that photocharges accumulated in the first floating diffusion node 530 may be transferred to the first drain node 550. On the contrary, if the first reset transistor is turned off, a channel may not be formed in a region between the first floating diffusion node 530 and the first drain node 550, so that photocharge transfer may not occur between the first floating diffusion node 530 and the first drain node 550.

[0050] The second reset gate RST2 may be disposed on a region between the second floating diffusion node 540 and the second drain node 560, while at least partially overlapping the second floating diffusion node 540 and the second drain node 560. The second reset gate RST2 may receive a second reset signal and control the turning on and off of the second reset transistor. If the second reset transistor is turned on, a channel may be formed in a region between the second floating diffusion node 540 and the second drain node 560, so that photocharge accumulated in the second floating diffusion node 540 may be transferred to the second drain node 560. On the contrary, if the second reset transistor is turned off, a channel may not be formed in a region between the second floating diffusion node 540 and the second drain node 560, so that photocharge transfer may not occur between the second floating diffusion node 540 and the second drain node 560.

[0051] The first source follower SF1 may have a gate connected to the first floating diffusion node 530 and may be connected between the power supply voltage VDD and the first selection transistor SX1. The first source follower SF1 may amplify a change in the potential of the first floating diffusion node 530, so that a signal corresponding to the change in the potential of the first floating diffusion node 530 may be transmitted to the first selection transistor SX1.

[0052] The second source follower SF2 may have a gate connected to the second floating diffusion node 540 and may be connected between the power supply voltage VDD and the second selection transistor SX2. The second source follower SF2 may amplify a change in the potential of the second floating diffusion node 540, so that a signal corresponding to the change in the potential of the second floating diffusion node 540 may be transmitted to the second selection transistor SX2.

[0053] The first selection transistor SX1 may be applied with a selection signal SEL through its gate and may be connected between the first source follower SF1 and the first column line COL1. The first selection transistor SX1 may be turned on according to the selection signal SEL, thereby outputting a signal corresponding to a change in the potential of the first floating diffusion node 530 provided from the first source follower SF1 to the first column line COL1.

[0054] The second selection transistor SX2 can be applied with a selection signal SEL through its gate and can be connected between the second source follower SF2 and the second column line COL2. The second selection transistor SX2 can be turned on according to the selection signal SEL, so that a signal corresponding to a change in the potential of the second floating diffusion node 540 provided from the second source follower SF2 can be output to the second column line COL2.

[0055] The unit pixel 500 can output the photocharge generated in the first period to the first column line COL1 through the first sensing circuit, and can output the photocharge generated in the second period to the second column line COL2 through the second sensing circuit. The first period and the second period can be continuous time periods. To this end, the first transmission transistor can be turned on in the first period and turned off in the second period, and the second transmission transistor can be turned off in the first period and turned on in the second period. For example, the first transmission signal V_TX1 (see Figure 3A ) and the second transmission signal V_TX2 (see Figure 3A ) may be signals having opposite phases. Each of the first transmission signal V_TX1 and the second transmission signal V_TX2 may have a specific phase difference (eg, 0 degrees, 90 degrees, 180 degrees, or 270 degrees) with respect to the clock signal MLS driving the light source 100.

[0056] exist Figure 2A In the example shown, the unit pixel includes a photoelectric conversion layer 524, whose width is greater than the width of the pinning layer 522. However, other implementations are also possible. For example, the width of the photoelectric conversion layer 524 can be substantially the same as the width of the pinning layer 522, or the width of the photoelectric conversion layer 524 can be less than the width of the pinning layer 522.

[0057] Figure 2B It is shown Figure 1 FIG. 1 is a cross-sectional view of another embodiment of a unit pixel.

[0058] Reference Figure 2B , the unit pixel 500' may correspond to Figure 1 Any unit pixel PX in the pixel array 300 shown.

[0059] The unit pixel 500' may include one photodiode 520' and may include two sensing circuits including a first sensing circuit and a second sensing circuit, each of which is capable of outputting an electrical signal obtained by sensing and amplifying photocharges generated at different timings to a corresponding column line. Figure 2A As described, the unit pixel 500' includes a photodiode 520' as an example of a photoelectric conversion element, and other photoelectric conversion elements (such as a phototransistor, a photogate, or other photosensitive circuits capable of converting incident light into a pixel signal (e.g., charge, voltage, or current)) other than the photodiode 520' may be included in the unit pixel 500'. The first sensing circuit may include a first transfer transistor, a first reset transistor, a first source follower, and a first selection transistor. Similarly, the second sensing circuit may include a second transfer transistor, a second reset transistor, a second source follower, and a second selection transistor.

[0060] The unit pixel 500' may include a substrate 510, a photodiode 520', a first floating diffusion node 530 and a second floating diffusion node 540, a first drain node 550 and a second drain node 560, a photodiode gate TD, a first transfer gate TX1 and a second transfer gate TX2, a first reset gate RST1 and a second reset gate RST2, a first source follower SF1 and a second source follower SF2, and a first selection transistor SX1 and a second selection transistor SX2. Figure 2B The structure of the unit pixel 500' is shown for illustration purposes. In some implementations, some components may be omitted or any additional components may be added.

[0061] Since the structures and operations of the components of the unit pixel 500' except the photodiode 520' are similar to those of the above reference Figure 2A The structures and operations of the corresponding components described are substantially the same, and thus detailed descriptions thereof will be omitted herein.

[0062] The photodiode 520' may receive or absorb incident light and accumulate photocharges corresponding to the amount of incident light. The photodiode 520' may be implemented by a pinned photodiode (PPD) and may include a first pinned layer 522', a second pinned layer 523, and a photoelectric conversion layer 524'.

[0063] The first pinned layer 522' and the second pinned layer 523 are disposed along the surface of the substrate 510 so that the second pinned layer 523 is disposed on both sides of the first pinned layer 522'. The first pinned layer 522' may be doped with p+ type impurities, and the second pinned layer 523 may be doped with p- type impurities. The first pinned layer 522' and the second pinned layer 523 may suppress the generation of dark current. Although each of the first pinned layer 522' and the second pinned layer 523 is doped with p-type ions, the doping concentration of the first pinned layer 522' may be higher than the doping concentration of the second pinned layer 523. In addition, the doping concentration of the second pinned layer 523 may be lower than the doping concentration of the substrate 510. In some implementations, the first pinned layer 522' and the second pinned layer 523 may have the same thickness as each other. In some other implementations, either layer of the first pinned layer 522' and the second pinned layer 523 may be thicker than the other layer.

[0064] The photoelectric conversion layer 524' may be doped with n-type impurities and disposed below the first pinning layer 522' and the second pinning layer 523. The photoelectric conversion layer 524' may generate and accumulate photocharges corresponding to the amount of incident light. Figure 2A The photoelectric conversion layers 524 are shown to have the same or different widths.

[0065] like Figure 2BAs shown, the second pinning layer 523 having a doping concentration lower than that of the first pinning layer 522' may be disposed below each of the first transfer gate TX1 and the second transfer gate TX2. Therefore, the second pinning layer 523, rather than the first pinning layer 522', may be disposed below each of the first transfer gate TX1 and the second transfer gate TX2. By disposing the second pinning layer 523, rather than the first pinning layer 522, below the first transfer gate TX1 and the second transfer gate TX2, a potential pocket that is often formed below the first transfer gate TX1 and the second transfer gate TX2 may be removed. The potential pocket is formed due to an increase in potential at a region where the transfer gates TX1 and TX2 and the photoelectric conversion layer 524' overlap each other, and this potential increase is caused when the impurity concentration of the overlapping region is higher than that of the channel region near the floating diffusion nodes 530 and 540. In this implementation, since the second pinning layer 523 having a lower doping concentration than the first pinning layer 522' is disposed under the transmission gates TX1 and TX2, a potential well that may be formed under the transmission gates TX1 and TX2 can be removed, so that the photocharge can be smoothly transferred when the transmission transistor is turned on. Therefore, by disposing the second pinning layer 523 having a lower impurity concentration than the first pinning layer 522' and the substrate 510 under the transmission gates TX1 and TX2, the potential well can be removed.

[0066] In addition, potential wells can cause image lag. Image lag is caused by photocharges that are temporarily trapped in the potential wells, and when the transfer transistor is turned off, such trapped photocharges can move back to the photodiode 520'. When the potential wells are removed, such unwanted transfer of trapped photocharges can also be removed, thereby preventing image lag.

[0067] Figure 3A It is shown Figure 2A Figure 2 is an exemplary representation of a partial area of ​​the device.

[0068] Reference Figure 3A , showing in more detail Figure 2A The first region 600 includes a photodiode 520, a photodiode gate TD, first and second transfer gates TX1 and TX2, and first and second floating diffusion nodes 530 and 540.

[0069] The photodiode gate TD may include a first gate dielectric layer GIF1 and a photodiode gate electrode G_TD sequentially stacked on the substrate 510 . The photodiode gate TD may be disposed on a region including a central portion of the photodiode 520 .

[0070] The first gate dielectric layer GIF1 may be disposed between the photodiode gate electrode G_TD and the substrate 510, and electrically isolates the photodiode gate electrode G_TD from the substrate 510. The first gate dielectric layer GIF1 may be or include an oxide or other dielectric material. Therefore, the material of the first gate dielectric layer GIF1 is not limited to oxide. The thickness of the first gate dielectric layer GIF1 may be referred to as a first thickness TH1.

[0071] The photodiode gate electrode G_TD can receive the photodiode signal V_TD, and in response to receiving the photodiode signal V_TD, the photodiode gate electrode G_TD can control the potential of the area corresponding to the lower side of the photodiode gate TD. The photodiode gate electrode G_TD can be or include polysilicon or other materials. Therefore, the material of the photodiode gate electrode G_TD is not limited to polysilicon.

[0072] The first transmission gate TX1 may include a gate dielectric layer including a first gate dielectric layer GIF1 and a second dielectric layer GIF2 and a first transmission gate electrode G_TX1 sequentially stacked on the substrate 510 .

[0073] The gate dielectric layer included in the first transmission gate TX1 may include a first gate dielectric layer GIF1 at least partially overlapping the photodiode 520 and a second gate dielectric layer GIF2 at least partially overlapping the first floating diffusion node 530. The first gate dielectric layer GIF1 and the second gate dielectric layer GIF2 may be disposed between the first transmission gate electrode G_TX1 and the substrate 510. The first gate dielectric layer GIF1 and the second gate dielectric layer GIF2 may electrically isolate the first transmission gate electrode G_TX1 from the substrate 510. The first gate dielectric layer GIF1 and the second gate dielectric layer GIF2 may be or include oxide or other dielectric materials. It should be noted that the material of the first gate dielectric layer GIF1 is not limited to oxide. The thickness of the first gate dielectric layer GIF1 may be a first thickness TH1, and the thickness of the second gate dielectric layer GIF2 may be a second thickness TH2. The first thickness TH1 may be greater than the second thickness TH2. Although Figure 3A The width of the first gate dielectric layer GIF1 and the width of the second gate dielectric layer GIF2 are shown to be the same as each other, but it should be noted that other implementations are possible. Thus, any one of the width of the first gate dielectric layer GIF1 and the width of the second gate dielectric layer GIF2 may be greater than the other.

[0074] The first transmission gate electrode G_TX1 may receive a first transmission signal V_TX1, and in response to receiving the first transmission signal V_TX1, the first transmission gate electrode G_TX1 may control a potential of a region corresponding to a lower side of the first transmission gate TX1. The first transmission gate electrode G_TX1 may be or include polysilicon or other materials. Therefore, the material of the first transmission gate electrode G_TX1 is not limited to polysilicon.

[0075] When the first transmission signal V_TX1 is applied to the first transmission gate electrode G_TX1, since the first gate dielectric layer GIF1 having the first thickness TH1 and the second gate dielectric layer GIF2 having the second thickness TH2 are disposed below the first transmission gate electrode G_TX1, the potential of the region corresponding to the lower side of the first gate dielectric layer GIF1 and the potential of the region corresponding to the lower side of the second gate dielectric layer GIF2 may be different from each other. The thinner the thickness of the gate dielectric layer, the greater the influence of the voltage applied to the gate electrode on the region corresponding to the lower side of the gate dielectric layer. Therefore, the potential of the region corresponding to the lower side of the first gate dielectric layer GIF1 having the first thickness TH1 is lower than the potential of the region corresponding to the lower side of the second gate dielectric layer GIF2 having the second thickness TH2.

[0076] The interval L1 between the photodiode 520 and the first floating diffusion node 530 and the interval L2 between the photodiode 520 and the second floating diffusion node 540 may be determined through experiments to provide a sufficient channel length to prevent a tunneling effect caused when the channel length is too short.

[0077] The second transmission gate TX2 may include a gate dielectric layer and a second transmission gate electrode G_TX2 sequentially stacked on the substrate 510 .

[0078] The gate dielectric layer included in the second transmission gate TX2 may include a first gate dielectric layer GIF1 at least partially overlapping the photodiode 520 and a second gate dielectric layer GIF2 at least partially overlapping the second floating diffusion node 540 .

[0079] When the second transmission signal V_TX2 is applied to the second transmission gate electrode G_TX2 as a voltage, since the first gate dielectric layer GIF1 having the first thickness TH1 and the second gate dielectric layer GIF2 having the second thickness TH2 are disposed below the second transmission gate electrode G_TX2, the potential of the area corresponding to the lower side of the first gate dielectric layer GIF1 and the potential of the area corresponding to the lower side of the second gate dielectric layer GIF2 may be different from each other. The thinner the thickness of the gate dielectric layer, the greater the area corresponding to the lower side of the gate dielectric layer is affected by the voltage applied to the gate electrode. Therefore, the potential of the area corresponding to the lower side of the first gate dielectric layer GIF1 having the first thickness TH1 is lower than the potential of the area corresponding to the lower side of the second gate dielectric layer GIF2 having the second thickness TH2.

[0080] The structure of the second transmission gate TX2 is substantially the same as that of the first transmission gate TX1 described above, and the materials of the corresponding components may be the same. Therefore, for ease of explanation, a detailed description of the second transmission gate TX2 will be omitted herein. The first transmission gate TX1 and the second transmission gate TX2 may have a layout and structure symmetrical to each other with respect to the photodiode gate TD.

[0081] The incident light incident into the unit pixel 500 can be focused on the area below the photodiode gate TD when passing through the microlens 610 disposed under the substrate 510. In this case, most of the photocharges generated by the incident light are generated and accumulated in the area below the photodiode gate TD. These photocharges can be transferred to the first floating diffusion node 530 or the second floating diffusion node 540 through the operation of the first transfer transistor or the second transfer transistor.

[0082] Figure 3B It is shown Figure 2B Figure 2 is an exemplary representation of a partial area of ​​the device.

[0083] Reference Figure 3B , showing in more detail Figure 2B The first region 600 ′ includes a photodiode 520 ′, a photodiode gate TD, a first transfer gate TX1 and a second transfer gate TX2 , and a first floating diffusion node 530 and a second floating diffusion node 540 .

[0084] Due to the above reference Figure 3A The features of the various components described can be applied to Figure 3B Therefore, the detailed description of the corresponding components will be omitted in this article.

[0085] Figures 4 to 7Example diagrams showing potential distributions during first to fourth periods of operation of a display unit pixel are respectively shown. Figure 4 is a diagram showing an exemplary representation of a potential distribution during a first period in a unit pixel.

[0086] Reference Figure 4 , shows the potential distribution in the first period, in which the photocharge generated by the photodiode 520 is transferred to the first floating diffusion node 530FD1. In the accompanying drawings, the potential in each region increases in the downward direction, and each transistor can form a potential barrier when turned off, thereby blocking the charge transfer between the source and the drain. If each transistor is turned on, the charge transfer between the source and the drain can be allowed. Each transistor can be turned on when a voltage of a logic high level is applied to its gate, and can be turned off when a voltage of a logic low level is applied to its gate. The following will refer to the assumption that the potential of the first floating diffusion node FD1 and the second floating diffusion node FD2 is the same as the potential of the power supply voltage VDD. Figures 4 to 7 However, it should be noted that this is only an example and other implementations are also possible.

[0087] In the first period, each of the first reset signal V_RST1, the second reset signal V_RST2, and the second transmission signal V_TX2 may have a logic low level, and the first transmission signal V_TX1 may have a logic high level. Therefore, each of the first reset transistor, the second reset transistor, and the second transmission transistor may be turned off, and the first transmission transistor may be turned on. The photodiode signal V_TD may have an intermediate voltage between a voltage corresponding to a logic high level of the first transmission signal V_TX1 and a voltage corresponding to a logic low level of the second transmission signal V_TX2. The intermediate voltage does not necessarily represent an average value of a voltage corresponding to a logic high level of the first transmission signal V_TX1 and a voltage corresponding to a logic low level of the second transmission signal V_TX2, but may represent a voltage lower than a voltage corresponding to a logic high level of the first transmission signal V_TX1 and higher than a voltage corresponding to a logic low level of the second transmission signal V_TX2.

[0088] The region corresponding to the photodiode gate TD has the intermediate potential VM, the region corresponding to the first gate dielectric layer GIF1 of the first transfer gate TX1 has the second high potential VH2 higher than the intermediate potential VM, and the region corresponding to the second gate dielectric layer GIF2 of the first transfer gate TX1 has the first high potential VH1 higher than the second high potential VH2. This is because, although the same voltage is applied to the first transfer gate TX1, the first high potential VH1 is higher than the second high potential VH2 due to the difference in thickness between the first gate dielectric layer GIF1 and the second gate dielectric layer GIF2.

[0089] Due to the presence of the microlens 610, the incident light is focused on the area corresponding to the lower side of the photodiode gate TD, so most of the photocharges may be generated in the area corresponding to the lower side of the photodiode gate TD. When the first transfer transistor is turned on, these photocharges may move to the first floating diffusion node FD1. At this time, the potential distribution of the first region is formed so that the potential changes from the intermediate potential VM to the first high potential VH1 through the second high potential VH2. Figure 4 As shown, the potential of the first region gradually increases from the intermediate potential VM to the first high potential VH1, thereby forming a potential slope in the direction from the photodiode 520 to the first floating diffusion node FD1. Therefore, the lateral field effect can be increased. As a result, the efficiency and speed of transferring the photocharge to the first floating diffusion node FD1 can be improved.

[0090] The region corresponding to the photodiode gate TD has the middle potential VM, the region of the second gate dielectric layer GIF2 corresponding to the second transfer gate TX2 has the first low potential VL1 lower than the middle potential VM, and the region of the first gate dielectric layer GIF1 corresponding to the second transfer gate TX2 has the second low potential VL2 lower than the first low potential VL1. This is because, although the same voltage is applied to the second transfer gate TX2, the first low potential VL1 is higher than the second low potential VL2 due to the difference in thickness between the first gate dielectric layer GIF1 and the second gate dielectric layer GIF2.

[0091] Since the intermediate potential VM is higher than the second low potential VL2 , most of the photo charges generated in the region corresponding to the lower side of the photodiode gate TD do not move to the second floating diffusion node FD2 due to the potential barrier formed by the second low potential VL2 .

[0092] Figure 5 is a diagram showing an exemplary representation of a potential distribution during the second period in a unit pixel.

[0093] Reference Figure 5 , shows a potential distribution in a second period, in which photocharges generated by the photodiode 520 are transferred to the second floating diffusion node 540FD2.

[0094] In the second period, each of the first reset signal V_RST1, the second reset signal V_RST2 and the first transmission signal V_TX1 may have a logic low level, and the second transmission signal V_TX2 may have a logic high level. Therefore, each of the first reset transistor, the second reset transistor and the first transmission transistor may be turned off, and the second transmission transistor may be turned on. The photodiode signal V_TD may have an intermediate voltage between a voltage corresponding to a logic low level of the first transmission signal V_TX1 and a voltage corresponding to a logic high level of the second transmission signal V_TX2. The intermediate voltage does not necessarily represent an average value of a voltage corresponding to a logic low level of the first transmission signal V_TX1 and a voltage corresponding to a logic high level of the second transmission signal V_TX2, but may represent a voltage higher than a voltage corresponding to a logic low level of the first transmission signal V_TX1 and lower than a voltage corresponding to a logic high level of the second transmission signal V_TX2.

[0095] Therefore, the region corresponding to the photodiode gate TD has the intermediate potential VM, the region of the first gate dielectric layer GIF1 corresponding to the second transfer gate TX2 has the second high potential VH2 higher than the intermediate potential VM, and the region of the second gate dielectric layer GIF2 corresponding to the second transfer gate TX2 has the first high potential VH1 higher than the second high potential VH2. This is because, although the same voltage is applied to the second transfer gate TX2, the first high potential VH1 is higher than the second high potential VH2 due to the difference in thickness between the first gate dielectric layer GIF1 and the second gate dielectric layer GIF2.

[0096] Due to the presence of the microlens 610, the incident light is focused on the area corresponding to the lower side of the photodiode gate TD, so most of the photocharges may be generated in the area corresponding to the lower side of the photodiode gate TD. When the second transfer transistor is turned on, these photocharges ( Figure 5 The light charges (shaded in the figure) can move to the second floating diffusion node FD2. At this time, the potential distribution of the first region is formed so that the potential changes from the intermediate potential VM to the first high potential VH1 through the second high potential VH2. Figure 5 As shown, the potential of the first region gradually increases from the intermediate potential VM to the first high potential VH1, thereby forming a potential slope in the direction from the photodiode 520 to the second floating diffusion node FD2. Therefore, the lateral field effect can be increased. As a result, the efficiency and speed of transferring the photocharge to the second floating diffusion node FD2 can be improved.

[0097] The region corresponding to the photodiode gate TD has the middle potential VM, the region of the second gate dielectric layer GIF2 corresponding to the first transfer gate TX1 has the first low potential VL1 lower than the middle potential VM, and the region of the first gate dielectric layer GIF1 corresponding to the first transfer gate TX1 has the second low potential VL2 lower than the first low potential VL1. This is because, although the same voltage is applied to the first transfer gate TX1, the first low potential VL1 is higher than the second low potential VL2 due to the difference in thickness between the first gate dielectric layer GIF1 and the second gate dielectric layer GIF2.

[0098] Since the intermediate potential VM is higher than the second low potential VL2 , most of the photo charges generated in the region corresponding to the lower side of the photodiode gate TD do not move to the first floating diffusion node FD1 due to the potential barrier formed by the second low potential VL2 .

[0099] In addition, since the first period corresponds to a relatively short period of time, some of the photocharges generated in the first period (photocharges not shaded) may not move to the first floating diffusion node FD1, and may drift under the second gate dielectric layer GIF2 of the first transfer gate TX1. In this regard, since the second low potential VL2 is lower than the first low potential VL1, the photocharges drifting under the second gate dielectric layer GIF2 of the first transfer gate TX1 may not move to the region corresponding to the photodiode gate TD due to the potential barrier formed by the second low potential VL2, and may move to the first floating diffusion node FD1. Since the photocharges drifting under the second gate dielectric layer GIF2 of the first transfer gate TX1 may form noise for the photocharges generated in the second period, the noise may be reduced by the potential barrier formed by the second low potential VL2. Therefore, by such a potential barrier, the demodulation contrast of the signal generated by the unit pixel 500 may be improved.

[0100] Figure 6 is a diagram showing a representation of an example of a potential distribution during a third period in a unit pixel.

[0101] Reference Figure 6 , shows a potential distribution in a third period in which an electric signal corresponding to photocharges accumulated in each of the first floating diffusion node FD1 and the second floating diffusion node FD2 is generated.

[0102] In the third period, each of the first reset signal V_RST1, the second reset signal V_RST2, the first transfer signal V_TX1, and the second transfer signal V_TX2 may have a logic low level. Therefore, each of the first reset transistor, the second reset transistor, the first transfer transistor, and the second transfer transistor may be turned off. The photodiode signal V_TD may have an intermediate voltage. According to another embodiment, the photodiode signal V_TD may have the same voltage as the voltage corresponding to the logic low level of the first transfer signal V_TX1 or the second transfer signal V_TX2, thereby reducing power consumption.

[0103] A voltage level according to the photocharge accumulated in the first floating diffusion node FD1 may be output as a first output signal SIG1 to the first column line COL1 through the first source follower SF1 and the first selection transistor SX1. A voltage level according to the photocharge accumulated in the second floating diffusion node FD2 may be output as a second output signal SIG2 to the second column line COL2 through the second source follower SF2 and the second selection transistor SX2.

[0104] Figure 7 is a diagram showing an exemplary representation of a potential distribution during a fourth period in a unit pixel.

[0105] Reference Figure 7 , shows a potential distribution in a fourth period in which each of the first floating diffusion node FD1 and the second floating diffusion node FD2 is reset.

[0106] In the fourth period, each of the first reset signal V_RST1 and the second reset signal V_RST2 may have a logic high level, and each of the first transfer signal V_TX1 and the second transfer signal V_TX2 may have a logic low level. Therefore, each of the first reset transistor and the second reset transistor may be turned on, and each of the first transfer transistor and the second transfer transistor may be turned off. The photodiode signal V_TD may have an intermediate voltage. According to another embodiment, the photodiode signal V_TD may have the same voltage as the voltage corresponding to the logic low level of the first transfer signal V_TX1 or the second transfer signal V_TX2, thereby reducing power consumption.

[0107] When the first reset transistor is turned on, the photocharges (unshaded charges) accumulated in the first floating diffusion node FD1 can move to the first drain node 550, thereby being discharged to the power supply voltage VDD. Similarly, when the second reset transistor is turned on, the photocharges (shaded charges) accumulated in the second floating diffusion node FD2 can move to the second drain node 560, thereby being discharged to the power supply voltage VDD.

[0108] Although various embodiments have been described above, those skilled in the art should understand that the described embodiments are merely exemplary. Therefore, the image sensor described herein should not be limited based on the described embodiments.

[0109] CROSS-REFERENCE TO RELATED APPLICATIONS

[0110] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2019-0153176, filed in the Korean Intellectual Property Office on November 26, 2019, which is incorporated herein by reference in its entirety as a part of the disclosure of this patent document.

Claims

1. An image sensing device, the image sensing device include: substrate; a photoelectric conversion element disposed in the substrate and configured to generate photocharges in response to incident light; a first floating diffusion node and a second floating diffusion node, the first floating diffusion node and the second floating diffusion node being disposed in the substrate to be spaced apart from the photoelectric conversion element at opposite sides of the photoelectric conversion element, respectively; a first transfer gate disposed on the substrate to at least partially overlap the photoelectric conversion element and the first floating diffusion node; as well as a second transfer gate disposed on the substrate to at least partially overlap the photoelectric conversion element and the second floating diffusion node, wherein each of the first transfer gate and the second transfer gate includes a first gate dielectric layer at least partially overlapping the photoelectric conversion element and a second gate dielectric layer at least partially overlapping the first floating diffusion node or the second floating diffusion node, and Wherein, the thickness of the first gate dielectric layer is greater than the thickness of the second gate dielectric layer.

2. The image sensing device according to claim 1, in, The photoelectric conversion element includes a pinned layer disposed along a surface of the substrate and a photoelectric conversion layer disposed under the pinned layer and doped with n-type impurities.

3. The image sensing device according to claim 2, in, The width of the photoelectric conversion layer is greater than the width of the pinning layer.

4. The image sensing device according to claim 2, in, The pinning layer includes a first pinning layer doped with p+ type impurities and a second pinning layer doped with p- type impurities, and the second pinning layer is disposed under the first transfer gate or the second transfer gate.

5. The image sensing device according to claim 1, further comprising: include: A photoelectric conversion gate is provided between the first transfer gate and the second transfer gate in a region corresponding to a central portion of the photoelectric conversion element.

6. The image sensing device according to claim 5, in, The photoelectric conversion gate includes a first gate dielectric layer and a photoelectric conversion gate electrode disposed above the first gate dielectric layer.

7. The image sensing device according to claim 1, in, The first transfer gate further includes a first transfer gate electrode disposed over the first gate dielectric layer and the second gate dielectric layer of the first transfer gate, and the second transfer gate further includes a second transfer gate electrode disposed over the first gate dielectric layer and the second gate dielectric layer of the second transfer gate.

8. The image sensing device according to claim 1, in, The first transmission gate is configured to receive a first transmission signal corresponding to a logic high level during a first period, and a potential of a region corresponding to a lower side of the first gate dielectric layer of the first transmission gate is lower than a potential of a region corresponding to a lower side of the second gate dielectric layer of the first transmission gate.

9. The image sensing device according to claim 8, in, The second transmission gate is configured to receive a second transmission signal corresponding to a logic low level during the first period, and a potential of a region corresponding to a lower side of the first gate dielectric layer of the second transmission gate is lower than a potential of a region corresponding to a lower side of the second gate dielectric layer of the second transmission gate.

10. The image sensing device according to claim 9, further comprising a photoelectric conversion gate disposed between the first transfer gate and the second transfer gate, and the photoelectric conversion gate is configured to receive a signal corresponding to an intermediate voltage between a voltage of the first transfer signal and a voltage of the second transfer signal during the first period.

11. The image sensing device according to claim 1, in, The second transmission gate is configured to receive a second transmission signal corresponding to a logic high level during a second period, and a potential of a region on a lower side of the first gate dielectric layer of the second transmission gate is lower than a potential of a region corresponding to a lower side of the second gate dielectric layer of the second transmission gate.

12. The image sensing device according to claim 11, in, The first transmission gate is configured to receive a first transmission signal corresponding to a logic low level during the second period, and a potential of a region corresponding to a lower side of the first gate dielectric layer of the first transmission gate is lower than a potential of a region corresponding to a lower side of the second gate dielectric layer of the first transmission gate.

13. The image sensing device according to claim 12, further comprising a photoelectric conversion gate disposed between the first transfer gate and the second transfer gate, and the photoelectric conversion gate is configured to receive a signal corresponding to an intermediate voltage between a voltage of the first transfer signal and a voltage of the second transfer signal during the second period.

14. The image sensing device according to claim 1, further comprising: include: A microlens is provided below the substrate and configured to focus incident light on a central portion of the photoelectric conversion element.

15. The image sensing device according to claim 1, in, The substrate includes a p-type epitaxial layer, and The first floating diffusion node and the second floating diffusion node are doped with n+ type impurities.

16. An image sensing device, the image sensing device include: substrate; a photoelectric conversion element disposed in the substrate and configured to generate photocharges in response to incident light; a first floating diffusion node and a second floating diffusion node, the first floating diffusion node and the second floating diffusion node being disposed in the substrate to be spaced apart from the photoelectric conversion element at opposite sides of the photoelectric conversion element, respectively; a first transfer gate disposed on the substrate to at least partially overlap one side of the photoelectric conversion element; a second transfer gate disposed on the substrate to at least partially overlap the other side of the photoelectric conversion element; as well as a photoelectric conversion gate, the photoelectric conversion gate being disposed between the first transmission gate and the second transmission gate, wherein each of the first transfer gate and the second transfer gate includes a first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer at least partially overlaps the photoelectric conversion element and has a first thickness, the second gate dielectric layer at least partially overlaps the first floating diffusion node or the second floating diffusion node and has a second thickness less than the first thickness, and The first transmission gate is configured to receive a first transmission signal corresponding to a logic high level, the first transmission signal providing a potential distribution that increases from a lower side of the second transmission gate to a lower side of the first transmission gate.

17. The image sensing device according to claim 16, in, The potential distribution increases in the following order: the lower side of the first gate dielectric layer of the second transfer gate, the lower side of the second gate dielectric layer of the second transfer gate, the lower side of the photoelectric conversion gate, the lower side of the first gate dielectric layer of the first transfer gate, and the lower side of the second gate dielectric layer of the first transfer gate.

18. The image sensing device according to claim 16, in, The second transmission gate is configured to receive a second transmission signal corresponding to a logic high level, and the second transmission signal provides a potential distribution that increases in the following order: a lower side of the first gate dielectric layer of the first transmission gate, a lower side of the second gate dielectric layer of the first transmission gate, a lower side of the photoelectric conversion gate, a lower side of the first gate dielectric layer of the second transmission gate, and a lower side of the second gate dielectric layer of the second transmission gate.

19. The image sensing device according to claim 16, in, The photoelectric conversion gate includes the first gate dielectric layer and a photoelectric conversion gate electrode disposed above the first gate dielectric layer.

20. The image sensing device according to claim 16, in, The first transfer gate includes a first transfer gate electrode disposed over the first gate dielectric layer and the second gate dielectric layer of the first transfer gate, and The second transfer gate includes a second transfer gate electrode disposed over the first gate dielectric layer and the second gate dielectric layer of the second transfer gate.

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