Semiconductor test structure

Abstract

The present invention relates to a semiconductor test structure, which is used as an extraction terminal of a gate electrode to be connected to an external test structure when testing the gate capacitance of a MOS device. The semiconductor test structure includes a substrate, on which a MOS device to be tested is provided; a pad for connecting to an external test structure; a top metal layer connected to both the pad and the gate electrode of the MOS device to be tested; and a bottom metal layer that is not interconnected with the substrate, the pad, and the top metal layer. The technical solution of the present invention reduces the total parasitic capacitance connected in parallel with the gate capacitance by a method of serially connecting multiple parasitic capacitances, thereby reducing the influence of the total parasitic capacitance on the test result of the gate capacitance and obtaining an accurate test result of the gate capacitance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device manufacturing, and particularly to a semiconductor test structure. Background Art

[0002] With the continuous development of semiconductor processes, integrated circuits have evolved from a few interconnected devices fabricated on a single chip to millions of devices, and the performance and complexity provided by current integrated circuits have also been continuously increasing. Metal-oxide-semiconductor (MOS) transistors, as the most fundamental devices in semiconductor manufacturing, are widely applied to various integrated circuits.

[0003] The thickness of the gate dielectric layer is an important specification parameter of MOS devices because it directly affects the accuracy of the threshold voltage of MOS devices. In the prior art, when testing the thickness of the gate dielectric layer, the capacitance-voltage test method is usually used to obtain the gate capacitance, and then the thickness of the gate dielectric layer is calculated based on the gate capacitance. However, there are large parasitic capacitances in the current gate capacitance test structure, resulting in a large deviation between the test result of the gate capacitance and the actual value. Therefore, in order to solve the problem of inaccurate test results of the existing gate capacitance, it is urgent to provide a reliable semiconductor test structure. Summary of the Invention

[0004] Based on this, it is necessary to provide a semiconductor test structure for the problem of inaccurate test results of gate capacitance.

[0005] In order to achieve the object of the present invention, the present invention adopts the following technical solutions:

[0006] A semiconductor test structure is used as an extraction terminal of a gate electrode to be connected with an external test structure when testing the gate capacitance of a MOS device. The semiconductor test structure is characterized in that it includes:

[0007] A substrate, on which a MOS device to be tested is provided;

[0008] A pad for connecting with an external test structure;

[0009] A top metal layer, which is connected to both the pad and the gate electrode of the MOS device to be tested;

[0010] A bottom metal layer, which is not interconnected with the gate electrode, the pad, and the top metal layer.

[0011] In one embodiment, the semiconductor test structure further includes at least one intermediate metal layer, which is disposed between the bottom metal layer and the top metal layer. The intermediate metal layer at least partially overlaps with the top metal layer and the bottom metal layer in the vertical direction, and the intermediate metal layer is not interconnected with at least one of the bottom metal layer and the top metal layer.

[0012] In one embodiment, the intermediate metal layer is not interconnected with the top metal layer and the bottom metal layer.

[0013] In one embodiment, the semiconductor test structure includes at least two intermediate metal layers, the at least two intermediate metal layers are both disposed between the bottom metal layer and the top metal layer, and adjacent top metal layer, at least two intermediate metal layers and bottom metal layer all at least partially overlap in the vertical direction, and at least one of the bottom metal layer and the top metal layer is not interconnected with any intermediate metal layer.

[0014] In one embodiment, the at least two intermediate metal layers are not interconnected with each other.

[0015] In one embodiment, the pad is disposed on the surface of the top metal layer.

[0016] In one embodiment, a passivation layer is provided on the surface of the top metal layer, the passivation layer has an opening, and the part of the top metal layer exposed in the opening constitutes the pad.

[0017] In one embodiment, the top metal layer and the gate electrode of the MOS device to be tested are connected through at least one interconnect metal layer and at least two conductive plugs, and the interconnect metal layer and the conductive plugs are not connected to the bottom metal layer.

[0018] In one embodiment, a dielectric layer is filled between the bottom metal layer and the top metal layer, and the dielectric constant of the material of the dielectric layer is not greater than 5.

[0019] In one embodiment, the material of the dielectric layer is silicon oxide or silicon nitride.

[0020] The above semiconductor test structure is used as a lead-out end of the gate electrode to be connected with an external test structure when testing the gate capacitance of a MOS device. The semiconductor test structure includes a substrate, on which a MOS device to be tested is provided; a pad for connecting an external test structure; a top metal layer connected to both the pad and the gate electrode of the MOS device to be tested; a bottom metal layer, and the bottom metal layer is not interconnected with the substrate, the pad and the top metal layer. The technical solution of the present invention reduces the total parasitic capacitance connected in parallel with the gate capacitance by the method of connecting multiple parasitic capacitances in series, thereby reducing the influence of the total parasitic capacitance on the test result of the gate capacitance and obtaining an accurate test result of the gate capacitance. Description of the Drawings

[0021] Figure 1 is a schematic structural diagram of a conventional semiconductor test structure;

[0022] Figure 2Schematic circuit diagram of parasitic capacitance in a traditional semiconductor test structure;

[0023] Figure 3 Schematic structural diagram of a semiconductor test structure in an embodiment;

[0024] Figure 4 Schematic structural diagram of a semiconductor test structure with partial metal layer connections in an embodiment;

[0025] Figure 5 is Figure 4 Schematic circuit diagram of parasitic capacitance in the semiconductor test structure in the embodiment;

[0026] Figure 6 Schematic structural diagram of a semiconductor test structure with no interconnection of metal layers in an embodiment;

[0027] Figure 7 is Figure 6 Schematic circuit diagram of parasitic capacitance in the semiconductor test structure in the embodiment;

[0028] Figure 8 Schematic diagram of the pad connection method in an embodiment;

[0029] Figure 9 Schematic structural diagram of a semiconductor test structure including a dielectric layer in an embodiment. Detailed implementation manners

[0030] For ease of understanding the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present invention more thorough and comprehensive.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this invention belongs. The terms used in the description of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0032] In the description of the present invention, it should be understood that the orientation or positional relationships indicated by the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention.

[0033] As Figure 1 shown is a semiconductor test structure of a traditional MOS device. During the manufacturing process of semiconductor devices, it is necessary to set conductive plugs between adjacent metal layers in the device region to form electrical connections between adjacent metal layers, thereby controlling the operation of corresponding devices. When depositing and etching in the device region to form conductive plugs, conductive plugs (351 and 352 in the figure) are also formed simultaneously in the semiconductor test structure. When testing using a traditional capacitive semiconductor test structure, a parasitic capacitance C1 is formed between the bottom metal layer 300 and the substrate 100, and a gate capacitance C real is formed between the gate electrode 220 and the substrate 100. The parasitic capacitance C1 and the gate capacitance C real constitute a parallel connection as Figure 2 shown, then the test capacitance C measure = C1 + C real The parasitic capacitance C1 will cause a large deviation between the test capacitance C measure and the gate capacitance C real , so the test result cannot reflect the true gate capacitance C real .

[0034] Figure 3 is a schematic structural diagram of a semiconductor test structure in an embodiment. The semiconductor test structure includes:

[0035] A substrate 100, on which a MOS device to be tested is provided;

[0036] A pad 500 for connecting an external test structure;

[0037] A top metal layer 400, which is connected to both the pad 500 and the gate electrode 220 of the MOS device to be tested;

[0038] A bottom metal layer 300, which is not interconnected with the gate electrode 220, the pad 500, and the top metal layer 400.

[0039] In this embodiment, the semiconductor test structure is used as the lead-out terminal of the gate electrode 220 to be connected to an external test structure when testing the gate capacitance of a MOS device. The MOS device is formed on the surface of the substrate 100, and the MOS device includes a gate dielectric layer 210 and a gate electrode 220. The material of the gate dielectric layer 210 is a high-K (dielectric constant K>7) metal oxide such as Ta2O5, TiO2, TiN, Al2O3, Pr2O3, La2O3, LaAlO3, HfO2, ZrO2, etc., so as to improve the carrier mobility and device performance. The material of the gate electrode 220 can be a polysilicon layer or a metal electrode layer. The semiconductor test structure in this embodiment is applicable to the gate capacitance test of MOS devices with different thicknesses and different materials. Therefore, the materials and thicknesses of the gate dielectric layer 210 and the gate electrode 220 of the MOS device are not specifically limited in this embodiment.

[0040] In one embodiment, the top metal layer 400 is connected to the gate electrode 220 of the MOS device to be tested through at least one interconnect metal layer 230 and at least two conductive plugs 240, and neither the interconnect metal layer 230 nor the conductive plug 240 is connected to the bottom metal layer 300. Specifically, the conductive plug 240 is formed through the following steps: using photolithography and etching processes, at least one through hole is formed in the dielectric layer on the surface of the interconnect metal layer 230 to penetrate the dielectric layer and expose the area on the interconnect metal layer 230 that needs to be electrically connected. Then, the through hole is filled with a conductive material, and the conductive material is planarized to form a conductive plug 240 located in the through hole. Further, before filling the conductive material, it also includes: forming a barrier layer on the sidewall and bottom of the through hole, and the barrier layer is used to prevent the diffusion or migration of the metal in the conductive plug 240. In this embodiment, through the connection structure of the at least one interconnect metal layer 230 and the at least two conductive plugs 240, the gate electrode 220 can be led out over a long distance in the horizontal direction and / or the vertical direction, and corresponding pads 500 are arranged in an area convenient for testing, so as to realize a more flexible and convenient gate capacitance test.

[0041] Optionally, the conductive plug 240 is a tungsten plug or a copper plug. By selecting an appropriate material for the conductive plug 240, a stable electrical connection between the top metal layer 400 and the gate electrode 220 can be formed. As Figure 3 shown, the lengths of the at least two conductive plugs 240 can be different.

[0042] Further, as Figure 4As shown, the semiconductor test structure further includes at least one intermediate metal layer 600, which is disposed between the bottom metal layer 300 and the top metal layer 400. The intermediate metal layer 600 at least partially overlaps with the top metal layer 400 and the bottom metal layer 300 in the vertical direction, and the intermediate metal layer 600 is not interconnected with at least one of the bottom metal layer 300 and the top metal layer 400. In the Figure 4 embodiment shown, the semiconductor test structure includes one intermediate metal layer 600, which is connected to the bottom metal layer 300 and not interconnected with the top metal layer 400. When the intermediate metal layer 600 at least partially overlaps with the top metal layer 400 in the vertical direction, a parallel plate capacitor structure is formed between the intermediate metal layer 600 and the top metal layer 400. It should be noted that in this embodiment, the area of each metal layer is not specifically limited. As long as at least some adjacent metal layers are not interconnected, the technical problem of excessive parasitic capacitance in the traditional test structure can be solved.

[0043] In Figure 4 the embodiment shown, a parasitic capacitance C1 is formed between the bottom metal layer 300 and the substrate 100, and a parasitic capacitance C3 is formed between the top metal layer 400 and the intermediate metal layer 600. The parasitic capacitances C1 and C3 are connected in series as shown in Figure 5 to jointly form a total parasitic capacitance C 寄 , and the total parasitic capacitance C 寄 is connected in parallel with the gate capacitance C real , so the test capacitance C measure = C 寄 + C real . The parasitic capacitances C 寄 , C1, and C3 satisfy the following formula: 1 / C 寄 = 1 / C1 + 1 / C3. From the formula, it can be seen that C 寄 is less than C1. The parasitic capacitance C 寄 in this embodiment makes the deviation between the test capacitance C measure and the gate capacitance C real less than the deviation in the traditional capacitive semiconductor test structure, thereby improving the accuracy of the gate capacitance C real test results.

[0044] Furthermore, the bottom metal layer 300, the intermediate metal layer 600, and the top metal layer 400 are not interconnected with each other. As shown in Figure 6As shown, a parasitic capacitance C1 is formed between the bottom metal layer 300 and the substrate 100, a parasitic capacitance C2 is formed between the middle metal layer 600 and the bottom metal layer 300, a parasitic capacitance C3 is formed between the top metal layer 400 and the middle metal layer 600, and the parasitic capacitances C1, C2, and C3 form a series connection as shown in Figure 7 to jointly form a total parasitic capacitance C 寄 . The total parasitic capacitance C 寄 and the gate capacitance C real form a parallel connection, so the test capacitance C measure = C 寄 + C real . The parasitic capacitances C 寄 , C1, C2, and C3 satisfy the following formula: 1 / C 寄 = 1 / C1 + 1 / C2 + 1 / C3. Compared with the embodiment shown in Figure 4 , by setting that there is no interconnection between the bottom metal layer 300, the middle metal layer 600, and the top metal layer 400, the parasitic capacitance C 寄 is further reduced, making the test result of the gate capacitance C real more accurate.

[0045] In one embodiment, the semiconductor test structure includes at least two middle metal layers 600, and the at least two middle metal layers 600 are all disposed between the bottom metal layer 300 and the top metal layer 400. At least one of the bottom metal layer 300 and the top metal layer 400 is not interconnected with any of the middle metal layers 600. In this embodiment, by increasing the number of middle metal layers 600, more parasitic capacitances can be formed. The more the parasitic capacitances in series connection, the smaller the capacitance value of the total parasitic capacitance C 寄 , and the smaller the influence on the test result of the gate capacitance C real . The adjacent top metal layer 400, at least two middle metal layers 600, and the bottom metal layer 300 all at least partially overlap in the vertical direction. In one example, the semiconductor test structure includes a bottom metal layer 300, a first middle metal layer, a second middle metal layer, and a top metal layer 400 arranged in sequence. The first middle metal layer at least partially overlaps with the bottom metal layer 300 and the second middle metal layer in the vertical direction. The second middle metal layer at least partially overlaps with the first middle metal layer and the top metal layer 400 in the vertical direction. By the adjacent metal layers at least partially overlapping in the vertical direction, a parallel plate capacitor structure is formed between the adjacent metal layers, and by connecting multiple parallel plate capacitors in series, the effect of reducing the total parasitic capacitance C 寄 is achieved.

[0046] According to the calculation formula in the foregoing embodiment, the interconnection between adjacent metal layers will cause the parasitic capacitance C寄 increases. Therefore, when the semiconductor test structure includes at least two intermediate metal layers 600, if there is no interconnection between the bottom metal layer 300, the at least two intermediate metal layers 600, and the top metal layer 400, the total parasitic capacitance of the semiconductor test structure is minimized.

[0047] In one embodiment, the pad 500 is disposed on the surface of the top metal layer 400. As Figure 8 shown, a passivation layer 800 is provided on the surface of the top metal layer 400. The passivation layer 800 has an opening, and the portion of the top metal layer 400 exposed in the opening constitutes the pad 500. Designers can select a more suitable setting method for the pad 500 according to the setting rules of the actual device structure and test requirements, so as to achieve more convenient gate capacitance testing.

[0048] Further, as Figure 9 shown, a first dielectric layer 710 is filled between the bottom metal layer 300 and the substrate 100. In one embodiment, a dielectric layer is also filled between the bottom metal layer 300 and the top metal layer 400. When an intermediate metal layer 600 is provided between the bottom metal layer 300 and the top metal layer 400, the dielectric layer is filled between adjacent metal layers, as Figure 9 the second dielectric layer 720 and the third dielectric layer 730 in. The materials of the respective dielectric layers may be different, but the dielectric constants of the selected dielectric layer materials are not greater than 5. By providing a dielectric layer with a low dielectric constant, the structures of the bottom metal layer 300, the intermediate metal layer 600, and the top metal layer 400 can be ensured to be stable, and the isolation performance of the formed dielectric layer can be ensured, and the parasitic capacitance in the semiconductor test structure can be reduced.

[0049] In one embodiment, the material of the dielectric layer is silicon oxide or silicon nitride, and the dielectric layer can be formed by atomic layer deposition (Atomic Layer Deposition) or chemical vapor deposition (Chemical Vapor Deposition), so as to ensure the thickness accuracy and film flatness of the dielectric layer.

[0050] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0051] The above-described embodiments merely represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all fall within the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.

Claims

1. A semiconductor test structure is used as a lead-out terminal of a gate electrode to connect with an external test structure when testing the gate capacitance of a MOS device, and is characterized in that, The semiconductor test structure includes: a substrate, on which a MOS device to be tested is provided, the MOS device includes a gate electrode and a gate dielectric layer, and the material of the gate dielectric layer is a high-K metal oxide; a pad for connecting to an external test structure; a top metal layer connected to both the pad and the gate electrode of the MOS device to be tested; a bottom metal layer not interconnected with the gate electrode, the pad and the top metal layer, and series parasitic capacitances are formed between the bottom metal layer and the substrate and between the bottom metal layer and the top metal layer.

2. The semiconductor test structure according to claim 1, wherein The semiconductor test structure further includes at least one intermediate metal layer provided between the bottom metal layer and the top metal layer, the intermediate metal layer at least partially overlaps with the top metal layer and the bottom metal layer in the vertical direction, and the intermediate metal layer is not interconnected with at least one of the bottom metal layer and the top metal layer.

3. The semiconductor test structure according to claim 2, wherein The intermediate metal layer is not interconnected with both the top metal layer and the bottom metal layer.

4. The semiconductor test structure according to claim 2, wherein The semiconductor test structure includes at least two intermediate metal layers, the at least two intermediate metal layers are all provided between the bottom metal layer and the top metal layer, and adjacent top metal layer, at least two intermediate metal layers and bottom metal layer at least partially overlap in the vertical direction, and at least one of the bottom metal layer and the top metal layer is not interconnected with any intermediate metal layer.

5. The semiconductor test structure according to claim 4, wherein The at least two intermediate metal layers are not interconnected with each other.

6. The semiconductor test structure according to claim 1, wherein The pad is provided on the surface of the top metal layer.

7. The semiconductor test structure according to claim 6, wherein A passivation layer is provided on the surface of the top metal layer, the passivation layer has an opening, and the part of the top metal layer exposed in the opening constitutes the pad.

8. The semiconductor test structure according to claim 1, characterized in that, The top metal layer and the gate electrode of the MOS device to be tested are connected through at least one interconnect metal layer and at least two conductive plugs, and the interconnect metal layer and the conductive plugs are not connected to the bottom metal layer.

9. The semiconductor test structure according to claim 1, wherein, A dielectric layer is filled between the bottom metal layer and the top metal layer, and the dielectric constant of the material of the dielectric layer is not greater than 5.

10. The semiconductor test structure according to claim 9, wherein, The material of the dielectric layer is silicon oxide or silicon nitride.

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