Operating method of electrically erasable programmable read-only memory

Abstract

An operating method of a charged erasable programmable read-only memory, wherein a transistor structure is arranged on a semiconductor substrate, and the transistor structure has a first conductive gate. At the same time, the same type of ions are implanted in the semiconductor substrate at the junction of the first conductive gate and the source and drain or in the ion doping region of the source and drain to increase the ion concentration in the region to reduce the voltage difference for writing and erasing. The operating method proposed by the corresponding element of the present invention includes setting the drain or source to a floating condition, thereby achieving rapid writing and erasing of a large number of memory cells. In addition to being applicable to a single-gate transistor structure, the present invention is more suitable for a charged erasable programmable read-only memory with a floating gate structure.

Description

Technical Field

[0001] The present invention relates to a powered erasable programmable read-only memory technology, and in particular to a fast writing and erasing operation method of the powered erasable programmable read-only memory. Background Art

[0002] In today's world of advanced computer information products, non-volatile memories such as Electrically Erasable Programmable Read Only Memory (EEPROM) and Flash are semiconductor storage devices that can be programmed multiple times electronically. Only a specific voltage is needed to erase the data in the memory in order to write new data, and the data will not disappear after the power is turned off. Therefore, they are widely used in various electronic products.

[0003] Since non-volatile memory is programmable, it uses stored charge to change the gate voltage of the memory's transistor, or does not store charge to leave the gate voltage of the original memory's transistor. The erase operation removes the charge stored in the non-volatile memory, so that the non-volatile memory returns to the gate voltage of the original memory's transistor. For current non-volatile memory, a high voltage difference is required when erasing, which will increase the area and process complexity.

[0004] In view of this, the inventor of this case has proposed a low-current and low-voltage-difference electrically erasable programmable read-only memory to address the deficiencies of the above-mentioned prior art. After further in-depth research, a low-voltage and fast operating method for this memory architecture has been proposed. Summary of the invention

[0005] The main purpose of the present invention is to provide an operating method of a charged erasable programmable read-only memory, which uses a charged erasable programmable read-only memory and increases the electric field between the transistor or the substrate and the gate by increasing the ion implantation concentration for the memory, thereby reducing the voltage difference between writing and erasing; at the same time, through the operating conditions of the present invention, the source or drain is set to floating, so as to achieve the effect of fast writing and fast erasing of a large number of memory cells.

[0006] To achieve the above-mentioned purpose, the present invention proposes an operating method of a charged erasable programmable read-only memory, which is applied to a charged erasable programmable read-only memory. The charged erasable programmable read-only memory mainly includes a semiconductor substrate on which at least one transistor structure is arranged. The transistor structure includes a first dielectric layer located on the surface of the semiconductor substrate, a first conductive gate arranged on the first dielectric layer, and at least two first ion-doped regions respectively located in the semiconductor substrate and on both sides of the first conductive gate to serve as a source and a drain respectively; wherein, the same type of ions are further implanted in the semiconductor substrate or in the first ion-doped region at the junction of the first conductive gate and the source and drain by ion implantation to increase the ion concentration and reduce the voltage difference between writing and erasing.

[0007] Of course, in addition to the single-gate transistor structure mentioned above, the present invention is also applicable to a floating gate structure. Therefore, in addition to the aforementioned transistor structure, it further includes a capacitor structure located on the surface of the semiconductor substrate and isolated from the transistor. The capacitor structure includes a second ion-doped region located in the semiconductor substrate, a second dielectric layer located on the surface of the second ion-doped region, and a second conductive gate stacked on the second dielectric layer, and the second conductive gate is electrically connected to the first conductive gate to serve as a floating gate.

[0008] As mentioned above, no matter it is a single gate transistor structure or a floating gate structure, the implanted same type ions can increase the ion concentration in the semiconductor substrate or in the first ion doping region by 1 to 10 times.

[0009] Wherein, when the transistor structure of the present invention is an N-type transistor, the first ion doping region or the second ion doping region is an N-type doping region, and the semiconductor substrate is a P-type semiconductor substrate or a semiconductor substrate with a P-type well. When the transistor structure of the present invention is a P-type transistor, the first ion doping region or the second ion doping region is a P-type doping region, and the semiconductor substrate is an N-type semiconductor substrate or a semiconductor substrate with an N-type well.

[0010] Regardless of whether it is a single gate structure or a floating gate structure, different operation methods are required due to the different regions where the ion concentration is increased and the different types of transistors.

[0011] When the transistor is an N-type transistor and the same type of ions are implanted in the first ion doping region to increase its ion concentration, the operating method of the present invention includes applying a gate voltage V to the first conductive gate or floating gate, the source, the drain and the semiconductor substrate respectively. g , source voltage V s , Drain voltage V d and substrate voltage V subp , and meet the following conditions:

[0012] When writing to the N-type transistor, V subp is ground (0), V d is high voltage (HV), V s is floating, and V g is high voltage (HV); or, satisfies V subp is ground (0), V s is high voltage (HV), V d is floating, and V g It is high voltage (HV).

[0013] When erasing the N-type transistor, V subp is ground (0), V d is high voltage (HV), V s is floating, and V g is floating; or, satisfies V subp is ground (0), V s is high voltage (HV), V d is floating, and V g For floating connection.

[0014] When the transistor is a P-type transistor and the same type of ions are implanted in the first ion doping region to increase its ion concentration, the operating method of the present invention includes applying a gate voltage V to the first conductive gate or floating gate, the source, the drain and the semiconductor substrate respectively. g , source voltage V s , drain voltage V d and substrate voltage V subn , and meet the following conditions:

[0015] When writing to the P-type transistor, V subn is high voltage (HV), V d is grounded, V s is floating, and V g is grounded; or, satisfies V subn is high voltage (HV), V s is grounded, V d is floating, and V g For grounding.

[0016] When erasing the P-type transistor, V subn is high voltage (HV), V d is grounded, V s is floating, and V g is floating; or, satisfies V subn is high voltage (HV), V s is grounded, V d is floating, and V g For floating connection.

[0017] The following is a detailed description of the specific embodiments in conjunction with the attached drawings, so that the purpose, technical content and effects achieved by the present invention can be more easily understood. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1a The schematic diagram of the structure of the electrically erasable programmable read-only memory of the present invention further performs ion implantation in the first ion doping region (source / drain).

[0019] Figure 1b It is a schematic structural diagram of the electrically erasable programmable read-only memory of the present invention and then ion implantation in a semiconductor substrate.

[0020] Figure 2 It is a schematic diagram of a single memory cell structure having an N-type transistor and a single gate structure according to the present invention.

[0021] Figure 3 It is a schematic diagram of a single memory cell structure having an N-type transistor and a single floating gate structure according to the present invention.

[0022] Figure 4 It is a schematic diagram of a single memory cell structure having a P-type transistor and a single gate structure according to the present invention.

[0023] Figure 5 It is a schematic diagram of a single memory cell structure having a P-type transistor and a single floating gate structure according to the present invention.

[0024] Description of reference numerals: 10-semiconductor substrate; 12-transistor structure; 14-first dielectric layer; 16-first conductive gate; 18-source; 20-drain; 22-ion; 30-P-type semiconductor substrate; 32-N-type transistor; 320-first dielectric layer; 322-first conductive gate; 3221-floating gate; 3222-control dielectric layer; 3223-control gate; 324-source; 326-drain; 34-N-type well capacitor; 340-N-type well; 342-second dielectric layer electrical layer; 344-second conductive gate; 36-isolation element; 38-single floating gate; 40-N-type semiconductor substrate; 42-P-type transistor; 420-first dielectric layer; 422-first conductive gate; 4221-floating gate; 4222-control dielectric layer; 4223-control gate; 424-source; 426-drain; 44-P-type well capacitor; 440-P-type well; 442-second dielectric layer; 444-second conductive gate; 46-isolation element; 48-single floating gate. DETAILED DESCRIPTION

[0025] The present invention mainly provides an operating method of a charged erasable programmable read-only memory, which is applied to the charged erasable programmable read-only memory. The charged erasable programmable read-only memory uses the increase of ion implantation concentration to increase the electric field between the transistor or the substrate and the gate, so as to reduce the voltage difference between writing and erasing. Through the operating method of the present invention, the operating voltage is applied to the gate, source and drain connected to all memory cells at the same time, and the source or drain is set to a floating condition during operation, so as to achieve the effect of fast writing and fast erasing of a large number of memory cells.

[0026] like Figure 1a and Figure 1b As shown, the electrically erasable programmable read-only memory proposed in the present invention mainly includes: a semiconductor substrate 10, and at least one transistor structure is formed on the semiconductor substrate 10, the transistor structure 12 includes a first dielectric layer 14 located on the surface of the semiconductor substrate 10, a first conductive gate 16 is provided on the first dielectric layer 14, and at least two first ion doped regions (18, 20) are respectively located in the semiconductor substrate 10 and located on both sides of the first conductive gate 16 to serve as the source 18 and the drain 20 respectively. Among them, the present invention can allow electrons to pass through the dielectric layer (oxide layer) by the voltage difference between the source / drain and the gate, or by the voltage difference between the substrate / well and the gate, so as to achieve low current writing and erasing. Therefore, there are two ways to increase the ion implantation concentration. One is as follows: Figure 1a As shown, ion implantation is used to implant the same type of ions 22 in the first ion doping regions 18 and 20 at the junction of the first conductive gate 16 and the source 18 and the drain 20. That is, if the first ion doping regions 18 and 20 are P-type, P-type ions 22 are implanted, and if they are N-type, N-type ions 22 are implanted to increase the ion concentration. The ion concentration in the first ion doping regions 18 and 20 is increased by 1 to 10 times of the original concentration, so as to apply a voltage difference between the transistor structure and the first conductive gate for writing and erasing, thereby reducing the voltage difference for writing and erasing. Another method is as follows Figure 1b As shown, ion implantation is used to implant the same type of ions 22 into the semiconductor substrate 10 at the junction of the first conductive gate 16 and the source 18 and the drain 20. That is, if the semiconductor substrate is P-type, P-type ions 22 are implanted, and if it is N-type, N-type ions 22 are implanted to increase its ion concentration. Similarly, the ion concentration in the semiconductor substrate 10 is increased by 1 to 10 times the original concentration, so as to apply a voltage difference between the semiconductor substrate and the first conductive gate for operation.

[0027] Continuing from the above, spacers (not shown) are further provided on both side walls of the first dielectric layer and the second conductive gate of the transistor structure, and the same type of ions implanted in the first ion doping region at the junction of the first conductive gate 16 and the source 18 and the drain 20 are first implanted before the formation of this spacer to increase the concentration of this doping region, and this first ion doping region 18, 20 further has a lightly doped drain (LDD). At this time, the preferred doping position is this lightly doped drain (LDD) region.

[0028] Among them, in addition to the above-mentioned single gate structure, the present invention also applies to the single floating gate structure by using the above two structures to increase the ion concentration. The only difference is that if it is a single floating gate structure, the present invention further includes a capacitor structure so that the second conductive gate of the capacitor structure is electrically connected to the first conductive gate to serve as a single floating gate. The detailed application and operation methods of various structures will be described in sequence as follows.

[0029] First, see Figure 2 As shown, a single memory cell structure of a electrically erasable programmable read-only memory includes a P-type semiconductor substrate 30, which may also be a semiconductor substrate with a P-type well. Taking the P-type semiconductor substrate 30 as an example, an N-type transistor 32 is arranged on the P-type semiconductor substrate 30, such as an N-type metal oxide semiconductor field effect transistor (MOSFET). The N-type transistor includes a first dielectric layer 320 located on the surface of the P-type semiconductor substrate 30, a first conductive gate 322 stacked on the first dielectric layer 320, and two N-type ion-doped regions located in the P-type semiconductor substrate 30, which serve as its source 324 and drain 326 respectively, and a channel is formed between the source 324 and the drain 326; wherein the first conductive gate 322 further includes a floating gate 3221, a control dielectric layer 3222 and a control gate 3223 from bottom to top, which are stacked on the first dielectric layer 320 respectively, and this is a single gate structure.

[0030] Secondly, please refer to Figure 3As shown, a single memory cell structure of a electrically erasable programmable read-only memory includes a P-type semiconductor substrate 30, on which an N-type transistor 32 and an N-well capacitor 34 are disposed, and the two are separated by an isolation element 36. The N-type transistor 32, such as an N-type metal oxide semiconductor field effect transistor (MOSFET), includes a first dielectric layer 320 located on the surface of the P-type semiconductor substrate 30, a first conductive gate 322 stacked on the first dielectric layer 320, and two N-type ion doped regions located in the P-type semiconductor substrate 30 to serve as its source 324 and drain 326 respectively, and a channel is formed between the source 324 and the drain 326. The N-type well capacitor 34 includes a second ion doped region in the P-type semiconductor substrate 30 as the N-type well 340, a second dielectric layer 342 is located on the surface of the N-type well 340, and a second conductive gate 344 is disposed on the second dielectric layer 342 to form a top plate-dielectric layer-bottom plate capacitor structure. The first conductive gate 322 of the N-type transistor 32 and the second conductive gate 344 of the N-type well capacitor 34 are electrically connected and isolated by the isolation element 36 to form a single floating gate 38 structure.

[0031] Please also see Figure 2 and Figure 3 As shown, whether it is Figure 2 or Figure 3 The memory cell structure shown in the figure, when the electrically erasable programmable read-only memory has an N-type transistor 32, and the same type of N-type or P-type ions are implanted in the ion doping region of the source 324 and the drain 326 near the junction of the first conductive gate 322, so as to increase the ion concentration, for example, by 1 to 10 times, the operating method of the present invention includes: applying a gate voltage V to the first conductive gate 322 or the single floating gate 38, the source 324, the drain 326 and the P-type semiconductor substrate 30 respectively g , source voltage V s , drain voltage V d and substrate voltage V subp , and the following conditions are met at the same time:

[0032] When writing to the N-type transistor 32, V subp is ground (0), V d is high voltage (HV), V s is floating, and V g is high voltage (HV); or, satisfies V subp is ground (0), V s is high voltage (HV), V d is floating, and V g is high voltage (HV); and

[0033] When erasing the N-type transistor 32, V subp is ground (0), V d is high voltage (HV), V s is floating, and V g is floating; or, satisfies V subp is ground (0), V s is high voltage (HV), V d is floating, and V g For floating connection.

[0034] Please refer to Figure 4 As shown, a single memory cell structure of a electrically erasable programmable read-only memory includes an N-type semiconductor substrate 40, which may also be a semiconductor substrate with an N-type well. Taking the N-type semiconductor substrate 40 as an example, a P-type transistor 42 is arranged on the N-type semiconductor substrate 40, such as a P-type metal oxide semiconductor field effect transistor (MOSFET). The P-type transistor includes a first dielectric layer 420 located on the surface of the N-type semiconductor substrate 40, a first conductive gate 422 stacked on the first dielectric layer 420, and two P-type ion-doped regions located in the N-type semiconductor substrate 40 to serve as its source 424 and drain 426 respectively, and a channel is formed between the source 424 and the drain 426; wherein the first conductive gate 422 further includes a floating gate 4221, a control dielectric layer 4222 and a control gate 4223 from bottom to top, which are stacked on the first dielectric layer 420 respectively, which is a single gate structure.

[0035] Then as Figure 5 As shown, a single memory cell structure of a electrically erasable programmable read-only memory includes an N-type semiconductor substrate 40, on which a P-type transistor 42 and a P-type well (N-well) capacitor 44 are disposed, and the two are separated by an isolation element 46. The P-type transistor 42, such as a P-type metal oxide semiconductor field effect transistor (MOSFET), includes a first dielectric layer 420 located on the surface of the N-type semiconductor substrate 40, a first conductive gate 422 stacked on the first dielectric layer 420, and two N-type ion doped regions located in the N-type semiconductor substrate 40 to serve as its source 424 and drain 426 respectively, and a channel is formed between the source 424 and the drain 426. The P-type well capacitor 44 includes a second ion doped region in the N-type semiconductor substrate 40 as the P-type well 440, a second dielectric layer 442 is located on the surface of the P-type well 440, and a second conductive gate 444 is disposed on the second dielectric layer 442 to form a top plate-dielectric layer-bottom plate capacitor structure. The first conductive gate 422 of the P-type transistor 42 and the second conductive gate 444 of the P-type well capacitor 44 are electrically connected and separated by an isolation element 46 to form a single floating gate 48 structure.

[0036] Please also check Figure 4 and Figure 5 As shown, whether it is Figure 4 or Figure 5 The memory cell structure shown in the figure, when the electrically erasable programmable read-only memory has a P-type transistor 42, and the ion doping region of the source 424 and the drain 426 near the junction of the first conductive gate 422 is further implanted with the same type of P-type or N-type ions to increase its ion concentration, for example, by 1 to 10 times. The operating method of the present invention includes: applying a gate voltage V to the first conductive gate 422 or the single floating gate 48, the source 424, the drain 426 and the N-type semiconductor substrate 40 respectively. g , source voltage V s , drain voltage V d and substrate voltage V subn , and the following conditions are met at the same time:

[0037] When writing to the P-type transistor 42, V subn is high voltage (HV), V d is grounded, V s is floating, and V g is grounded; or, satisfies V subn is high voltage (HV), V s is grounded, V d is floating, and V g For grounding.

[0038] When erasing the P-type transistor 42, V subn is high voltage (HV), V d is grounded, V s is floating, and V g is floating; or, satisfies V subn is high voltage (HV), V s is grounded, V d is floating, and V g For floating connection.

[0039] According to the electrically erasable programmable read-only memory provided by the present invention, since writing and erasing during operation are related to the concentration of the input, and may even affect the applied voltages of the source, drain, and gate, as long as there is a sufficient voltage difference between the source, drain, and gate, the writing and erasing effects can be achieved. Therefore, negative voltage can also be used instead of grounding, which can reduce the high voltage required by the prior art. For this memory architecture that can achieve low-voltage operation, the present invention specifically proposes that the source or drain can be set to a floating condition when writing or erasing, making the operation of the memory cell simpler and faster.

[0040] The embodiments described above are only for illustrating the technical ideas and features of the present invention, and their purpose is to enable those familiar with the art to understand the contents of the present invention and implement them accordingly. They cannot be used to limit the patent scope of the present invention. That is, all equivalent changes or modifications made according to the spirit disclosed by the present invention should still be included in the patent scope of the present invention.

Claims

1. An operating method of a charged erasable programmable read-only memory, the charged erasable programmable read-only memory comprising a semiconductor substrate on which at least one N-type transistor structure is disposed, the N-type transistor structure having a first conductive gate and at least two first ion-doped regions located in the semiconductor substrate and on both sides of the first conductive gate to serve as a source and a drain respectively, and the first ion-doped regions at the junction of the first conductive gate and the source and the drain are further implanted with the same type of ions to increase their ion concentration, characterized in that: The method of operation includes: A gate voltage V is applied to the first conductive gate, the source, the drain and the semiconductor substrate respectively. g , source voltage V s , Drain voltage V d and substrate voltage V subp , and meet the following conditions: When writing to the N-type transistor structure, V subp is ground (0), V d is high voltage (HV), V s is floating, and V g is high voltage (HV); or, satisfies V subp is ground (0), V s is high voltage (HV), V d is floating, and V g is high voltage (HV); and When erasing the N-type transistor structure, V subp is ground (0), V d is high voltage (HV), V s is floating, and V g is floating; or, satisfies V subp is ground (0), V s is high voltage (HV), V d is floating, and V g For floating connection.

2. The method for operating a electrically erasable programmable read-only memory according to claim 1, wherein: The electrically erasable programmable read-only memory further includes a capacitor structure located on the surface of the semiconductor substrate and isolated from the at least one N-type transistor structure. The capacitor structure includes a second ion doped region located in the semiconductor substrate, and a second conductive gate electrically connected to the first conductive gate to serve as a single floating gate. At this time, the single floating gate is applied with the gate voltage V g .

3. The method for operating a electrically erasable programmable read-only memory according to claim 1, wherein: Implanting the same type of ions increases the ion concentration in the semiconductor substrate or in the first ion doping region by 1 to 10 times.

4. The method for operating a electrically erasable programmable read-only memory according to claim 1, wherein: The N-type transistor structure is an N-type metal oxide semi-field effect transistor.

5. The method for operating a electrically erasable programmable read-only memory according to claim 1, wherein: The first ion doped region further includes a lightly doped drain.

6. An operating method of a charged erasable programmable read-only memory, the charged erasable programmable read-only memory comprising a semiconductor substrate on which at least one P-type transistor structure is disposed, the P-type transistor structure having a first conductive gate and at least two first ion-doped regions located in the semiconductor substrate and on both sides of the first conductive gate to serve as a source and a drain respectively, and the first ion-doped regions at the junction of the first conductive gate and the source and the drain are further implanted with the same type of ions to increase their ion concentration, characterized in that: The method of operation includes: A gate voltage V is applied to the first conductive gate, the source, the drain and the semiconductor substrate respectively. g , source voltage V s , Drain voltage V d and substrate voltage V subn , and meet the following conditions: When writing to the P-type transistor structure, V subn is high voltage (HV), V d is grounded, V s is floating, and V g is grounded; or, satisfies V subn is high voltage (HV), V s is grounded, V d is floating, and V g for grounding; and When erasing the P-type transistor structure, V subn is high voltage (HV), V d is grounded, V s is floating, and V g is floating; or, satisfies V subn is high voltage (HV), V s is grounded, V d is floating, and V g For floating connection.

7. The method for operating a electrically erasable programmable read-only memory according to claim 6, wherein: The electrically erasable programmable read-only memory further includes a capacitor structure located on the surface of the semiconductor substrate and isolated from the at least one P-type transistor structure. The capacitor structure includes a second ion-doped region located in the semiconductor substrate, and a second conductive gate electrically connected to the first conductive gate to serve as a single floating gate. At this time, the single floating gate is applied with the gate voltage V g .

8. The method for operating a electrically erasable programmable read-only memory according to claim 6, wherein: Implanting the same type of ions increases the ion concentration in the semiconductor substrate or in the first ion doping region by 1 to 10 times.

9. The method for operating a electrically erasable programmable read-only memory according to claim 6, wherein: The P-type transistor structure is a P-type metal oxide half field effect transistor.

10. The method for operating a electrically erasable programmable read-only memory according to claim 6, wherein: The first ion doped region further includes a lightly doped drain.

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