Solid-state imaging device and video recording apparatus

Abstract

The solid-state imaging device (100) according to the present disclosure includes: a first semiconductor substrate (201) including a floating diffusion portion (221) for temporarily holding an electrical signal output from a photoelectric conversion element (203); and a second semiconductor substrate (301) facing the first semiconductor substrate (201). Here, the second semiconductor substrate (301) includes a first transistor (310) disposed on a side facing the first semiconductor substrate (201). The first transistor includes: a channel (315) extending along the thickness direction of the second semiconductor substrate (301); and a multi-gate (313) extending along the thickness direction of the second semiconductor substrate (301) and sandwiching the channel (315) therebetween. The multi-gate (313) of the first transistor (310) is connected to the floating diffusion portion (221). The video recording device of the present invention includes the above solid-state imaging device. The present invention can improve the photoelectric conversion efficiency of the photoelectric conversion element.

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging device and a video recording apparatus. Background Art

[0002] There is a three-dimensional packaging technology in which a plurality of semiconductor substrates are stacked. For example, a solid-state imaging device has a known structure in which a first semiconductor substrate on which a pixel region is formed and a second semiconductor substrate on which a logic circuit is formed are stacked (for example, see Patent Document 1).

[0003] List of Cited Documents

[0004] Patent Documents

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2010-245506 Summary of the Invention

[0006] Problems to be Solved by the Invention

[0007] The solid-state imaging device disclosed in Patent Document 1 cannot ensure sufficient space for arranging pixel transistors. Thus, a conceivable solution is, for example, to separate the substrate into a substrate on which a photoelectric conversion element is formed and a substrate on which a pixel transistor is formed, and stack these substrates.

[0008] However, such a structure may require long wiring to connect the substrate on which the photoelectric conversion element is formed and the substrate on which the pixel transistor is formed, resulting in a decrease in the photoelectric conversion efficiency of the photoelectric conversion element.

[0009] Therefore, the present disclosure provides a solid-state imaging device and a video recording apparatus that can improve the photoelectric conversion efficiency of a photoelectric conversion element by reducing the wiring length between mutually stacked substrates.

[0010] Means for Solving the Problems

[0011] The solid-state imaging device according to the present disclosure includes: a first semiconductor substrate including a floating diffusion portion for temporarily holding an electrical signal output from a photoelectric conversion element; and a second semiconductor substrate facing the first semiconductor substrate. Here, the second semiconductor substrate includes a first transistor disposed on a side facing the first semiconductor substrate, the first transistor including: a channel extending along the thickness direction of the second semiconductor substrate; and a multi-gate extending along the thickness direction of the second semiconductor substrate and sandwiching the channel therebetween. Moreover, the multi-gate of the first transistor is connected to the floating diffusion portion.

[0012] The video recording device according to the present disclosure includes: the above solid-state imaging element; an optical system that captures incident light from a subject to form an image on the imaging surface of the solid-state imaging element; and a signal processing circuit that processes an output signal from the solid-state imaging element. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a diagram showing an example of a schematic configuration of a solid-state imaging element to which each embodiment of the present disclosure is applicable.

[0014] Figure 2 is a diagram showing Figure 1 an example of sensor pixels and a readout circuit in

[0015] Figure 3 is a diagram showing Figure 1 an example of sensor pixels and a readout circuit in

[0016] Figure 4 is a diagram showing Figure 1 an example of sensor pixels and a readout circuit in

[0017] Figure 5 is a diagram showing Figure 1 an example of sensor pixels and a readout circuit in

[0018] Figure 6 is a diagram showing an example of a connection method between a plurality of readout circuits and a plurality of vertical signal lines.

[0019] Figure 7 is a diagram showing Figure 1 an example of a cross-sectional structure in the horizontal direction of the solid-state imaging element in

[0020] Figure 8 is a diagram showing Figure 1 an example of a cross-sectional structure in the horizontal direction of the solid-state imaging element in

[0021] Figure 9 is a diagram showing Figure 1 an example of a wiring layout in the horizontal plane in the solid-state imaging element in

[0022] Figure 10 is a diagram showing Figure 1 an example of a wiring layout in the horizontal plane in the solid-state imaging element in

[0023] Figure 11 is a diagram showing Figure 1 an example of a wiring layout in the horizontal plane in the solid-state imaging element in

[0024] Figure 12 is a diagram showing Figure 1A diagram showing an example of a wiring layout in a horizontal plane of a solid-state imaging device.

[0025] Figure 13 It is a diagram showing Figure 1 a modified example of a cross-sectional structure in the horizontal direction of a solid-state imaging device in.

[0026] Figure 14 It is a diagram showing Figure 1 a modified example of a cross-sectional structure in the horizontal direction of a solid-state imaging device in.

[0027] Figure 15 It is a diagram showing Figure 1 a modified example of a cross-sectional structure in the horizontal direction of a solid-state imaging device in.

[0028] Figure 16 It is a diagram showing Figure 1 a modified example of a cross-sectional structure in the horizontal direction of a solid-state imaging device in.

[0029] Figure 17 It is a diagram showing Figure 1 a modified example of a cross-sectional structure in the horizontal direction of a solid-state imaging device in.

[0030] Figure 18 It is a diagram showing Figure 1 a modified example of a cross-sectional structure in the horizontal direction of a solid-state imaging device in.

[0031] Figure 19 It is a diagram showing Figure 1 a modified example of a cross-sectional structure in the horizontal direction of a solid-state imaging device in.

[0032] Figure 20 It is a diagram showing Figure 1 a modified example of the circuit structure of a solid-state imaging device in the structure shown and any of its modified examples.

[0033] Figure 21 It is a diagram showing Figure 20 an example of a solid-state imaging device in which three substrates are stacked.

[0034] Figure 22 It is a diagram showing an example in which a logic circuit is separately formed on a substrate on which sensor pixels are arranged and a substrate on which a readout circuit is arranged.

[0035] Figure 23 It is a diagram showing an example in which a logic circuit is formed on a third substrate.

[0036] Figure 24 It is a diagram showing a part of the cross-section of a solid-state imaging device according to the first embodiment of the present disclosure.

[0037] Figure 25 It is a schematic diagram near the bonding position of a stack of solid-state imaging elements according to a first embodiment of the present disclosure.

[0038] Figure 26 It is a schematic diagram showing the structure of an enlarged transistor according to a first embodiment of the present disclosure.

[0039] Figure 27 It is a flowchart showing an example of the manufacturing process of a solid-state imaging element according to a first embodiment of the present disclosure.

[0040] Figure 28 It is a flowchart showing an example of the manufacturing process of a solid-state imaging element according to a first embodiment of the present disclosure.

[0041] Figure 29 It is a flowchart showing an example of the manufacturing process of a solid-state imaging element according to a first embodiment of the present disclosure.

[0042] Figure 30 It is a flowchart showing an example of the manufacturing process of a solid-state imaging element according to a first embodiment of the present disclosure.

[0043] Figure 31 It is a flowchart showing an example of the manufacturing process of a solid-state imaging element according to a first embodiment of the present disclosure.

[0044] Figure 32 It is a schematic diagram of a solid-state imaging element according to a comparative example of the present disclosure.

[0045] Figure 33 It is a schematic diagram showing the structure of an enlarged transistor in a solid-state imaging element according to a first modification of a first embodiment of the present disclosure.

[0046] Figure 34 It is a diagram showing a part of the cross-section of a solid-state imaging element according to a second modification of a first embodiment of the present disclosure.

[0047] Figure 35 It is a diagram showing a part of the cross-section of a solid-state imaging element according to a third modification of a first embodiment of the present disclosure.

[0048] Figure 36 It is a schematic diagram near the bonding position of a stack of solid-state imaging elements according to a second embodiment of the present disclosure.

[0049] Figure 37 It is a diagram showing an example of the schematic structure of an imaging system including the above solid-state imaging element.

[0050] Figure 38 It is shown in Figure 37A diagram of an example of an imaging process implemented in an imaging system.

[0051] Figure 39 A diagram showing an example of a schematic configuration of an imaging system according to a modified example including the above solid-state imaging device.

[0052] Figure 40 A block diagram showing an example of a schematic configuration of a vehicle control system.

[0053] Figure 41 An explanatory diagram showing an example of the installation positions of an out-of-vehicle information detection unit and an imaging unit.

[0054] Figure 42 A diagram showing an example of a schematic configuration of an endoscopic surgical system.

[0055] Figure 43 A block diagram showing an example of a functional configuration of a camera and a CCU (Camera Control Unit). Detailed Description of the Invention

[0056] Now, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following embodiments, the same parts are given the same reference numerals, and redundant descriptions are omitted.

[0057] [Schematic Configuration Example of Solid-State Imaging Device]

[0058] Hereinafter, with reference to Figures 1 to 19 a schematic configuration example of a solid-state imaging device will be described.

[0059] (Circuit Configuration Example of Solid-State Imaging Device)

[0060] Figure 1 A diagram showing a schematic configuration example of a solid-state imaging device 1 to which an embodiment of the present disclosure is applied. The solid-state imaging device 1 converts received light into an electrical signal and outputs the electrical signal as a pixel signal. In the given example, the solid-state imaging device 1 is formed as a complementary metal oxide semiconductor (CMOS) image sensor.

[0061] As Figure 1 shown, the solid-state imaging device 1 includes three substrates: a first substrate 10, a second substrate 20, and a third substrate 30. The solid-state imaging device 1 is an imaging device having a three-dimensional structure formed by bonding these three substrates together. The first substrate 10, the second substrate 20, and the third substrate 30 are stacked in this order.

[0062] The first substrate 10 includes a plurality of sensor pixels 12 for performing photoelectric conversion disposed on a semiconductor substrate 11. The plurality of sensor pixels 12 are arranged in a matrix form within a pixel region 13 of the first substrate 10. The second substrate 20 includes a readout circuit 22 disposed on a semiconductor substrate 21 for outputting a pixel signal corresponding to the charge output from the sensor pixel 12, wherein one readout circuit 22 is arranged for every four sensor pixels 12. The second substrate 20 includes a plurality of pixel driving lines 23 extending along the row direction and a plurality of vertical signal lines 24 extending along the column direction. The third substrate 30 includes a logic circuit 32 disposed on a semiconductor substrate 31 for processing the pixel signal. For example, the logic circuit 32 includes a vertical driving circuit 33, a column signal processing circuit 34, a horizontal driving circuit 35, and a system control circuit 36. The logic circuit 32 (or more specifically, the horizontal driving circuit 35) outputs the output voltage Vout of each sensor pixel 12 to the outside. In the logic circuit 32, for example, a low-resistance region may be formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode, and the low-resistance region contains silicides such as CoSi 2 or NiSi formed by using a self-aligned silicide (SALICIDE) process.

[0063] For example, the vertical driving circuit 33 sequentially selects the plurality of sensor pixels 12 row by row. For example, the column signal processing circuit 34 performs correlated double sampling (CDS) processing on the pixel signals output from each of the sensor pixels 12 in the row selected by the vertical driving circuit 33. For example, the column signal processing circuit 34 extracts the signal level of the pixel signal by performing CDS processing and holds the pixel data corresponding to the amount of light received by each sensor pixel 12. For example, the horizontal driving circuit 35 sequentially outputs the pixel data held in the column signal processing circuit 34 to the outside. For example, the system control circuit 36 controls the driving of each block of the vertical driving circuit 33, the column signal processing circuit 34, and the horizontal driving circuit 35 in the logic circuit 32.

[0064] Figures 2 to 5 Examples of the sensor pixel 12 and the readout circuit 22 are respectively shown. A description will be given below of the case where one readout circuit 22 is shared by four sensor pixels 12. The term "shared" here means that the outputs from the four sensor pixels 12 are input to the shared readout circuit 22. However, note that the sharing unit is not limited to a specific number of pixels. For example, the output from one sensor pixel 12 may be input to one readout circuit 22. In addition, as in this example, the outputs from four sensor pixels 12 may be input to one readout circuit 22.

[0065] As shown Figure 2 in the figure, each sensor pixel 12 includes components similar to those in other sensor pixels 12. In Figure 2 order to distinguish the components between the respective sensor pixels 12, identification numbers 1, 2, 3, or 4 are marked at the end of the symbols of the components of each sensor pixel 12. Hereinafter, when it is necessary to distinguish the components between the respective sensor pixels 12, identification numbers are marked at the end of the symbols of the components of each sensor pixel 12. When it is not necessary to distinguish the components between the respective sensor pixels 12, the identification numbers at the end of the symbols of the components of each sensor pixel 12 are omitted.

[0066] For example, each sensor pixel 12 includes: a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion section FD that temporarily holds the charge output from the photodiode PD via the transfer transistor TR. The photodiode PD corresponds to a specific example of the "photoelectric conversion element" of the present disclosure. The photodiode PD performs photoelectric conversion to generate charge corresponding to the received light amount. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line such as a ground wire (GND). The drain of the transfer transistor TR is electrically connected to the floating diffusion section FD, and the gate of the transfer transistor TR is electrically connected to the pixel drive line 23 (see Figure 1 ). For example, the transfer transistor TR is a CMOS transistor.

[0067] The floating diffusion sections FD of the respective sensor pixels 12 sharing a readout circuit 22 are electrically connected to each other and also electrically connected to the input terminal of the shared readout circuit 22. For example, the readout circuit 22 includes a reset transistor RST, a selection transistor SEL, and an amplification transistor AMP. Note that the selection transistor SEL can be omitted as needed. The source of the reset transistor RST as the input terminal of the readout circuit 22 is electrically connected to the floating diffusion section FD, and the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the amplification transistor AMP. The gate of the reset transistor RST is electrically connected to the pixel drive line 23 (see Figure 1 ). The source of the amplification transistor AMP is electrically connected to the drain of the selection transistor SEL, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. The source of the selection transistor SEL as the output terminal of the readout circuit 22 is electrically connected to the vertical signal line 24, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 23 (see Figure 1 ).

[0068] When the transfer transistor TR is in the ON state, the charge in the photodiode PD is transferred to the floating diffusion FD. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is in the ON state, the potential of the floating diffusion FD is reset to the potential of the power supply line VDD. The selection transistor SEL controls the timing of outputting the pixel signal from the readout circuit 22. The amplification transistor AMP generates a voltage signal corresponding to the level of the charge held in the floating diffusion FD as the pixel signal. The amplification transistor AMP is used to form a source follower amplifier and outputs a pixel signal having a voltage corresponding to the level of the charge generated in the photodiode PD. When the selection transistor SEL is in the ON state, the amplification transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to this potential to the column signal processing circuit 34 via the vertical signal line 24. For example, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are CMOS transistors.

[0069] Note that, as Figure 3 shown, the selection transistor SEL may be arranged between the power supply line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 23 (see Figure 1 ). The source of the amplification transistor AMP, which is the output terminal of the readout circuit 22, is electrically connected to the vertical signal line 24, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST.

[0070] In addition, as Figure 4 and Figure 5As shown, an FD transfer transistor FDG may be provided between the source of the reset transistor RST and the gate of the amplification transistor AMP. The FD transfer transistor FDG is used when switching the conversion efficiency. Generally, a small pixel signal is generated when imaging in a dim place. When performing charge-voltage conversion based on Q = CV, as the capacitance C of the floating diffusion section FD increases, the voltage V generated by the conversion in the amplification transistor AMP decreases. Conversely, when imaging in a bright place, a large pixel signal is generated, and therefore, unless the FD capacitance C is large, the floating diffusion section FD will not be able to receive all the charges from the photodiode PD. In addition, in order to avoid the voltage V generated by the conversion in the amplification transistor AMP from being too high, the FD capacitance C needs to be large enough. Considering these matters, when the FD transfer transistor FDG is in the ON state, since the gate capacitance of the FD transfer transistor FDG is added, the total FD capacitance C increases. Conversely, when the FD transfer transistor FDG is in the OFF state, the total FD capacitance C decreases. Thus, by turning the FD transfer transistor FDG on / off, the FD capacitance C can be made variable, thereby enabling the switching of the conversion efficiency.

[0071] Figure 6 FIG. is an example showing the connection manner between a plurality of readout circuits 22 and a plurality of vertical signal lines 24. When a plurality of readout circuits 22 are arranged along the extending direction of the vertical signal lines 24, i.e., the column direction, each of the plurality of vertical signal lines 24 can be allocated to each readout circuit 22 one-to-one. For example, as Figure 6 shown, when four readout circuits 22 are arranged along the extending direction of the vertical signal lines 24, each of the four vertical signal lines 24 can be allocated to each readout circuit 22 one-to-one. Note that in Figure 6 , in order to distinguish each vertical signal line 24 from each other, identification numbers 1, 2, 3, or 4 are marked at the end of the symbol of each vertical signal line 24.

[0072] (Example of the physical structure of the solid-state imaging device)

[0073] Figure 7 and Figure 8 are diagrams respectively showing examples of the cross-sectional structure of the solid-state imaging device 1 in the horizontal direction. Figure 7 and Figure 8 The upper side views of each show Figure 1 an example of the cross-sectional structure of the first substrate 10 in the horizontal direction in Figure 7 and Figure 8 The lower side views of each show Figure 1 an example of the cross-sectional structure of the second substrate 20 in the horizontal direction in Figure 7 shows an example of the structure of four sensor pixels 12 of 2×2 arranged in two groups along the second direction H, whileFigure 8 An example of a configuration is shown in which four groups of 2×2 of four sensor pixels 12 are arranged along the first direction V and the second direction H. Note that Figure 7 and Figure 8 In the upper cross-sectional view of each, Figure 1 A diagram showing an example of the surface structure of the semiconductor substrate 11 is superimposed on a diagram showing an example of the cross-sectional structure of the first substrate 10 in the horizontal direction. Figure 7 and Figure 8 In the lower cross-sectional view of each, Figure 1 A diagram showing an example of the surface configuration of the semiconductor substrate 21 is superimposed on a diagram showing an example of the cross-sectional configuration of the second substrate 20 in the horizontal direction.

[0074] like Figure 7 and Figure 8 As shown, the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 are arranged in the plane of the first substrate 10 along the first direction V (ie, Figure 7 The up and down direction) or along the second direction H (ie, Figure 8 The left and right directions in the middle are arranged in a strip shape. Figure 7 and Figure 8 The case where the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 are arranged in two rows along the first direction V or the second direction H is illustrated. For example, the first direction V or the second direction H is parallel to one of the two arrangement directions (i.e., the row direction and the column direction) of the plurality of sensor pixels 12 arranged in a matrix form. For example, in the four sensor pixels 12 of the common readout circuit 22, the four floating diffusions FD are arranged close to each other across the pixel separation portion 43. In the four sensor pixels 12 of the common readout circuit 22, the gate electrodes TG of the four transfer transistors TR are arranged to surround the four floating diffusions FD. For example, the four gate electrodes TG form a ring shape.

[0075] An insulating layer 53 exists in a portion of the semiconductor substrate 21 where a plurality of through wirings 54 penetrate. The insulating layer 53 includes a plurality of blocks extending along a first direction V or a second direction H. The semiconductor substrate 21 includes a plurality of island-like blocks 21A extending along the first direction V or the second direction H, and the plurality of island-like blocks 21A are arranged side by side in a second direction H or a first direction V orthogonal to the first direction V or the second direction H with the insulating layer 53 interposed therebetween. In each block 21A, for example, a plurality of sets of reset transistors RST, amplification transistors AMP, and selection transistors SEL are provided. For example, one readout circuit 22 shared by four sensor pixels 12 includes: a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL arranged in a region facing the four sensor pixels 12. For example, one readout circuit 22 shared by four sensor pixels 12 includes: an amplification transistor AMP in a block 21A immediately adjacent to the left side of the insulating layer 53; and a reset transistor RST and a selection transistor SEL in a block 21A immediately adjacent to the right side of the insulating layer 53.

[0076] Figures 9 to 12 are diagrams respectively showing examples of wiring layouts in a horizontal plane in the solid-state imaging device 1. Figures 9 to 12 Examples are respectively shown in which one readout circuit 22 shared by four sensor pixels 12 is arranged in a region facing the four sensor pixels 12. For example, Figures 9 to 12 the wirings shown are arranged in different layers in a wiring layer (not shown) provided on the pixel transistors. For example, the wiring layer includes: a plurality of pixel driving lines 23; a plurality of vertical signal lines 24; and pad electrodes (not shown) exposed on the surface of the wiring layer and used for electrical connection between the second substrate 20 and the third substrate 30.

[0077] As Figure 9 shown, for example, four adjacent through wirings 54 are electrically connected to a connection wiring 55. The four adjacent through wirings 54 are further electrically connected via the connection wiring 55 and a connection portion 59 to the gate of the amplification transistor AMP included in the block 21A immediately adjacent to the left side of the insulating layer 53 and to the gate of the reset transistor RST included in the block 21A immediately adjacent to the right side of the insulating layer 53.

[0078] As Figure 10As shown, for example, the power supply line VDD is arranged at a position facing each of the readout circuits 22 arranged side by side along the second direction H. For example, the power supply line VDD is electrically connected to the drain of the amplification transistor AMP and the drain of the reset transistor RST in each of the readout circuits 22 arranged side by side along the second direction H via the connection portion 59. For example, two pixel drive lines 23 are arranged at positions facing each of the readout circuits 22 arranged side by side along the second direction H. For example, one of the two pixel drive lines 23 is the wiring RSTG, which is electrically connected to the gate of the reset transistor RST in each of the readout circuits 22 arranged side by side along the second direction H. For example, the other pixel drive line 23 is the wiring SELG, which is electrically connected to the gate of the selection transistor SEL in each of the readout circuits 22 arranged side by side along the second direction H. In each readout circuit 22, for example, the source of the amplification transistor AMP and the drain of the selection transistor SEL are electrically connected to each other via the wiring 25.

[0079] As Figure 11 shown, for example, two power supply lines VSS are arranged at positions facing each of the readout circuits 22 arranged side by side along the second direction H. For example, each power supply line VSS is electrically connected to a plurality of through wirings 47 at positions facing each of the sensor pixels 12 arranged side by side along the second direction H. For example, four pixel drive lines 23 are arranged at positions facing each of the readout circuits 22 arranged side by side along the second direction H. For example, each of the four pixel drive lines 23 is a wiring TRG as follows: which is electrically connected to one of the four sensor pixels 12 corresponding to each of the readout circuits 22 arranged side by side along the second direction H via the through wiring 48. That is, the four pixel drive lines 23 serving as control lines are electrically connected to the gate TG of the transfer transistor TR of each of the sensor pixels 12 arranged side by side along the second direction H. Note that in Figure 11 order to distinguish the wirings TRG from each other, an identification number 1, 2, 3, or 4 is marked at the end of the symbol of each wiring TRG.

[0080] As Figure 12 shown, for example, the vertical signal line 24 is arranged at a position facing each of the readout circuits 22 arranged side by side along the first direction V. For example, the vertical signal line 24 serving as an output line is electrically connected to the source of the amplification transistor AMP which is the output end of each of the readout circuits 22 arranged side by side along the first direction V.

[0081] (First Modification Example)

[0082] Figure 13 And Figure 14These are diagrams showing modified examples of the cross-sectional structure of the solid-state imaging device 1 in the horizontal direction. In Figure 13 and Figure 14 the upper side views of each show modified examples of the cross-sectional structure of the first substrate 10 in the horizontal direction in Figure 1 , and Figure 13 and Figure 14 the lower side views of each show modified examples of the cross-sectional structure of the second substrate 20 in the horizontal direction in Figure 1 . Note that in the upper side cross-sectional views of Figure 13 and Figure 14 , on the diagram showing the modified example of the cross-sectional structure of the first substrate 10 in the horizontal direction in Figure 1 , a diagram showing a modified example of the surface structure of the semiconductor substrate 11 in Figure 1 is superimposed. In addition, in the lower side cross-sectional views of Figure 13 and Figure 14 , on the diagram showing the modified example of the cross-sectional structure of the second substrate 20 in the horizontal direction in Figure 1 , a diagram showing a modified example of the surface structure of the semiconductor substrate 21 is superimposed.

[0083] As Figure 13 and Figure 14 show, a plurality of through wirings 54, a plurality of through wirings 48, and a plurality of through wirings 47, which are shown in the form of a plurality of points arranged in a matrix, are arranged in a band shape along the Figure 13 and Figure 14 left-right direction (i.e., the second direction H) in the plane of the first substrate 10. Note that Figure 13 and Figure 14 illustrate a case where a plurality of through wirings 54, a plurality of through wirings 48, and a plurality of through wirings 47 are arranged in two rows along the second direction H. Among the four sensor pixels 12 sharing the readout circuit 22, for example, the four floating diffusion portions FD are arranged close to each other with the pixel separation portion 43 therebetween. Among the four sensor pixels 12 sharing the readout circuit 22, the four transfer electrodes TG1, TG2, TG3, and TG4 are arranged so as to surround the four floating diffusion portions FD. For example, the four transfer gates TG form an annular shape.

[0084] The insulating layer 53 includes a plurality of blocks extending along the second direction H. The semiconductor substrate 21 includes a plurality of island-like blocks 21A extending along the second direction H, and the plurality of island-like blocks 21A are arranged side by side along the first direction V orthogonal to the second direction H with the insulating layer 53 therebetween. In each block 21A, for example, a reset transistor RST, an amplifying transistor AMP, and a selection transistor SEL are provided. For example, one readout circuit 22 shared by the four sensor pixels 12 is arranged not directly facing the four sensor pixels 12 but offset in the first direction V.

[0085] In Figure 13 , a readout circuit 22 shared by four sensor pixels 12 includes: a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL in a region of the second substrate 20 that is offset in the first direction V with respect to the region facing the four sensor pixels 12. For example, a readout circuit 22 shared by four sensor pixels 12 includes: an amplification transistor AMP, a reset transistor RST, and a selection transistor SEL arranged in a block 21A.

[0086] In Figure 14 , a readout circuit 22 shared by four sensor pixels 12 includes: a reset transistor RST, an amplification transistor AMP, a selection transistor SEL, and an FD transfer transistor FDG in a region of the second substrate 20 that is offset in the first direction V with respect to the region facing the four sensor pixels 12. For example, a readout circuit 22 shared by four sensor pixels 12 includes: an amplification transistor AMP, a reset transistor RST, a selection transistor SEL, and an FD transfer transistor FDG arranged in a block 21A.

[0087] In this modification example, for example, a readout circuit 22 shared by four sensor pixels 12 is not directly facing the four sensor pixels 12, but is offset in the first direction V from the position where the readout circuit 22 is directly facing the four sensor pixels 12. In this case, the wiring 25 (see Figure 10 ) can be shortened, or the wiring 25 can be omitted, and the shared impurity region can form the source of the amplification transistor AMP and the drain of the selection transistor SEL. Thereby, the size of the readout circuit 22 can be reduced, or the size of other parts in the readout circuit 22 can be increased.

[0088] (Second modification example)

[0089] Figure 15 is a diagram showing a modification example of the cross-sectional structure of the solid-state imaging device 1 in the horizontal direction. Figure 15 Shows Figure 7 a modification example of the cross-sectional structure in

[0090] In this modification example, the semiconductor substrate 21 includes a plurality of island-shaped blocks 21A arranged side by side along the first direction V and the second direction H with an insulating layer 53 therebetween. In each block 21A, for example, a set of a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL is arranged. In this case, crosstalk that may occur between adjacent readout circuits 22 can be suppressed by the insulating layer 53, so as to suppress a reduction in the resolution of the reproduced image or deterioration of the image quality due to color mixing.

[0091] (Third Modified Example)

[0092] Figure 16 This is a diagram showing a modified example of the cross-sectional structure of the solid-state imaging device 1 in the horizontal direction described above. Figure 16 It shows Figure 15 a modified example of the cross-sectional structure in

[0093] In this modified example, for example, one readout circuit 22 shared by four sensor pixels 12 is arranged not directly facing the four sensor pixels 12 but shifted in the first direction V. Additionally, in this modified example, as in the second modified example, the semiconductor substrate 21 includes a plurality of island-like blocks 21A arranged side by side along the first direction V and the second direction H with an insulating layer 53 therebetween. In each block 21A, for example, a set of a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL are arranged. In this modified example, a plurality of through wirings 47 and a plurality of through wirings 54 are also arranged along the second direction H. Specifically, the plurality of through wirings 47 are arranged between four through wirings 54 sharing a certain readout circuit 22 and four through wirings 54 sharing another readout circuit 22 adjacent to the certain readout circuit 22 in the second direction H. In this case, crosstalk that may occur between adjacent readout circuits 22 can be suppressed by the insulating layer 53 and the through wiring 47, so as to suppress a reduction in the resolution of the reproduced image or deterioration in image quality due to color mixing.

[0094] (Fourth Modified Example)

[0095] Figure 17 This is a diagram showing a modified example of the cross-sectional structure of the solid-state imaging device 1 in the horizontal direction described above. Figure 17 It shows Figure 7 a modified example of the cross-sectional structure in

[0096] In this modified example, the first substrate 10 has a photodiode PD and a transfer transistor TR arranged for each sensor pixel 12, and one floating diffusion portion FD is shared by every four sensor pixels 12. Therefore, in this modified example, one through wiring 54 is arranged for every four sensor pixels 12.

[0097] Among the plurality of sensor pixels 12 arranged in a matrix form, for the sake of convenience, four sensor pixels 12 corresponding to a region obtained by shifting the unit region of four sensor pixels 12 sharing one floating diffusion portion FD by one sensor pixel 12 in the first direction V are referred to as four sensor pixels 12A. Then, in this modified example, the first substrate 10 has a through wiring 47 shared by every four sensor pixels 12A. Therefore, in this modified example, one through wiring 47 is arranged for every four sensor pixels 12A.

[0098] In this modified example, the first substrate 10 includes a pixel separation portion 43 that separates the photodiode PD and the transfer transistor TR for each sensor pixel 12. When viewed from the normal direction of the semiconductor substrate 11, the pixel separation portion 43 does not completely surround the sensor pixel 12, but includes gaps as unformed regions near the through-wiring 54 connected to the floating diffusion portion FD and near the through-wiring 47. Thus, these gaps enable four sensor pixels 12 to share one through-wiring 54, and enable four sensor pixels 12A to share one through-wiring 47. In this modified example, the second substrate 20 includes a readout circuit 22 provided for every four sensor pixels 12 sharing the floating diffusion portion FD.

[0099] Figure 18 FIG. is a diagram showing a cross-sectional structure of the solid-state imaging device 1 of this modified example in the horizontal direction. Figure 18 shows Figure 15 a modified example of the cross-sectional structure in. In this modified example, the first substrate 10 has a photodiode PD and a transfer transistor TR arranged for each sensor pixel 12, and every four sensor pixels 12 share one floating diffusion portion FD. In addition, the first substrate 10 includes a pixel separation portion 43 that separates the photodiode PD and the transfer transistor TR for each sensor pixel 12.

[0100] Figure 19 FIG. is a diagram showing a cross-sectional structure of the solid-state imaging device 1 of this modified example in the horizontal direction. Figure 19 shows Figure 16 a modified example of the cross-sectional structure in. In this modified example, the first substrate 10 has a photodiode PD and a transfer transistor TR arranged for each sensor pixel 12, and every four sensor pixels 12 share one floating diffusion portion FD. In addition, the first substrate 10 includes a pixel separation portion 43 that separates the photodiode PD and the transfer transistor TR for each sensor pixel 12.

[0101] (Fifth Modified Example)

[0102] Figure 20 FIG. is a diagram showing the circuit structure of the solid-state imaging device 1 of this modified example. The solid-state imaging device 1 according to this modified example is a CMOS image sensor equipped with a column-parallel ADC.

[0103] As Figure 20As shown, the solid-state imaging device 1 according to this modification is configured to include, in addition to a pixel region 13 in which a plurality of sensor pixels 12 each including a photoelectric conversion element are two-dimensionally arranged in a matrix form, a vertical drive circuit 33, a column signal processing circuit 34, a reference voltage supply unit 38, a horizontal drive circuit 35, a horizontal output line 37, and a system control circuit 36.

[0104] In such a system configuration, the system control circuit 36 generates a clock signal serving as a reference for operations of the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, etc., and control signals, etc., based on the master clock MCK, and supplies the clock signal, the control signals, etc. to the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, etc.

[0105] In addition, the vertical drive circuit 33 is formed together with each sensor pixel 12 in the pixel region 13 on a first substrate 10, and the vertical drive circuit 33 is also formed on a second substrate 20 on which a readout circuit 22 is formed. The column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, the horizontal output line 37, and the system control circuit 36 are formed on a third substrate 30.

[0106] Although not shown here, as a configuration of the sensor pixel 12, in addition to having a photodiode PD, for example, it further includes a transfer transistor TR for transferring the charge obtained by photoelectric conversion in the photodiode PD to a floating diffusion section FD. In addition, although not shown here, as a configuration of the readout circuit 22, it may include a three-transistor configuration in which a reset transistor RST for controlling the potential of the floating diffusion section FD, an amplification transistor AMP for outputting a signal corresponding to the potential of the floating diffusion section FD, and a selection transistor SEL for selecting a pixel are arranged.

[0107] In the pixel region 13, the sensor pixels 12 are two-dimensionally arranged. For an m-row × n-column pixel arrangement, pixel drive lines 23 are wired for each row, and vertical signal lines 24 are wired for each column. One end of each of the plurality of pixel drive lines 23 is connected to an output terminal corresponding to each row in the vertical drive circuit 33. The vertical drive circuit 33 includes a shift register, etc., and controls the row address and row scanning in the pixel region 13 through the plurality of pixel drive lines 23.

[0108] For example, the column signal processing circuit 34 includes analog-to-digital conversion circuits (ADCs) 34-1 to 34-m respectively provided for each pixel column in the pixel region 13 (i.e., for each vertical signal line 24), to convert the analog signals output from each sensor pixel 12 in the pixel region 13 by column into digital signals and output the digital signals.

[0109] For example, the reference voltage supply unit 38 includes a digital-to-analog conversion circuit (DAC) 38A as a means for generating a reference voltage Vref having a so-called ramp waveform in which the level changes in a slanted manner over time. Note that the means for generating the reference voltage Vref having a ramp waveform is not limited to the DAC 38A.

[0110] Under the control of the control signal CS1 given by the system control circuit 36, the DAC 38A generates a reference voltage Vref having a ramp waveform based on the clock CK provided by the system control circuit 36, and supplies the reference voltage Vref to the ADCs 34-1 to ADC 34-m of the column signal processing circuit 34.

[0111] Note that each of the ADCs 34-1 to ADC 34-m is configured to be able to selectively perform an AD conversion operation corresponding to the following two operation modes: one operation mode is the normal frame rate mode, in which information in all the sensor pixels 12 is read by using the progressive scanning method; the other operation mode is the high-speed frame rate mode, in which the exposure time of the sensor pixels 12 is set to 1 / N compared to the normal frame rate mode, so that the frame rate is N times (e.g., twice). The switching of the above operation modes is performed under the control of the control signals CS2 and CS3 given by the system control circuit 36. In addition, instruction information for switching the operation mode between the normal frame rate mode and the high-speed frame rate mode is provided from an external system controller (not shown) to the system control circuit 36.

[0112] The ADCs 34-1 to ADC 34-m respectively have the same configuration, and thus the following description is made taking the ADC 34-m as an example. The ADC 34-m includes a comparator 34A, an up / down counter (U / D CNT) 34B as an example of a counting device, a transmission switch 34C, and a memory device 34D.

[0113] Comparator 34A compares the signal voltage Vx of the vertical signal line 24 with a reference voltage Vref, where the signal voltage Vx corresponds to the signals output from the respective sensor pixels 12 in the n-th column in the pixel region 13, and the reference voltage Vref has a ramp waveform and is supplied from a reference voltage supply unit 38. For example, when the reference voltage Vref is higher than the signal voltage Vx, the output Vco is at the "H (high)" level, and when the reference voltage Vref is equal to or lower than the signal voltage Vx, the output Vco is at the "L (low)" level.

[0114] Under the control of the control signal CS2 given by the system control circuit 36, the up / down counter 34B, which is an asynchronous counter, and the DAC 38A are simultaneously supplied with the clock CK by the system control circuit 36, and count down (downward) or up (upward) synchronously with the clock CK to measure the comparison period from the start to the end of the comparison operation performed by the comparator 34A.

[0115] Specifically, in the normal frame rate mode, during the operation of reading out signals from one sensor pixel 12, the up / down counter 34B counts down during the first readout operation to measure the comparison time in the first readout operation, and counts up during the second readout operation to measure the comparison time in the second readout operation.

[0116] On the other hand, in the high-speed frame rate mode, the count result related to the sensor pixels 12 in a certain row is held, and subsequently, for the sensor pixels 12 in the next row, the up / down counter 34B counts down from the previous count result during the first readout operation to measure the comparison time in the first readout operation, and counts up during the second readout operation to measure the comparison time in the second readout operation.

[0117] Under the control of the control signal CS3 given by the system control circuit 36, in the normal frame rate mode, when the counting operation of the up / down counter 34B related to the sensor pixels 12 in a certain row is completed, the transfer switch 34C becomes on (closed) state, and transfers the count result of the up / down counter 34B to the memory device 34D.

[0118] On the other hand, for example, in the high-speed frame rate with N = 2, when the counting operation of the up / down counter 34B related to the sensor pixels 12 in a certain row is completed, the transfer switch 34C remains in the off (open) state. Subsequently, when the counting operation of the up / down counter 34B related to the sensor pixels 12 in the next row is completed, the transfer switch 34C becomes on state, and transfers the count results of the up / down counter 34B for two vertical pixels to the memory device 34D.

[0119] In this way, through the operations of the comparators 34A and the up / down counters 34B in each of the ADCs 34-1 to ADC 34-m, the analog signals provided column by column from the respective sensor pixels 12 in the pixel region 13 via the vertical signal lines 24 are converted into N-bit digital signals, and the digital signals are stored in the memory device 34D.

[0120] The horizontal drive circuit 35 includes a shift register or the like, and controls the column addresses and column scanning of the ADCs 34-1 to ADC 34-m in the column signal processing circuit 34. Under the control of the horizontal drive circuit 35, the N-bit digital signals generated by the AD conversion in each of the ADCs 34-1 to ADC 34-m are sequentially read out to the horizontal output lines 37, and then output as imaging data via the horizontal output lines 37.

[0121] In addition to the above components, for example, a circuit (not shown because it is not directly related to the present disclosure) that performs various signal processes on the imaging data output via the horizontal output lines 37 may also be provided.

[0122] In the solid-state imaging device 1 equipped with the column-parallel ADC according to this modified example having the above configuration, the counting result of the up / down counter 34B can be selectively transmitted to the memory device 34D through the transfer switch 34C, and thus, the counting operation of the up / down counter 34B and the operation of reading out the counting result of the up / down counter 34B to the horizontal output lines 37 can be independently controlled.

[0123] Figure 21 Illustrated is Figure 20 an example in which the solid-state imaging device 1 in

[0124] In this modified example, a pixel region 13 including a plurality of sensor pixels 12 is formed at the central portion on the first substrate 10, and a vertical drive circuit 33 is formed around the pixel region 13.

[0125] In addition, on the second substrate 20, a readout circuit region 15 including a plurality of readout circuits 22 is formed at the central portion, and a vertical drive circuit 33 is formed around the readout circuit region 15.

[0126] Furthermore, on the third substrate 30, a column signal processing circuit 34, a horizontal drive circuit 35, a system control circuit 36, horizontal output lines 37, and a reference voltage supply unit 38 are formed.

[0127] With the above configuration, as Figure 1In the foregoing structure and its modified examples, the chip size is not increased or the miniaturization of the area per pixel is not hindered due to the structure for electrically connecting the substrates to each other. Thereby, a solid-state imaging device 1 having a three-layer structure that does not hinder the miniaturization of the area per pixel can be provided with a chip size equivalent to that of an existing chip. Note that the vertical drive circuit 33 may be formed only on the first substrate 10 or only on the second substrate 20.

[0128] (Sixth Modified Example)

[0129] Figure 22 A modified example of the cross-sectional structure of the solid-state imaging device 1 as this modified example is shown. In Figure 1 In the foregoing structure and its modified examples, the solid-state imaging device 1 includes three substrates, i.e., a first substrate 10, a second substrate 20, and a third substrate 30, which are stacked. However, in Figure 1 In the foregoing structure and its modified examples, the solid-state imaging device 1 may include two substrates, i.e., a first substrate 10 and a second substrate 20, which are stacked.

[0130] In this case, for example, as Figure 22 shown, the logic circuit 32 is separately formed on the first substrate 10 and the second substrate 20. Note that in the circuit 32A of the logic circuit 32 disposed on the first substrate 10 side, a transistor having the following gate structure is provided: in this gate structure, a high-k dielectric film made of a material capable of withstanding high-temperature processing (e.g., a high-k material) and a metal gate electrode are stacked. On the other hand, in the circuit 32B of the logic circuit 32 disposed on the second substrate 20 side, a low-resistance region is formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode, and the low-resistance region contains silicides such as CoSi 2 or NiSi. Therefore, the low-resistance region containing the silicide is formed of a compound of the material of the semiconductor substrate and the metal.

[0131] Therefore, when forming the sensor pixel 12, high-temperature processing such as thermal oxidation can be used. Further, in the circuit 32B of the logic circuit 32 disposed on the second substrate 20 side and which is a part of the logic circuit 32, when a low-resistance region 26 containing a silicide is provided on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode, the contact resistance can be reduced. Thereby, the operation in the logic circuit 32 can be performed at a higher speed.

[0132] Figure 23 is a diagram showing a modified example of the cross-sectional structure of the solid-state imaging device 1 in the structure and its modified examples as Figure 1 shown. In as Figure 1In the logic circuit 32 on the third substrate 30 in the illustrated structure and its modified examples, a low-resistance region 37 may be formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode. The low-resistance region 37 includes silicides such as CoSi 2 or NiSi formed by using a self-aligned silicide (SALICIDE) process. Therefore, when forming the sensor pixel 12, high-temperature processing such as thermal oxidation can be used. In addition, when a low-resistance region 37 containing a silicide is provided on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode in the logic circuit 32, the contact resistance can be reduced. Thereby, the operation in the logic circuit 32 can be performed at a higher speed.

[0133] [First Embodiment]

[0134] Now, the solid-state imaging device according to the first embodiment will be described with reference to Figures 24 to 33 .

[0135] (Example of the overall structure of the solid-state imaging device)

[0136] Figure 24 is a diagram showing a part of the cross-section of the solid-state imaging device 100 according to the first embodiment of the present disclosure. As Figure 24 shown, the solid-state imaging device 100 has a structure in which the laminate 200, the laminate 300, and the laminate 400 are bonded together. Figure 24 The plane 230 shown is the plane where the laminate 200 and the laminate 300 are bonded together. In addition, Figure 24 the plane 340 shown is the plane where the laminate 300 and the laminate 400 are bonded together. These laminates 200 to 400 are electrically connected to each other.

[0137] The color filter 211 is disposed below the laminates 200 to 400, that is, at the lower part of the laminate 200. An on-chip lens 212 is disposed below the color filter 211. The on-chip lens 212 is used to focus the irradiated light. The focused light is guided to the photoelectric conversion element 203 included in the laminate 200 via the color filter 211.

[0138] The laminate 200 has the following structure: a multilayer film for forming transistors and the like is laminated on the substrate 201. The substrate 201 is a semiconductor substrate such as an N-type silicon substrate. In the substrate 201, for example, a P-type semiconductor region 202 (P-well) is formed. An N-type semiconductor region is formed in the semiconductor region 202, whereby a photoelectric conversion element 203 such as a photodiode having a PN junction is formed. The photoelectric conversion element 203 converts the received light into an electrical signal corresponding to the amount of the received light through photoelectric conversion.

[0139] As P + type semiconductor region hole accumulation diode (HAD) 204 is formed above the photoelectric conversion element 203. The HAD 204 functions as a hole accumulation layer to suppress dark current generated on the surface of the photoelectric conversion element 203 which is an N-type photodiode.

[0140] On the substrate 201, an N-type transfer transistor 220 is arranged. The transfer transistor 220 includes a floating diffusion portion (FD) 221 as an N-type source region. The transfer transistor 220 transfers the electrical signal output from the photoelectric conversion element 203 to the pixel transistor. The FD 221 temporarily holds the electrical signal output from the photoelectric conversion element 203.

[0141] The HAD 204 and the transfer transistor 220 including the FD 221 are covered with an insulating film 250.

[0142] The stacked body 300 has the following structure: wherein, a multilayer film for forming transistors etc. is stacked on the substrate 301. The substrate 301 is a semiconductor substrate such as a P-type silicon substrate. The stacked body 300 is turned upside down and bonded to the insulating film 250 in the stacked body 200.

[0143] On the substrate 301, that is, on the side of the substrate 301 facing the substrate 201, pixel transistors such as an N-type amplification transistor 310, an N-type reset transistor 320, and an N-type selection transistor (not shown) are arranged. The pixel transistors perform processing for reading out an electrical signal corresponding to the amount of light received by the photoelectric conversion element 203.

[0144] A wiring 313d is connected to the gate electrode 313 of the amplification transistor 310. The wiring 313d is connected to the source region 321 of the reset transistor 320. In addition, the wiring 313d is connected to the FD 221 of the transfer transistor 220 via a contact 221c.

[0145] Pixel transistors such as the amplification transistor 310 and the reset transistor 320 are covered with an insulating film 350. Therefore, the insulating film 250 and the insulating film 350 are joined together on a plane 230 which is the bonding surface of the stacked body 200 and the stacked body 300.

[0146] On the lower surface side of the substrate 301, that is, on the side opposite to the side where the pixel transistors are arranged, wirings D1 to D4 are formed in a four-layer form. The wiring D1 is a wiring formed in the first layer which is the lowermost layer. The wiring D4 is a wiring formed in the fourth layer which is the uppermost layer. Note that the number of wiring layers is not limited to four, but can be changed to any number according to design conditions and the like.

[0147] The wirings D1 to D4 are covered with an insulating film 360.

[0148] The stacked body 400 has the following structure: wherein, a multilayer film for forming transistors and the like is stacked on the substrate 401. The substrate 401 is a semiconductor substrate such as a silicon substrate. The stacked body 400 is turned upside down and bonded to the wiring D4 of the stacked body 300. In Figure 24 In the example of, the bonding point 402 between the wiring D4 and the wiring in the stacked body 400 overlaps with the pixel region where the pixels are arranged.

[0149] A plurality of logic transistors Tr arranged on the substrate 401, that is, on the side of the substrate 401 facing the substrate 301, are connected to the wiring in the stacked body 400. The wiring in the stacked body 400 and the logic transistors Tr are covered with an insulating film 450. The wiring in the stacked body 400 and the logic transistors Tr constitute a logic circuit. The logic circuit corresponds to the peripheral circuit in the solid-state imaging device 100, which is used, for example, to process the electrical signals generated in the photoelectric conversion element 203 and the like.

[0150] (Example of the detailed structure of the solid-state imaging device)

[0151] Hereinafter, a detailed structure example of the solid-state imaging device 100 according to the first embodiment will be described with reference to Figure 25 FIG. Figure 25 FIG. is a schematic view near the bonding position of the stacked bodies 200 and 300 of the solid-state imaging device 100 according to the first embodiment of the present disclosure. Figure 25 In (a) of FIG., a plan view of the side of the stacked body 300 where the pixel transistors are formed is shown, and Figure 25 In (b) to (d) of FIG., cross-sectional views near the bonding position of the stacked bodies 200 and 300 are shown. Figure 25 In (b) of FIG., a cross-sectional view taken along the line A-A' of (a) of FIG. is shown, Figure 25 In (c) of FIG., a cross-sectional view taken along the line B-B' of (a) of FIG. is shown, and Figure 25 In (d) of FIG., a cross-sectional view taken along the line C-C' of (a) of FIG. is shown. Note that in (a) of FIG., the insulating film 350 and the contact 221c are omitted. In addition, in Figure 25 In (a) of FIG., the insulating film 350 and the contact 221c are omitted. In addition, in Figure 25 In (d) of FIG., a cross-sectional view taken along the line C-C' of (a) of FIG. is shown. Note that in (a) of FIG., the insulating film 350 and the contact 221c are omitted. In addition, in Figure 25 In (a) of FIG., the insulating film 350 and the contact 221c are omitted. In addition, in Figure 25 In (a) of FIG., the insulating film 350 and the contact 221c are omitted. In addition, inFigure 25 In (b) thereof, the position of the contact member 223c is offset.

[0152] As Figure 25 shown in (c), the solid-state imaging device 100 includes a substrate 201 as a first semiconductor substrate, and this semiconductor substrate includes an FD 221 for temporarily holding an electrical signal output from the photoelectric conversion element 203. The HAD 204 is disposed above the photoelectric conversion element 203. A contact member 204c connected to the upper-layer wiring is connected to the HAD 204. The contact member 204c is grounded via the upper-layer wiring to fix the substrate potential of the substrate 201 to 0V. The FD 221 is a source region of the transfer transistor 220. The transfer transistor 220 includes a gate insulating film 224 disposed on the substrate 201 and a gate electrode 223 disposed on the gate insulating film 224. A contact member 223c connected to the upper-layer wiring is connected to the gate electrode 223. The contact member 223c is connected to a peripheral circuit including a logic transistor Tr via the upper-layer wiring and the wiring in the laminate 400. The transfer transistor 220 transfers the electrical signal output from the photoelectric conversion element 203 to the amplification transistor 310.

[0153] The solid-state imaging device 100 includes a substrate 301 as a second semiconductor substrate facing the substrate 201. The substrate 301 includes an amplification transistor 310 as a first transistor on a side facing the substrate 201. The amplification transistor 310 includes: a channel 315 extending along the thickness direction of the substrate 301; and a gate electrode 313 as a multi-gate extending along the thickness direction of the substrate 301 and sandwiching the channel 315 therebetween. The channel 315 is formed of a part of the substrate 301, and when a voltage is applied to the gate electrode 313, the channel 315 serves as a current path between a source region 311 and a drain region 312 described later. A gate insulating film 314 is interposed between the channel 315 and the gate electrode 313. For example, the amplification transistor 310 is configured as a triple-gate transistor in which the gate electrode 313 is connected to the channel 315 on three sides with the gate insulating film 314 interposed therebetween. The amplification transistor 310 amplifies the electrical signal transferred from the photoelectric conversion element 203 by the transfer transistor 220 and outputs the amplified electrical signal.

[0154] As Figure 25As shown in (d), the substrate 301 includes a reset transistor 320 on the side facing the substrate 201, which is a second transistor having a source region 321. The reset transistor 320 includes: a channel 325 extending along the thickness direction of the substrate 301; and a gate electrode 323, which is a multi-gate extending along the thickness direction of the substrate 301 and sandwiching the channel 325 therebetween. The channel 325 is formed of a part of the substrate 301, and when a voltage is applied to the gate electrode 323, the channel 325 serves as a current path between the source region 321 and the drain region 322 described later. A gate insulating film 324 is interposed between the channel 325 and the gate electrode 323. For example, the reset transistor 320 is configured as a triple-gate transistor in which the gate electrode 323 is connected to the channel 325 on three sides with the gate insulating film 324 therebetween. The reset transistor 320 resets (initializes) the potential of the gate electrode 313 of the amplification transistor 310 to the power supply potential. The reset transistor 320 also serves as a transistor for resetting the potential of the FD 221.

[0155] The gate electrode 323 of the reset transistor 320 is connected to wirings D1 to D4 which are signal lines for transmitting electrical signals from the surface side of the substrate 301 on the side opposite to the surface facing the substrate 201. Specifically, the gate electrode 323 is connected to the wirings D1 to D4 via contacts 323c. The wirings D1 to D4 are connected to a peripheral circuit including logic transistors Tr via wirings in the laminate 400 to transmit and receive electrical signals.

[0156] As Figure 25 As shown in (b), the substrate 301 includes a selection transistor 330 on the side facing the substrate 201. The selection transistor 330 includes: a channel 335 extending along the thickness direction of the substrate 301; and a gate electrode 333, which is a multi-gate extending along the thickness direction of the substrate 301 and sandwiching the channel 335 therebetween. The channel 335 is formed of a part of the substrate 301, and when a voltage is applied to the gate electrode 333, the channel 335 serves as a current path between the source region 331 and the drain region 332 described later. A gate insulating film 334 is interposed between the channel 335 and the gate electrode 333. For example, the selection transistor 330 is configured as a triple-gate transistor in which the gate electrode 333 is connected to the channel 335 on three sides with the gate insulating film 334 therebetween. The selection transistor 330 selects whether to transmit an electrical signal to the wirings D1 to D4 in the upper layer for processing the electrical signal amplified in the amplification transistor 310.

[0157] As Figure 25As shown in (a) therein, the gate electrode 313 of the amplifying transistor 310 and the gate electrode 333 of the selection transistor 330 are arranged in parallel. The gate electrode 333 of the selection transistor 330 and the gate electrode 323 of the reset transistor 320 are arranged orthogonal to each other.

[0158] As Figure 25 shown in (c) therein, the gate electrode 313 of the amplifying transistor 310 is connected to the FD 221. Specifically, the solid-state imaging device 100 includes a contact 221c for connecting the facing surfaces of the gate electrode 313 and the FD 221. That is, in Figure 25 this example, through the contact 221c made of polysilicon or the like, the surface of the gate electrode 313 closest to the substrate 201 extending in the thickness direction of the substrate 301 toward the substrate 201 and the outermost surface of the substrate 201 where the FD 221 is arranged on the surface layer of the substrate 201 are connected. In other words, the contact 221c connects the gate electrode 313 and the FD 221 at the shortest distance.

[0159] The gate electrode 313 of the amplifying transistor 310 is connected to the source region 321 of the reset transistor 320. Specifically, the gate electrode 313 of the amplifying transistor 310 extends toward the reset transistor 320, thereby forming a wiring 313d. The gate electrode 313 of the amplifying transistor 310 and the source region 321 of the reset transistor 320 are connected to each other through the wiring 313d.

[0160] As Figure 25 shown in (b) therein, the substrate 301 includes source regions 311 and 331 extending from one surface side of the substrate 301 to the other surface side, and also includes drain regions 312, 322, and 332 extending from one surface side of the substrate 301 to the other surface side. For example, the source region 311 and the drain region 312 have an N-type conductivity with an impurity concentration of 1×10 18 cm -3 or more, and are included in the amplifying transistor 310. For example, the source region 331 and the drain region 332 have an N-type conductivity with an impurity concentration of 1×10 18 cm -3 or more, and are included in the selection transistor 330. The drain region 332 of the selection transistor 330 is connected to the source region 311 of the amplifying transistor 310. For example, the drain region 322 has an N-type conductivity with an impurity concentration of 1×10 18 cm -3 or more, and is included in the reset transistor 320.

[0161] Here, note that the source region 321 of the reset transistor 320 also has N-type conductivity. However, the source region 321 of the reset transistor 320 is formed only in the surface layer portion of the substrate 301 on the surface side facing the substrate 201, and does not reach the surface on the opposite side of the substrate 301. The region extending from the FD221 via the contact 221c, the gate electrode 313 of the amplification transistor 310, and the wiring 313d to reach the source region 321 of the reset transistor 320 is the FD region serving as the floating diffusion portion. The source region 321 is formed smaller than other regions to avoid an increase in the FD capacitance.

[0162] The source regions 311 and 331 are connected to the wirings D1 to D4 which are signal lines for transmitting electrical signals on the surface side of the substrate 301 on the side opposite to the surface facing the substrate 201. Specifically, the source region 311 is connected to the wirings D1 to D4 via the contact 311c. The source region 331 is connected to the wirings D1 to D4 via the contact 331c. The wirings D1 to D4 are connected to the peripheral circuit including the logic transistor Tr via the wiring in the laminate 400 to transmit and receive electrical signals.

[0163] The drain regions 312, 322, and 332 are connected to the power supply potential from the surface side of the substrate 301 on the side opposite to the surface facing the substrate 201. Specifically, the drain region 312 is connected to the wirings D1 to D4 via the contact 312c. The drain region 322 is connected to the wirings D1 to D4 via the contact 322c. The drain region 332 is connected to the wirings D1 to D4 via the contact 332c. The wirings D1 to D4 are connected to the power supply potential.

[0164] (Example of the detailed structure of the gate electrode)

[0165] As described above, for example, the pixel transistors arranged on the substrate 301 are configured as triple-gate transistors. Here, taking the amplification transistor 310 as an example, with reference to Figure 26 The structure of the triple-gate transistor will be described in more detail. The reset transistor 320 and the selection transistor 330 are configured in a similar manner to the amplification transistor 310 described below.

[0166] Figure 26 is a schematic diagram showing the structure of the amplification transistor 310 according to the first embodiment of the present disclosure. Figure 26 In (a) is an exploded perspective view of the amplification transistor 310, and Figure 26 In (b) is a perspective view of the amplification transistor 310.

[0167] As Figure 26As shown, the source region 311, the drain region 312, and the channel 315 sandwiched therebetween are formed in a plate shape standing upright along the stacking direction SD of the stacked body 300.

[0168] A part of the source region 311, the entire channel 315, and a part of the drain region 312 are covered with the gate insulating film 314. For example, the gate insulating film 314 is made of a high-k (high dielectric constant) material such as Al 2 O 3 , TiO 2 , Ta 2 O 5 , HfO 2 , HfSiON, HfSiO 4 , ZrO 2 , ZrSiO 4 , La 2 O 3 or Y 2 O 3 and the like.

[0169] The gate insulating film 314 is covered with the gate electrode 313. For example, the gate electrode 313 can be made of polysilicon. The amplifying transistor 310 can be a metal gate transistor whose gate electrode 313 is made of a metal-based material such as TaCx, W, WNx, or TiN.

[0170] In the amplifying transistor 310 configured as a triple-gate transistor, the gate width is the length obtained by adding the width (thickness of the plate) of the plate-shaped channel to twice its height.

[0171] As described above, the amplifying transistor 310 includes an N-type source region 311, an N-type drain region 312, and a P-type channel 315 sandwiched between these two regions. In addition, the insulating film 360 is disposed directly below the main body of the NPN structure of the amplifying transistor 310. That is, the amplifying transistor 310 has an FD-SOI (Fully Depleted Silicon-On-Insulator) structure.

[0172] (Example of manufacturing process of solid-state imaging device)

[0173] Hereinafter, an example of the manufacturing process of the solid-state imaging device 100 according to the first embodiment will be described with reference to Figures 27 to 31 . Figures 27 to 31 is a flowchart showing an example of the manufacturing process of the solid-state imaging device 100 according to the first embodiment of the present disclosure. Note that the left diagram in Figures 27 to 31 is a cross-sectional view taken along line A-A' in (a) in Figure 25 during the manufacturing process of the solid-state imaging device 100. In Figures 27 to 31The central figure is a cross-sectional view taken along line B-B' in (a) of Figure 25 during the manufacturing process of the solid-state imaging device 100. In Figures 27 to 31 The figure on the right is a cross-sectional view taken along line C-C' in (a) of Figure 25 during the manufacturing process of the solid-state imaging device 100.

[0174] As shown in Figure 27 (a1), (b1), and (c1) of, element isolation is performed on a substrate 301 such as a P-type silicon substrate, and then channels 315 and 325 are formed by forming a trench TR. Although not shown, a channel 335 is also formed at the same time.

[0175] As shown in Figure 27 (a2), (b2), and (c2) of, gate insulating films 314, 324, and 334 are formed to cover channels 315, 325, and 335. In addition, gate electrodes 313, 323, and 333 are formed to cover the gate insulating films 314, 324, and 334.

[0176] Then, N-type source regions 311, 321, and 331 and N-type drain regions 312, 322, and 332 are formed in the substrate 301 on both sides of the gate electrodes 313, 323, and 333 so that they have an impurity concentration of 1×10 18 cm -3 or more. The source regions 311 and 331 and the drain regions 312, 322, and 332 are formed to reach the depth of the trench TR. The source region 321 is formed shallower than the other source regions 311 and 331.

[0177] As shown in Figure 27 (a3), (b3), and (c3) of, while an insulating film 350 covering each component is stacked on the substrate 301, a wiring 313d connecting the gate electrode 313 and the source region 321 is formed. The insulating film 350 is stacked until all components including the wiring 313d are completely filled.

[0178] As shown in Figure 28 (a1), (b1), and (c1) of, in a substrate 201 such as an N-type silicon substrate, a P-type semiconductor region 202 is formed, a photoelectric conversion element 203 such as an N-type photodiode is formed, and a HAD 204 as a + P-type semiconductor region is formed.

[0179] In addition, a gate insulating film 224 is formed on the substrate 201, and a gate electrode 223 is formed on the gate insulating film 224. Then, an FD 221 as an N-type source region is formed in the substrate 201 near the gate electrode 223.

[0180] After that, an insulating film 250 covering each component is formed on the substrate 201. On the substrate 201 on which each component is formed, the substrate 301 is placed upside down so that the surface on which the pixel transistors are formed faces the substrate 201.

[0181] As Figure 28 shown in (a2), (b2), and (c2) in [reference], the substrate 201 and the substrate 301 are bonded together. In this process, the insulating film 250 formed on the substrate 201 and the insulating film 350 formed on the substrate 301 are joined together.

[0182] Thereby, the transfer transistor 220 on the substrate 201 and the pixel transistors on the substrate 301 face each other. In addition, the wiring 313d extending from the gate electrode 313 is disposed directly above the FD 221 on the substrate 201.

[0183] As Figure 29 shown in (a1), (b1), and (c1) in [reference], the substrate 301 is thinned by grinding the surface of the substrate 301 opposite to the side on which the pixel transistors are formed. For example, the substrate 301 is thinned until the following state is reached: the main substrate 301 is removed so that the ends on the side opposite to the side covered by the gate electrodes 313, 323, and 333 of the channels 315, 325, and 335 are exposed, the U-shaped ends of the gate insulating films 314, 324, and 334 are exposed, and the U-shaped ends of the gate electrodes 313, 323, and 333 are exposed. However, note that the main substrate 301 can also be designed to be retained. As Figure 29 shown in (a1), (b1), and (c1) in [reference], in the case where the main substrate 301 is removed, each pixel transistor has an FD - SOI structure.

[0184] Note that although a part of the ground substrate 301 remains in a divided state around each pixel transistor, such a substrate 301 is not shown in the following drawings.

[0185] As Figure 29 shown in (a2), (b2), and (c2) in [reference], ion implantation or the like is performed from the surface of the substrate 301 opposite to the side on which the pixel transistors are formed at positions corresponding to the source regions 311 and 331 and the drain regions 312, 322, and 332, so that it has an impurity concentration of 1×10 18 cm -3 or more. Thereby, the source regions 311 and 331 and the drain regions 312, 322, and 332 extending from one surface side to the other surface side of the substrate 301 are obtained.

[0186] As shown Figure 30 in (a1), (b1), and (c1) of FIG. 612, an insulating film 360 is formed on a substrate 301 to cover each component. Then, a through hole TH is formed, which penetrates the insulating films 360, 350, and 250, the wiring 313d, and reaches the FD221 in the substrate 201.

[0187] As shown Figure 30 in (a2), (b2), and (c2) of FIG. 615, the through hole TH is filled with a conductive material such as polysilicon until it reaches the height of the wiring 313d, to form a contact 221c that connects the wiring 313d and the FD 221.

[0188] As shown Figure 31 in (a1), (b1), and (c1) of FIG. 618, the insulating films 350 and 360 above the wiring 313d are backfilled with an insulating material such as SiO 2 etc.

[0189] As shown Figure 31 in (a2), (b2), and (c2) of FIG. 621, a contact 223c is formed on the gate electrode 223 and connected to the upper layer wiring. A contact 204c is formed on the HAD 204 and connected to the upper layer wiring.

[0190] In addition, a contact 323c is formed on the gate electrode 323 and connected to the wirings D1 to D4. Although not shown, a contact 333c is formed on the gate electrode 333 and connected to the wirings D1 to D4.

[0191] In addition, contacts 311c and 331c are formed on the source regions 311 and 331 and connected to the wirings D1 to D4. Contacts 312c, 322c, and 332c are formed on the drain regions 312, 322, and 332 and connected to the wirings D1 to D4.

[0192] After that, a laminate 400 in which a peripheral circuit including a logic transistor Tr and wirings are formed is bonded to the laminate 300. In this process, the insulating film 450 in the laminate 400 and the insulating film 360 in the laminate 300 are joined together. In addition, the wiring in the laminate 400 is connected to the wiring D4 in the laminate 300. Thereby, the wirings D1 to D4 are properly connected to the peripheral circuit, the ground line, the power supply potential, etc. in the laminate 400.

[0193] Thus, the manufacturing process of the solid-state imaging device 100 of the first embodiment is completed.

[0194] (Comparative Example)

[0195] Refer to Figure 32, a comparison is made below between the configuration of the comparative example and that of the first embodiment. Figure 32 FIG. is a schematic diagram showing a solid-state imaging device according to a comparative example of the present disclosure.

[0196] In the solid-state imaging device according to Patent Document 1, a semiconductor substrate on which a pixel region is formed and a semiconductor substrate on which a logic circuit is formed are bonded together. That is, a photoelectric conversion element and a pixel transistor are formed on the same semiconductor substrate. However, this configuration cannot ensure sufficient space for arranging the pixel transistors. For example, when the size of the amplification transistor among the pixel transistors is small, it is difficult to sufficiently increase the transconductance gm or sufficiently reduce the noise.

[0197] Then, for example, a conceivable solution is to separate the substrate into a substrate on which a photoelectric conversion element is formed and a substrate on which a pixel transistor is formed, and bond these two substrates together. In Figure 32 such a configuration is shown as a comparative example.

[0198] As Figure 32 shown, the solid-state imaging device of the comparative example is provided with a transfer transistor 220' including an FD 221' on a substrate 201' including a photoelectric conversion element 203' and a HAD 204'. A substrate 301' is disposed above the substrate 201'. On the upper surface of the substrate 301', that is, on the surface opposite to the substrate 201', an amplification transistor 310', a reset transistor 320', and a selection transistor 330' are disposed. These pixel transistors are planar transistors. In addition, the gate electrode of the amplification transistor 310' and the source region of the reset transistor 320' are connected to the FD 221' via a contact 221c' and a wiring D1'.

[0199] However, this configuration makes it necessary to extend the contact 221c' to the level of the wiring D1', resulting in a greater total wiring length. In addition, it also results in a complex configuration for connecting the gate electrode of the amplification transistor 310' and the source region of the reset transistor 320' to the FD 221'. Therefore, the capacitance of the wiring related to the FD 221' increases, and the capacitance of the entire FD region also increases. Thereby, the photoelectric conversion efficiency of the photoelectric conversion element 203' decreases.

[0200] In the solid-state imaging device 100 of the first embodiment, each pixel transistor is configured as a triple-gate transistor and is arranged facing the substrate 201 side. Thereby, the gate electrode 313 of the amplification transistor 310 can be close to the FD 221. In addition, the source region 321 of the reset transistor 320 can be close to the FD 221. Therefore, the length of the overall wiring related to the FD 221, that is, the length of the contact 221c and the wiring 313d, can be reduced, thereby improving the photoelectric conversion efficiency of the photoelectric conversion element 203.

[0201] In the solid-state imaging device 100 of the first embodiment, each pixel transistor is configured as a triple-gate transistor. Therefore, while the amplification transistor 310 faces the substrate 201 side, the U-shaped ends of the gate electrode 323 of the reset transistor 320 also face the wirings D1 to D4. Thereby, the gate electrode 323 can be connected to the wirings D1 to D4 from the side of the substrate 301 facing the wirings D1 to D4.

[0202] In the solid-state imaging device 100 of the first embodiment, each pixel transistor is configured as a triple-gate transistor. Thereby, the gate width of the pixel transistor can be expanded in the direction perpendicular to the surface of the substrate 301 without increasing the occupied area relative to the substrate 301, thereby further reducing noise and increasing the transconductance gm.

[0203] In the solid-state imaging device 100 of the first embodiment, each pixel transistor has an FD-SOI structure. Thereby, miniaturization of the pixel transistor can be achieved, and at the same time, the parasitic capacitance can be reduced to obtain a high-speed pixel transistor.

[0204] The solid-state imaging device 100 of the first embodiment includes source regions 311 and 331 and drain regions 312, 322, and 332 that are distributed throughout the thickness direction of the substrate 301. Therefore, while the pixel transistor faces the substrate 201 side, the source regions 311 and 331 and the drain regions 312, 322, and 332 can be connected to the wirings D1 to D4 from the side of the substrate 301 facing the wirings D1 to D4. Therefore, the form in which the source regions 311 and 331 and the drain regions 312, 322, and 332 are connected to the wirings D1 to D4 is not complicated. In addition, since each pixel transistor is a triple-gate transistor, the gate electrodes 313, 323, and 333 have higher controllability over the channels 315, 325, and 335. Therefore, even if the source regions 311 and 331 and the drain regions 312, 322, and 332 with high impurity concentrations are distributed across the lower surface to the upper surface of the substrate 301, short circuits between the source regions 311, 321, and 331 and the drain regions 312, 322, and 332 can be suppressed.

[0205] With the above configuration, the solid-state imaging element 100 of the first embodiment can fully utilize the advantages of arranging the photoelectric conversion element 203 and the pixel transistor on different substrates 201 and 301. That is, compared with the case where the photoelectric conversion element and the pixel transistor are arranged on the same substrate, the area of ​​any one of the photoelectric conversion element 203 and the pixel transistor can be further expanded. In addition, the number of pixels per unit area can be increased.

[0206] In addition, in the solid-state imaging element 100 of the first embodiment, the substrate 201 and the substrate 301 are connected via the contact 221c. In addition, the substrate 301 and the substrate 401 are connected by the wiring D3 in the substrate 301 and the wiring in the substrate 401. With these structures, compared with the case where each substrate is connected to each other through a silicon through hole (TSV: Through Silicon Via) provided in the peripheral area of ​​the substrate, the area required for the connection between the substrates is reduced. Thereby, the chip size of the solid-state imaging element 100 can be reduced. Alternatively, the pixel area can be enlarged with the same chip size.

[0207] In the solid-state imaging element 100 of the first embodiment, the contact 221c and the junction 402 of the wiring D3 in the substrate 301 and the wiring in the substrate 401 are arranged in the pixel region. This can further reduce the chip size or expand the pixel region.

[0208] (First Modification)

[0209] Refer to the following Figure 33 A solid-state imaging element according to a first modification example of the first embodiment will be described. Figure 33 1 is a schematic diagram showing the configuration of an amplifier transistor in a solid-state imaging element according to a first variant of the first embodiment of the present disclosure. The amplifier transistor of the first variant is a multi-gate transistor of a different type from that in the first embodiment. The reset transistor of the first variant and the selection transistor of the first variant are configured in a manner similar to the amplifier transistor described below.

[0210] like Figure 33 As shown in (a) of FIG. 1 , the amplifier transistor 310a of the first modification is configured as a dual-gate transistor in which a gate electrode 313a is connected to a channel at two sides via a gate insulating film 314a. That is, the amplifier transistor 310a includes an N-type source region 311a, an N-type drain region (not shown), and a P-type channel (not shown) sandwiched therebetween.

[0211] Both sides of a part of the source region 311a, both sides of the entire channel, and both sides of a part of the drain region are covered with the gate insulating film 314a. As in the first embodiment, the gate insulating film 314a is made of a high-k material or the like. In the figure, the lower ends of a part of the source region 311a, the lower ends of the entire channel, and the lower ends of a part of the drain region are covered with the insulating film 316in.

[0212] The gate insulating film 314a and the insulating film 316in are covered with the gate electrode 313a. The wiring 313da connected to the source region of the reset transistor or the like extends from the gate electrode 313a. As in the first embodiment, the gate electrode 313a and the wiring 313da are made of polycrystalline silicon, a metal-based material, or the like.

[0213] In the amplifying transistor 310a configured as a double-gate transistor, the gate width is twice the height of the plate-shaped channel.

[0214] The amplifying transistor 310a of the first modification example may also be configured as a transistor having an FD-SOI structure in which the insulating film 360 is disposed directly below the body of the NPN structure.

[0215] As Figure 33 shown in (b) of [], the amplifying transistor 310b of the first modification example is configured as a full-surround transistor having a gate-all-around (GAA) structure in which the gate electrode 313b is connected to the channel on four sides with the gate insulating film 314b interposed therebetween. That is, the amplifying transistor 310b includes an N-type source region 311b, an N-type drain region (not shown), and a P-type channel (not shown) sandwiched therebetween.

[0216] The source region 311b, the channel, and the drain region are in the form of upright plates with respect to the insulating film 360. The source region 311b includes wings 311w that are V-shaped and in contact with the insulating film 360. The drain region includes wings (not shown) that are V-shaped and in contact with the insulating film 360.

[0217] The entire periphery of a part of the source region 311b, the entire periphery of the entire channel, and the entire periphery of a part of the drain region are covered with the gate insulating film 314b. As in the first embodiment, the gate insulating film 314b is made of a high-k material or the like.

[0218] The gate insulating film 314b is covered with the gate electrode 313b. The wiring 313db connected to the source region of the reset transistor or the like extends from the gate electrode 313b. As in the first embodiment, the gate electrode 313b and the wiring 313db are made of polycrystalline silicon, a metal-based material, or the like.

[0219] In the amplifying transistor 310b configured as a perimeter transistor, the length of the perimeter of the plate-shaped channel is the gate width.

[0220] The amplifying transistor 310b of the first modification example may also be configured as a transistor having an FD-SOI structure in which the insulating film 360 is disposed directly below the body of the NPN structure.

[0221] As an example of the pixel transistor, the triple-gate transistor in the first embodiment, the double-gate transistor and the perimeter transistor in the first modification example have been shown above; however, the configuration of the pixel transistor is not limited thereto. The pixel transistor may be arbitrarily selected from various types of multi-gate transistors.

[0222] Thereby, a pixel transistor can be formed that can make contact with both the substrate side on which the photoelectric conversion element is formed and the upper wiring side of the pixel transistor.

[0223] Moreover, thereby, the pixel transistor is also allowed to have higher controllability over the channel. Therefore, source and drain regions can be formed that can make contact with both the substrate side on which the photoelectric conversion element is formed and the upper wiring side of the pixel transistor while suppressing a short circuit between the source and drain regions.

[0224] (Second Modification Example)

[0225] The following refers to Figure 34 to describe the solid-state imaging device 110 according to the second modification example of the first embodiment. Figure 34 FIG. is a diagram showing a part of a cross section of the solid-state imaging device 110 according to the second modification example of the first embodiment of the present disclosure.

[0226] As Figure 34 shown, in the solid-state imaging device 110 of the second modification example, the gate electrode 223x of the transfer transistor 220 extends into the photodiode 203. That is, the transfer transistor 220 may include a gate electrode 223x formed as a vertical transfer gate.

[0227] (Third Modification Example)

[0228] The following refers to Figure 35 to describe the solid-state imaging device 120 according to the third modification example of the first embodiment. Figure 35 FIG. is a diagram showing a part of a cross section of the solid-state imaging device 120 according to the third modification example of the first embodiment of the present disclosure.

[0229] As Figure 35As shown, in the solid-state imaging device 120 of the third modification example, the electrical connection between the stacked body 300 and the stacked body 400 is made in a region facing the peripheral region 14 of the stacked body 200. The peripheral region 14 corresponds to the frame region of the stacked body 200 and is provided at the periphery of the pixel region 13. The stacked body 300 has a plurality of pad electrodes 58 in the region facing the peripheral region 14, and the stacked body 400 includes a plurality of pad electrodes 64 in the region facing the peripheral region 14. The stacked body 300 and the stacked body 400 are electrically connected to each other by joining the pad electrodes 58 and 64 provided in the region facing the peripheral region 14.

[0230] In this way, the stacked body 300 and the stacked body 400 are connected by the mutual joining of the pad electrodes 58 and 64. Therefore, for example, compared with the case where each stacked body is connected by TSVs arranged in the peripheral region of the stacked body, the chip size can be reduced or the pixel region can be enlarged.

[0231] [Second Embodiment]

[0232] Now, the solid-state imaging device of the second embodiment will be described with reference to Figure 36 . Figure 36 is a schematic view near the bonding position of the stacked body of the solid-state imaging device according to the second embodiment of the present disclosure. The solid-state imaging device of the second embodiment is different from the solid-state imaging device of the first embodiment described above in that the selection transistor 530 is arranged on a substrate 501 different from the substrate on which the amplification transistor 310e and the like are arranged.

[0233] Note that Figure 36 (a) in is a cross-sectional view taken along line A-A' in (a) of Figure 25 , Figure 36 (b) in is a cross-sectional view taken along line B-B' in (a) of Figure 25 , and Figure 36 (c) in is a cross-sectional view taken along line C-C' in (a) of Figure 25 .

[0234] As Figure 36 shown, the solid-state imaging device of the second embodiment includes a stacked body 200, a stacked body 300e bonded to the stacked body 200, and a stacked body 500 bonded to the stacked body 300e.

[0235] The substrate 301e of the stacked body 300e does not have a selection transistor. That is, the substrate 301e such as a P-type silicon substrate includes an amplification transistor 310e and a reset transistor 320.

[0236] For example, the amplifying transistor 310e is a triple-gate transistor including an N-type source region 311e, an N-type drain region 312e, a P-type channel 315e, a gate insulating film 314e, and a gate electrode 313e. However, the amplifying transistor 310e may also be other multi-gate transistors such as a double-gate transistor or a fully surrounding gate transistor. For example, the amplifying transistor 310e is formed to be larger than the amplifying transistor 310 of the first embodiment by an amount corresponding to the non-arrangement of the selection transistor on the substrate 301e.

[0237] The solid-state imaging device of the second embodiment includes: a substrate 501 as a third semiconductor substrate, which is arranged on the side opposite to the substrate 201 as the first semiconductor substrate with respect to the substrate 301e as the second semiconductor substrate in a facing manner. That is, the laminate 300e and the laminate 500 including the substrate 501 are joined together on a plane 355 between the insulating film 360 covering the substrate 301e and the insulating film 550 covering the substrate 501.

[0238] The substrate 501 such as a P-type silicon substrate includes a selection transistor 530 that selects whether to transmit an electrical signal amplified in the amplifying transistor 510e to the wirings D1 to D4 serving as signal lines. The selection transistor 530 is arranged on the surface opposite to the side facing the substrate 301e. For example, the selection transistor 530 includes a source region 531, a channel 535, and a drain region 532 arranged at the surface layer of the substrate 501, and is formed as a planar transistor including a gate insulating film 534 on the substrate 501 and a gate electrode 533 on the gate insulating film 534.

[0239] The drain region 532 of the selection transistor 530 is connected to the source region 311e of the amplifying transistor 310e via a contact 532c, a wiring D2, and a contact 311c. The source region 531 of the selection transistor 530 is connected to an upper-layer wiring via a contact 531c.

[0240] In the solid-state imaging device of the second embodiment, the selection transistor 530 is arranged on a substrate 501 different from the substrate 301e. Thereby, the amplifying transistor 310e on the substrate 301e can be made larger, so that noise can be further reduced and the transconductance gm can be further increased.

[0241] Note that in the configuration of the second embodiment, the selection transistor 530 is selected as a planar transistor, but this is not restrictive. As in the first embodiment and the like, the selection transistor may be configured as a multi-gate transistor such as a triple-gate transistor. In this case, the source region and the drain region of the selection transistor may be entirely distributed in the thickness direction of the substrate on which the selection transistor is formed. Therefore, the drain region and the source region 311e of the amplification transistor 310e can be connected to each other with the facing surfaces. In addition, the source region and the upper wiring can be connected to each other with the facing surfaces. At this time, the up-down direction of the selection transistor may be inconsequential.

[0242] [Third Embodiment]

[0243] Figure 37 FIG. is an example showing a schematic configuration of the imaging system 2, which includes any one of the solid-state imaging elements of the first and second embodiments and their modified examples. Therefore, any one of the solid-state imaging elements of the first and second embodiments and their modified examples can be arranged in the imaging system 2. Hereinafter, the imaging system 2 including the solid-state imaging element 100 of the first embodiment will be described as an example.

[0244] The imaging system 2 used as a video recording device is, for example, an electronic device such as the following: an imaging device such as a digital camera or a video camera, or a portable terminal device such as a smart phone or a tablet terminal. For example, the imaging system 2 includes the solid-state imaging element 100 of the first embodiment, a DSP (Digital Signal Processor) circuit 141, a frame memory 142, a display unit 143, a storage unit 144, an operation unit 145, and a power supply unit 146. In the imaging system 2, the solid-state imaging element 100, the DSP circuit 141, the frame memory 142, the display unit 143, the storage unit 144, the operation unit 145, and the power supply unit 146 are connected to each other via a bus 147.

[0245] The solid-state imaging device 100 outputs image data corresponding to incident light. The DSP circuit 141 is a signal processing circuit that processes the signal, i.e., the image data, output from the solid-state imaging device 100. The frame memory 142 temporarily holds the image data processed by the DSP circuit 141 in units of frames. For example, the display unit 143 includes a panel-type display device such as a liquid crystal panel or an organic electro-luminescence (EL) panel, and displays a moving image or a still image captured by the solid-state imaging device 100. The storage unit 144 records the image data including the moving image or the still image captured by the solid-state imaging device 100 on a recording medium such as a semiconductor memory or a hard disk. The operation unit 145 issues operation instructions for various functions of the imaging system 2 according to the operations of the user. The power supply unit 146 appropriately supplies various power sources serving as the operation power for the above-mentioned power supply objects to the solid-state imaging device 100, the DSP circuit 141, the frame memory 142, the display unit 143, the storage unit 144, and the operation unit 145.

[0246] Next, the imaging process performed in the imaging system 2 will be described.

[0247] Figure 38 An example of a flowchart showing the imaging operation in the imaging system 2 is shown. Through the operation of the operation unit 145 by the user or the like, the imaging system 2 receives the start of imaging (step S101). Then, the operation unit 145 sends an imaging instruction to the solid-state imaging device 100 (step S102). When receiving the imaging instruction, the system control circuit (for example, refer to the system control circuit 36 in Figure 1 ) of the solid-state imaging device 100 performs imaging based on a predetermined imaging method (step S103).

[0248] The solid-state imaging device 100 outputs the image data obtained through imaging to the DSP circuit 141. Here, the image data refers to the following data: which represents the pixel signals of all pixels generated based on the charges temporarily held in the floating diffusion section FD. Based on the image data input from the solid-state imaging device 100, the DSP circuit 141 performs predetermined signal processing such as noise reduction processing (step S104). The DSP circuit 141 holds the image data after the predetermined signal processing in the frame memory 142, and the frame memory 142 stores the image data in the storage unit 144 (step S105). In this way, imaging is performed in the imaging system 2.

[0249] Since the imaging system 2 includes a miniaturized or more refined solid-state imaging device 100, a small or more refined imaging system 2 can be provided.

[0250] (Modification example)

[0251] Figure 39 FIG. is a diagram showing an example of a schematic configuration of an imaging system 231 according to a modified example, which includes any one of the solid-state imaging devices of the first and second embodiments and their modified examples. That is, the imaging system 231 is a modified example of the above-described imaging system 2. Hereinafter, an imaging system 231 including the solid-state imaging device 100 of the first embodiment will be described as an example.

[0252] As Figure 39 shown, the imaging system 231 includes an optical system 232, a shutter device 233, a solid-state imaging device 100, a control circuit 205, a signal processing circuit 206, a monitor 207, and a memory 208, and is capable of capturing still images and moving images.

[0253] The optical system 232 includes one or more lenses and guides light (incident light) from a subject to the solid-state imaging device 100 to form an image on the light-receiving surface of the solid-state imaging device 100.

[0254] The shutter device 233 is disposed between the optical system 232 and the solid-state imaging device 100, and controls the light irradiation period and the light shielding period of the solid-state imaging device 100 under the control of the control circuit 205.

[0255] Corresponding to the light that forms an image on the light-receiving surface via the optical system 232 and the shutter device 233, the solid-state imaging device 100 accumulates signal charges for a certain period of time. The signal charges accumulated in the solid-state imaging device 100 are transferred according to a drive signal (timing signal) provided from the control circuit 205.

[0256] The control circuit 205 outputs drive signals for controlling the transfer operation of the solid-state imaging device 100 and the shutter operation of the shutter device 233, thereby driving the solid-state imaging device 100 and the shutter device 233.

[0257] The signal processing circuit 206 performs various signal processes on the signal charges output from the solid-state imaging device 100. The image (image data) obtained by performing the signal process by the signal processing circuit 206 is provided to the monitor 207 for display, or is provided to the memory 208 for storage (recording).

[0258] Even in such a configured imaging system 231, it is possible to achieve low-noise imaging on all pixels by applying the solid-state imaging device 100.

[0259] (Application Example 1)

[0260] The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device provided in any type of moving body such as an automobile, an electric vehicle, a hybrid vehicle, a motorcycle, a bicycle, a personal mobility vehicle, an airplane, a drone, a ship, a robot, etc.

[0261] Figure 40 FIG. is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving body control system to which the technology according to the present disclosure can be applied.

[0262] The vehicle control system 12000 includes a plurality of electronic control units interconnected via a communication network 12001. In Figure 40 the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio-video output unit 12052, and a vehicle-mounted network interface (I / F: interface) 12053 are shown.

[0263] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device for devices such as a driving force generation device for generating the driving force of the vehicle, such as an internal combustion engine or a drive motor; a driving force transmission mechanism for transmitting the driving force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating the braking force of the vehicle, etc.

[0264] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 serves as a control device for devices such as a keyless entry system, a smart key system, an electric window device, or various lights such as a headlight, a taillight, a brake light, a turn signal, or a fog light. In this case, radio waves or signals from a portable device replacing the key can be input to the body system control unit 12020. The body system control unit 12020 receives the input radio waves or signals and controls the door lock device, the electric window device, and the lights of the vehicle, etc.

[0265] The vehicle external information detection unit 12030 detects information about the exterior of the vehicle on which the vehicle control system 12000 is installed. For example, the vehicle external information detection unit 12030 is connected to the imaging unit 12031. The vehicle external information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle and receives the captured image. Based on the received image, the vehicle external information detection unit 12030 can perform object detection processing or distance detection processing on objects such as people, vehicles, obstacles, signs, or text on the road surface.

[0266] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of the received light. The imaging unit 12031 can output the electrical signal as an image and can also output the electrical signal as ranging information. In addition, the light received by the imaging unit 12031 can be visible light or non-visible light such as infrared light.

[0267] The vehicle interior information detection unit 12040 detects information about the interior of the vehicle. For example, the vehicle interior information detection unit 12040 is connected to the driver state detection unit 12041 for detecting the state of the driver. For example, the driver state detection unit 12041 includes a camera that images the driver. Based on the detection information input from the driver state detection unit 12041, the vehicle interior information detection unit 12040 can calculate the fatigue level or concentration level of the driver or can determine whether the driver is dozing off.

[0268] Based on the information about the interior or exterior of the vehicle acquired by the vehicle external information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can calculate the control target values of the driving force generating device, the steering mechanism, or the braking device and can output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an advanced driver assistance system (ADAS: advanced driver assistance system), and the functions of the advanced driver assistance system include: collision avoidance or impact mitigation of the vehicle, following driving based on the inter-vehicle distance, constant-speed driving, vehicle collision warning, or vehicle lane departure warning, etc.

[0269] In addition, based on the information about the surroundings of the vehicle acquired by the vehicle external information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can perform cooperative control such as autonomous driving aimed at enabling the vehicle to drive autonomously without relying on the operation of the driver by controlling the driving force generating device, the steering mechanism, the braking device, etc.

[0270] In addition, based on the information about the outside of the vehicle acquired by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control instruction to the vehicle body system control unit 12020. For example, based on the positions of the preceding vehicle or oncoming vehicle detected by the vehicle exterior information detection unit 12030, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlamp to switch from high beam to low beam.

[0271] The sound / image output unit 12052 sends an output signal that is at least one of sound and image to an output device that can notify information visually or auditorily to the passengers of the vehicle or the outside of the vehicle. In Figure 40 the example, as the output device, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are shown. For example, the display unit 12062 may include at least one of an on-board display and a head-up display.

[0272] Figure 41 is a diagram showing an example of the arrangement position of the imaging unit 12031.

[0273] In Figure 41 the vehicle 12100 includes imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0274] For example, the imaging units 12101 to 12105 are arranged at positions such as the front nose of the vehicle 12100, side mirrors, rear bumper, rear door, and upper part of the windshield inside the vehicle compartment. The imaging unit 12101 arranged at the front nose and the imaging unit 12105 arranged at the upper part of the windshield inside the vehicle compartment mainly acquire images of the front area of the vehicle 12100. The imaging units 12102 and 12103 arranged at the side mirrors mainly acquire images of the side area of the vehicle 12100. The imaging unit 12104 arranged at the rear bumper or rear door mainly acquires images of the rear area of the vehicle 12100. The images of the front area acquired by the imaging units 12101 and 12105 are mainly used to detect the preceding vehicle, pedestrians, obstacles, traffic signals, traffic signs, or lanes, etc.

[0275] Note that Figure 41An example of the imaging ranges of imaging units 12101 to 12104 is shown. Imaging range 12111 represents the imaging range of imaging unit 12101 arranged at the front nose, imaging ranges 12112 and 12113 respectively represent the imaging ranges of imaging units 12102 and 12103 arranged at the side mirrors, and imaging range 12114 represents the imaging range of imaging unit 12104 arranged at the rear bumper or the rear door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead image of vehicle 12100 viewed from above can be obtained.

[0276] At least one of imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0277] For example, based on the distance information obtained from imaging units 12101 to 12104, microcomputer 12051 can extract a three-dimensional object as a preceding vehicle by calculating the distance from each three-dimensional object within imaging ranges 12111 to 12114 and the change in this distance over time (i.e., the relative speed with respect to vehicle 12100). The three-dimensional object is especially the three-dimensional object closest to vehicle 12100 on the driving path of vehicle 12100, and the three-dimensional object is traveling in a direction substantially the same as that of vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h). In addition, microcomputer 12051 can set a vehicle-to-vehicle distance to be ensured in front of the vehicle in advance, and can execute automatic braking control including following-stop control, or automatic acceleration control including following-start control, etc. In this way, cooperative control such as autonomous driving aimed at enabling the vehicle to drive autonomously without relying on the driver's operation can be executed.

[0278] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can classify the three-dimensional object data of a three-dimensional object into data of other three-dimensional objects such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, etc., and then extract them, and can use the extracted data to automatically avoid obstacles. For example, the microcomputer 12051 identifies the obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult for the driver to visually recognize. Then, the microcomputer 12051 determines the collision risk indicating the degree of risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and thus the vehicle may collide with the obstacle, the microcomputer 12051 can output an alarm to the driver via the audio speaker 12061 or the display unit 12062, or can perform forced deceleration or avoidance steering via the drive system control unit 12010 to achieve driving support for avoiding collision.

[0279] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can identify a pedestrian by determining whether there is a pedestrian in the images captured by the imaging units 12101 to 12104. For example, such identification of a pedestrian is performed through the following process: a process of extracting feature points in the images captured by the imaging units 12101 to 12104 that are infrared cameras; and a process of determining whether the object is a pedestrian by performing pattern matching processing on a series of feature points representing the object contour. When the microcomputer 12051 determines that there is a pedestrian in the images captured by the imaging units 12101 to 12104 and thus identifies the pedestrian, the audio and image output unit 12052 controls the display unit 12062 to superimpose and display a rectangular contour line for emphasizing the identified pedestrian. In addition, the audio and image output unit 12052 can control the display unit 12062 to display an icon or the like representing the pedestrian at a desired position.

[0280] Examples of the mobile body control system to which the technology according to the present disclosure can be applied have been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 in the configuration described above. Specifically, the solid-state imaging device according to any one of the above-described first and second embodiments and their modifications can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to provide a captured image with low noise and high refinement. Therefore, in the mobile body control system, the captured image can be used to perform control with high precision.

[0281] (Application Example 2)

[0282] Figure 42 FIG. is a schematic configuration example showing an endoscopic surgical system to which the technology according to the present disclosure can be applied.

[0283] Figure 42 FIG. shows a state where a surgeon 11131, such as a doctor, is performing surgery on a patient 11132 on an examination table 11133 using an endoscopic surgical system 11000. As shown in the figure, the endoscopic surgical system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy treatment tool 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0284] The endoscope 11100 includes a lens barrel 11101 and a camera 11102. A region of the lens barrel 11101 having a predetermined length from the end is inserted into the body cavity of the patient 11132, and the camera 11102 is connected to the proximal end of the lens barrel 11101. In the illustrated example, the endoscope 11100 is formed as a so-called rigid endoscope having a rigid lens barrel 11101, but the endoscope 11100 may also be formed as a so-called flexible endoscope having a flexible lens barrel.

[0285] An opening is provided at the end of the lens barrel 11101, and an objective lens is embedded in the opening. A light source device 11203 is connected to the endoscope 11100. The light generated by the light source device 11203 is guided to the end of the lens barrel 11101 by an optical waveguide extending inside the lens barrel 11101, and is irradiated onto an observation object in the body cavity of the patient 11132 via the objective lens. Note that the endoscope 11100 may be a direct-view endoscope, an oblique-view endoscope, or a side-view endoscope.

[0286] An optical system and any one of the solid-state imaging elements according to the first and second embodiments and their modified examples described above are provided inside the camera 11102. The reflected light (i.e., observation light) from the observation object is focused on the solid-state imaging element by the optical system. The solid-state imaging element performs photoelectric conversion on the observation light to generate an electrical signal corresponding to the observation light (i.e., an image signal corresponding to the observation image). This image signal is sent as raw data to a camera control unit (CCU) 11201.

[0287] The CCU 11201 includes a central processing unit (CPU) or a graphics processing unit (GPU), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. In addition, the CCU 11201 receives an image signal from the camera 11102, and performs various image processing operations such as imaging processing (demosaicing processing) on the image signal to display an image based on the image signal.

[0288] Under the control of the CCU 11201, the display device 11202 displays an image based on the image signal that has undergone image processing by the CCU 11201.

[0289] The light source device 11203 includes a light source such as a light emitting diode (LED), and provides illumination light for imaging the surgical site, etc. to the endoscope 11100.

[0290] The input device 11204 is an input interface for the endoscopic surgical system 11000. The user can input various information or commands to the endoscopic surgical system 11000 through the input device 11204. For example, the user can input commands for changing imaging conditions such as the type, magnification, and focal length of the illumination light emitted from the endoscope 11100.

[0291] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 to cauterize or incise tissues, or seal blood vessels, etc. To ensure the field of view of the endoscope 11100 and the working space of the surgeon 11131, the pneumoperitoneum device 11206 sends gas into the body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to expand the body cavity. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various forms such as text, image, or chart.

[0292] Note that the light source device 11203 that supplies illumination light for the endoscope 11100 when imaging a surgical site may include a white light source, which may be constituted by, for example, an LED, a laser light source, or a combination of both. In the case of constituting the white light source by a combination of RGB laser light sources, the output intensity and output timing of each wavelength of various colors can be controlled with high precision. Therefore, white balance adjustment of the captured image can be performed in the light source device 11203. Further, in this case, by irradiating the object to be observed with the laser beams from the respective RGB laser light sources in a time division manner and controlling the driving of the solid-state imaging element of the camera 11102 in synchronization with the irradiation timing, images corresponding to R, G, and B can be captured in a time division manner. By using this method, a color image can be obtained even when a color filter is not provided in the solid-state imaging element.

[0293] In addition, the driving of the light source device 11203 can be controlled so that the intensity of the output light changes at a predetermined time interval. By controlling the driving of the solid-state imaging element of the camera 11102 in synchronization with the change timing of the light intensity, acquiring images in a time division manner, and synthesizing the images, a high dynamic range image without so-called blocked-up shadows or blown-out highlights can be generated.

[0294] Furthermore, the light source device 11203 can be configured to be able to provide light in a predetermined wavelength band corresponding to special light observation. For example, in special light observation, so-called narrow band imaging can be performed as follows: by utilizing the wavelength dependence of light absorption in body tissues, light having a narrower wavelength band than the illumination light (i.e., white light) during normal observation is irradiated, whereby specific tissues such as blood vessels on the mucosal surface layer are imaged with high contrast. Alternatively, in special light observation, fluorescence observation in which an image is obtained from fluorescence generated by irradiating excitation light can be performed. For example, in fluorescence observation, autofluorescence observation in which excitation light is irradiated onto body tissues to observe the fluorescence generated in the body tissues can be performed, or a fluorescence image can be obtained by locally injecting a reagent such as indocyanine green (ICG) into body tissues and irradiating the body tissues with excitation light corresponding to the fluorescence wavelength of the reagent, and so on. The light source device 11203 can be configured to be able to provide at least one of narrow band light or excitation light corresponding to such special light observation.

[0295] Figure 43 is shown Figure 42Block diagram of an example of the functional configuration of the camera 11102 and the CCU 11201 shown.

[0296] The camera 11102 includes a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera 11102 and the CCU 11201 can be communicably connected to each other via a transmission cable 11400.

[0297] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. The observation light incident from the end of the lens barrel 11101 is guided to the camera 11102 and enters the lens unit 11401. The lens unit 11401 includes a combination of a plurality of lenses including a zoom lens and a focusing lens.

[0298] The imaging unit 11402 includes a solid-state imaging device. The solid-state imaging device included in the imaging unit 11402 can be a single element of a so-called single-board type or a plurality of elements of a so-called multi-board type. In the case where the imaging unit 11402 includes a multi-board type solid-state imaging device, each solid-state imaging device can generate image signals corresponding to R, G, and B respectively, and these image signals can be synthesized to obtain a color image. Alternatively, the imaging unit 11402 can include a pair of solid-state imaging devices for respectively acquiring a right-eye image signal and a left-eye image signal corresponding to three-dimensional (3D) display. With 3D display, the surgeon 11131 can more accurately grasp the depth of the living tissue in the surgical site. Note that in the case where the imaging unit 11402 includes a multi-board type solid-state imaging device, a plurality of lens units 11401 can be provided corresponding to each solid-state imaging device.

[0299] In addition, the imaging unit 11402 does not necessarily have to be provided on the camera 11102. For example, the imaging unit 11402 can be provided inside the lens barrel 11101 immediately after the objective lens.

[0300] The drive unit 11403 includes an actuator and, under the control of the camera control unit 11405, causes the zoom lens and the focusing lens in the lens unit 11401 to move a predetermined distance along the optical axis. Thereby, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0301] The communication unit 11404 includes a communication device for sending and receiving various information to and from the CCU 11201. The communication unit 11404 sends the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0302] In addition, the communication unit 11404 receives a control signal for controlling the driving of the camera 11102 from the CCU 11201, and supplies the control signal to the camera control unit 11405. For example, such a control signal includes information related to imaging conditions such as information for specifying the frame rate of the captured image, information for specifying the exposure value during imaging, and information for specifying the magnification and focus of the captured image.

[0303] Note that the imaging conditions such as the frame rate, exposure value, magnification, or focus can be appropriately specified by the user, or can be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 should include so-called auto exposure (AE), autofocus (AF), and auto white balance (AWB) functions.

[0304] The camera control unit 11405 controls the driving of the camera 11102 based on the control signal received from the CCU 11201 via the communication unit 11404.

[0305] The communication unit 11411 includes a communication device for transmitting various information to and receiving various information from the camera 11102. The communication unit 11411 receives the image signal transmitted from the camera 11102 via the transmission cable 11400.

[0306] In addition, the communication unit 11411 transmits a control signal for controlling the driving of the camera 11102 to the camera 11102. The image signal and the control signal can be transmitted through electrical communication, optical communication, or the like.

[0307] The image processing unit 11412 performs various image processes on the RAW data (i.e., the image signal) transmitted from the camera 11102.

[0308] The control unit 11413 executes various controls related to imaging of the surgical site or the like by the endoscope 11100 and display of the captured image obtained by imaging the surgical site or the like. For example, the control unit 11413 generates a control signal for controlling the driving of the camera 11102.

[0309] In addition, based on the image signal after image processing has been performed by the image processing unit 11412, the control unit 11413 causes the display device 11202 to display the captured image that reflects the surgical site and the like. During this process, the control unit 11413 can use various image recognition techniques to recognize various objects in the captured image. For example, the control unit 11413 can recognize surgical tools 11110 such as surgical forceps, specific living body parts, bleeding, and haze when using the energy treatment tool 11112 by detecting the edge shape or color of the objects included in the captured image. When causing the display device 11202 to display the captured image, the control unit 11413 can use the above recognition results to superimpose and display various surgical support information on the image of the surgical site. By superimposing and presenting the surgical support information to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can perform the surgery reliably.

[0310] The transmission cable 11400 that connects the camera 11102 and the CCU 11201 can be an electrical signal cable corresponding to electrical signal communication, an optical fiber corresponding to optical communication, or a composite cable thereof.

[0311] Here, in the illustrated example, communication is performed in a wired manner using the transmission cable 11400; however, communication between the camera 11102 and the CCU 11201 can be performed wirelessly.

[0312] The example of the endoscopic surgical system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the imaging unit 11402 provided in the camera 11102 of the endoscope 11100 in the configuration described above. By applying the technology according to the present disclosure to the imaging unit 11402, the imaging unit 11402 can be miniaturized or made more refined, and thus, a small or more refined endoscope 11100 can be provided.

[0313] [Other Embodiments]

[0314] Note that the effects described herein are merely exemplary and not restrictive, and there may be other effects.

[0315] In addition, the present technology may have the following technical solutions.

[0316] (1) A solid-state imaging device, comprising:

[0317] A first semiconductor substrate including a floating diffusion portion for temporarily holding an electrical signal output from a photoelectric conversion element; and

[0318] A second semiconductor substrate facing the first semiconductor substrate,

[0319] Among them, the second semiconductor substrate includes a first transistor disposed on a side facing the first semiconductor substrate, and the first transistor includes:

[0320] A channel extending along the thickness direction of the second semiconductor substrate; and

[0321] A multi-gate extending along the thickness direction of the second semiconductor substrate and sandwiching the channel therebetween,

[0322] And the multi-gate of the first transistor is connected to the floating diffusion portion.

[0323] (2) The solid-state imaging device according to (1) further includes:

[0324] A contact member that connects the mutually facing surfaces of both the multi-gate and the floating diffusion portion.

[0325] (3) The solid-state imaging device according to (1) or (2), wherein

[0326] The second semiconductor substrate includes a second transistor disposed on a side facing the first semiconductor substrate, the second transistor includes a source region, and

[0327] The multi-gate of the first transistor is connected to the source region of the second transistor.

[0328] (4) The solid-state imaging device according to any one of (1) to (3), wherein

[0329] The second semiconductor substrate includes:

[0330] A source region extending from one surface side of the second semiconductor substrate and reaching the other surface side of the second semiconductor substrate; and

[0331] A drain region extending from one surface side of the second semiconductor substrate and reaching the other surface side of the second semiconductor substrate,

[0332] The source region is connected to a signal line for transmitting the electrical signal from the surface side of the second semiconductor substrate on the opposite side of the surface facing the first semiconductor substrate, and

[0333] The drain region is connected to a power supply potential from the surface side of the second semiconductor substrate on the opposite side of the surface facing the first semiconductor substrate.

[0334] (5) The solid-state imaging device according to (1) or (2), wherein

[0335] The second semiconductor substrate includes a second transistor disposed on a side facing the first semiconductor substrate, and the second transistor includes:

[0336] a channel extending along the thickness direction of the second semiconductor substrate; and

[0337] a multi-gate extending along the thickness direction of the second semiconductor substrate and sandwiching the channel therebetween,

[0338] and the multi-gate of the second transistor is connected to a signal line for transmitting the electrical signal from the surface side at the opposite side of the surface of the second semiconductor substrate facing the first semiconductor substrate.

[0339] (6) The solid-state imaging device according to (5), wherein

[0340] the first transistor includes an amplifying transistor that amplifies the electrical signal output from the photoelectric conversion element, and

[0341] the second transistor includes a reset transistor that resets the potential of the multi-gate of the amplifying transistor to a power supply potential.

[0342] (7) The solid-state imaging device according to (6), wherein

[0343] the second semiconductor substrate includes a selection transistor that selects whether to transmit the electrical signal amplified by the amplifying transistor to the signal line.

[0344] (8) The solid-state imaging device according to (6), further comprising:

[0345] a third semiconductor substrate facing the second semiconductor substrate and disposed on a side of the second semiconductor substrate opposite to the first semiconductor substrate,

[0346] wherein the third semiconductor substrate includes a selection transistor that selects whether to transmit the electrical signal amplified by the amplifying transistor to the signal line.

[0347] (9) The solid-state imaging device according to any one of (6) to (8), wherein

[0348] the first semiconductor substrate includes a transfer transistor that transfers the electrical signal output from the photoelectric conversion element to the amplifying transistor.

[0349] (10) A video recording device, comprising:

[0350] Solid-state imaging device;

[0351] An optical system that captures incident light from a subject and forms an image on the imaging surface of the solid-state imaging device; and

[0352] A signal processing circuit that processes the output signal from the solid-state imaging device,

[0353] wherein the solid-state imaging device includes:

[0354] A first semiconductor substrate including a floating diffusion portion for temporarily holding an electrical signal output from the photoelectric conversion element; and

[0355] A second semiconductor substrate facing the first semiconductor substrate,

[0356] The second semiconductor substrate includes a first transistor disposed on a side facing the first semiconductor substrate, and the first transistor includes:

[0357] A channel extending along the thickness direction of the second semiconductor substrate; and

[0358] A multi-gate extending along the thickness direction of the second semiconductor substrate and sandwiching the channel therebetween,

[0359] And the multi-gate of the first transistor is connected to the floating diffusion portion.

[0360] List of reference numerals

[0361] 100: Solid-state imaging device

[0362] 200, 300, 400: Laminates

[0363] 201, 301, 401: Substrates

[0364] 203: Photoelectric conversion element

[0365] 204: HAD (Hole Accumulation Diode)

[0366] 220: Transfer transistor

[0367] 221: FD (Floating Diffusion Portion)

[0368] 221c, 312c, 322c, 323c, 331c: Contacts

[0369] 310: Amplification transistor

[0370] 311, 321, 331: Source regions

[0371] 312, 322, 332: Drain regions

[0372] 313: Gate electrode

[0373] 313d: Wiring

[0374] 320: Reset transistor

[0375] 330: Selection transistor

Claims

1. A solid-state imaging device, comprising: a first semiconductor substrate including a floating diffusion portion for temporarily holding an electrical signal output from a photoelectric conversion element; and a second semiconductor substrate facing the first semiconductor substrate, wherein the second semiconductor substrate includes a first transistor disposed on a side facing the first semiconductor substrate, the first transistor including: a channel extending along the thickness direction of the second semiconductor substrate; and a multi-gate extending along the thickness direction of the second semiconductor substrate and sandwiching the channel therebetween, and the multi-gate of the first transistor is connected to the floating diffusion portion, wherein the second semiconductor substrate includes a second transistor disposed on a side facing the first semiconductor substrate, the second transistor including: a source region extending from one surface side of the second semiconductor substrate and reaching the other surface side of the second semiconductor substrate, the other surface side of the second semiconductor facing the first semiconductor substrate; and a drain region extending from one surface side of the second semiconductor substrate and reaching the other surface side of the second semiconductor substrate, the source region is connected to a signal line for transmitting the electrical signal from the surface side of the second semiconductor substrate located on the opposite side of the surface facing the first semiconductor substrate, and the drain region is connected to a power supply potential from the surface side of the second semiconductor substrate located on the opposite side of the surface facing the first semiconductor substrate.

2. The solid-state imaging device according to claim 1, further comprising: a contact connecting the mutually facing surfaces of the multi-gate and the floating diffusion portion.

3. The solid-state imaging device according to claim 1, wherein the multi-gate of the first transistor is connected to the source region of the second transistor.

4. The solid-state imaging device according to claim 1, wherein the second transistor includes: a channel extending along the thickness direction of the second semiconductor substrate; and a multi-gate extending along the thickness direction of the second semiconductor substrate and sandwiching the channel therebetween, and the multi-gate of the second transistor is connected to the signal line.

5. The solid-state imaging device according to claim 4, wherein the first transistor is an amplification transistor that amplifies the electrical signal output from the photoelectric conversion element, and the second transistor is a reset transistor that resets the potential of the multi-gate of the amplification transistor to a power supply potential.

6. The solid-state imaging device according to claim 5, wherein the second semiconductor substrate includes a selection transistor that selects whether to transmit the electrical signal amplified by the amplification transistor to the signal line.

7. The solid-state imaging device according to claim 5, further comprising: a third semiconductor substrate facing the second semiconductor substrate and disposed on the side of the second semiconductor substrate opposite to the first semiconductor substrate, Among them, the third semiconductor substrate includes a selection transistor that selects whether to transmit the electrical signal amplified by the amplification transistor to the signal line.

8. The solid-state imaging device according to any one of claims 5 to 7, wherein, the first semiconductor substrate includes a transfer transistor that transfers the electrical signal output from the photoelectric conversion element to the amplification transistor.

9. A video recording device, comprising: the solid-state imaging device according to any one of claims 1 to 8; an optical system that captures incident light from a subject and forms an image on the imaging surface of the solid-state imaging device; and a signal processing circuit that processes an output signal from the solid-state imaging device.

Images