Instruction prefetching method, device, equipment and medium

Abstract

The present application discloses an instruction prefetching method, device, equipment and medium, and relates to data storage technology, wherein the method comprises: before the processor core obtains the required instructions from the target buffer corresponding to it, precompiling the instructions in the target buffer; if it is determined according to the precompilation result that there is a jump instruction in the target buffer, and the branch instruction with the jump instruction is not cached in the target buffer, then prefetching the uncached branch instruction from the instruction cache area to the candidate buffer corresponding to the processor core, to wait for the processor core to obtain the branch instruction from the candidate buffer; wherein the target buffer and the candidate buffer are alternately reused during the instruction prefetching process. The embodiment of the present application can improve the instruction fetching efficiency of each processor core, reduce the time delay of instruction fetching, and reduce the influence of the coverage of cache instructions on the operation of the processor without increasing the processing and manufacturing cost of the processor.

Description

Technical Field

[0001] The embodiments of the present application relate to computer technology, specifically to data storage technology, and more particularly to an instruction prefetching method, apparatus, device and medium. Background Art

[0002] Prefetch instruction operations are widely used in various processors to improve processor performance. Currently, for multi-core processors, prefetch instruction operations are mainly implemented in the following two ways:

[0003] Solution 1: Add a first-level register cache to each processor core. The size of this cache is generally the read path bandwidth of the instruction cache (icache). Read multiple instructions from icache at a time and store them in the added register cache. When the instructions in the register cache are used up, continue to read multiple instructions from icache. When instruction branch jumps and other operations occur in each processor core, if the jump address (pc value) is not in the register cache, it is necessary to wait for the core to read the instructions from icache again into the register cache, which will cause a long delay and affect the processor performance. In addition, if the register cache size is consistent with the icache read bandwidth, in order to avoid the current read back instruction overwriting the previously cached instruction, it is necessary to wait for the previously cached instruction to be used up before starting the next instruction fetch operation, which further increases the instruction fetch delay.

[0004] Solution 2: Add a level of icache in each processor core to reduce the instruction fetch delay caused by multi-core competition. Each core reads instructions from the icache in its own core. When the read instruction is not in the icache in the core, it initiates a read request to the next level of icache. However, adding a level of icache in each processor core will undoubtedly increase the overall area of ​​the processor and increase the processing and manufacturing cost of the processor. Summary of the invention

[0005] The embodiments of the present application disclose an instruction prefetching method, apparatus, device and medium, which improve the instruction fetching efficiency of each processor core, reduce the time delay of instruction fetching, and reduce the impact of cache instruction coverage on processor operation without increasing the processing and manufacturing cost of the processor.

[0006] In a first aspect, an embodiment of the present application discloses an instruction prefetching method, comprising:

[0007] Before the processor core obtains the required instructions from the target buffer corresponding to the processor core, precompile the instructions in the target buffer;

[0008] If it is determined according to the precompilation result that there is a jump instruction in the target buffer, and the branch instruction with the jump instruction is not cached in the target buffer, the uncached branch instruction is pre-fetched from the instruction cache area to a candidate buffer corresponding to the processor core, so as to wait for the processor core to obtain the branch instruction from the candidate buffer;

[0009] The target buffer and the candidate buffer are alternately multiplexed during the instruction prefetch process.

[0010] One embodiment of the above application has the following advantages or beneficial effects: through instruction precompilation and dynamic utilization of two buffers, the instruction fetch efficiency of each processor core is improved, the time delay of instruction fetch is reduced, and the impact of cache instruction coverage on processor operation is reduced without increasing the processing and manufacturing cost of the processor.

[0011] Optionally, pre-fetching the uncached branch instruction from the instruction cache area to a candidate buffer corresponding to the processor core includes:

[0012] The smallest instruction address among the uncached branch instructions is used as the first address, a preset number of instructions are pre-fetched from the instruction cache area, and cached in a candidate buffer corresponding to the processor core, wherein the uncached branch instructions are included in the preset number of instructions.

[0013] One embodiment of the above application has the following advantages or beneficial effects: by taking the smallest instruction address among the uncached branch instructions as the first address, as many required instructions as possible can be pre-fetched on the basis of ensuring that the previously executed branch instructions are pre-fetched.

[0014] Optionally, pre-fetching the uncached branch instruction from the instruction cache area to a candidate buffer corresponding to the processor core includes:

[0015] determining whether the uncached branch instruction is cached in a candidate buffer corresponding to the processor core;

[0016] If not, the uncached branch instruction is pre-fetched from the instruction cache into the candidate buffer.

[0017] Optionally, when the processor core obtains the branch instruction from the candidate buffer, the current instruction fetch buffer object is switched from the target buffer to the candidate buffer;

[0018] Accordingly, the method further includes:

[0019] Before the processor core obtains the branch instruction from the candidate buffer, the instructions in the candidate buffer are precompiled to determine the branch instructions that are not cached in the candidate buffer.

[0020] Optionally, precompiling the instructions in the target buffer includes:

[0021] The instructions in the target buffer are precompiled using a branch jump prediction algorithm.

[0022] Optionally, after precompiling the instructions in the target buffer, the method further includes:

[0023] If prediction failure information is received, instruction addresses are matched in sequence between registers of the target buffer and registers of the candidate buffer during the process of the processor core executing the target jump instruction, and the buffer where the branch instruction of the target jump instruction is located is determined.

[0024] One embodiment of the above application has the following advantages or beneficial effects: since two buffers are used simultaneously to perform instruction prefetching, with the alternating use of the two buffers, it is possible to pre-cache as many instructions as possible during the instruction prefetching process. Even if there is a branch instruction prediction failure, the branch instruction prefetching situation can be covered to a large extent, thereby reducing the waiting time for branch instruction refetching.

[0025] Optionally, the method further includes:

[0026] If, based on the instruction address match, it is determined that the branch instructions of the target jump instruction are not in the target buffer and the candidate buffer, the address of the branch instruction of the target jump instruction is used as the first address, and a preset number of instructions are pre-fetched from the instruction cache area and cached in the candidate buffer.

[0027] In a second aspect, an embodiment of the present application discloses an instruction prefetching device, comprising:

[0028] An instruction pre-compilation module, used for pre-compiling instructions in a target buffer before the processor core obtains required instructions from the target buffer corresponding to the processor core;

[0029] an instruction prefetch module, configured to, if it is determined according to the precompilation result that there is a jump instruction in the target buffer and the branch instruction of the jump instruction is not cached in the target buffer, prefetch the uncached branch instruction from the instruction cache area to a candidate buffer corresponding to the processor core, so as to wait for the processor core to obtain the branch instruction from the candidate buffer;

[0030] The target buffer and the candidate buffer are alternately multiplexed during the instruction prefetch process.

[0031] In a third aspect, an embodiment of the present application further discloses an electronic device, including:

[0032] at least one processor; and

[0033] a memory communicatively connected to the at least one processor; wherein,

[0034] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the instruction prefetching method as described in any of the embodiments of the present application.

[0035] In a fourth aspect, an embodiment of the present application further discloses a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable the computer to execute the instruction prefetching method as described in any one of the embodiments of the present application.

[0036] According to the technical solution of the embodiment of the present application, by precompiling the instructions in the target buffer before the processor core obtains the required instructions from the corresponding target buffer, the jump instructions and the corresponding branch instructions are determined, and the branch instructions that are not cached in the target buffer are pre-cached in the candidate buffer to wait for the processor core to obtain them, thereby solving the problem of branch instruction acquisition delay in the existing instruction pre-fetching scheme, and improving the instruction fetching efficiency of each processor core without increasing the processing and manufacturing cost of the processor, reducing the time delay of instruction fetching, and reducing the impact of cache instruction coverage on processor operation, thereby improving processor performance. Other effects of the above optional method will be described in conjunction with specific embodiments below. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present application.

[0038] Figure 1 is a flow chart of an instruction prefetching method disclosed in an embodiment of the present application;

[0039] Figure 2 is a flowchart of another instruction prefetching method disclosed in an embodiment of the present application;

[0040] Figure 3 It is a structural schematic diagram of an instruction prefetching device disclosed in an embodiment of the present application;

[0041] Figure 4 It is a block diagram of an electronic device disclosed according to an embodiment of the present application. DETAILED DESCRIPTION

[0042] The following is a description of exemplary embodiments of the present application in conjunction with the accompanying drawings, including various details of the embodiments of the present application to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present application. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0043] Figure 1 This is a flowchart of an instruction prefetching method disclosed in an embodiment of the present application. This embodiment can be applied to the situation of how to reduce the instruction reading delay of each core of the processor when there is an instruction jump. The method of this embodiment can be executed by an instruction prefetching device, which can be implemented in software and / or hardware and can be integrated in any electronic device with computing capabilities, and the processor of the electronic device includes at least one core.

[0044] In an embodiment of the present application, for a processor including at least one core, two buffers can be pre-set for each core, respectively identified as a target buffer and a candidate buffer, that is, different processor cores each correspond to a target buffer and a candidate buffer. The buffer is a storage area in the device memory. In order to increase the device memory to retain enough available buffers, the area and manufacturing cost of the processor itself will not be increased. Among them, the target buffer refers to the buffer object currently fetched by the processor core during the operation of the processor core, and the candidate buffer is used to cache specific instructions that are not cached in the target buffer in advance. For example, before obtaining the required instructions, the processor core determines the buffer where the current required instructions are located by matching the instruction address in the register, and then uses the buffer as the current target buffer. As the instruction reading and instruction processing continue, the roles of the two buffers can be alternately changed.

[0045] When the processor core has a need to fetch instructions, it first accesses two buffers to obtain the required instructions. When it is determined that there are no required instructions in the two buffers, it accesses the previous level instruction cache (icache) to obtain the required instructions and cache them in the buffer to wait for the processor core to obtain them. The size of each target buffer and candidate buffer is related to the read bandwidth (cacheline) of the instruction cache area, and can be set according to actual needs. For example, the size of each buffer can be set based on a read bandwidth of the instruction cache area. To facilitate the explanation of the embodiments of the present application, the following specifically takes a processor core as an example to illustrate the present application.

[0046] like Figure 1As shown, the instruction prefetching method disclosed in this embodiment may include:

[0047] S101 . Before a processor core obtains required instructions from a corresponding target buffer, precompile instructions in the target buffer.

[0048] Among them, pre-compilation or pre-decoding refers to compiling the instructions in the buffer in advance to determine which instructions in the buffer belong to jump instructions and the branch instructions corresponding to the jump instructions. A jump instruction refers to a specific instruction that will continue to jump to execute the next related instruction after the processor core executes the instruction. The jump instructions determined by instruction pre-compilation include inevitable jump instructions and predicted jump instructions. The inevitable jump instruction refers to an instruction that will definitely perform an instruction jump after the instruction is executed. The predicted jump instruction refers to an instruction that has a certain probability of performing an instruction jump after the instruction is executed, or it may not perform an instruction jump. Regarding the implementation of instruction pre-compilation or pre-decoding, any available instruction pre-compilation technology in the prior art can be used. For example, the instruction pre-decoder in the processor can be used to perform pre-compilation of instructions, and any available instruction branch prediction algorithm in the prior art can be used to predict the branch instruction of the instruction jump.

[0049] In this embodiment, the instructions in the target buffer are precompiled, including precompilation of each instruction in the target buffer, or compiling instructions whose addresses are equal to the instruction address currently required by the processor core, and whose addresses are greater than the instruction address currently required by the processor core, so as to determine whether there is a jump instruction in the instructions whose addresses are equal to and greater than the instruction address currently required by the processor core. A parallel compilation method can be adopted in the process of precompilation of each instruction. While setting two buffers for each processor core, registers are allocated to the two buffers respectively to record the addresses of the instructions cached in each buffer. After the branch instruction of the jump instruction in the target buffer is determined by instruction precompilation, it can be determined whether the branch instruction is cached in the target buffer by matching the instruction address in the register of the target buffer.

[0050] By precompiling the instructions in the target buffer before the processor core obtains the required instructions from the corresponding target buffer, it is possible to precompile multiple instructions including at least the required instruction before executing the required instruction, and cache the branch instructions that are not cached in the target buffer in advance in the candidate buffer, thereby reducing the waiting time for obtaining branch instructions and the time delay of instruction fetching; and, by caching the prefetched instructions in another buffer outside the target buffer, it is possible to avoid overwriting the unexecuted instructions in the target buffer, thereby reducing the impact of the overwriting of cached instructions on the operation of the processor.

[0051] S102. If it is determined based on the precompilation result that there is a jump instruction in the target buffer, and the branch instruction of the jump instruction is not cached in the target buffer, the uncached branch instruction is prefetched from the instruction cache area to the candidate buffer corresponding to the processor core to wait for the processor core to obtain the branch instruction from the candidate buffer.

[0052] Specifically, the instructions that are not cached in the target buffer and that correspond to the jump instructions that have not been acquired or executed are pre-acquired from the previous level instruction cache area and cached in the candidate buffer. Exemplarily, the target buffer and the candidate buffer are represented as buffer0 and buffer1, respectively. A total of 16 instructions with instruction addresses of 1-16 are cached in the target buffer buffer0. Before the processor core acquires the required instruction with address 9 from the target buffer buffer0, the instructions with addresses 11, 13, and 15 are determined to be jump instructions through instruction precompilation, and the branch instruction corresponding to the jump instruction with address 11 has an address of 14, the branch instruction corresponding to the jump instruction with address 13 has an address of 20, and the branch instruction corresponding to the jump instruction with address 15 has an address of 16. Through address matching, it can be determined that the branch instruction with address 20 is the jump instruction. If the instruction is not cached in the target buffer buffer0, the instruction prefetch method is used to pre-cache the branch instruction with address 20 in the candidate buffer buffer1, so that after the processor core executes the jump instruction with address 13, the instruction fetch buffer object is switched from the target buffer buffer0 to the candidate buffer buffer1, and the branch instruction with address 20 is obtained from the candidate buffer buffer1. After the buffer switching, the candidate buffer buffer1 is equivalent to the new target buffer, and the target buffer buffer0 is equivalent to the new candidate buffer. That is, in this embodiment, the target buffer and the candidate buffer are alternately reused during the instruction prefetch process.

[0053] Optionally, when the processor core obtains a branch instruction from the candidate buffer, the current instruction fetch buffer object is switched from the target buffer to the candidate buffer; accordingly, the method of this embodiment also includes: before the processor core obtains the branch instruction from the candidate buffer, the instructions in the candidate buffer are precompiled to determine the branch instructions that are not cached in the candidate buffer. That is, after the buffer is switched, the candidate buffer before the switch becomes the new target buffer, and the above operations S101-S102 are repeatedly performed in the candidate buffer to implement the prefetching of branch instructions again. As the processor core instruction fetching operation continues, when there is an instruction jump, the roles of the target buffer and the candidate buffer are dynamically switched, and the precompilation of instructions and the prefetching of branch instructions are cyclically performed between the two buffers.

[0054] Optionally, pre-fetching uncached branch instructions from an instruction cache area into a candidate buffer corresponding to a processor core includes:

[0055] The smallest instruction address among the uncached branch instructions is used as the first address, a preset number of instructions are pre-fetched from the instruction cache area, and cached in a candidate buffer corresponding to the processor core, wherein the uncached branch instructions are included in the preset number of instructions.

[0056] Continuing with the above example, among the three branch instructions with addresses 14, 20, and 16, address 20 is used as the first address, and a total of 16 instructions with addresses 20-35 are prefetched from the instruction cache and cached in the candidate buffer. By taking the smallest instruction address among the branch instructions that are not cached as the first address, it is possible to prefetch as many required instructions as possible on the basis of ensuring that the branch instructions that are executed first are prefetched. The number of instructions prefetched each time is related to the read bandwidth of the instruction cache. For example, the number of instructions prefetched each time can be determined based on a read bandwidth of the instruction cache. The instructions in the instruction cache are stored in order of the size of the instruction addresses. When prefetching instructions therefrom, they are prefetched based on the order of the first addresses of the instructions.

[0057] It should be noted that in this embodiment, if there are unexecuted instructions in the candidate buffer before the branch instruction is stored in the candidate buffer, the unexecuted instructions are usually regarded as useless instructions and can be overwritten without affecting the normal operation of the processor.

[0058] On the basis of the above technical solution, optionally, pre-fetching the uncached branch instructions from the instruction cache area to the candidate buffer corresponding to the processor core includes:

[0059] determining whether an uncached branch instruction is cached in a candidate buffer corresponding to a processor core;

[0060] If not, the uncached branch instructions are pre-fetched from the instruction cache into the candidate buffer.

[0061] Due to the alternating use of the target buffer and the candidate buffer, some instructions may have been cached in the candidate buffer before the instructions are obtained from the target buffer. Therefore, after pre-compiling the instructions in the target buffer, determining the jump instructions and the corresponding branch instructions, and determining the branch instructions that are not cached in the target buffer, further address matching is performed in the registers of the candidate buffer to determine whether the aforementioned branch instructions that are not cached are cached in the candidate buffer. If it is determined that they are cached in the candidate buffer, there is no need to perform instruction prefetching operations at present, and instructions continue to be obtained from the target buffer; if it is determined that they are not cached in the candidate buffer, an instruction prefetching operation is performed to prefetch the uncached branch instructions from the instruction cache area to the candidate buffer.

[0062] In addition, if the instructions in the target buffer are precompiled and it is determined that there is no jump instruction in the target buffer, a preset number of instructions are sequentially pre-fetched from the instruction cache area based on the instruction with the largest instruction address in the target buffer and cached in the candidate buffer. Continuing with the above example, a total of 16 instructions with instruction addresses of 1-16 are cached in the target buffer buffer0. Through instruction precompilation, it is determined that there is no jump instruction in the target buffer buffer0, and a total of 16 instructions with instruction addresses of 17-32 are sequentially pre-fetched from the instruction cache area and cached in the candidate buffer.

[0063] According to the technical solution of this embodiment, before the processor core obtains the required instructions from the corresponding target buffer, the instructions in the target buffer are precompiled to determine the jump instructions and the corresponding branch instructions, and the branch instructions that are not cached in the target buffer are pre-cached in the candidate buffer to wait for the processor core to obtain them. This solves the problem of branch instruction acquisition delay in the existing instruction prefetching scheme. Through the dynamic use of the two buffers, the instruction fetch efficiency of each processor core is improved, the time delay of instruction fetch is reduced, and the influence of cache instruction coverage on processor operation is reduced, thereby improving processor performance.

[0064] Figure 2 1 is a flowchart of another instruction prefetching method disclosed in an embodiment of the present application, which is further optimized and expanded based on the above technical solution and can be combined with the above optional implementation methods. Figure 2 As shown, the method of this embodiment may include:

[0065] S201. Before a processor core obtains required instructions from a target buffer corresponding to the processor core, the instructions in the target buffer are precompiled using a branch jump prediction algorithm.

[0066] S201. If prediction failure information is received, in the process of executing the target jump instruction, the processor core sequentially performs instruction address matching in the registers of the target buffer and the registers of the candidate buffer to determine the buffer where the branch instruction of the target jump instruction is located.

[0067] In this embodiment, the jump instructions determined by instruction precompilation include necessary jump instructions and predicted jump instructions. The necessary jump instructions refer to instructions that will definitely perform an instruction jump after the instruction is executed, and the predicted jump instructions refer to instructions that have a certain probability of performing an instruction jump after the instruction is executed, or may not perform an instruction jump.

[0068] The target instruction refers to an instruction that fails to predict the branch instruction using the branch jump prediction algorithm and is actually a jump instruction type. Since the instruction fetch buffer object of the current processor core is the target buffer, therefore, in the process of executing the target jump instruction, it is possible to first determine whether the branch instruction of the target jump instruction is cached in the target buffer. If so, the required branch instruction can be directly obtained from the target buffer. If not, the determination is continued in the candidate buffer; if it is determined that the branch instruction of the target jump instruction is cached in the candidate buffer, the instruction fetch buffer object is switched from the target buffer to the candidate buffer, that is, the candidate buffer becomes the new target buffer, and at the same time, before obtaining the required instruction from the candidate buffer, the instructions in the candidate buffer are precompiled and the branch instruction is prefetched.

[0069] Since two buffers are used simultaneously to perform instruction prefetching in this embodiment, with the alternating use of the two buffers, it is possible to pre-cache as many instructions as possible during the instruction prefetching process. Even if there is a branch instruction prediction failure, the branch instruction prefetching situation can be covered to a large extent, thereby reducing the waiting time for branch instruction refetching.

[0070] Furthermore, the method of this embodiment also includes: if it is determined based on instruction address matching that the branch instruction of the target jump instruction is not in the target buffer and the candidate buffer, that is, the branch instruction is not cached in the target buffer and the candidate buffer, then the address of the branch instruction of the target jump instruction is used as the first address, and a preset number of instructions are pre-fetched from the instruction cache area and cached in the candidate buffer, including replacement of the cached instructions in the candidate buffer. The preset number of instruction fetches can be set adaptively.

[0071] In addition, if it is determined by performing address matching in the registers of the two buffers that the instruction currently required by the processor core is not stored in the target buffer, nor is it cached in the candidate buffer, then the instruction prefetch device can send an instruction fetch request to the instruction cache area based on the instruction required by the processor core, so that the required instruction is read from the instruction cache area and cached in the candidate buffer. If the instruction prefetch device generates another instruction fetch request during the instruction fetch process based on the previous instruction fetch request, including the process from sending the instruction fetch request to retrieving the required instruction, it is determined whether the instruction address carried in the later generated instruction fetch request is consistent with the instruction address carried in the previous instruction fetch request. If they are consistent, the later instruction fetch request does not need to be sent repeatedly, thereby avoiding the sending of repeated instruction fetch requests and improving instruction fetch efficiency.

[0072] According to the technical solution of this embodiment, since two buffers are used simultaneously to perform instruction prefetching, with the alternating use of the two buffers, it is possible to pre-cache as many instructions as possible during the instruction prefetching process. Even if there is a branch instruction prediction failure, the branch instruction prefetching situation can be covered to a large extent, so that instruction addresses can be matched in the registers of the target buffer and the registers of the candidate buffer in turn, and the buffer where the branch instruction of the target jump instruction is located can be determined, thereby reducing the waiting time for re-fetching the branch instruction and improving the instruction fetching efficiency.

[0073] Figure 3 This is a schematic diagram of the structure of an instruction prefetching device disclosed in an embodiment of the present application. This embodiment can be applied to the situation of how to reduce the instruction reading delay of each core of the processor when there is an instruction jump. The device of this embodiment can be implemented in software and / or hardware, and can be integrated on any electronic device with computing capability, and the processor of the electronic device includes at least one core.

[0074] like Figure 3 As shown, the instruction prefetching device 300 disclosed in this embodiment includes an instruction precompilation module 301 and an instruction prefetching module 302, wherein:

[0075] The instruction pre-compilation module 301 is used to pre-compile the instructions in the target buffer before the processor core obtains the required instructions from the target buffer corresponding to it;

[0076] The instruction prefetch module 302 is used for, if it is determined according to the precompilation result that there is a jump instruction in the target buffer, and the branch instruction of the jump instruction is not cached in the target buffer, then prefetching the uncached branch instruction from the instruction cache area to a candidate buffer corresponding to the processor core, so as to wait for the processor core to obtain the branch instruction from the candidate buffer;

[0077] The target buffer and the candidate buffer are alternately reused during the instruction prefetch process.

[0078] Optionally, the instruction prefetch module 302 is specifically used for:

[0079] If it is determined based on the precompilation result that there is a jump instruction in the target buffer, and the branch instruction with the jump instruction is not cached in the target buffer, the smallest instruction address among the uncacheable branch instructions is used as the first address, and a preset number of instructions are pre-fetched from the instruction cache area and cached in the candidate buffer corresponding to the processor core, wherein the uncacheable branch instruction is included in the preset number of instructions.

[0080] Optionally, the instruction prefetch module 302 is specifically used for:

[0081] If it is determined according to the precompilation result that there is a jump instruction in the target buffer, and the branch instruction with the jump instruction is not cached in the target buffer, then determining whether the uncached branch instruction is cached in the candidate buffer corresponding to the processor core;

[0082] If not, the uncached branch instructions are pre-fetched from the instruction cache into the candidate buffer.

[0083] Optionally, when the processor core obtains a branch instruction from the candidate buffer, the current instruction fetch buffer object is switched from the target buffer to the candidate buffer;

[0084] Correspondingly, the instruction pre-compilation module 301 is also used for:

[0085] Before the processor core obtains the branch instruction from the candidate buffer, the instructions in the candidate buffer are precompiled to determine the branch instructions that are not cached in the candidate buffer.

[0086] Optionally, the instruction pre-compilation module 301 is specifically used for:

[0087] The instructions in the target buffer are precompiled using a branch jump prediction algorithm.

[0088] Optionally, the device of this embodiment further includes:

[0089] The buffer determination module is used to match the instruction address in the register of the target buffer and the register of the candidate buffer in turn during the process of the processor core executing the target jump instruction after the instruction precompilation module 301 performs the operation of precompilation of the instructions in the target buffer, if a prediction failure information is received, to determine the buffer where the branch instruction of the target jump instruction is located.

[0090] Optionally, the instruction prefetch module 302 is further used for:

[0091] If based on instruction address matching, it is determined that the branch instructions of the target jump instruction are not in the target buffer and the candidate buffer, the address of the branch instruction of the target jump instruction is used as the first address, and a preset number of instructions are pre-fetched from the instruction cache area and cached in the candidate buffer.

[0092] The instruction prefetching device 300 disclosed in the embodiment of the present application can execute the instruction prefetching method disclosed in the embodiment of the present application, and has the corresponding functional modules and beneficial effects of the execution method. The contents not described in detail in this embodiment can refer to the description in any method embodiment of the present application.

[0093] According to an embodiment of the present application, the present application also provides an electronic device and a readable storage medium.

[0094] like Figure 4 As shown, Figure 4 It is a block diagram of an electronic device for implementing the instruction prefetching method in the embodiment of the present application. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices and other similar computing devices. The components shown herein, their connections and relationships, and their functions are only used as examples, and are not intended to limit the implementation of the embodiments of the present application described and / or required herein.

[0095] like Figure 4 As shown, the electronic device includes: one or more processors 401, a memory 402, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. The various components are connected to each other using different buses and can be installed on a common mainboard or installed in other ways as needed. The processor can process instructions executed in the electronic device, including instructions stored in or on the memory to display graphical information of a graphical user interface (GUI) on an external input / output device (such as a display device coupled to the interface). In other embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple electronic devices can be connected, and each device provides some necessary operations, for example, as a server array, a group of blade servers, or a multi-processor system. Figure 4 A processor 401 is taken as an example.

[0096] The memory 402 is a non-transient computer-readable storage medium provided in an embodiment of the present application. The memory stores instructions executable by at least one processor to enable the at least one processor to perform the instruction prefetching method provided in an embodiment of the present application. The non-transient computer-readable storage medium of an embodiment of the present application stores computer instructions, which are used to enable a computer to perform the instruction prefetching method provided in an embodiment of the present application.

[0097] The memory 402 is a non-transient computer-readable storage medium that can be used to store non-transient software programs, non-transient computer executable programs and modules, such as the program instructions / modules corresponding to the instruction prefetching method in the embodiment of the present application, for example, Figure 3 The illustrated instruction pre-compilation module 301 and instruction pre-fetching module 302. The processor 401 executes various functional applications and data processing of the server by running non-transient software programs, instructions and modules stored in the memory 402, that is, implements the instruction pre-fetching method in the above method embodiment.

[0098] The memory 402 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required by at least one function; the data storage area may store data created according to the use of the electronic device of the instruction prefetching method, etc. In addition, the memory 402 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory 402 may optionally include a memory remotely arranged relative to the processor 401, and these remote memories may be connected to the electronic device for implementing the instruction prefetching method in this embodiment through a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0099] The electronic device for implementing the instruction prefetching method in this embodiment may further include: an input device 403 and an output device 404. The processor 401, the memory 402, the input device 403 and the output device 404 may be connected via a bus or other means. Figure 4 The example of connecting through bus is taken in the following.

[0100] The input device 403 can receive input digital or character information, and generate key signal input related to user settings and function control of the electronic device used to implement the instruction prefetching method in this embodiment, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator rod, one or more mouse buttons, a trackball, a joystick and other input devices. The output device 404 may include a display device, an auxiliary lighting device and a tactile feedback device, wherein the auxiliary lighting device is such as a light emitting diode (LED); the tactile feedback device is such as a vibration motor. The display device may include, but is not limited to, a liquid crystal display (LCD), an LED display and a plasma display. In some embodiments, the display device may be a touch screen.

[0101] Various implementations of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, application specific integrated circuits (ASICs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0102] These computer programs, also referred to as programs, software, software applications, or codes, include machine instructions for programmable processors, and may be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. As used herein, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, device, and / or means for providing machine instructions and / or data to a programmable processor, such as a disk, an optical disk, a memory, a programmable logic device (PLD), including a machine-readable medium that receives machine instructions as machine-readable signals. The term "machine-readable signal" refers to any signal for providing machine instructions and / or data to a programmable processor.

[0103] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user, such as a cathode ray tube (CRT) or an LCD monitor; and a keyboard and a pointing device, such as a mouse or a trackball, through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback; and input from the user can be received in any form, including acoustic input, voice input, or tactile input.

[0104] The systems and techniques described herein may be implemented in a computing system that includes back-end components, e.g., as a data server, or in a computing system that includes middleware components, e.g., an application server, or in a computing system that includes front-end components, e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein, or in a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication, such as a communication network. Examples of communication networks include: a Local Area Network (LAN), a Wide Area Network (WAN), and the Internet.

[0105] A computer system may include clients and servers. Clients and servers are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship to each other.

[0106] According to the technical solution of this embodiment, before the processor core obtains the required instructions from the corresponding target buffer, the instructions in the target buffer are precompiled to determine the jump instructions and the corresponding branch instructions, and the branch instructions that are not cached in the target buffer are pre-cached in the candidate buffer to wait for the processor core to obtain them. This solves the problem of branch instruction acquisition delay in the existing instruction prefetching scheme. Through the dynamic use of the two buffers, the instruction fetching efficiency of each processor core is improved, the time delay of instruction fetching is reduced, and the influence of cache instruction coverage on processor operation is reduced without increasing the processing and manufacturing cost of the processor.

[0107] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this application can be executed in parallel, sequentially or in different orders, as long as the expected results of the technical solution disclosed in this application can be achieved, and this document is not limited here.

[0108] The above specific implementations do not constitute a limitation on the protection scope of this application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of this application should be included in the protection scope of this application.

Claims

1. An instruction prefetching method, characterized in that: include: Before the processor core obtains the required instructions from the target buffer corresponding to the processor core, precompile the instructions in the target buffer in parallel; If it is determined according to the precompilation result that there is a jump instruction in the target buffer, and the branch instruction with the jump instruction is not cached in the target buffer, the uncached branch instruction is pre-fetched from the instruction cache area to a candidate buffer corresponding to the processor core, so as to wait for the processor core to obtain the branch instruction from the candidate buffer; Wherein, the target buffer and the candidate buffer are alternately multiplexed during instruction prefetching; The step of pre-fetching the uncached branch instructions from the instruction cache area to the candidate buffer corresponding to the processor core includes: The smallest instruction address among the uncached branch instructions is used as the first address, a preset number of instructions are pre-fetched from the instruction cache area, and cached in a candidate buffer corresponding to the processor core, wherein the uncached branch instructions are included in the preset number of instructions.

2. The method according to claim 1, characterized in that: The pre-fetching of the uncached branch instruction from the instruction cache area to the candidate buffer corresponding to the processor core includes: determining whether the uncached branch instruction is cached in a candidate buffer corresponding to the processor core; If not, the uncached branch instruction is pre-fetched from the instruction cache into the candidate buffer.

3. The method according to claim 1, characterized in that When the processor core obtains the branch instruction from the candidate buffer, the current instruction fetch buffer object is switched from the target buffer to the candidate buffer; Accordingly, the method further includes: Before the processor core obtains the branch instruction from the candidate buffer, the instructions in the candidate buffer are precompiled to determine the branch instructions that are not cached in the candidate buffer.

4. The method according to claim 1, characterized in that Precompiling the instructions in the target buffer includes: The instructions in the target buffer are precompiled using a branch jump prediction algorithm.

5. The method according to claim 4, characterized in that After precompiling the instructions in the target buffer, the method further includes: If prediction failure information is received, instruction addresses are matched in sequence between registers of the target buffer and registers of the candidate buffer during the process of the processor core executing the target jump instruction, and the buffer where the branch instruction of the target jump instruction is located is determined.

6. The method according to claim 5, characterized in that The method further comprises: If, based on the instruction address match, it is determined that the branch instructions of the target jump instruction are not in the target buffer and the candidate buffer, the address of the branch instruction of the target jump instruction is used as the first address, and a preset number of instructions are pre-fetched from the instruction cache area and cached in the candidate buffer.

7. An instruction prefetching device, characterized in that: include: An instruction pre-compilation module, used for pre-compilation of instructions in a target buffer in parallel before the processor core obtains the required instructions from the target buffer corresponding to the processor core; an instruction prefetch module, configured to, if it is determined according to the precompilation result that there is a jump instruction in the target buffer and the branch instruction of the jump instruction is not cached in the target buffer, prefetch the uncached branch instruction from the instruction cache area to a candidate buffer corresponding to the processor core, so as to wait for the processor core to obtain the branch instruction from the candidate buffer; Wherein, the target buffer and the candidate buffer are alternately multiplexed during instruction prefetching; Among them, the instruction prefetch module is specifically used for: The smallest instruction address among the uncached branch instructions is used as the first address, a preset number of instructions are pre-fetched from the instruction cache area, and cached in a candidate buffer corresponding to the processor core, wherein the uncached branch instructions are included in the preset number of instructions.

8. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the instruction prefetching method according to any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to enable the computer to execute the instruction prefetching method according to any one of claims 1 to 6.

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