Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention relates to a semiconductor device and a method for preparing the semiconductor device. The method for preparing the semiconductor device comprises: providing a layer to be etched; forming a patterned first mask layer on the layer to be etched; forming a patterned second mask layer on the layer to be etched, the second mask layer and the first mask layer jointly define an opening, the opening exposes the layer to be etched; using the first mask layer and the second mask layer as masks, etching the layer to be etched to form a pattern to be etched. The method for preparing the semiconductor device makes the feature sizes of the first mask layer and the second mask layer larger when the feature sizes of the device are the same, and makes it possible to further reduce the feature sizes of the device, and can also improve the yield of the device and save costs.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor device and a method for preparing the semiconductor device. Background Art

[0002] Integrated circuit (IC), also known as microcircuit, microchip, chip, is a way of miniaturizing circuits (mainly semiconductor devices, but also passive components, etc.) in electronics, and is usually manufactured on the surface of semiconductor wafers. For example, DRAM (Dynamic Random Access Memory), that is, dynamic random access memory chip, is the most common memory chip. Over the years, DRAM has continued to develop towards smaller form factors, allowing each chip to package more circuits. This increases the capacity per unit area, reduces costs and increases functionality, but requires the minimum line width and spacing of integrated circuit design to continue to shrink. However, when the feature size of the exposure line approaches the theoretical resolution limit of the exposure system, the imaging of the silicon wafer surface will be severely distorted, resulting in a serious decline in the quality of the lithography pattern. Summary of the invention

[0003] Based on this, in order to solve the above problems, the present invention provides a semiconductor device and a method for preparing the semiconductor device.

[0004] The present invention provides a method for preparing a semiconductor device, comprising: providing a layer to be etched; forming a patterned first mask layer on the layer to be etched; forming a patterned second mask layer on the layer to be etched, the second mask layer and the first mask layer jointly defining an opening, the opening exposing the layer to be etched; using the first mask layer and the second mask layer as masks, etching the layer to be etched to form a pattern to be etched.

[0005] The method for preparing the semiconductor device can increase the characteristic dimensions of the first mask layer and the second mask layer when the characteristic dimensions of the device are the same, and further reduce the characteristic dimensions of the device, thereby improving the yield of the device and saving costs.

[0006] In one embodiment, the first mask layer includes a plurality of mutually parallel first strip masks, the second mask layer includes a plurality of mutually parallel second strip masks, and the plurality of first strip masks and the plurality of second strip masks are alternately arranged in parallel.

[0007] In one embodiment, at least one side of the first strip mask has equidistantly arranged recesses, at least one side of the second strip mask has equidistantly arranged recesses, the recesses of the first strip mask and the second strip mask constitute the opening, and the recesses of the second strip mask and the first strip mask constitute the opening.

[0008] In one embodiment, two sides of the first stripe mask and two sides of the second stripe mask have concave portions arranged at equal intervals, and the concave portions of the first stripe mask and the concave portions of the second stripe mask form the opening.

[0009] In one embodiment, two sides of the first strip mask or the second strip mask have equidistantly arranged concave portions, and the concave portions of the first strip mask and the second strip mask form the opening or the concave portions of the second strip mask and the first strip mask form the opening.

[0010] In one embodiment, the shape of the recess includes triangle, arc or rectangle.

[0011] In one embodiment, the first mask layer includes a plurality of first windows, the second mask layer includes a plurality of second windows, and the first mask layer and the second mask layer are staggered to form the opening.

[0012] The present invention also provides a semiconductor device, comprising: a layer to be etched; a patterned first mask layer formed on the layer to be etched; a patterned second mask layer formed on the layer to be etched, the second mask layer and the first mask layer jointly define an opening, and the opening exposes the layer to be etched.

[0013] The semiconductor device described above makes the characteristic dimensions of the first mask layer and the second mask layer larger when the characteristic dimensions of the device are the same, and makes it possible to further reduce the characteristic dimensions of the device, thereby improving the yield of the device and saving costs.

[0014] In one embodiment, the first mask layer includes a plurality of mutually parallel first strip masks, the second mask layer includes a plurality of mutually parallel second strip masks, and the plurality of first strip masks and the plurality of second strip masks are alternately arranged in parallel.

[0015] In one embodiment, at least one side of the first strip mask has equidistantly arranged recesses, at least one side of the second strip mask has equidistantly arranged recesses, the recesses of the first strip mask and the second strip mask constitute the opening, and the recesses of the second strip mask and the first strip mask constitute the opening.

[0016] In one embodiment, two sides of the first stripe mask and two sides of the second stripe mask have concave portions arranged at equal intervals, and the concave portions of the first stripe mask and the concave portions of the second stripe mask form the opening.

[0017] In one embodiment, two sides of the first strip mask or the second strip mask have equidistantly arranged concave portions, and the concave portions of the first strip mask and the second strip mask form the opening or the concave portions of the second strip mask and the first strip mask form the opening.

[0018] In one embodiment, the shape of the recess includes triangle, arc or rectangle.

[0019] In one embodiment, the first mask layer includes a plurality of first windows, the second mask layer includes a plurality of second windows, and the first mask layer and the second mask layer are staggered to form the opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A flow chart of a method for preparing a semiconductor device of the present invention;

[0021] Figure 2 to Figure 5 It is a structural schematic diagram presented in each step of the method for preparing a semiconductor device of the present invention;

[0022] Figure 6a is a top view of a first mask layer in a semiconductor device in one embodiment of the present invention;

[0023] Figure 6b is a top view of a second mask layer in a semiconductor device in one embodiment of the present invention;

[0024] Figure 6c A top view of a first mask layer and a second mask layer in a semiconductor device in an embodiment of the present invention;

[0025] Figure 7a is a top view of a first mask layer in a semiconductor device in another embodiment of the present invention;

[0026] Figure 7b is a top view of a second mask layer in a semiconductor device in another embodiment of the present invention;

[0027] Figure 7c is a top view of a first mask layer and a second mask layer in a semiconductor device in another embodiment of the present invention;

[0028] Figure 8a is a top view of a first mask layer in a semiconductor device in another embodiment of the present invention;

[0029] Figure 8b is a top view of a second mask layer in a semiconductor device in another embodiment of the present invention;

[0030] Figure 8c is a top view of a first mask layer and a second mask layer in a semiconductor device in another embodiment of the present invention;

[0031] Figure 9a is a top view of a first mask layer in a semiconductor device in another embodiment of the present invention;

[0032] Figure 9b is a top view of a second mask layer in a semiconductor device in another embodiment of the present invention;

[0033] Fig.9c is a top view of a first mask layer and a second mask layer in a semiconductor device in another embodiment of the present invention;

[0034] Fig.10a is a top view of a first mask layer in a semiconductor device in another embodiment of the present invention;

[0035] Fig.10b is a top view of a second mask layer in a semiconductor device in another embodiment of the present invention;

[0036] Fig.10c is a top view of a first mask layer and a second mask layer in a semiconductor device in another embodiment of the present invention;

[0037] Fig.11a is a top view of a first mask layer in a semiconductor device in another embodiment of the present invention;

[0038] Fig.11b is a top view of a second mask layer in a semiconductor device in another embodiment of the present invention;

[0039] Fig.11c FIG. 4 is a top view of a first mask layer and a second mask layer in a semiconductor device in another embodiment of the present invention.

[0040] 10 Layer to be etched 20 First mask layer 201 The first stripe mask 202 First Window 30 Second mask layer 301 Second stripe mask 302 Second window 40 Opening 50 concavity DETAILED DESCRIPTION

[0041] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0043] In the description of the present invention, it is necessary to understand that the terms "upper", "lower", "vertical", "horizontal", "inside", "outside", etc., indicating the orientation or positional relationship, are based on the method or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0044] An embodiment, such as Figure 1 As shown, a method for preparing a semiconductor device is provided, including: providing a layer to be etched 10; forming a patterned first mask layer 20 on the layer to be etched 10; forming a patterned second mask layer 30 on the layer to be etched 10, the second mask layer 30 and the first mask layer 20 jointly define an opening 40, and the opening 40 exposes the layer to be etched 10; using the first mask layer 20 and the second mask layer 30 as masks, etching the layer to be etched to form a pattern to be etched.

[0045] In this embodiment, the method for preparing the semiconductor device increases the characteristic dimensions of the first mask layer 20 and the second mask layer 30 when the characteristic dimensions of the devices are the same, and makes it possible to further reduce the characteristic dimensions of the devices, thereby improving the yield of the devices and saving costs.

[0046] S10: providing a layer 10 to be etched, such as Figure 2 shown.

[0047] S20: forming a patterned first mask layer 20 on the layer to be etched 10, such as Figure 3 shown.

[0048] In one embodiment, the method for forming the first mask layer 20 includes a chemical vapor deposition or atomic layer deposition process, and the material of the first mask layer 20 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, amorphous carbon, polycrystalline silicon, hafnium oxide, titanium oxide, zirconium oxide, titanium nitride, tantalum nitride, and titanium.

[0049] S30: forming a patterned second mask layer 30 on the layer to be etched 10, wherein the second mask layer 30 and the first mask layer 20 together define an opening 40, wherein the opening 40 exposes the layer to be etched 10, such as Figure 4 shown.

[0050] In one embodiment, the method for forming the second mask layer 30 includes a chemical vapor deposition or atomic layer deposition process, and the material of the second mask layer 30 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, amorphous carbon, polycrystalline silicon, hafnium oxide, titanium oxide, zirconium oxide, titanium nitride, tantalum nitride, and titanium.

[0051] S40: Using the first mask layer 20 and the second mask layer 30 as masks, etching the layer to be etched 10 to form a pattern to be etched, such as Figure 5 shown.

[0052] In this embodiment, the material of the first mask layer 20 is different from the material of the second mask layer 30 and has a large etching selectivity ratio.

[0053] In another embodiment, between S20 and S30, a dielectric layer is formed on the first mask layer 20. After the dielectric layer is formed on the first mask layer 20, a second mask layer 30 is formed on the dielectric layer, and at this time, the first mask layer 20 and the second mask layer 30 are not located on the same plane. The material of the dielectric layer is different from the material of the first mask layer 20 and the material of the second mask layer 30 and has a large etching selectivity ratio, wherein the material of the first mask layer 20 and the material of the second mask layer 30 can be the same.

[0054] In one embodiment, the method of forming the dielectric layer includes a chemical vapor deposition or atomic layer deposition process, and the material of the dielectric layer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, amorphous carbon, polycrystalline silicon, hafnium oxide, titanium oxide, zirconium oxide, titanium nitride, tantalum nitride, and titanium.

[0055] In one embodiment, opening 40 comprises a bit line contact hole.

[0056] In one embodiment, the first mask layer 20 includes a plurality of mutually parallel first strip masks 201 , and the second mask layer 30 includes a plurality of mutually parallel second strip masks 301 . The plurality of first strip masks 201 and the plurality of second strip masks 301 are alternately arranged in parallel.

[0057] In this embodiment, a plurality of first strip masks 201 are arranged at equal intervals, and a plurality of second strip masks 301 are arranged at equal intervals.

[0058] In one embodiment, at least one side of the first strip mask 201 has recesses 50 arranged at equal distances, at least one side of the second strip mask 301 has recesses 50 arranged at equal distances, the recesses 50 of the first strip mask 201 and the second strip mask 301 define openings 40, and the recesses 50 of the second strip mask 301 and the first strip mask 201 define openings 40. For example, one side of the first strip mask 201 and one side of the second strip mask 301 have recesses 50 arranged at equal distances, and the recesses 50 of the first strip mask 201 and the recesses 50 of the second strip mask 301 define openings 40. Figure 8a , Figure 8b , Figure 8c shown.

[0059] In one embodiment, the two sides of the first strip mask 201 and the two sides of the second strip mask 301 have equidistantly arranged concave portions 50, and the concave portions 50 of the first strip mask 201 and the concave portions 50 of the second strip mask 301 define an opening 40, such as Figure 6a , Figure 6b , Figure 6c shown.

[0060] In one embodiment, two sides of the first strip mask 201 or the second strip mask 301 have equidistantly arranged recesses 50, and the recesses 50 of the first strip mask 201 and the second strip mask 301 define an opening 40 or the recesses 50 of the second strip mask 301 and the first strip mask 201 define an opening 40. Figure 7a , Figure 7b , Figure 7c shown.

[0061] In one embodiment, the shape of the recess 50 includes a triangle, an arc, or a rectangle.

[0062] In one embodiment, the shape of the recess 50 is triangular, such as Figure 6a , Figure 6b , Figure 6c shown.

[0063] In one embodiment, the shape of the recess 50 is arc-shaped, such as Fig.10a , Fig.10b , Fig.10c shown.

[0064] In one embodiment, the shape of the recess 50 is rectangular, such as Figure 9a , Figure 9b , Fig.9c shown.

[0065] In one embodiment, the first mask layer 20 includes a plurality of first windows 202, the second mask layer 30 includes a plurality of second windows 302, and the first mask layer 20 and the second mask layer 30 are arranged in a staggered manner to define an opening 40. Fig.11a , Fig.11b , Fig.11c shown.

[0066] In this embodiment, the first windows 202 are arranged in an array, and the second windows 302 are arranged in an array. The shapes of the first windows 202 and the second windows 302 include, but are not limited to, rectangles.

[0067] An embodiment, such as Figure 4 As shown, a semiconductor device is provided, including: a layer to be etched 10; a patterned first mask layer 20 formed on the layer to be etched 10; a patterned second mask layer 30 formed on the layer to be etched 10, the second mask layer 30 and the first mask layer 20 jointly define an opening 40, and the opening 40 exposes the layer to be etched 10.

[0068] In this embodiment, the semiconductor device described above makes the characteristic dimensions of the first mask layer 20 and the second mask layer 30 larger when the characteristic dimensions of the devices are the same, and makes it possible to further reduce the characteristic dimensions of the devices, thereby improving the yield of the devices and saving costs.

[0069] In one embodiment, the material of the first mask layer 20 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, amorphous carbon, polysilicon, hafnium oxide, titanium oxide, zirconium oxide, titanium nitride, tantalum nitride, and titanium.

[0070] In one embodiment, the material of the second mask layer 30 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, amorphous carbon, polysilicon, hafnium oxide, titanium oxide, zirconium oxide, titanium nitride, tantalum nitride, and titanium.

[0071] In this embodiment, the material of the first mask layer 20 is different from the material of the second mask layer 30 and has a large etching selectivity ratio.

[0072] In another embodiment, a dielectric layer is further included between the first mask layer 20 and the second mask layer 30. The material of the dielectric layer is different from the material of the first mask layer 20 and the material of the second mask layer 30 and has a large etching selectivity ratio.

[0073] In one embodiment, the material of the dielectric layer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, amorphous carbon, polysilicon, hafnium oxide, titanium oxide, zirconium oxide, titanium nitride, tantalum nitride, and titanium.

[0074] In one embodiment, opening 40 comprises a bit line contact hole.

[0075] In one embodiment, the first mask layer 20 includes a plurality of mutually parallel first strip masks 201 , and the second mask layer 30 includes a plurality of mutually parallel second strip masks 301 . The plurality of first strip masks 201 and the plurality of second strip masks 301 are alternately arranged in parallel.

[0076] In this embodiment, a plurality of first strip masks 201 are arranged at equal intervals, and a plurality of second strip masks 301 are arranged at equal intervals.

[0077] In one embodiment, at least one side of the first strip mask 201 has recesses 50 arranged at equal distances, at least one side of the second strip mask 301 has recesses 50 arranged at equal distances, the recesses 50 of the first strip mask 201 and the second strip mask 301 define openings 40, and the recesses 50 of the second strip mask 301 and the first strip mask 201 define openings 40. For example, one side of the first strip mask 201 and one side of the second strip mask 301 have recesses 50 arranged at equal distances, and the recesses 50 of the first strip mask 201 and the recesses 50 of the second strip mask 301 define openings 40. Figure 8a , Figure 8b , Figure 8c shown.

[0078] In one embodiment, the two sides of the first strip mask 201 and the two sides of the second strip mask 301 have equidistantly arranged concave portions 50, and the concave portions 50 of the first strip mask 201 and the concave portions 50 of the second strip mask 301 define an opening 40, such as Figure 6a , Figure 6b , Figure 6c shown.

[0079] In one embodiment, two sides of the first strip mask 201 or the second strip mask 301 have equidistantly arranged recesses 50, and the recesses 50 of the first strip mask 201 and the second strip mask 301 define an opening 40 or the recesses 50 of the second strip mask 301 and the first strip mask 201 define an opening 40. Figure 7a , Figure 7b , Figure 7c shown.

[0080] In one embodiment, the shape of the recess 50 includes a triangle, an arc, or a rectangle.

[0081] In one embodiment, the shape of the recess 50 is triangular, such as Figure 6a , Figure 6b , Figure 6c shown.

[0082] In one embodiment, the shape of the recess 50 is arc-shaped, such as Fig.10a , Fig.10b , Fig.10c shown.

[0083] In one embodiment, the shape of the recess 50 is rectangular, such as Figure 9a , Figure 9b , Fig.9c shown.

[0084] In one embodiment, the first mask layer 20 includes a plurality of first windows 202, the second mask layer 30 includes a plurality of second windows 302, and the first mask layer 20 and the second mask layer 30 are arranged in a staggered manner to define an opening 40. Fig.11a , Fig.11b , Fig.11c shown.

[0085] In this embodiment, the first windows 202 are arranged in an array, and the second windows 302 are arranged in an array. The shapes of the first windows 202 and the second windows 302 include, but are not limited to, rectangles.

[0086] The formation order and position of the above-mentioned first mask layer 20 and the second mask layer 30 can be interchanged, the layout direction of the opening 40 relative to the layer to be etched 10 can be adjusted arbitrarily according to needs, and the layout direction of the first mask layer 20 and the second mask layer 30 relative to the layer to be etched 10 can be adjusted arbitrarily according to needs, and the above-mentioned should be considered as within the scope recorded in this specification.

[0087] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0088] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a layer to be etched; Forming a patterned first mask layer on the layer to be etched, wherein the first mask layer comprises a plurality of first strip masks parallel to each other, and at least one side of the first strip masks has concave portions arranged at equal intervals; A patterned second mask layer is formed on the layer to be etched, wherein the second mask layer comprises a plurality of second strip masks parallel to each other, a plurality of the first strip masks and a plurality of the second strip masks are alternately arranged in parallel, the second mask layer and the first mask layer jointly define an opening, at least one side of the second strip mask has concave portions arranged at equal intervals, the concave portions of the first strip mask and the second strip mask constitute the opening, the concave portions of the second strip mask and the first strip mask constitute the opening, and the opening exposes the layer to be etched; The layer to be etched is etched using the first mask layer and the second mask layer as masks to form a pattern to be etched.

2. The method for preparing a semiconductor device according to claim 1, wherein: The two side edges of the first stripe mask and the two side edges of the second stripe mask have concave portions arranged at equal intervals, and the concave portions of the first stripe mask and the concave portions of the second stripe mask form the openings.

3. The method for preparing a semiconductor device according to claim 1, characterized in that: Two sides of the first stripe mask or the second stripe mask have equidistantly arranged concave portions, and the concave portions of the first stripe mask and the second stripe mask form the openings, or the concave portions of the second stripe mask and the first stripe mask form the openings.

4. The method for preparing a semiconductor device according to any one of claims 1 to 3, characterized in that: The shape of the concave portion includes a triangle, an arc or a rectangle.

5. The method for preparing a semiconductor device according to claim 1, characterized in that: The first mask layer includes a plurality of first windows, the second mask layer includes a plurality of second windows, and the first mask layer and the second mask layer are staggered to form the opening.

6. A semiconductor device, characterized in that: include: A layer to be etched; A patterned first mask layer is formed on the layer to be etched, wherein the first mask layer comprises a plurality of first strip masks parallel to each other, and at least one side of the first strip masks has concave portions arranged at equal intervals; A patterned second mask layer is formed on the layer to be etched, the second mask layer includes a plurality of second strip masks parallel to each other, a plurality of the first strip masks and a plurality of the second strip masks are alternately arranged in parallel, at least one side of the second strip masks has concave portions arranged at equal intervals, the second mask layer and the first mask layer jointly define an opening, the concave portions of the first strip masks and the second strip masks constitute the opening, the concave portions of the second strip masks and the first strip masks constitute the opening, and the opening exposes the layer to be etched; The material of the first mask layer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, amorphous carbon, polysilicon, hafnium oxide, titanium oxide, zirconium oxide, titanium nitride, tantalum nitride, and titanium.

7. The semiconductor device according to claim 6, characterized in that The two side edges of the first stripe mask and the two side edges of the second stripe mask have concave portions arranged at equal intervals, and the concave portions of the first stripe mask and the concave portions of the second stripe mask form the openings.

8. The semiconductor device according to claim 6, characterized in that Two sides of the first stripe mask or the second stripe mask have equidistantly arranged concave portions, and the concave portions of the first stripe mask and the second stripe mask form the openings, or the concave portions of the second stripe mask and the first stripe mask form the openings.

9. The semiconductor device according to any one of claims 6 to 8, characterized in that: The shape of the concave portion includes a triangle, an arc or a rectangle.

10. The semiconductor device according to claim 6, wherein: The first mask layer includes a plurality of first windows, the second mask layer includes a plurality of second windows, and the first mask layer and the second mask layer are staggered to form the opening.

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