An active clamping circuit for secondary side synchronous rectification spike voltage clamping

Abstract

The present invention discloses an active clamping circuit for secondary-side synchronous rectification spike voltage clamping, which includes a full-bridge synchronous rectification circuit 101, a PMOS active clamping unit circuit 102, an active clamping driving and control unit circuit 103, and a synchronous rectification freewheeling inductor 104; the full-bridge synchronous rectification circuit 101 is connected to the secondary side of the transformer, the positive output is connected to the positive input of the PMOS active clamping unit circuit 102, and the negative output is connected to the negative input of the PMOS active clamping unit circuit 102; the positive output of the PMOS active clamping unit circuit 102 is connected to the positive input of the active clamping driving and control unit circuit 103, and the negative output is connected to the negative input of the active clamping driving and control unit circuit 103; the positive output of the active clamping driving and control unit circuit 103 is connected to the synchronous rectification freewheeling inductor 104, and the negative output is grounded. The beneficial effects of the present invention are as follows: it can effectively reduce the drain oscillation spike voltage of the secondary-side synchronous rectification MOS transistor and reduce the breakdown voltage requirement of the secondary-side synchronous rectification MOS transistor.

Description

Technical Field

[0001] The present invention relates to a secondary-side synchronous full-bridge rectifier circuit for a power supply, and specifically, to an active clamping circuit for clamping the spike voltage in secondary-side synchronous rectification. Background Art

[0002] In some power supplies with low-voltage and high-current output, if diodes are used for rectification on the secondary side, the loss is large and the efficiency is low. Generally, MOS transistors are used for synchronous rectification on the secondary side to improve the efficiency. However, in some circuit topologies such as hard half-bridge, hard full-bridge, phase-shifted full-bridge and other topologies, due to the leakage inductance of the transformer or the externally added resonant inductance, an oscillating spike voltage much higher than the normal voltage will be formed on the drain of the secondary-side synchronous rectification MOS transistor. The amplitude and duration of this spike voltage are affected by factors such as leakage inductance and the parasitic Coss of the MOS transistor.

[0003] Due to the existence of the spike voltage, generally, a MOS transistor with a higher breakdown voltage needs to be selected as the synchronous rectification transistor or an absorption clamping circuit is adopted.

[0004] If a MOS transistor with a higher breakdown voltage is used, since the internal resistance of the MOS transistor with a higher breakdown voltage will be correspondingly larger and the switching speed is slower, the overall efficiency of the machine will become lower.

[0005] If a clamping circuit is used to absorb the spike voltage, a MOS transistor with a low breakdown voltage can be used. The absorption clamping circuit is generally divided into active and passive absorption circuits.

[0006] Among them, for a passive absorption circuit such as an RCD clamping circuit, it achieves the absorption effect by consuming energy itself, which affects the efficiency and generates a large amount of heat. Due to the heat generation, a certain volume is required for heat dissipation.

[0007] However, the active clamping circuit generally has a too complex control circuit, and the timing requirements for the primary and secondary sides are relatively strict. In some abnormal operating states, it is easy to fail to release energy, resulting in clamping failure.

[0008] The patent document with the application number "CN202010147952.1" discloses an active MOSFET voltage clamping circuit, a clamping method and a double-pulse test circuit. Although this circuit, compared with the passive clamping circuit, directly follows the conduction voltage of the power device and does not require correction of the forward conduction voltage drop of the diode, this circuit cannot reduce the breakdown voltage requirement of the secondary-side synchronous rectification MOS transistor. Summary of the Invention

[0009] The purpose of the present invention is to propose an active clamping circuit for clamping the spike voltage in secondary-side synchronous rectification in view of the above problems.

[0010] An active clamping circuit for secondary side synchronous rectification spike voltage clamping, comprising a full-bridge synchronous rectification circuit 101, a PMOS active clamping unit circuit 102, an active clamping drive and control unit circuit 103, and a synchronous rectification freewheeling inductor 104;

[0011] The full-bridge synchronous rectification circuit 101 is connected to the secondary side of the transformer, and the output is connected to the PMOS active clamping unit circuit 102;

[0012] The output of the PMOS active clamping unit circuit 102 is connected to the active clamping drive and control unit circuit 103;

[0013] The positive output of the active clamping drive and control unit circuit 103 is connected to the synchronous rectification freewheeling inductor 104, and the negative output is grounded.

[0014] Preferably, each of the four bridge arms in the full-bridge synchronous rectification circuit 101 includes a field effect transistor QA, a field effect transistor QB, a field effect transistor QC, and a field effect transistor QD.

[0015] Preferably, the PMOS active clamping unit circuit 102 includes a capacitor CV, a resistor R2, a resistor R5, a diode D7, a diode D8, and a PMOS transistor; the capacitor CV, the resistor R2, and the PMOS transistor are connected in series, and by switching the on or off state of the PMOS transistor, the spike voltage existing at the drains of QA to QD is clamped on the capacitor CV.

[0016] Preferably, the diode D7, the diode D8, and the resistor R5 form an auxiliary clamping circuit and are connected in parallel with the resistor R2 and the PMOS transistor, and together with the capacitor CV, the resistor R2, and the PMOS transistor, the spike voltage existing at the drains of QA to QD is clamped on the capacitor CV.

[0017] Preferably, the active clamping drive and control unit circuit 103 includes a capacitor C50, a diode D9, a resistor R20, a resistor R68, a diode D22, a resistor R21, a resistor R1, a capacitor C104, a driver U8, a capacitor C47, a resistor R67, and a diode D6. By charging and discharging C50, the output voltage of the driver U8 is changed to achieve charge and discharge control of the circuit.

[0018] Preferably, the capacitor C50 is connected in series with the resistor R68 and the diode D22; the resistor R68 is connected in parallel with the diode D9 and R20; the resistor R21 is connected in parallel with the diode D22; one end of the positive input terminal of the driver U8 is connected between the resistor R68 and the diode D22, and the other end is grounded, and the positive output terminal is connected to the PMOS transistor; the diode D6 and the resistor R7 are connected in parallel between the driver U8 and the PMOS transistor; the capacitor C47 is connected in series between the driver U8 and the PMOS transistor; the R1 is connected to the enable terminal of the driver U8 and the positive input terminal of the driver U8; the capacitor C104 is connected to the enable terminal of the driver U8 and the ground terminal.

[0019] The beneficial effects of the present invention are as follows: it can effectively reduce the drain oscillation spike voltage of the secondary synchronous rectifier MOS transistor, reduce the withstand voltage requirement of the secondary synchronous rectifier MOS transistor, enable the use of a lower-voltage synchronous rectifier MOS transistor in some applications to improve the overall efficiency. At the same time, the active clamp has small self-power loss, higher efficiency, less heat generation, and smaller overall volume compared to the passive RCD clamp. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is the schematic diagram of the present invention. [[ID=X]]

[0021] Figure 2 is the internal schematic diagram of the rectification absorption process of the present invention.

[0022] Figure 3 is the internal schematic diagram of the freewheeling process of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0023] The present invention will be further described below with reference to the accompanying drawings.

[0024] As Figure 1 shown, an active clamp circuit for clamping the spike voltage of the secondary synchronous rectification includes a full-bridge synchronous rectification circuit 101, a PMOS active clamp unit circuit 102, an active clamp drive and control unit circuit 103, and a synchronous rectification freewheeling inductor 104;

[0025] The full-bridge synchronous rectification circuit 101 is connected to the secondary side of the transformer, and the output is connected to the PMOS active clamp unit circuit 102;

[0026] The output of the PMOS active clamp unit circuit 102 is connected to the active clamp drive and control unit circuit 103;

[0027] The positive output terminal of the active clamp drive and control unit circuit 103 is connected to the synchronous rectification freewheeling inductor 104, and the negative output terminal is grounded.

[0028] Preferably, each of the four bridge arms in the full-bridge synchronous rectification circuit 101 includes a field-effect transistor QA, a field-effect transistor QB, a field-effect transistor QC, and a field-effect transistor QD.

[0029] Preferably, the PMOS active clamping unit circuit 102 includes a capacitor CV, a resistor R2, a resistor R5, a diode D7, a diode D8, and a PMOS transistor; the capacitor CV, the resistor R2, and the PMOS transistor are connected in series, and by switching the on or off state of the PMOS transistor, the peak voltage existing at the drains of QA to QD is clamped on the capacitor CV.

[0030] The diode D7, the diode D8, and the resistor R5 form an auxiliary clamping circuit and are connected in parallel with the resistor R2 and the PMOS transistor. The capacitor CV, the resistor R2, and the PMOS transistor clamp the peak voltage existing at the drains of QA to QD on the capacitor CV.

[0031] The active clamping drive and control unit circuit 103 includes a capacitor C50, a diode D9, a resistor R20, a resistor R68, a diode D22, a resistor R21, a resistor R1, a capacitor C104, a driver U8, a capacitor C47, a resistor R67, and a diode D6. By charging and discharging C50, the output voltage of the driver U8 is changed to achieve the charge and discharge control of the circuit.

[0032] The capacitor C50 is connected in series with the resistor R68 and the diode D22; the resistor R68 is connected in parallel with the diode D9 and R20; the resistor R21 is connected in parallel with the diode D22; one end of the positive input terminal of the driver U8 is connected between the resistor R68 and the diode D22, and the other end is grounded, and the positive output terminal is connected to the PMOS transistor; the diode D6 and the resistor R7 are connected in parallel and connected between the driver U8 and the PMOS transistor; the capacitor C47 is connected in series between the driver U8 and the PMOS transistor; the R1 is connected to the enable terminal of the driver U8 and the positive input terminal of the driver U8; the capacitor C104 is connected to the enable terminal of the driver U8 and the ground terminal.

[0033] The field-effect transistors QA to QD and the transformer form a secondary-side full-bridge synchronous rectification circuit 101, and the synchronous rectification function is realized by modulating the switching of the field-effect transistors QA to QD; the PMOS active clamping unit circuit 102 includes a capacitor CV, a resistor R2, a PMOS transistor, a diode D7, a diode D8, and a resistor R5, where the diode D7, the diode D8, and the resistor R5 are an auxiliary clamping circuit and can be selected or discarded according to requirements; the main functions of the capacitor CV, the resistor R2, and the PMOS transistor are that when there is a peak voltage at the drains of QA to QD, the peak voltage forms a loop through the capacitor CV, the resistor R2, and the body diode of the PMOS transistor to clamp the peak voltage energy at the drains of QA to QD on the capacitor CV.

[0034] As Figure 2As shown, at this time, in the active clamp drive and control unit circuit, during the rectification process of field effect transistors QA to QD, capacitor C50 is charged, the non-inverting input terminal of driver U8 is at a high level, U8 outputs a high level, and the PMOS transistor is turned off. At this time, capacitor CV can only be charged and cannot release electrical energy.

[0035] Only when the rectification of field effect transistors QA to QD ends and inductor L3 conducts freewheeling, due to the freewheeling of inductor L3, the voltage at its front end will be pulled down to zero or even a negative voltage. At this time, the lower end of capacitor C50 will be pulled down to a negative voltage and clamped to about -0.7V by diode D22. At this time, the non-inverting input terminal of driver U8 is at a low level, U8 outputs a low level, the PMOS transistor conducts, and the current on the capacitor discharges to the load through the PMOS transistor and the freewheeling inductor L3, completing a cycle of charge and discharge process.

[0036] It should be understood that in this embodiment, the active clamp circuit for clamping the secondary side synchronous rectification spike voltage mainly includes a rectification absorption process.

[0037] Rectification absorption process: During this process, the spike voltage generated by T1 is rectified by QA~QD, and the current forms a loop through CV, R2, and PMOS. At this time, the body diode of PMOS conducts forward (the lower end of C50 is coupled to a high level and clamped by D22 to prevent damage to U8. U8 inputs a high level signal, U8 outputs a high level, and PMOS is turned off), storing the spike voltage energy in CV to achieve spike voltage clamping. In addition, D7 is used as an auxiliary bypass path and can be optionally installed.

[0038] As Figure 3 shown, in the next cycle, field effect transistors QA to QD will enter the rectification state again, capacitor CV will be energized again, and when inductor L3 conducts freewheeling, capacitor CV releases energy to the load. The energy of the spike voltage is absorbed and released to the load without loss and is all transferred to the load, with high efficiency.

[0039] Considering some abnormal states such as voltage backflow, the circuit can still work normally, and only when capacitor CV releases energy, it releases through QA to QD.

[0040] In this circuit structure, the volume of the components is relatively small, and it has great advantages in the application of high power density power supplies.

[0041] Its timing is completely determined by the voltage at the front end of inductor L3. As long as the voltage at the front end of L3 is high, the PMOS transistor is in the cut-off state, capacitor CV absorbs and clamps, storing the spike voltage energy. When the voltage at the front end of L3 becomes low, the PMOS transistor is in the conducting state, and capacitor CV releases energy to prepare for clamping in the next cycle. The timing is simple, efficient, and reliable.

[0042] It should be understood that in this embodiment, the active clamp circuit for clamping the secondary side synchronous rectification spike voltage mainly includes a freewheeling process.

[0043] Freewheeling process: QA~QD are turned on to short-circuit T1. Since the inductor current of L3 cannot change suddenly, freewheeling continues. The upper end of the CV capacitor is pulled down to 0V, and the lower end of C50 is pulled to a negative voltage and clamped to -0.7V by D22 to ensure that U8 is not damaged. The input signal of U8 becomes low level, and the output of U8 is low level. POMS is turned on, and the energy stored in the CV capacitor is released through PMOS, R2, L3, and the load to form a loop, preparing for the next rectification cycle. In addition, R5 and D8 are auxiliary bypasses to prevent the on-time of POMS from being too short when the freewheeling energy is very small, resulting in incomplete release of the CV energy. They can be selected and installed according to the situation.

[0044] The rectification process and the freewheeling process run alternately. The spike voltage generated by T1 is clamped, and at the same time, the energy of the spike voltage is finally released to the load end with less loss.

[0045] The above are only the preferred embodiments of the present invention, and do not limit the patent scope of the present invention accordingly. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present invention.

Claims

1. An active clamping circuit for secondary side synchronous rectification spike voltage clamping, characterized in that, It includes a full-bridge synchronous rectification circuit (101), a PMOS active clamping unit circuit (102), an active clamping drive and control unit circuit (103), and a synchronous rectification freewheeling inductor (104); The full-bridge synchronous rectification circuit (101) is connected to the secondary side of the transformer, and its output is connected to the PMOS active clamping unit circuit (102); The output of the PMOS active clamping unit circuit (102) is connected to the active clamping drive and control unit circuit (103); The positive output of the active clamping drive and control unit circuit (103) is connected to the synchronous rectification freewheeling inductor (104), and the negative output is grounded; Each of the four arms in the full-bridge synchronous rectification circuit (101) includes a field effect transistor (QA), a field effect transistor (QB), a field effect transistor (QC), and a field effect transistor (QD); The active clamping circuit for secondary side synchronous rectification spike voltage clamping includes a rectification absorption process and a freewheeling process; The rectification absorption process: During this process, after the spike voltage generated by the transformer (T1) is rectified by the field effect transistors (QA) to (QD), the current forms a loop through the capacitor (CV), resistor (R2), and PMOS transistor. At this time, the PMOS transistor is forward-conducted, the lower end of the capacitor (C50) is coupled to a high level, which is clamped by the diode (D22) to prevent damage to the driver (U8). The driver (U8) inputs a high-level signal, the driver (U8) outputs a high level, the PMOS transistor turns off, and the spike voltage energy is stored in the capacitor (CV) to achieve spike voltage clamping; The freewheeling process: The field effect transistors (QA) to (QD) are turned on to short-circuit the transformer (T1). Since the inductor current of the inductor (L3) cannot change suddenly, it continues to freewheel. The upper end of the capacitor (CV) is pulled down to 0V, and the lower end of the capacitor (C50) is pulled to a negative voltage and clamped to -0.7V by the diode (D22) to ensure that the driver (U8) is not damaged. The input signal of the driver (U8) becomes a low level, the driver (U8) outputs a low level, the PMOS transistor is turned on, and the energy stored in the capacitor (CV) is released through the PMOS transistor, resistor (R2), inductor (L3), and load to form a loop, preparing for the next rectification cycle.

2. The active clamping circuit for secondary side synchronous rectification spike voltage clamping according to claim 1, wherein The PMOS active clamping unit circuit (102) includes a capacitor (CV), a resistor (R2), a resistor (R5), a diode (D7), a diode (D8), and a PMOS transistor; the capacitor (CV), resistor (R2), and PMOS transistor are connected in series. By switching the on or off state of the PMOS transistor, the spike voltage existing at the drains of the field effect transistors (QA) to (QD) is clamped on the capacitor (CV).

3. The active clamping circuit for secondary side synchronous rectification spike voltage clamping according to claim 2, wherein The diode (D7), diode (D8), and resistor (R5) form an auxiliary clamping circuit and are connected in parallel with the resistor (R2) and PMOS transistor to assist the capacitor (CV), resistor (R2), and PMOS in clamping the spike voltage existing at the drains of the field effect transistors (QA) to (QD) on the capacitor (CV).

4. An active clamping circuit for sub-edge synchronous rectification spike voltage clamping according to claim 1, characterized in that, The active clamp drive and control unit circuit (103) includes a capacitor (C50), a diode (D9), a resistor (R20), a resistor (R68), a diode (D22), a resistor (R21), a resistor (R1), a capacitor (C104), a driver (U8), a capacitor (C47), a resistor (R67), and a diode (D6). By charging and discharging the capacitor (C50), the output voltage of the driver (U8) is changed to achieve the charge and discharge control of the circuit.

5. An active clamping circuit for secondary side synchronous rectification spike voltage clamping according to claim 4, characterized in that, The capacitor (C50) is connected in series with the resistor (R68) and the diode (D22); the resistor (R68) is connected in parallel with the diode (D9) and the resistor (R20); the resistor (R21) is connected in parallel with the diode (D22); one end of the positive input terminal of the driver (U8) is connected between the resistor (R68) and the diode (D22), and the other end is grounded. The positive output terminal is connected to the PMOS transistor; the diode (D6) and the resistor (R67) are connected in parallel and connected between the driver (U8) and the PMOS transistor; the capacitor (C47) is connected in series between the driver (U8) and the PMOS transistor; the resistor (R1) is connected to the enable terminal of the driver (U8) and the positive input terminal of the driver (U8); the capacitor (C104) is connected to the enable terminal of the driver (U8) and the ground terminal.

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