Method and device for allocating registers, compilation method and device, and electronic device

Abstract

The present application provides a method and apparatus for allocating registers, a compiling method and apparatus, and an electronic device. The electronic device may include: one or more processing units; a storage unit for storing one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors implement the register allocation method or compiling method according to the embodiment of the present application.

Description

Technical Field

[0001] The present application relates to the field of computing technology, and in particular, to a method and device for allocating registers, a compiling method and device, an electronic device, and a computer-readable medium. Background Art

[0002] In chip architecture, there are generally multiple registers, such as scalar registers and vector registers. When compiling code for a chip of a certain architecture, one of the tasks that needs to be completed is register allocation. Register allocation is a method of increasing program execution speed by allocating program virtual registers to registers as much as possible. Register allocation is one of the most important issues in compiler optimization. Good register allocation can greatly increase program execution speed (more than 250%).

[0003] The above information disclosed in the Background section is only for enhancement of understanding of the background of the present application and therefore it may contain information that does not constitute the prior art that is already known to a person of ordinary skill in the art. Summary of the invention

[0004] The present application aims to provide a method and device for allocating registers, a compiling method and device, and an electronic device, which can improve code execution performance.

[0005] The user features and advantages of the present application will become apparent from the following detailed description, or may be learned in part from the practice of the present application.

[0006] According to one aspect of the present application, a method for allocating registers is provided, comprising: allocating a first type of register to a first type of virtual register; after the allocation of the first type of register is completed, allocating a second type of register to a second type of virtual register, wherein when allocating the second type of register, if the second type of virtual register overflows, first selecting an available first type of register for overflow, wherein the width of the first type of register is greater than the width of the second type of register.

[0007] According to another aspect of the present application, a compilation method is provided, comprising: establishing a virtual register survival range, wherein the virtual register survival range includes a survival range of a first type of virtual register and a survival range of a second type of virtual register; and allocating first type registers and second type registers based on the virtual register survival range using the aforementioned register allocation method.

[0008] According to another aspect of the present application, an electronic device is provided, comprising: one or more processing units; a storage unit for storing one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors implement the aforementioned method.

[0009] According to another aspect of the present application, a computer-readable medium is provided, on which a computer program is stored, and when the program is executed by a processor, the aforementioned method is implemented.

[0010] According to the embodiment of the present application, the allocation of different registers has a certain degree of independence, so that the same set of core algorithms can be applied to different registers. At the same time, the allocation of different registers has a certain order of precedence, for example, after the allocation of vector registers, the allocation of scalar registers is performed, so that the allocation result of the vector registers can be obtained. When the scalar register needs to overflow, a safe strategy is selected, such as selecting a vector register to overflow the scalar register without causing the overflow of the vector register. In this way, since various registers are fully utilized, the code performance can be effectively improved and the program execution speed can be improved.

[0011] It should be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other objects, features and advantages of the present application will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

[0013] Figure 1A Shows an example of how a graph coloring algorithm allocates registers.

[0014] Figure 1B An example of allocating registers for a linear scan algorithm is shown.

[0015] Figure 2 A method of allocating registers according to an exemplary embodiment of the present application is shown.

[0016] Figure 3 A method of allocating registers according to another exemplary embodiment of the present application is shown.

[0017] Figure 4 The compiling method according to an exemplary embodiment of the present application is shown.

[0018] Figure 5 A method for establishing a virtual register survival range according to an exemplary embodiment of the present application is shown.

[0019] Figure 6 A register allocation device according to an exemplary embodiment of the present application is shown.

[0020] Figure 7 A compiling device according to an exemplary embodiment of the present application is shown.

[0021] Figure 8 A block diagram of an electronic device according to an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0022] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this application will be comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0023] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0024] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0025] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0026] The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0027] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0028] Before describing the embodiments of the present application, some terms involved in the embodiments of the present application are explained.

[0029] Compilation: Compilation is the conversion of intermediate representation (IR) into another IR. Compilation is divided into front-end, middle-end and back-end. The target code obtained by the back-end is closely related to the target architecture.

[0030] Scalar register: A register used to perform scalar calculations.

[0031] Vector register: A register used for special purposes, generally wider than a scalar register, and can be viewed as consisting of a fixed number of scalar registers.

[0032] Physical registers: Registers that actually exist in the target architecture, which can include scalar registers and vector registers.

[0033] Intermediate representation (IR): A compiler is usually organized as a series of processing passes. As the compiler continues to deduce knowledge about the compiled code, this information must be passed from one pass to another. Therefore, to deduce all the facts about the program, the compiler needs a representation, which is called an intermediate representation, or IR for short. IR can include pseudo-instructions. IR is divided into multiple layers. Higher-level (more abstract) IR may not have the concept of virtual registers, only the concept of variables; while lower-level (more concrete, closer to the target machine) IR may not have the concept of variables, only the concept of virtual and physical registers.

[0034] Virtual register: A number of operands in the source file during the compilation process. In the process of converting from a higher-level IR to a lower-level IR, the concept of "variable" will be mapped to the concept of "virtual register". Therefore, in this application, virtual registers and variables can be used interchangeably and have the same meaning. Those skilled in the art can understand their use according to the context. There can be an unlimited number of "virtual registers", but they will eventually be mapped to a limited number of physical registers on the target machine.

[0035] Register allocation: The process of mapping virtual registers to physical registers. When compiling code for a processor of a certain architecture, register allocation is a method to improve the program execution speed by allocating virtual registers to registers (physical registers) as much as possible, that is, making as many variables reside in registers. The register allocation process can be understood as establishing a one-to-many mapping relationship between virtual registers and physical registers. Register allocation is one of the most important tasks in compilation, and good register allocation can greatly improve the program execution speed.

[0036] Spill: When performing register allocation, if the number of physical registers is insufficient, the value in the current register is placed in another address space (usually the stack) and retrieved from the other address space when needed. Generally, spilling to the stack is relatively slow, and moving between different registers is faster. A simple spill algorithm is as follows: For a variable in a selected live range to be spilled, insert a store instruction after each definition of the variable and a load instruction before each use of the variable. Obviously, this algorithm will insert a large number of redundant store and load instructions.

[0037] Program point: In the IR representation, the position points on both sides of an instruction are called program points, which can be represented and distinguished by numbers.

[0038] Live range: Assume that the instructions in the IR are numbered in order (for example, the order in which pseudo-instructions appear in the intermediate representation), sometimes also called program point numbers. If the live range of variable v is the interval [i, j], it means that there is no instruction numbered j1 (j1 > j) such that variable v is active at j1, and there is no instruction numbered i1 (i1 < i) such that variable v is active at i1. The technical solution of this application is not limited to the traditional sense of live range, and can also be applied to the concept of live range in a strict sense or an optimized sense, such as the set of live ranges. A live range is the set of all program points when a variable is strictly active.

[0039] Data flow analysis: Data flow analysis is a compile-time technique that collects program semantic information from program code and determines the definition and use (def-use) of variables at compile time through algebraic methods. Data flow analysis can be used to obtain variable survival information, that is, which variables are "surviving" at a given program point. The survival information gives clues to the survival range, so that the survival range of variables can be easily established by scanning the program points of the intermediate representation. Through data flow analysis, the behavior of the program at runtime can be discovered without actually running the program, which can help everyone understand the program. Data flow analysis is used to solve problems such as compilation optimization, program verification, debugging, testing, parallelization, vectorization, and chip programming environment.

[0040] Graph coloring algorithm: The register allocation problem is abstracted into a graph coloring problem. Each node in the graph represents the life cycle of a variable. The life cycle starts from the first time the variable is defined (assigned) to the last time it is used before the next assignment. The edge between two nodes indicates that the survival intervals of the two variables conflict or interfere with each other because of overlap. Generally speaking, if two variables survive at a certain point in the function at the same time, they conflict with each other and cannot occupy the same register. In order to use the graph coloring algorithm, a conflict graph must be constructed. The nodes in the graph represent the survival intervals and the edges represent the conflict relationships. If there is no edge connecting two nodes, they can be assigned to the same register. Figure 1A It is shown that 4 registers (r0-r3) are allocated for 6 variables (af) without causing conflicts.

[0041] Linear scan algorithm: The linear scan algorithm allocates registers based on the survival interval of the variable. The linear scan algorithm stores all variables in the order of the starting point of the variable survival interval, and stores the variables that are currently allocated (occupied) registers in the order of the end point of the variable survival interval. The number of overlapping variable intervals only changes when encountering the start and end points of a variable survival interval, so when a new variable survival interval appears, consider how to allocate registers for it. When the end point of a variable survival interval is earlier than the start point of another variable survival interval, the registers allocated to this variable can be released and reallocated to another variable. Figure 1BAn example of allocating 2 registers to the survival intervals of 5 variables is shown, where AE represents variables, the horizontal line to the right of the variable represents the survival interval, and the numbers 1-5 represent the steps of allocating registers by the linear scan algorithm. As can be seen from the figure, in step 1, a register is allocated to the survival interval of variable A. In step 2, a register is allocated to the survival interval of variable B, and at this time, the two survival intervals of variables A and B are allocated with registers. In step 3, since there are no registers available for allocation, variable C overflows. In step 4, since the register allocated to A can be released, the register is reallocated to the survival interval of variable D, and at this time, the two survival intervals of variables D and B are allocated with registers. In step 5, since the register allocated to B can be released, the register is reallocated to the survival interval of variable E, and at this time, the two survival intervals of variables D and E are allocated with registers.

[0042] The technical solution of this application is described in detail below.

[0043] For a multi-register architecture, such as a computing architecture including both vector registers and scalar registers, there are two common register allocation methods. The first is to allocate various registers separately, and the second is to allocate various registers in a mixed manner.

[0044] The first method is simpler to implement. It uses the similarity of different register allocation processes and can be extended to all architectures. Taking the architecture that includes scalar registers and vector registers as an example, the main idea of ​​the first method is to treat all types of registers as scalar registers based on the similarity of different register allocation processes, and only treat them specially when some special treatment is required.

[0045] The second method can generate higher performance code and require shorter compilation time in some architectures than the first method. Still taking the architecture including scalar registers and vector registers as an example, this method treats vector registers as scalar registers before overflow occurs, and uses the same method to allocate them inside each register. Once overflow occurs, the virtual scalar register will be overflowed to the stack, and the virtual vector register will overflow to the scalar register first. The overflow code is inserted, and a new virtual scalar register is introduced to be allocated. The whole process constitutes a loop until there are no more virtual registers to be allocated in the queue.

[0046] The first approach does not take into account the characteristics of the architecture, so it will produce relatively low-performance code. For example, when the vector registers are insufficient, it usually overflows directly to the memory, which is much slower than overflowing to the scalar register first and then considering whether to overflow to the memory.

[0047] The second method allocates various registers together in a mixed manner, taking into account the characteristics of the architecture, and can generate better code than the first method in the above-mentioned situation. However, the inventors have found that in some cases, such as when the resources of vector registers are not particularly tight, or when they are not particularly tight at certain moments, this method still only considers the overflow of vector registers to scalar registers, and does not notice that the overflow of scalar registers to vector registers may also improve performance.

[0048] Based on this, the present application proposes a register allocation framework for a compilation process and a compilation method, which can reduce the compilation time of register allocation and improve the performance of compiled generated code.

[0049] The register allocation method and the compilation method according to the embodiments of the present application are described in detail below.

[0050] Figure 2 The method for allocating registers according to an exemplary embodiment of the present application is shown. The method according to this embodiment can be used for allocating registers of different widths, for example, for allocating vector registers and scalar registers. The method according to this embodiment can be used for register allocation during source program compilation.

[0051] See also Figure 2 At S201, the method for allocating registers according to the exemplary embodiment of the present application includes allocating first-type registers for first-type virtual registers.

[0052] In an example embodiment, according to the actual computing architecture, it is necessary to allocate multiple registers of different widths, such as first-type registers and second-type registers, where the width of the first-type registers is greater than the width of the second-type registers. For example, the first-type registers may be 512-bit wide vector registers, and the second-type registers may be 48-bit wide scalar registers.

[0053] According to an exemplary embodiment, survival information of the first type of virtual registers is obtained by, for example, data flow analysis, that is, which variables are "surviving" at a given program point. The survival information provides clues to the survival range. Then, the survival range of the first type of virtual registers can be easily established by scanning the intermediate representation of the source file. Based on the established survival range of the first type of virtual registers, the first type of registers can be allocated by, for example, a linear scanning algorithm. According to other embodiments, the first type of registers can also be allocated by other algorithms such as a graph coloring algorithm. It is easy to understand that here, the first type of virtual register and the first type of register correspond to the same variable type.

[0054] See also Figure 2In S203, after the allocation of the first type of registers is completed, the second type of registers are allocated to the second type of virtual registers.

[0055] According to an example embodiment, similar to the allocation of the first type register, based on the established survival interval of the second type virtual register, the second type register can be allocated by, for example, a linear scan algorithm. According to other embodiments, the second type register can also be allocated by other algorithms such as a graph coloring algorithm. It is easy to understand that here, the second type virtual register and the second type register correspond to the same variable type.

[0056] The survival range of the second type virtual register can be established in a similar manner to the survival range of the second type virtual register. Optionally, the survival range of the first type virtual register and the survival range of the second type virtual register can use the same representation logic and be obtained by scanning the intermediate representation once, thereby reducing register allocation time, as described in detail in the following embodiments.

[0057] See also Figure 2 In S205, it is determined whether the second type virtual register overflows. If overflow occurs, the process proceeds to S207; otherwise, other subsequent processing may be performed, such as performing other register allocation or performing code optimization processing based on the register allocation result.

[0058] See also Figure 2 In step S207, when allocating the second type register, if the second type virtual register overflows, the available first type register is first selected for overflow. In this way, the operation efficiency of the compiled code can be improved by multiplexing the first type register to avoid overflow to the memory, such as the stack space.

[0059] According to this embodiment, the allocation of different registers has a certain degree of independence, so that the same set of core algorithms can be applied to different registers. At the same time, the allocation of different registers has a certain order, that is, hierarchical allocation. For example, after allocating the vector registers, the scalar registers are allocated, so that the allocation results of the vector registers can be obtained. When the scalar register needs to overflow, a safe strategy is selected, such as selecting a vector register to overflow the scalar register without causing the overflow of the vector register. In this way, since various registers are fully utilized, the code performance can be effectively improved and the program execution speed can be improved.

[0060] Figure 3 A method of allocating registers according to another exemplary embodiment of the present application is shown.

[0061] Figure 3 The method shown is similar to Figure 2 The methods shown are basically similar, except that Figure 3 It also shows the situation where the first type register overflows and the situation where the second type register overflows to the stack space. Therefore, the detailed description of the same or similar steps will be omitted here.

[0062] See also Figure 3 , at S301, first type registers are allocated.

[0063] In S302A, if the first type register overflows, go to S302B; otherwise, go to S303.

[0064] At S302B, overflow to the second type register.

[0065] In S303, after the allocation of the first type of registers is completed, the allocation of the second type of registers is performed.

[0066] In S305, it is determined whether the second type virtual register overflows. If overflow occurs, the process goes to S306; otherwise, other subsequent processing may be performed, such as performing other register allocation or performing code optimization processing based on the register allocation result.

[0067] In S306, it is determined whether there is an available first type register. If there is an available first type register, the process proceeds to S307; otherwise, the process proceeds to S309.

[0068] In S307, the available first type register is selected for overflow. In this way, the first type register is reused to avoid overflow to the memory, such as the stack space, so that the running efficiency of the compiled code can be improved.

[0069] At S309 , when there is no available first type register, overflow is performed to the stack space.

[0070] According to this embodiment, once an overflow occurs, the vector register will first overflow to the scalar register, and the scalar register will overflow to the stack when there is no available vector register. In this way, the vector register will first overflow to the scalar register instead of directly overflowing to the memory, which can improve the execution efficiency of the code.

[0071] Figure 4 The compiling method according to the exemplary embodiment of the present application is shown. The aforementioned register allocation method can be used in the compiling method.

[0072] As described above, during the compilation process, according to the actual computing architecture, it is necessary to allocate multiple registers of different widths, such as first type registers and second type registers, where the width of the first type registers is greater than the width of the second type registers.

[0073] See also Figure 4Before allocating registers, at S401, a virtual register survival range is established. The virtual register survival range may include a unified survival range of a first type virtual register and a survival range of a second type virtual register.

[0074] According to some embodiments, after obtaining the survival information of the first and second type virtual registers by using, for example, data flow analysis, the survival ranges of the first and second type virtual registers may be easily established by scanning the intermediate representation of the source file once.

[0075] See also Figure 4 At S403, based on the established virtual register survival range, the first type register and the second type register are allocated using the aforementioned register allocation method according to the embodiment of the present application. For the sake of brevity, the aforementioned register allocation method is not repeatedly described here.

[0076] According to some embodiments, see Figure 4 S405 may also include performing code optimization based on the register allocation result, including but not limited to eliminating unnecessary move instructions.

[0077] According to some embodiments, see Figure 4 , S407 may also include rewriting the code based on the allocation result and the optimized code, including rewriting registers and inserting overflow codes, etc. For example, according to the allocation result of the first type register and the second type register, rewrite the corresponding first type virtual register and second type virtual register. In addition, the code rewriting may also include inserting corresponding overflow codes at the first type overflow point and the second type overflow point as described later. Those skilled in the art should be familiar with register rewriting and inserting overflow codes, which will not be described here.

[0078] As described above, according to the compilation method of this embodiment, the allocation of different registers has a certain order, for example, after the vector register is allocated, the scalar register is allocated, so that the allocation result of the vector register can be obtained. When the scalar register needs to overflow, a safe strategy is selected, such as selecting a vector register to overflow the scalar register without causing the overflow of the vector register. In this way, since various registers are fully utilized, the performance of the compiled code can be effectively improved and the program execution speed can be improved.

[0079] Figure 5 A method for establishing a virtual register survival range according to an exemplary embodiment of the present application is shown. Figure 5 The method shown can be used to Figure 4 The compilation method shown.

[0080] See also Figure 5At S501, an intermediate representation of a source file is obtained, wherein the intermediate representation includes a first type virtual register, a second type virtual register, and instructions acting on the first type virtual register and the second type virtual register.

[0081] In S503, increasing or decreasing program point numbers are uniformly established for the instructions in sequence.

[0082] According to an example embodiment, a unified program point number is established for instructions acting on the first type virtual register and the second type virtual register, so that the survival interval can be established using the same representation logic later. According to an example embodiment, for example, the program point number is uniformly established to increase or decrease according to the order in which the pseudo instructions appear in the intermediate representation, but the present application is not limited thereto.

[0083] According to some embodiments, the program point numbering may be established as n*m P , n is the serial number of the program point, m and P are predetermined natural numbers greater than 1.

[0084] For example, in the following intermediate representation, m is 2, P is 2, and the program point number is a multiple of 4 (2 to the power of 2).

[0085] (28)r1=1 (32)

[0086] (20)r2=2 (24)

[0087] (12)v2=f(r1,r2) (16)

[0088] (4) v1 = v2 + v1 (8)

[0089] r1 and r2 are second-type virtual registers (eg, virtual scalar registers), v2 is a first-type virtual register (eg, virtual vector register), and f is a function, indicating that the left side is generated by calculation using the two virtual registers on the right side.

[0090] At S505, the program point number is used to indicate the survival range of the first type virtual register and the survival range of the second type virtual register.

[0091] According to some embodiments, after obtaining the liveness information of the first and second types of virtual registers by using, for example, data flow analysis, the liveness intervals of the first and second types of virtual registers can be easily represented by program point numbers, for example, by scanning the intermediate representation of the source file once. For example, assuming that the instructions in the IR are numbered in order (e.g., the order in which the pseudo-instructions appear in the IR), that is, the program point numbers, by traversing the program point numbers of the IR, the liveness interval [i, j] of variable v can be obtained, that is: there is no instruction numbered j1 (j1 > j) such that variable v is live at j1, and there is no instruction numbered i1 (i1 < i) such that variable v is live at i1.

[0092] For example, in the previous example, r1 starts to be live at program point number 28 and is no longer live at the next program point number 12 of program point number 16. Therefore, the liveness interval of r1 is [28, 16]. Similarly, the liveness interval of r2 is [20, 16], and the liveness interval of v2 is [12, 8].

[0093] In S507, when an overflow occurs in the first type of virtual register or the second type of virtual register, the liveness interval of the virtual register is updated.

[0094] According to some embodiments, during the process of allocating the first type of register and the second type of register, if an overflow occurs in the first type of virtual register, a first type of overflow interval is inserted at the corresponding first type of overflow point to be used for adding a first type of overflow pseudo-instruction and the second type of virtual register, and a first type of overflow point number is established for the first type of overflow interval.

[0095] For example, according to some embodiments, the first type of overflow point number differs from the adjacent previous program point number by m K , where K is a predetermined integer less than P.

[0096] For example, in the following intermediate representation, K is taken as 1, and the first type of overflow point number differs from the adjacent previous program point number by 2 1 , that is, the first type of overflow point number is 2 1 times a multiple but not a multiple of 2 2 times.

[0097] (28) r1 = 1 (32)

[0098] (20) r2 = 2 (24)

[0099] (12) v2 = f(r1, r2) (16)

[0100] (10) r3, r4 = spill(v1) (10)

[0101] (4) v1 = v2 + v1 (8)

[0102] r3 and r4 are added second type virtual registers (eg, virtual scalar registers), and spill(v1) is a first type overflow pseudo instruction.

[0103] Thus, according to the exemplary embodiment, when it is necessary to analyze the allocation of multiple registers, it is not desirable to regenerate the survival interval for each register, so a strategy similar to incremental modification is adopted. Based on the current analysis results, the partially affected survival interval is locally modified instead of re-establishing the survival interval. When the exponential interval form is used, the original survival interval does not need to be changed when simulating the insertion of overflow code.

[0104] For example, according to the hierarchical allocation algorithm of registers, when the first level of allocation finds that the vector registers are insufficient, they are overflowed to the scalar registers (in actual operation, the pseudo-instruction spill is not inserted at the current stage, but the overflow intervals for r3 and r4 are symbolically inserted, and enter the second level of scalar register allocation together with the survival intervals of r1 and r2). Since the difference between every two program points is 4, it is considered that the instruction spill is inserted at a program point such as 10 that is a multiple of 2 but not a multiple of 4. It can be seen that the generation of such survival intervals will not change the original survival intervals such as r1 and r2, because the positions with specific attributes have been "reserved".

[0105] According to the example embodiment, the survival interval of the new virtual scalar register generated by the overflow of the vector register to the scalar register does not need to be further calculated, and can be directly obtained through the life cycle of the original vector register (for example, equal to the survival interval of the original virtual vector register; or the set of the original virtual vector register overflow interval and adjacent program points, etc., which can be adjusted or optimized according to actual conditions and specific algorithms by those skilled in the art), so that the same processing mode as the original scalar register can be adopted for the mode of vector register overflow to the scalar register.

[0106] According to some embodiments, when the second type virtual register overflows, a second type overflow interval is inserted at the corresponding second type overflow point for adding a second type overflow pseudo instruction, and a second type overflow point number is established for the second type overflow interval, and the second type overflow point number differs from the previous adjacent program point number or the first type overflow point number by m. Q , Q is a predetermined integer less than K.

[0107] For example, in the following intermediate representation, Q is 0, and the second type overflow point number differs from the first type overflow point number by 2. 0 , that is, the second type of overflow point number is 2 0 A multiple of but not 21 multiples of.

[0108] (28)r1=1 (32)

[0109] (20)r2=2 (24)

[0110] (12)v2=f(r1,r2) (16)

[0111] (10)r3,r4=spill(v1) (10)

[0112] (9)ram3,ram4=spill(r3,r4) (9)

[0113] (4) v1 = v2 + v1 (8)

[0114] R3 and r4 are added second type virtual registers (eg, virtual scalar registers), and spill(r3, r4) is a second type overflow pseudo instruction.

[0115] In the example, according to the hierarchical allocation algorithm of registers, when allocating scalar registers in the second layer, each line (including the overflow line) is regarded as the original code (of course, in fact, spill is not actually inserted in the first layer allocation, here, the survival intervals corresponding to all program points that are divisible by 2 but not by 4 are treated as real scalar intervals for register allocation analysis except those that have been analyzed), and no actual code is inserted in case of "overflow", but only the overflow interval of the scalar register is generated.

[0116] According to the embodiments of the present application described above, a uniform increasing or decreasing program point number is established for the instructions in the intermediate representation. For example, the program point is represented as a multiple of 4, the vector register overflow point is a multiple of 2 but not a multiple of 4, and the scalar register overflow point is an odd number. Different types of registers can be compatible, so that the entire process of establishing the variable's survival range can use the same representation logic.

[0117] According to the example embodiment, in the process of establishing the survival interval, no storage and loading code is inserted at the overflow point, so fine-tuning and optimization can be performed after the analysis is completed.

[0118] According to some embodiments, during the register allocation process, if a first-type virtual register overflows, after inserting a first-type overflow interval at a corresponding first-type overflow point to add a first-type overflow pseudo instruction and a second-type virtual register, the survival interval of the added second-type virtual register can be directly obtained using the survival interval of the original first-type virtual register. Therefore, the interval of the scalar generated by the overflow can be given without additional analysis.

[0119] For example, for the added second type virtual registers r3 and r4, the survival interval [12,8] of the original first type virtual register v2 can be directly used to determine the survival interval of r3 and r4 to be, for example, [12,8]. Of course, it can also be adjusted or optimized according to the actual situation and specific algorithm, which will not be repeated here.

[0120] According to an exemplary embodiment, when allocating the second type register, the second type register is also allocated for the survival range [12, 8] of the added second type virtual register.

[0121] In an example embodiment, when a scalar register overflows, an overflow interval of the scalar register is generated. Then, the survival interval of the allocated vector register can be combined for analysis, and the idle vector register can be used for overflow without conflicting with the survival interval of the allocated vector register, thereby improving the performance of the compiled code. If the survival interval unified representation logic compatible with multiple registers according to the present application is not adopted, it will be necessary to perform a very expensive data flow analysis again to recalculate the survival interval.

[0122] Thus, according to the exemplary embodiment, the allocation of vector registers and scalar registers will not be mixed, but a set of survival interval representation logic can be used together. For example, as a distinction, during analysis, program points that are divisible by 4 are real program points; points that are divisible by 2 but not by 4 are virtual program points of vector registers (overflow points generated by virtual vector register overflow); odd program points (for example, as in the previous example, points that are divisible by 2 but not by 4) are virtual program points of vector registers (overflow points generated by virtual vector register overflow); 0 Divisible but not by 2 1 The program point that is divisible by an integer is a virtual program point of the scalar register (a program point generated by a virtual scalar register overflow). In this way, the corresponding overflow interval analysis can be performed through the overflow point represented specifically, and the insertion position of the overflow code can be recorded.

[0123] According to an exemplary embodiment, program point numbers are integrated into commonly used survival interval analysis to form a unified survival interval representation method. This survival interval representation method combined with the analysis process can reduce compilation time and generate higher quality target code.

[0124] The above mainly introduces the embodiments of the present application from the perspective of the method. Those skilled in the art should easily appreciate that, in combination with the operations or steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Those skilled in the art can use different ways to implement the described functions for each specific operation or method, and such implementation should not be considered to be beyond the scope of the present application.

[0125] The following describes the device embodiments of the present application. For details not disclosed in the device embodiments of the present application, reference can be made to the method embodiments of the present application.

[0126] Figure 6 The register allocation device according to an exemplary embodiment of the present application is shown. The device can be used to execute the above register allocation method.

[0127] like Figure 6 As shown, the register allocation device 600 according to the exemplary embodiment includes a first allocation module 601 and a second allocation module 603. The second allocation module 603 includes a first overflow processing module 6031.

[0128] See also Figure 6 With reference to the above description, the first allocation module 601 is used to allocate first-type registers to first-type virtual registers.

[0129] The second allocation module 603 is used to allocate second type registers to second type virtual registers after the allocation of the first type registers is completed. The width of the first type registers is greater than the width of the second type registers.

[0130] The first overflow processing module 6031 of the second allocation module 603 is used for selecting overflow to the first type of register when overflow occurs in the second type of virtual register.

[0131] The register allocation device according to this embodiment can perform functions similar to those of the method provided above. For other functions, reference can be made to the above description and will not be repeated here.

[0132] Figure 7 A compiling device according to an exemplary embodiment of the present application is shown. The device can be used to execute the above-mentioned compiling method.

[0133] like Figure 7 As shown, the compiling device 700 according to the exemplary embodiment includes a survival interval establishing module 701 , a register allocating device 703 , an optimizing module 705 , and a rewriting module 707 .

[0134] See also Figure 7 Referring to the above description, the survival interval establishment module 701 is used to establish a virtual register survival interval. The virtual register survival interval includes a survival interval of a first type virtual register and a survival interval of a second type virtual register.

[0135] The register allocation device 703 may be the register allocation device described above, and is used to allocate the first type registers and the second type registers based on the virtual register survival range.

[0136] The optimization module 705 performs code optimization based on the allocation results of the first type registers and the second type registers.

[0137] The rewriting module 707 performs code rewriting based on the allocation result and the optimized code.

[0138] The compiling device according to this embodiment can perform functions similar to those of the method provided above. For other functions, reference can be made to the above description and will not be repeated here.

[0139] Figure 8 A block diagram of an electronic device according to an exemplary embodiment of the present application is shown.

[0140] Refer to the following Figure 8 The electronic device 200 according to this embodiment of the present application is described. Figure 8 The electronic device 200 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0141] like Figure 8 As shown, the electronic device 200 is in the form of a general computing device. The components of the electronic device 200 may include, but are not limited to: at least one processing unit 210, at least one storage unit 220, a bus 230 connecting different system components (including the storage unit 220 and the processing unit 210), a display unit 240, etc.

[0142] The storage unit 220 stores program codes, and the program codes can be executed by the processing unit 210, so that the processing unit 210 executes the methods described in this specification according to various embodiments of the present application.

[0143] The storage unit 220 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 2201 and / or a cache memory unit 2202 , and may further include a read-only memory unit (ROM) 2203 .

[0144] The storage unit 220 may also include a program / utility 2204 having a set (at least one) of program modules 2205, such program modules 2205 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0145] Bus 230 may represent one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0146] The electronic device 200 may also communicate with one or more external devices 300 (e.g., keyboards, pointing devices, Bluetooth devices, etc.), may also communicate with one or more devices that enable a user to interact with the electronic device 200, and / or communicate with any device that enables the electronic device 200 to communicate with one or more other computing devices (e.g., routers, modems, etc.). Such communication may be performed via an input / output (I / O) interface 250. Furthermore, the electronic device 200 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 260. The network adapter 260 may communicate with other modules of the electronic device 200 via the bus 230. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 200, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0147] The present application also provides a computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, the steps of the above method are implemented.

[0148] The embodiment of the present application also provides a computer program product, which can be operated to enable a computer to execute some or all of the steps recorded in the above method embodiment.

[0149] Those skilled in the art can clearly understand that the technical solution of the present application can be implemented with the help of software and / or hardware. The "unit" and "module" in this specification refer to software and / or hardware that can independently complete or cooperate with other components to complete specific functions, where the hardware can be, for example, a field programmable gate array (FPGA), an integrated circuit (IC), etc.

[0150] It should be noted that, for the sake of simplicity of description, the aforementioned method embodiments are all expressed as a series of action combinations, but those skilled in the art should know that the present application is not limited to the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously.

[0151] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0152] The embodiments of the present application are described and explained in detail above. It should be clearly understood that the present application describes how to form and use specific examples, but the present application is not limited to any details of these examples. On the contrary, based on the teaching of the contents disclosed in the present application, these principles can be applied to many other embodiments.

[0153] Through the description of the example embodiments, it is easy for those skilled in the art to understand that the register allocation method and the compilation method according to the embodiments of the present application have at least one or more of the following advantages.

[0154] According to the embodiment of the present application, the allocation of different registers has a certain degree of independence, so that the same set of core algorithms can be applied to different registers. At the same time, the allocation of different registers has a certain order of precedence, for example, after the allocation of vector registers, the allocation of scalar registers is performed, so that the allocation result of the vector registers can be obtained. When the scalar register needs to overflow, a safe strategy is selected, such as selecting a vector register to overflow the scalar register without causing the overflow of the vector register. In this way, since various registers are fully utilized, the code performance can be effectively improved and the program execution speed can be improved.

[0155] According to some embodiments, by reducing unnecessary data flow analysis and avoiding the introduction of overly complex dependencies (complex dependencies may even lead to non-convergence), the compilation time can be reduced. In addition, the performance of the compiled generated code can be improved by appropriately overflowing between different registers.

[0156] According to some embodiments, uniformly establishing increasing or decreasing program point numbers for instructions in the intermediate representation can be compatible with different types of registers, so that the entire establishment process of the variable's survival range can use the same representation logic.

[0157] According to some embodiments, during the process of establishing the survival interval, no storage or loading code is inserted at the overflow point, so fine-tuning and optimization can be performed after the analysis is completed.

[0158] According to some embodiments, if a first type virtual register overflows, after a first type overflow interval is inserted at a corresponding first type overflow point to add a first type overflow pseudo instruction and a second type virtual register, the survival interval of the added second type virtual register is directly obtained using the survival interval of the original first type virtual register, thereby improving compilation efficiency.

[0159] According to some embodiments, the survival interval of the new virtual scalar register generated by the overflow of the vector register to the scalar register does not need to be further calculated, and can be directly obtained through the survival cycle of the original vector register, so that the same processing mode as the original scalar register can be used for the mode of vector register overflow to the scalar register. Similar intervals can also be generated when the scalar register overflows, so as to analyze the survival interval of the allocated vector register in combination, and overflow is performed using the idle vector register without conflicting with the survival interval of the allocated vector register. If the survival interval unified representation logic compatible with multiple registers according to the present application is not adopted, it will be necessary to perform a very costly data flow analysis again to recalculate the survival interval.

[0160] According to some embodiments, the allocation of vector registers and scalar registers will not be mixed, but a set of survival interval representation logic can be used together. In this way, the insertion position of the overflow code can be recorded through the overflow point of the specific representation.

[0161] According to an exemplary embodiment, program point numbers are integrated into commonly used survival interval analysis to form a unified survival interval representation method. This survival interval representation method combined with the analysis process can reduce compilation time and generate higher quality target code.

[0162] The foregoing content can be better understood in accordance with the following terms:

[0163] Clause 1. A method for allocating registers, characterized in that the method comprises:

[0164] Allocating first type registers for first type virtual registers;

[0165] After the allocation of the first type of registers is completed, the second type of registers are allocated to the second type of virtual registers,

[0166] When allocating the second type register, if the second type virtual register overflows, the available first type register is first selected for overflow, wherein the width of the first type register is greater than the width of the second type register.

[0167] Clause 2. The method according to clause 1, wherein the allocating the second type register further comprises:

[0168] When the second-type virtual register overflows, if there is no available first-type register, the register overflows to the stack space.

[0169] Clause 3. The method according to clause 1 is characterized in that when allocating the first type of register, if the first type of virtual register overflows, the overflow is selected to overflow to the second type of register.

[0170] Clause 4. The method according to clause 1, characterized in that:

[0171] The allocating of the first type registers includes:

[0172] Allocating first-type registers based on the survival intervals of the first-type virtual registers; and

[0173] The allocating of the second type registers comprises:

[0174] The second type of registers are allocated based on the survival range of the first type of virtual registers and the survival range of the second type of virtual registers.

[0175] Clause 5. The method according to Clause 4, characterized in that the survival range of the first type virtual register and the survival range of the second type virtual register use the same representation logic.

[0176] Clause 6. The method of clause 1, wherein the first type of register comprises a vector register and the second type of register comprises a scalar register.

[0177] Clause 7. A method for compiling, characterized in that the method comprises:

[0178] Establishing a virtual register survival range, wherein the virtual register survival range includes a survival range of a first type of virtual register and a survival range of a second type of virtual register;

[0179] Based on the virtual register survival range, the first type register and the second type register are allocated using the method for allocating registers according to any one of clauses 1 to 6.

[0180] Clause 8. The method according to clause 7, wherein establishing the virtual register survival range comprises:

[0181] Obtaining an intermediate representation of a source file, the intermediate representation comprising a first type virtual register, a second type virtual register, and instructions acting on the first type virtual register and the second type virtual register;

[0182] Uniformly establish increasing or decreasing program point numbers for the instructions in sequence;

[0183] Using the program point number to indicate the survival range of the first type virtual register and the survival range of the second type virtual register;

[0184] When the first type virtual register or the second type virtual register overflows, the virtual register survival range is updated.

[0185] Clause 9. The method according to clause 8, characterized in that

[0186] The step of uniformly establishing increasing or decreasing program point numbers for the instructions in sequence includes:

[0187] Establish a program point number for the instruction, the program point number is n*m P , n is the serial number of the program point, m and P are predetermined natural numbers greater than 1;

[0188] The updating of the virtual register survival interval includes: when the first type virtual register overflows, inserting a first type overflow interval at a corresponding first type overflow point for adding a first type overflow pseudo instruction and a second type virtual register, and establishing a first type overflow point number for the first type overflow interval, wherein the first type overflow point number differs from a previous adjacent program point number by m K , K is a predetermined integer less than P;

[0189] When the second-type virtual register overflows, a second-type overflow interval is inserted at the corresponding second-type overflow point for adding a second-type overflow pseudo instruction, and a second-type overflow point number is established for the second-type overflow interval, and the second-type overflow point number differs from the previous adjacent program point number or the first-type overflow point number by m. Q , Q is a predetermined integer less than K.

[0190] Clause 10. The method according to clause 9, wherein establishing the virtual register survival range further comprises:

[0191] The survival range of the added second type virtual register is directly obtained by using the survival range of the original first type virtual register.

[0192] Clause 11. The method according to clause 10, wherein the allocating the first type register and the second type register further comprises:

[0193] Allocating the second type registers includes allocating the second type registers to the survival interval of the added second type virtual registers.

[0194] Clause 12. The method according to clause 11, characterized in that the method further comprises:

[0195] Perform code optimization based on the allocation results of the first type register and the second type register;

[0196] Code rewriting is performed based on the allocation result and the optimized code.

[0197] Clause 13. The method according to clause 12, wherein the code rewriting based on the allocation result and the optimized code comprises:

[0198] Rewriting corresponding first-type virtual registers and second-type virtual registers according to the allocation results of the first-type registers and the second-type registers; and

[0199] Corresponding overflow codes are inserted at the first type overflow point and the second type overflow point.

[0200] Clause 14: A register allocation apparatus comprising:

[0201] A first allocation module, configured to allocate first-type registers to first-type virtual registers;

[0202] a second allocation module, configured to allocate a second type of register to a second type of virtual register after the allocation of the first type of register is completed, wherein the width of the first type of register is greater than the width of the second type of register;

[0203] Wherein, the second allocation module includes:

[0204] The first overflow processing module is used for selecting overflow to the first type of register when overflow occurs in the second type of virtual register.

[0205] Clause 15: A compiling device comprising:

[0206] A survival interval establishment module, used to establish a virtual register survival interval, wherein the virtual register survival interval includes a survival interval of a first type of virtual register and a survival interval of a second type of virtual register;

[0207] The register allocation apparatus of clause 14 is configured to allocate first type registers and second type registers based on the virtual register survival range.

[0208] Clause 16: An electronic device, characterized in that the electronic device comprises:

[0209] one or more processing units;

[0210] A storage unit for storing one or more programs;

[0211] When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of clauses 1-13.

[0212] Clause 17: A computer-readable medium, characterized in that a computer program is stored on the computer-readable medium, and when the program is executed by a processor, it implements the method described in any one of Clauses 1-13.

[0213] The exemplary embodiments of the present application are specifically shown and described above. It should be understood that the present application is not limited to the detailed structures, configurations or implementations described herein; on the contrary, the present application is intended to cover various modifications and equivalent configurations included in the spirit and scope of the appended claims.

Claims

1. A method for allocating registers, characterized in that: The method comprises: Allocating first-type registers for first-type virtual registers based on the survival interval of the first-type virtual registers; After the allocation of the first type of registers is completed, the second type of registers are allocated to the second type of virtual registers based on the survival interval of the first type of virtual registers and the survival interval of the second type of virtual registers, Wherein, when allocating the second type register, if the second type virtual register overflows, first select the available first type register for overflow to reuse the first type register and avoid overflow to the stack space, wherein the width of the first type register is greater than the width of the second type register; wherein the survival interval refers to: assuming that the instructions in the intermediate representation are numbered in sequence, the survival interval of the variable v is the interval [i, j], then it means: there is no instruction numbered j1, where j1>j, so that the variable v is active at j1, and there is no instruction numbered i1, where i1<i, so that the variable v is active at i1.

2. The method according to claim 1, characterized in that The allocating of the second type registers also includes: When the second-type virtual register overflows, if there is no available first-type register, the register overflows to the stack space.

3. The method according to claim 1, characterized in that When allocating the first type register, if the first type virtual register overflows, the overflow is selected to the second type register.

4. The method according to claim 1, characterized in that The survival range of the first type virtual register and the survival range of the second type virtual register use the same representation logic.

5. The method according to claim 1, characterized in that The first type of registers includes vector registers and the second type of registers includes scalar registers.

6. A method for compiling, characterized in that The method comprises: Establishing a virtual register survival range, wherein the virtual register survival range includes a survival range of a first type of virtual register and a survival range of a second type of virtual register; Based on the virtual register survival range, the first type register and the second type register are allocated using the method for allocating registers according to any one of claims 1 to 5.

7. The method according to claim 6, characterized in that The step of establishing a virtual register survival interval includes: Obtaining an intermediate representation of a source file, the intermediate representation comprising a first type virtual register, a second type virtual register, and instructions acting on the first type virtual register and the second type virtual register; Uniformly establish increasing or decreasing program point numbers for the instructions in sequence; Using the program point number to indicate the survival range of the first type virtual register and the survival range of the second type virtual register; When the first type virtual register or the second type virtual register overflows, the virtual register survival range is updated.

8. The method according to claim 7, characterized in that The step of uniformly establishing increasing or decreasing program point numbers for the instructions in sequence includes: Establish a program point number for the instruction, the program point number is n*m P , n is the serial number of the program point, m and P are predetermined natural numbers greater than 1; The updating of the virtual register survival interval includes: when the first type virtual register overflows, inserting a first type overflow interval at a corresponding first type overflow point for adding a first type overflow pseudo instruction and a second type virtual register, and establishing a first type overflow point number for the first type overflow interval, wherein the first type overflow point number differs from a previous adjacent program point number by m K , K is a predetermined integer less than P; When the second-type virtual register overflows, a second-type overflow interval is inserted at the corresponding second-type overflow point for adding a second-type overflow pseudo instruction, and a second-type overflow point number is established for the second-type overflow interval, and the second-type overflow point number differs from the previous adjacent program point number or the first-type overflow point number by m. Q , Q is a predetermined integer less than K.

9. The method according to claim 8, characterized in that The step of establishing a virtual register survival interval further includes: The survival range of the added second type virtual register is directly obtained by using the survival range of the original first type virtual register.

10. The method according to claim 9, characterized in that The allocating of the first type register and the second type register also includes: Allocating the second type registers includes allocating the second type registers to the survival interval of the added second type virtual registers.

11. The method according to claim 10, characterized in that The method further comprises: Perform code optimization based on the allocation results of the first type register and the second type register; Code rewriting is performed based on the allocation result and the optimized code.

12. The method according to claim 11, characterized in that The code rewriting based on the allocation result and the optimized code includes: Rewriting corresponding first-type virtual registers and second-type virtual registers according to the allocation results of the first-type registers and the second-type registers; and Corresponding overflow codes are inserted at the first type overflow point and the second type overflow point.

13. An electronic device, characterized in that: The electronic device comprises: one or more processing units; A storage unit for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1-12.

14. A computer readable medium, characterized in that The computer readable medium stores a computer program, and when the program is executed by a processor, the method according to any one of claims 1 to 12 is implemented.

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