Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the forming method comprising: providing a substrate, the substrate being formed with a dielectric layer, a material of the dielectric layer being an oxygen-containing material; forming an opening in the dielectric layer; forming a barrier layer on a sidewall of the opening by using an atomic layer deposition process, the barrier layer at least comprising a first barrier layer covering a sidewall surface of the opening, and in the process of forming the first barrier layer, the atomic layer deposition process uses a modified precursor containing hydrogen. In the process of forming the first barrier layer, the modified precursor containing hydrogen is used to form a hydroxyl bond on the sidewall surface of the opening, the hydroxyl bond is more likely to adsorb a reaction precursor used in the atomic layer deposition process, thereby improving the thickness uniformity of the barrier layer, and accordingly improving the performance of the barrier layer, and further improving the performance of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] Atomic layer deposition (ALD) process is generally to deposit continuous multiple atomic layers on a substrate in a deposition chamber maintaining a negative pressure (a pressure lower than atmospheric pressure). The process includes multiple sub-deposition steps, which include: introducing a first reaction precursor into the deposition chamber, the first reaction precursor is adsorbed on the substrate surface; stopping the introduction of the first reaction precursor into the deposition chamber, and flowing an inert purge gas through the deposition chamber to remove the remaining first reaction precursor not adsorbed on the substrate from the deposition chamber; introducing a second reaction precursor into the deposition chamber, the second reaction precursor reacts with the first reaction precursor adsorbed on the substrate surface; stopping the introduction of the second reaction precursor into the deposition chamber, and flowing an inert purge gas through the deposition chamber to remove the by-products after the second reaction precursor reacts with the first reaction precursor from the deposition chamber.

[0003] In the existing semiconductor manufacturing process, the atomic layer deposition process is mainly used in a hole, an opening or a trench with a small line width and a large depth-width ratio. With the further development of the semiconductor device manufacturing process, the feature size of the device is getting smaller and smaller, and therefore, the depth-width ratio of the hole, the opening or the trench is getting larger and larger, thereby increasing the difficulty of the atomic layer deposition process. SUMMARY

[0004] The problem solved by embodiments of the present application is to provide a semiconductor structure and a forming method thereof, and to improve the performance of the semiconductor structure.

[0005] To solve the above problem, embodiments of the present application provide a forming method of a semiconductor structure, which includes: providing a substrate, a dielectric layer is formed on the substrate, and a material of the dielectric layer is an oxygen-containing material; forming an opening in the dielectric layer; forming a barrier layer on a sidewall of the opening by using an atomic layer deposition process, the barrier layer at least includes a first barrier layer covering a surface of the sidewall of the opening, and in the process of forming the first barrier layer, the atomic layer deposition process uses a modified precursor containing hydrogen.

[0006] Correspondingly, the embodiment of the present application also provides a semiconductor structure, comprising: a substrate; a dielectric layer on the substrate, the material of the dielectric layer being an oxygen-containing material; an opening in the dielectric layer; and a barrier layer on the sidewall of the opening, the barrier layer being formed by an atomic layer deposition process, the barrier layer at least comprising a first barrier layer covering the sidewall surface of the opening, and in the process of forming the first barrier layer, the atomic layer deposition process uses a modified precursor containing hydrogen.

[0007] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0008] The embodiment of the present application forms a barrier layer on the sidewall of the opening by an atomic layer deposition process, the barrier layer at least comprising a first barrier layer covering the sidewall surface of the opening, and in the process of forming the first barrier layer, the atomic layer deposition process uses a modified precursor containing hydrogen; wherein the material of the dielectric layer is an oxygen-containing material, and through the modified precursor containing hydrogen, hydrogen and oxygen can react with each other to form a hydroxyl (-OH) bond on the sidewall surface of the opening, thereby realizing modification of the sidewall surface of the opening, the hydroxyl bond being more likely to adsorb the reaction precursor used in the atomic layer deposition process, thereby providing a good adsorption environment for the reaction precursor, that is, through the modified precursor containing hydrogen, the adsorption capacity and adsorption amount of the reaction precursor used in the atomic layer deposition on the sidewall surface of the opening are improved, and the atomic mass of hydrogen is small, so the modified precursor containing hydrogen is more likely to reach the bottom position of the opening, thereby improving the adsorption amount uniformity of hydrogen atoms on the sidewall of the opening at various depth positions, and therefore, in combination with the above two factors, the thickness uniformity of the barrier layer on the sidewall of the opening is improved, thereby improving the performance of the barrier layer and further improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figures 1-2 is a structure diagram corresponding to each step in a forming method of a semiconductor structure;

[0010] Figure 3 is a barrier layer formed by the forming method shown in Figures 1-2 ;

[0011] Figures 4-8 is a structure diagram corresponding to each step in a forming method of a semiconductor structure according to an embodiment of the present application;

[0012] Figures 9-10 is a principle diagram of forming a first barrier layer in the embodiment shown in Figures 4-8 ;

[0013] Figure 11 is a local area electron microscope diagram of the first barrier layer formed by the forming method shown in Figures 4-8 ;

[0014] Figures 12-18 is a structure diagram corresponding to each step in another embodiment of the method for forming a semiconductor structure. DETAILED DESCRIPTION

[0015] With the further development of the semiconductor device fabrication process, the feature size of the device is getting smaller and smaller, and therefore, the aspect ratio of the hole, opening or trench is getting larger and larger, which increases the difficulty of the atomic layer deposition process, thus easily leading to the performance degradation of the semiconductor structure.

[0016] The reason for the performance degradation of the semiconductor structure will be analyzed in combination with a method for forming a semiconductor structure. Figures 1-2 is a structure diagram corresponding to each step in another embodiment of the method for forming a semiconductor structure.

[0017] REFERENCE Figure 1 , a substrate 10 is provided, a dielectric layer 20 is formed on the substrate 10, and an opening 25 is formed in the dielectric layer 20; by using an atomic layer deposition process, a barrier material layer 35 conformally covering the side wall and bottom of the opening 25 and the top of the dielectric layer 20 is formed.

[0018] As an example, a gate structure 11 is formed on the substrate 10, source / drain doped regions 12 are formed in the substrate 10 on both sides of the gate structure 11, a dielectric layer 20 covers the source / drain doped regions 12, and openings 25 are formed on both sides of the gate structure 11 and penetrate through the dielectric layer 20 above the source / drain doped regions 12, the openings 25 are used to provide a spatial position for the subsequent formation of a contact hole plug. The barrier material layer 35 is an insulating material, for example, silicon nitride.

[0019] REFERENCE Figure 2 , the barrier material layer 35 on the top of the dielectric layer 20 and the bottom of the opening 25 is removed (as shown in Figure 1 , the remaining barrier material layer 35 on the side wall of the opening 20 is retained as a barrier layer 30.

[0020] The barrier layer 30 is used to prevent the conductive material in the contact hole plug from diffusing into the dielectric layer 20, so as to improve the performance of the semiconductor structure. However, in combination with reference Figure 3 , Figure 3is an electron microscope image of a partial region of the barrier layer 30 formed by the above method. The reaction precursor used in the atomic layer deposition process is relatively difficult to reach the bottom of the opening 25, which results in that the reaction precursor is relatively difficult to be adsorbed on the sidewall surface of the opening 25 at a position close to the bottom of the opening 25. Moreover, as the device feature size is reduced, the aspect ratio of the opening 25 is increasingly large, which further increases the difficulty of the reaction precursor to reach the bottom of the opening 25. Therefore, the step coverage of the barrier material layer 35 is poor, and the thickness of the barrier material layer 35 on the sidewall of the opening 25 gradually decreases from the top to the bottom of the opening 25, thereby resulting in the decrease of the thickness uniformity of the barrier layer 30 and further resulting in the decrease of the performance of the barrier layer 30. For example, the diffusion barrier effect of the barrier layer 30 is poor.

[0021] To solve the technical problem, an embodiment of the present application provides a method for forming a semiconductor structure, which comprises the following steps: providing a substrate, a dielectric layer is formed on the substrate, and the material of the dielectric layer is an oxygen-containing material; forming an opening in the dielectric layer; and forming a barrier layer on the sidewall of the opening by using an atomic layer deposition process, wherein the barrier layer at least comprises a first barrier layer covering the sidewall surface of the opening, and a modified precursor containing hydrogen is used in the atomic layer deposition process in the process of forming the first barrier layer. By using the modified precursor containing hydrogen, the thickness uniformity of the barrier layer on the sidewall of the opening is improved, thereby improving the performance of the barrier layer and further improving the performance of the semiconductor structure.

[0022] In order to make the above object, features and advantages of the embodiments of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0023] Figures 4-8 is a schematic diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present application.

[0024] Reference Figure 4 A substrate 100 is provided, and a dielectric layer 200 is formed on the substrate, and the material of the dielectric layer 200 is an oxygen-containing material.

[0025] In this embodiment, the substrate 100 is a substrate. Specifically, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, or other materials, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrate. In other embodiments, the substrate includes a substrate and a fin protruding from the substrate.

[0026] In this embodiment, the gate structure 110 is formed on the substrate 100. The part of the substrate 100 under the gate structure 110 is used as a channel region. The gate structure 110 can be a polysilicon gate structure or a metal gate structure. Specifically, the gate structure 110 is a polysilicon gate structure, which includes a gate dielectric layer 111 and a gate electrode layer 112 on the gate dielectric layer 111. As an example, the material of the gate dielectric layer 111 is silicon oxide and the material of the gate electrode layer 112 is polysilicon. In other embodiments, when the gate structure is a metal gate structure, the gate structure accordingly includes a high-k gate dielectric layer and a metal gate electrode layer on the high-k gate dielectric layer.

[0027] The source / drain doped regions 120 are formed in the substrate 100 on both sides of the gate structure 110, which are used as source regions or drain regions of the semiconductor structure to be formed. The type of the doping ions in the source / drain doped regions 120 is the same as the conductivity type of the transistor corresponding to the semiconductor structure to be formed. For example, when the semiconductor structure to be formed is a P-type transistor, the type of the doping ions in the source / drain doped regions 120 is P-type, and the P-type ions are B ions, Ga ions or In ions; when the semiconductor structure to be formed is an N-type transistor, the type of the doping ions in the source / drain doped regions 120 is N-type, and the N-type ions are P ions, As ions or Sb ions.

[0028] As an example, the source / drain doped regions 120 are formed by ion implantation on both sides of the gate structure 110. In other embodiments, the source / drain doped regions can also be formed by epitaxy, and the source / drain doped regions are accordingly formed in an epitaxial layer. When the semiconductor structure to be formed is a P-type transistor, the material of the epitaxial layer is Si or SiGe; when the semiconductor structure to be formed is an N-type transistor, the material of the epitaxial layer is Si, SiP or SiC.

[0029] In this embodiment, the dielectric layer 200 covers the source / drain doped regions 120. Specifically, the dielectric layer 200 also covers the gate structure 110. The dielectric layer 200 is used to provide a process platform for the formation of a subsequent contact hole plug, and also used to isolate adjacent transistors. The dielectric layer 200 can be a single-layer structure or a stacked structure. As an example, the dielectric layer 200 is a single-layer structure, and the material of the dielectric layer 200 is silicon oxide. In other embodiments, the material of the dielectric layer can also be an insulating material such as silicon nitride or silicon oxynitride.

[0030] Referring to Figure 5 An opening 205 is formed in the dielectric layer 200.

[0031] The opening 205 is used to provide a spatial position for the formation of a subsequent contact hole plug. Therefore, the opening 205 is located on both sides of the gate structure 110 and penetrates the dielectric layer 200 above the source / drain doped regions 120.

[0032] In this embodiment, the anisotropic dry etching process is used to etch the dielectric layer 200 on both sides of the gate structure 110 to form the opening 205. By selecting the anisotropic dry etching process, the sidewall profile quality of the opening 205 can be improved.

[0033] It should be noted that as the device feature size gradually decreases, the aspect ratio of the opening 205 also increases. In this embodiment, the depth of the opening 205 is greater than or equal to 20 nanometers, and the aspect ratio of the opening 205 is greater than or equal to 7. For example, the aspect ratio of the opening 205 is 7 to 8.

[0034] In this embodiment, the opening 205 is only in the dielectric layer 200 above the source-drain doped region 120. In other embodiments, the opening can also penetrate the dielectric layer above the gate structure.

[0035] Reference Figure 6 The atomic layer deposition process is used to form a barrier layer 300 on the sidewall of the opening 205, and the barrier layer 300 at least includes a first barrier layer 310 covering the sidewall surface of the opening 205. During the formation of the first barrier layer 310, the atomic layer deposition process uses a modified precursor containing hydrogen.

[0036] The material of the dielectric layer 200 is an oxygen-containing material. By using the modified precursor containing hydrogen, hydrogen and oxygen can react to form a hydroxyl (-OH) bond on the sidewall surface of the opening 205, thereby modifying the sidewall surface of the opening 205. The hydroxyl bond is more easily adsorbed by the reaction precursor used in the atomic layer deposition process, thereby providing a good adsorption environment for the reaction precursor. That is, by using the modified precursor containing hydrogen, the adsorption capacity and amount of the reaction precursor on the sidewall surface of the opening 205 are improved, and the sidewall surface of the opening 205 at each depth position can easily reach a nearly saturated adsorption amount. Moreover, hydrogen has a small atomic mass, and the modified precursor containing hydrogen can more easily reach the bottom position of the opening 205, thereby improving the uniformity of the adsorption amount of hydrogen atoms on the sidewall of the opening 205 at each depth position. Therefore, by comprehensively considering the above two factors, the thickness uniformity of the first barrier layer 310 is improved, which in turn improves the thickness uniformity of the barrier layer 300, thereby improving the performance of the barrier layer 300, and further improving the performance of the semiconductor structure.

[0037] In this embodiment, the material of the dielectric layer 200 is silicon oxide, so hydrogen will also react with silicon to form a silicon-hydrogen (Si-H) bond on the sidewall surface of the opening 205. The silicon-hydrogen bond is also more easily adsorbed by the reaction precursor.

[0038] In combination with reference Figure 11 An electron microscope image of a local area of the first barrier layer 310 formed by the above method is shown. As Figure 11As shown, the thickness uniformity of the barrier layer 300 on the sidewall of the opening 205 is better in the direction from the top to the bottom of the opening 205 (as shown by the arrow). Figure 6

[0039] In this embodiment, the barrier layer 300 is formed by using an atomic layer deposition process. Therefore, after the barrier layer 300 is formed, the barrier layer 300 conformally covers the sidewall and the bottom of the opening 205 and the top of the dielectric layer 200. Accordingly, the step coverage of the first barrier layer 310 formed by the foregoing method is higher. The step coverage of the first barrier layer 310 at the position close to the bottom of the opening 205 is about 91.7%, thereby improving the step coverage of the barrier layer 300.

[0040] In this embodiment, the atomic layer deposition process is a plasma-enhanced atomic layer deposition (PEALD) process. The process temperature of the plasma-enhanced atomic layer deposition process is lower, which can reduce the influence on the performance of the semiconductor structure and reduce the thermal budget. Moreover, the process controllability of the plasma-enhanced atomic layer deposition process is higher. Accordingly, the modified precursor and each reaction precursor of the atomic layer deposition process are ionized and excited by plasma, so that the modified precursor and each reaction precursor are introduced into the deposition chamber in the form of pulses.

[0041] In this embodiment, the modified precursor is hydrogen. In other embodiments, the modified precursor can also be deuterium or an isotope gas of hydrogen.

[0042] The material of the first barrier layer 310 is a dielectric material containing nitrogen. The material of the first barrier layer 310 can include one or more of silicon nitride, silicon carbon nitride, silicon carbon nitrogen oxide, silicon oxynitride, boron nitride, and boron carbon nitride. By selecting the dielectric material containing nitrogen, the first barrier layer 310 has a higher density, thereby improving the diffusion prevention effect of the barrier layer 300. Moreover, by selecting the dielectric material, the first barrier layer 310 can be formed by the atomic layer deposition process. In this embodiment, the material of the first barrier layer 310 is silicon nitride. Silicon nitride is easy to form by the atomic layer deposition process, has high process compatibility, and is conducive to reducing the process cost and easy to form.

[0043] ​In the step of forming the first barrier layer 310, the step of the atomic layer deposition process comprises: performing at least one sub-layer deposition process. Specifically, the sub-layer deposition process comprises: introducing a first reaction precursor into the deposition chamber, the first reaction precursor being adsorbed on the sidewall surface of the opening 205; after the first reaction precursor is adsorbed on the sidewall surface of the opening 205, discharging the excess first reaction precursor not adsorbed on the sidewall surface of the opening 205 from the deposition chamber; after the excess first reaction precursor is discharged from the deposition chamber, introducing a second reaction precursor and a hydrogen-containing modification precursor into the deposition chamber, the modification precursor modifying the sidewall surface of the opening 205, and the second reaction precursor reacting with the first reaction precursor; and discharging by-products after the second reaction precursor reacts with the first reaction precursor from the deposition chamber.

[0044] Generally, in the process of the first sub-layer deposition process, after the first reaction precursor is introduced into the deposition chamber, the adsorption capacity of the first reaction precursor on the sidewall surface of the opening 205 is poor, and thus a large amount of the first reaction precursor is discharged in the step of discharging the excess first reaction precursor not adsorbed on the sidewall surface of the opening 205 from the deposition chamber. After the second reaction precursor and the hydrogen-containing modification precursor are introduced into the deposition chamber, the hydrogen-containing modification precursor modifies the sidewall surface of the opening 205 to form a hydroxyl bond on the sidewall surface of the opening 205. Correspondingly, in the process of the second sub-layer deposition process performed subsequently, after the first reaction precursor is introduced into the deposition chamber, the adsorption capacity of the hydroxyl bond on the first reaction precursor is high, which improves the adsorption capacity and the adsorption amount of the first reaction precursor on the sidewall surface of the opening 205, so that more second reaction precursors react with the first reaction precursor. In summary, the hydrogen-containing modification precursor in the previous sub-layer deposition process is used to provide an adsorption environment for the subsequent sub-layer deposition process.

[0045] Furthermore, if the hydrogen-containing modification precursor is introduced into the deposition chamber alone, the hydrogen-containing modification precursor is easily discharged directly from the deposition chamber, and thus the second reaction precursor and the hydrogen-containing modification precursor are introduced into the deposition chamber at the same time to improve the stability of the hydrogen-containing modification precursor in the deposition chamber, so as to ensure the normal operation of the deposition process.

[0046] In this embodiment, the material of the first barrier layer 310 is silicon nitride, and thus in the process of forming the first barrier layer 310, the first reaction precursor is a silicon source gas, such as SiH2I2 or SiH2Cl2, and the second reaction precursor is a nitrogen source gas, such as N2 or NH3. As an example, the first reaction precursor is SiH2I2, and the second reaction precursor is N2. It should be noted that the second reaction precursor is a nitrogen source gas, so that the surface of the first barrier layer 310 is a nitrogen atom layer, which is beneficial to improving the etching resistance of the first barrier layer 310.

[0047] In the embodiment, in the process of forming the first barrier layer 310, the cleaning gas is introduced into the deposition chamber and discharged from the deposition chamber after the second reaction precursor reacts with the first reaction precursor in each sub-deposition process, so as to discharge the by-products after the second reaction precursor reacts with the first reaction precursor. The cleaning gas includes nitrogen, so as to reduce the influence on the next sub-deposition process.

[0048] The number of sub-deposition processes is determined according to the target thickness of the first barrier layer 310 and the area required to be covered by the first barrier layer 310. With the increase of the number of sub-deposition processes, the thickness of the first barrier layer 310 increases accordingly. In the embodiment, the first barrier layer 310 meeting the target thickness is formed after the multiple sub-deposition processes are performed.

[0049] Figure 9 and Figure 10 The principle diagram of forming the first barrier layer 310 is shown. As shown in Figure 9 and Figure 10 After the hydrogen-containing modified precursor is introduced into the deposition chamber in the previous sub-deposition process, the modified precursor is adsorbed on the side wall surface and bottom surface of the opening 205 and the top surface of the opening 205 to form a hydroxyl bond or a silicon-hydrogen bond. Correspondingly, in the subsequent sub-deposition process, after the first reaction precursor (for example, SiH2I2) is introduced into the deposition chamber, the first reaction precursor is ionized into SiH- bond, the SiH- bond combines with the hydroxyl bond or the silicon-hydrogen bond; after the by-products after the first reaction precursor combines with the modified precursor are discharged from the deposition chamber, a monatomic layer of silicon is formed on the side wall surface and bottom surface of the opening 205 and the top surface of the opening 205; after the modified precursor and the second reaction precursor (for example, N2) are introduced into the deposition chamber, the nitrogen atom reacts with the monatomic layer of silicon, and the modified precursor continues to be adsorbed on the area where the monatomic layer is not formed to form a hydroxyl bond or a silicon-hydrogen bond; after the by-products after the second reaction precursor reacts with the first reaction precursor are discharged from the deposition chamber, a Si-N film is formed. In the subsequent sub-deposition process, the modified precursor is also adsorbed on the surface of the Si-N film to form an N-H bond, and the N-H bond is easy to adsorb the first reaction precursor and combine with the SiH- bond, so as to form another Si-N film on the Si-N film. Therefore, by performing multiple sub-deposition processes, multiple Si-N films can be formed, and the multiple Si-N films are stacked to form the first barrier layer 310.

[0050] In the embodiment, in the process of forming the first barrier layer 310, the parameters of the atomic layer deposition process include: the gas flow of the first reaction precursor is 0.001-1 sccm, the gas flow of the second reaction precursor is 1-1000 sccm, the source radio frequency power is 500-1000 W, the chamber pressure is 10-30 torr, and the process temperature is 300-400℃.

[0051] The gas flow of the first reaction precursor should not be too small or too large. If the gas flow of the first reaction precursor is too small, the coverage area of the single-layer Si-N film is too small, thereby causing the manufacturing efficiency to decrease; in each sub-deposition process, the adsorption amount of the first reaction precursor has a saturation value, and if the gas flow of the first reaction precursor is too large, the process resources and costs are also easily wasted. Therefore, in the embodiment, the gas flow of the first reaction precursor is 0.001-1 sccm, for example, 0.01 sccm, 0.015 sccm, 0.05 sccm, or 0.5 sccm.

[0052] Therefore, in the embodiment, according to the gas flow of the first reaction precursor, the gas flow of the second reaction precursor is 1-1000 sccm, for example, 10 sccm, 15 sccm, 20 sccm, or 50 sccm.

[0053] The greater the source radio frequency power is, the stronger the dissociation ability of each reaction precursor and the modified precursor is, but when the source radio frequency power is too large, the uniformity of dissociation is poor, thereby causing the thickness uniformity of the first barrier layer 310 to be poor, and further affecting the thickness uniformity of the barrier layer 300. Therefore, in the embodiment, the source radio frequency power is 500-1000 W, for example, 600 W, 700 W, or 800 W.

[0054] The smaller the chamber pressure is, the higher the vacuum degree in the deposition chamber is, and after each reaction precursor and the modified precursor are dissociated, they are easily discharged from the deposition chamber, that is, the reaction time is shortened, thereby causing the formation quality and the thickness uniformity of the first barrier layer 310 to be poor, and in the embodiment, the plasma enhanced atomic layer deposition process is adopted, the generation of the plasma needs a medium, and if the pressure is too small, the plasma cannot be generated, thereby affecting the normal progress of the deposition process; if the pressure is too large, the reaction precursor, the hydrogen-containing modified precursor, or the byproduct cannot be discharged from the chamber. Therefore, in the embodiment, the chamber pressure is 10-30 torr, for example, 15 torr, 20 torr, or 25 torr.

[0055] Increasing the process temperature is conducive to improving the speed of dissociation and reaction. When the process temperature is too low, the speed of dissociation or reaction is prone to be too slow. However, when the process temperature is too high, the performance of the semiconductor structure is prone to be adversely affected, and the thermal budget is also prone to be increased. Therefore, in this embodiment, the process temperature is 300-400 ℃, for example, 350 ℃.

[0056] Correspondingly, the gas flow of the modified precursor is reasonably adjusted according to the gas flow of the first reaction precursor, so as to ensure that a good adsorption environment is provided for the first reaction precursor. The gas flow of the modified precursor should not be too small or too large. If the gas flow of the modified precursor is too small, the modification effect of the modified precursor on the sidewall surface of the opening 205 is prone to be poor, it is difficult to ensure that the hydrogen-containing modified precursor can reach the bottom position of the opening 205, and it is difficult to ensure that the sidewall surface of the opening 205 near the bottom position of the opening 205 has enough hydroxyl bonds or silicon-hydrogen bonds, thereby reducing the adsorption effect on the reaction precursor, and further adversely affecting the thickness uniformity and step coverage of the barrier layer 300. If the gas flow of the modified precursor is too large, when the modified precursor can make the sidewall surface of the opening 205 at each depth position reach a nearly saturated adsorption amount, it will cause waste of process cost and resources. Therefore, in this embodiment, the gas flow of the modified precursor is 1-5 sccm, for example, 2 sccm or 3 sccm.

[0057] In this embodiment, the barrier layer 300 has a laminated structure, and the barrier layer 300 further includes a second barrier layer 320 conformally covering the first barrier layer 310. The second barrier layer 320 and the first barrier layer 310 are sequentially and continuously formed in the same deposition chamber, and the etch resistance of the second barrier layer 320 is greater than that of the first barrier layer 310.

[0058] In the formation process of the semiconductor structure, subsequent processes usually include a wet etching process, for example, a diluted hydrofluoric acid (DHF) is used for wet etching. As known from the foregoing, in the process of forming the first barrier layer 310, the hydrogen-containing modified precursor is used, and therefore, the first barrier layer 310 is prone to contain hydrogen impurities, and the activity of hydrogen is relatively high, which is prone to increase the wet etch rate (WER) of the first barrier layer 310. Therefore, by forming the second barrier layer 320 with higher etch resistance, the second barrier layer 320 is used to protect the first barrier layer 310, improve the overall etch resistance of the barrier layer 300, and correspondingly reduce the wet etch rate of the barrier layer 300.

[0059] Specifically, after forming the first barrier layer 310, the second barrier layer 320 conformally covering the first barrier layer 310 is continuously formed in the same deposition chamber, so that the steps of forming the second barrier layer 320 and the first barrier layer 310 are more coherent, the barrier layer 300 is less likely to have defects, and process time is also saved. The deposition chamber refers to a chamber in a deposition device for realizing deposition of a film layer.

[0060] In this embodiment, the same reaction precursor is used to form the first barrier layer 310 and the second barrier layer 320. That is, after forming the first barrier layer 310, the modified precursor containing hydrogen is stopped from being introduced into the deposition chamber, and the process compatibility of forming the first barrier layer 310 and the second barrier layer 320 is high, and the process modification is small.

[0061] The aforementioned sub-layer deposition process for forming the first barrier layer 310 is taken as the first sub-layer deposition process, and in the step of forming the second barrier layer 320, the step of the atomic layer deposition process includes: performing at least one second sub-layer deposition process. Specifically, the step of the second sub-layer deposition process includes: introducing the first reaction precursor into the deposition chamber, and the first reaction precursor is adsorbed on the surface of the first barrier layer 310; after the first reaction precursor is adsorbed on the surface of the first barrier layer 310, the excess first reaction precursor not adsorbed on the surface of the first barrier layer 310 is discharged from the deposition chamber; after the excess first reaction precursor is discharged from the deposition chamber, the second reaction precursor is introduced into the deposition chamber, and the second reaction precursor reacts with the first reaction precursor adsorbed on the surface of the first barrier layer 310; and the by-products after the second reaction precursor reacts with the first reaction precursor are discharged from the deposition chamber.

[0062] In this embodiment, during each second sub-layer deposition process, after the second reaction precursor reacts with the first reaction precursor, a purge gas is introduced into the deposition chamber and discharged from the deposition chamber, so that the by-products after the second reaction precursor reacts with the first reaction precursor are discharged from the deposition chamber with the purge gas. The purge gas includes nitrogen, thereby reducing the influence on the next second sub-layer deposition process.

[0063] In this embodiment, the step of discharging the by-products after the second reaction precursor reacts with the first reaction precursor from the deposition chamber in the last first sub-layer deposition process is continuously performed with the step of introducing the first reaction precursor into the deposition chamber in the first second sub-layer deposition process, so that the first barrier layer 310 and the second barrier layer 320 conformally covering the first barrier layer 310 are sequentially and continuously formed.

[0064] In the embodiment, the second reaction precursor is introduced into the deposition chamber after the byproduct of the reaction between the first reaction precursor and the second reaction precursor is exhausted from the deposition chamber, that is, after the deposition of the second sub-layer is completed, the first reaction precursor is introduced into the deposition chamber immediately, and the deposition of the second sub-layer is completed until the second barrier layer 320 is formed.

[0065] It should be noted that the thickness of the barrier layer 300 should not be too small or too large. If the thickness of the barrier layer 300 is too small, the effect of preventing the conductive material in the contact hole plug from diffusing into the dielectric layer 200 is reduced. If the thickness of the barrier layer 300 is too large, the space occupied by the barrier layer 300 is too large, which affects the formation quality and performance of the contact hole plug. Therefore, in the embodiment, the thickness of the barrier layer 300 is 3-4 nm, for example, 3.5 nm.

[0066] It should be further noted that when the barrier layer 300 includes the second barrier layer 320 and the first barrier layer 310, the thickness of the first barrier layer 310 should not be too small or too large. If the thickness of the first barrier layer 310 is too small, the thickness uniformity of the first barrier layer 310 and the step coverage of the first barrier layer 310 are poor, which correspondingly reduces the thickness uniformity and the step coverage of the barrier layer 300, thereby reducing the performance of the barrier layer 300. If the thickness of the first barrier layer 310 is too large, the thickness of the second barrier layer 320 is correspondingly too small, which reduces the protection effect of the second barrier layer 320 on the first barrier layer 310 and is not conducive to improving the wet etching rate of the barrier layer 300. Therefore, in the embodiment, the thickness of the first barrier layer 310 is 2-2.5 nm, for example, 2.1 nm or 2.3 nm.

[0067] In addition, the barrier layer 300 is taken as an example of a stacked structure in the embodiment. In other embodiments, the barrier layer can also be a single-layer structure, that is, the barrier layer only includes the first barrier layer.

[0068] Reference Figure 7 The forming method further includes: removing the barrier layer 300 located at the bottom of the opening 205 and the top of the dielectric layer 200.

[0069] By removing the barrier layer 300 located at the bottom of the opening 205 and the top of the dielectric layer 200, the barrier layer 300 on the sidewall of the opening 205 is reserved, thereby preparing for the subsequent formation of the contact hole plug. The barrier layer 300 on the sidewall of the opening 205 is used to prevent the conductive material in the contact hole plug from diffusing into the dielectric layer 200, thereby improving the performance of the semiconductor structure.

[0070] In this embodiment, the blocking layer 300 is etched by a maskless etching process, so that the blocking layer 300 on the sidewall of the opening 205 is reserved. Specifically, the maskless etching process is an anisotropic dry etching process.

[0071] Reference is made to Figure 8 After the blocking layer 300 on the bottom of the opening 205 and the top of the dielectric layer 200 is removed, the method further includes forming a contact hole plug 130 in the opening 205 to electrically connect the source / drain doped region 120.

[0072] The contact hole plug 130 is electrically connected to the source / drain doped region 120, and the contact hole plug 130 is used to electrically connect the source / drain doped region 120 to other circuits. In this embodiment, the material of the contact hole plug 130 is W, which can be formed by chemical vapor deposition, sputtering or electroplating. In other embodiments, the material of the contact hole plug can also be Al, Cu, Ag or Au, etc.

[0073] Figures 12-18 is a structural schematic diagram corresponding to each step in another embodiment of the method for forming the semiconductor structure.

[0074] The same as the foregoing embodiments, the same is not described again. The difference between this embodiment and the foregoing embodiments is that, as shown in Figure 17 The opening 505 is used as a top blocking slot in the blocking slots.

[0075] Reference is made to Figure 12 and Figure 13 , Figure 12 is a top view, Figure 13 is Figure 12 is a sectional view along the CC1 cutting line, providing a substrate 400 (as shown in Figure 13 The substrate 400 includes a plurality of adjacent device unit regions 400a and isolation regions 400b between adjacent device unit regions, and the substrate 400 of the device unit region 400a and the isolation region 400b forms a gate structure 410, the gate structure 410 exposes the substrate 400 to form a dielectric layer 500, and the dielectric layer 500 covers the sidewall of the gate structure 410.

[0076] The device unit region 400a is used to form a device, and the isolation region 400b is used to define the formation area of the blocking structure, which can be a single diffusion break (SDB) isolation structure. The blocking structure is used to isolate adjacent device unit regions 400a in a direction perpendicular to the extension direction of the gate structure 410. For specific description of the substrate 400, the gate structure 410 and the dielectric layer 500, reference can be made to the corresponding description in the foregoing embodiments, which is not described again here.

[0077] Reference is made toFigure 14 The gate structure 410 located in the isolation region 400b is removed to form an initial opening 505a in the dielectric layer 500.

[0078] The initial opening 505a is used for preparing the formation of an opening.

[0079] In this embodiment, the mask layer (e.g., photoresist layer) is used to expose the gate structure 410 to be removed, and the mask layer is used as an etching mask to remove the exposed gate structure 410. After the gate structure 410 located in the isolation region 400b is removed, the mask layer is removed. As an example, a dry etching process is used to remove the gate structure 410 located in the isolation region 400b, thereby improving the topography quality of the initial opening 505a.

[0080] Reference is made to FIG. 5B. Figure 15 After the gate structure 410 located in the isolation region 400b is removed, the sidewall of the initial opening 505a (as shown in FIG. 5B) is laterally etched in a direction parallel to the surface of the substrate 400, so that the initial opening 505a forms an opening 505. Figure 13

[0081] The opening 505 is used as a top blocking trench, and the opening 505 is used to define the formation position of the blocking trench. Moreover, the opening 505 is used to provide a process basis for the subsequent formation of a blocking layer.

[0082] In this embodiment, a wet etching process is used to laterally etch the dielectric layer 500 exposed by the initial opening 505a. The wet etching process has isotropic etching characteristics, thereby being able to increase the opening size of the initial opening 505a to form the opening 505 with a larger opening size. The opening size of the opening 505 can be set according to process requirements, for example, the opening size of the opening 505 is set according to the depth of the subsequent blocking trench.

[0083] Reference is made to FIG. 6. Figure 16 The atomic layer deposition process is used to form a blocking layer 600 on the sidewall of the opening 505, and the blocking layer 600 at least includes a first blocking layer 610 covering the surface of the sidewall of the opening 505. In the process of forming the first blocking layer 610, the atomic layer deposition process uses a modified precursor containing hydrogen.

[0084] ​The bottom blocking groove is formed in the substrate 400 by etching a portion of the thickness of the bottom of the opening 505 with the barrier layer 600 as a mask. The bottom blocking groove and the top blocking groove are connected to form a blocking groove in a T shape. The barrier layer 600 is used to adjust the opening size of the bottom blocking groove. Therefore, in the process of forming the top blocking groove, the opening size of the bottom of the bottom blocking groove and the depth of the blocking groove can meet the process requirements by appropriately increasing the opening size of the opening 505, which correspondingly increases the process window of forming the blocking groove and reduces the process difficulty of forming the blocking groove. For example, due to the limitation of the etching process, the opening size of the bottom blocking groove gradually decreases in the direction from the top to the bottom of the opening 505. Therefore, by appropriately increasing the opening size of the opening 505 and cooperating with the barrier layer 600, the overall appearance quality of the blocking groove is improved while the depth of the blocking groove meets the process requirements, which facilitates the subsequent filling of the material of the blocking structure in the blocking groove. Moreover, in the process of etching the substrate 400, the barrier layer 600 can protect the exposed dielectric layer 500 on the sidewall of the opening 505.

[0085] In this embodiment, the material of the first barrier layer 610 is silicon nitride.

[0086] In this embodiment, the barrier layer 600 further includes a second barrier layer 620 conformally covering the first barrier layer 610. The second barrier layer 620 and the first barrier layer 610 are sequentially and continuously formed in the same deposition chamber. The etching resistance of the second barrier layer 620 is greater than that of the first barrier layer 610.

[0087] It should be noted that the barrier layer 600 conformally covers the sidewall and bottom of the opening 505 and the top of the dielectric layer 500. Therefore, after the barrier layer 600 is formed, a maskless etching process is used to etch the barrier layer 600, remove the barrier layer 600 located at the bottom of the opening 505 and the top of the dielectric layer 500, and retain the barrier layer 600 located at the sidewall of the opening 505, thereby preparing for the subsequent etching of the substrate 400. Specifically, the maskless etching process is an anisotropic dry etching process.

[0088] The specific description of the barrier layer 600 can refer to the description in the foregoing embodiments, which will not be repeated here.

[0089] Reference Figure 17 The bottom blocking groove 405 is formed in the substrate 400 by etching a portion of the thickness of the bottom of the top blocking groove (i.e., the opening 405) with the barrier layer 600 located at the sidewall of the opening 505 as a mask.

[0090] The bottom blocking groove 405 and the top blocking groove form a blocking groove (not labeled), thereby providing a spatial position for the subsequent formation of the blocking structure.

[0091] In the embodiment, the anisotropic dry etching process is used to etch part of the thickness of the substrate 400 at the bottom of the top blocking trench, so as to improve the flatness of the sidewall of the bottom blocking trench 405, and to easily control the opening size and depth of the bottom blocking trench 405, and to further improve the performance of the semiconductor structure. In the above-mentioned manner of forming the blocking layer 600, the thickness uniformity of the blocking layer 600 is good, that is, the performance of the blocking layer 600 is high, so that the masking effect is guaranteed. Moreover, the etching resistance of the second blocking layer 620 is greater than that of the first blocking layer 610, and the loss of the blocking layer 600 is smaller in the process of etching the substrate 400, so as to further guarantee the masking effect.

[0092] In the embodiment, the blocking layer 600 is reserved after the bottom blocking trench 405 is formed. The blocking layer 600 is a dielectric material, and by reserving the blocking layer 600, the step of removing the blocking layer 600 by using an additional process is omitted, so as to simplify the process steps.

[0093] Reference Figure 18 The blocking structure 700 is formed in the blocking trench (not shown). Specifically, the blocking structure 700 is formed in the top blocking trench (i.e., the opening 505) and the bottom blocking trench 405. The blocking structure 700 is used to realize the electrical isolation of the adjacent device unit region 400a.

[0094] The material of the blocking structure 700 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In the embodiment, the material of the blocking structure 700 is silicon oxide, which improves the adhesion of the blocking structure 700 in the blocking trench and reduces the probability of dislocation.

[0095] Correspondingly, the embodiment of the present application also provides a semiconductor structure. In combination with reference Figure 7 and Figure 8 , a structural schematic diagram of an embodiment of the semiconductor structure of the present application is shown, Figure 7 is a structural schematic diagram without showing the contact hole plug.

[0096] The semiconductor structure includes: a substrate 100; a dielectric layer 200 located on the substrate 100, the material of the dielectric layer 200 being an oxygen-containing material; an opening 205 located in the dielectric layer 200; a blocking layer 300 located on the sidewall of the opening 205, the blocking layer 300 being formed by using an atomic layer deposition process, the blocking layer 300 at least including a first blocking layer 310 covering the surface of the sidewall of the opening 205, and in the process of forming the first blocking layer 310, the atomic layer deposition process uses a modified precursor containing hydrogen.

[0097] In the process of forming the first barrier layer 310, the hydrogen-containing modified precursor forms hydroxyl (-OH) bonds on the sidewall surface of the opening 205, the hydroxyl bonds are more easily adsorbed by the reaction precursor used in the atomic layer deposition process, which correspondingly improves the adsorption capacity and adsorption amount of the reaction precursor on the sidewall surface of the opening 205; and the hydrogen-containing modified precursor is more easily to reach the bottom position of the opening 205, thereby improving the adsorption amount uniformity of hydrogen atoms on the sidewall of the opening 205 at various depth positions; in combination of the above two factors, the thickness uniformity of the first barrier layer 310 is improved, which correspondingly improves the thickness uniformity of the barrier layer 300, thereby improving the performance of the barrier layer 300, and further improving the performance of the semiconductor structure.

[0098] In this embodiment, the substrate 100 is a substrate. In other embodiments, the substrate includes a substrate and a fin portion protruding from the substrate.

[0099] In this embodiment, the substrate 100 is formed with a gate structure 110. The gate structure 110 can be a polysilicon gate structure or a metal gate structure. In this embodiment, the gate structure 110 is a polysilicon gate structure, which includes a gate dielectric layer 111 and a gate electrode layer 112 located on the gate dielectric layer 111.

[0100] The substrate 100 on both sides of the gate structure 110 is formed with a source / drain doped region 120. The type of doped ions in the source / drain doped region 120 is the same as the transistor conduction type corresponding to the semiconductor structure to be formed.

[0101] The dielectric layer 200 covers the source / drain doped region 120. Specifically, the dielectric layer 200 also covers the gate structure 110. The dielectric layer 200 is used to provide a process platform for the formation of the contact hole plug, and also used to isolate adjacent transistors. As an embodiment, the dielectric layer 200 is a single layer structure, and the material of the dielectric layer 200 is silicon oxide.

[0102] For specific description of the substrate 100, the gate structure 110, the source / drain doped region 120 and the dielectric layer 200, reference can be made to the corresponding description of the foregoing embodiments, which will not be repeated here.

[0103] The opening 205 is used to provide a spatial position for the formation of the contact hole plug. Therefore, the opening 205 is located on both sides of the gate structure 110 and penetrates through the dielectric layer 200 above the source / drain doped region 120. As the device feature size gradually decreases, the aspect ratio of the opening 205 becomes larger and larger. In this embodiment, the depth of the opening 205 is greater than or equal to 20 nanometers, and the aspect ratio of the opening 205 is greater than or equal to 7, for example, the aspect ratio is 7 to 8.

[0104] It should be noted that in the embodiment, the opening 205 is only in the dielectric layer 200 above the source-drain doped region 120. In other embodiments, the opening can also penetrate the dielectric layer above the gate structure.

[0105] In the embodiment, the barrier layer 300 is located on the sidewall of the opening 205, which is used to prevent the conductive material in the contact hole plug from diffusing into the dielectric layer 200, thereby improving the performance of the semiconductor structure. As described above, the barrier layer 300 located on the sidewall of the opening 205 has high thickness uniformity, thereby improving its diffusion prevention effect.

[0106] In the embodiment, the material of the dielectric layer 200 is silicon oxide, and in the process of forming the first barrier layer 310, hydrogen will also react with silicon to form a silicon-hydrogen (Si-H) bond on the surface of the sidewall of the opening 205. The silicon-hydrogen bond is also more prone to adsorb the reaction precursor, thereby further improving the thickness uniformity of the barrier layer 300.

[0107] The material of the first barrier layer 310 is a nitrogen-containing dielectric material, which can include one or more of silicon nitride, silicon carbon nitride, silicon carbon nitrogen oxide, silicon oxynitride, boron nitride, and boron carbon nitride. In the embodiment, the material of the first barrier layer 310 is silicon nitride. Silicon nitride has high process compatibility, which is beneficial to reduce process cost and easy to form.

[0108] In the embodiment, the barrier layer 300 further includes a second barrier layer 320 conformally covering the first barrier layer 310, and the etch resistance of the second barrier layer 320 is greater than that of the first barrier layer 310. In the process of forming the semiconductor structure, a wet etching process is usually included. As described above, in the process of forming the first barrier layer 310, the atomic layer deposition process uses a modified precursor containing hydrogen, so the first barrier layer 310 is prone to contain hydrogen impurity elements, which is prone to cause the wet etching rate of the first barrier layer 310 to be high; the second barrier layer 320 is used to protect the first barrier layer 310, thereby improving the overall etch resistance of the barrier layer 300, and correspondingly reducing the wet etching rate of the barrier layer 300.

[0109] In the embodiment, the material of the second barrier layer 320 is the same as that of the first barrier layer 310, and the second barrier layer 320 does not contain hydrogen impurity elements. Therefore, in the process of forming the barrier layer 300, the same reaction precursor can be used to sequentially and continuously form the first barrier layer 310 and the second barrier layer 320.

[0110] It should be noted that if the thickness of the barrier layer 300 is too small, the effect of the barrier layer 300 for preventing the conductive material in the contact hole plug from diffusing into the dielectric layer 200 is reduced; if the thickness of the barrier layer 300 is too large, the space occupied by the barrier layer 300 is too large, thereby affecting the formation quality and performance of the contact hole plug. Therefore, the thickness of the barrier layer 300 is 3-4 nm, for example, 3.5 nm.

[0111] It should also be noted that when the barrier layer 300 includes the second barrier layer 320 and the first barrier layer 310, if the thickness of the first barrier layer 310 is too small, the thickness uniformity of the first barrier layer 310 and the step coverage of the first barrier layer 310 are poor, which correspondingly reduces the thickness uniformity and step coverage of the barrier layer 300, thereby reducing the performance of the barrier layer 300; if the thickness of the first barrier layer 310 is too large, the thickness of the second barrier layer 320 is correspondingly too small, thereby easily reducing the protection effect of the second barrier layer 320 on the first barrier layer 310, which is not conducive to improving the wet etching rate of the barrier layer 300. Therefore, in the embodiment, the thickness of the first barrier layer 310 is 2-2.5 nm, for example, 2.1 nm or 2.3 nm.

[0112] In addition, the embodiment takes the barrier layer 300 as a stack structure for illustration. In other embodiments, the barrier layer can also be a single-layer structure, i.e., the barrier layer only includes the first barrier layer.

[0113] As shown in Figure 8 , the semiconductor structure further includes: a contact hole plug 130 located in the opening 205 exposed by the barrier layer 300 and electrically connected to the source / drain doped region 120.

[0114] The contact hole plug 130 is electrically connected to the source / drain doped region 120, and is used to realize the electrical connection between the source / drain doped region 120 and other circuits. In the embodiment, the material of the contact hole plug 130 is W. In other embodiments, the material of the contact hole plug can also be a metal material such as Al, Cu, Ag, or Au.

[0115] The semiconductor structure in the embodiment can be formed by using the forming method in the first embodiment, or can be formed by using other forming methods. For the specific description of the semiconductor structure in the embodiment, reference can be made to the corresponding description in the foregoing embodiments, which will not be repeated here.

[0116] In combination with reference to Figure 17 and Figure 18 , a structure schematic diagram of another embodiment of the semiconductor structure of the present application is shown, Figure 17 is a structure schematic diagram without a blocking structure.

[0117] The same as the foregoing embodiments, and details are not repeated. The difference between the present embodiment and the foregoing embodiments is that, as shown in FIG. 5, the opening 505 is used as a top blocking slot in the blocking slot. Figure 17

[0118] In the present embodiment, the substrate 400 includes a plurality of adjacent device unit regions 400a and isolation regions 400b between the adjacent device unit regions 400a, and the gate structure 410 is formed on the substrate 400 of the device unit region 400a.

[0119] The isolation region 400b is used to define a forming region of the blocking structure, and the blocking structure can be a single diffusion blocking isolation structure. The blocking structure is used to isolate the adjacent device unit regions 400a in a direction perpendicular to the extending direction of the gate structure 410.

[0120] For specific descriptions of the substrate 400, the gate structure 410 and the dielectric layer 500, reference can be made to the corresponding descriptions in the foregoing embodiments, and details are not repeated herein.

[0121] Correspondingly, the dielectric layer 500 is located on the substrate 400 exposed by the gate structure 410, and the dielectric layer 500 covers the sidewall of the gate structure 410. The opening 505 is used to define the position of the blocking slot. Moreover, the opening 505 is used to provide a process basis for the formation of the blocking layer 600. In the present embodiment, the opening 505 is located in the dielectric layer 500 of the isolation region 400b, and the opening 505 is used as a top blocking slot.

[0122] The semiconductor structure further includes: a bottom blocking slot 405 located in the substrate 400 of the isolation region 400b, the bottom blocking slot 405 is in communication with the top blocking slot, and the sidewall of the bottom blocking slot 405 is flush with the sidewall of the blocking layer 600; and a blocking structure 700 located in the top blocking slot and the bottom blocking slot 405.

[0123] The top blocking slot and the bottom blocking slot 405 are used to constitute a blocking slot, the blocking layer 600 is located on the sidewall of the opening 505, and the blocking layer 600 is used as an etching mask for forming the bottom blocking slot 405. Under the action of the blocking layer 600, the blocking slot is in a T shape. The blocking layer 600 can adjust the opening size of the bottom blocking slot 405. In the process of forming the opening 505, the opening size of the bottom of the bottom blocking slot 405 and the depth of the blocking slot can meet the process requirements by appropriately increasing the opening size of the opening 505, which correspondingly increases the process window for forming the blocking slot and reduces the process difficulty for forming the blocking slot. The thickness uniformity of the first blocking layer 610 is high, and correspondingly, the thickness uniformity of the blocking layer 600 is also high, so that the mask effect of the blocking layer 600 is guaranteed, thereby improving the performance of the semiconductor structure.

[0124] ​In this embodiment, the material of the first barrier layer 610 is silicon nitride.

[0125] In this embodiment, barrier layer 600 has a stacked structure and further includes a second barrier layer 620 that conformally covers first barrier layer 610. The second barrier layer 620 has a greater etch resistance than the first barrier layer 610. Therefore, during etching of substrate 400, loss of barrier layer 600 is minimized, further ensuring its masking function. Specifically, second barrier layer 620 and first barrier layer 610 are made of the same material. For a detailed description of barrier layer 600, please refer to the description in the previous embodiment and will not be repeated here.

[0126] like Figure 18 As shown, the blocking structure 700 is located in the blocking groove (not shown). Specifically, the blocking structure 700 is located in the top blocking groove (i.e., the opening 505) and the bottom blocking groove 405. The blocking structure 700 is used to achieve electrical isolation between adjacent device unit areas 400a. Therefore, the material of the blocking structure 700 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride oxide. In this embodiment, the material of the blocking structure 700 is silicon oxide, thereby improving the adhesion of the blocking structure 700 in the blocking groove and reducing the probability of dislocation.

[0127] The semiconductor structure of this embodiment can be formed by the formation method described in the second embodiment, or by other formation methods. For the detailed description of the semiconductor structure of this embodiment, reference can be made to the corresponding description in the previous embodiment, and this embodiment will not be repeated here.

[0128] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate, a dielectric layer is formed on the substrate, and a material of the dielectric layer is an oxygen-containing material; forming an opening in the dielectric layer; forming a barrier layer on a sidewall of the opening by using an atomic layer deposition process, the barrier layer at least comprises a first barrier layer covering a sidewall surface of the opening, and in the process of forming the first barrier layer, the atomic layer deposition process uses a hydrogen-containing modified precursor to react with the dielectric layer containing oxygen material to form a hydroxyl bond on the sidewall surface of the opening; the modified precursor is used to provide an adsorption environment for a reaction precursor of the atomic layer deposition process; the modified precursor comprises hydrogen, deuterium or an isotope gas of hydrogen; in the step of forming the first barrier layer, the atomic layer deposition process comprises at least one sub-layer deposition process; the sub-layer deposition process comprises: introducing a first reaction precursor into a deposition chamber, the first reaction precursor is adsorbed on the sidewall surface of the opening; after the first reaction precursor is adsorbed on the sidewall surface of the opening, the excess first reaction precursor not adsorbed on the sidewall surface of the opening is discharged from the deposition chamber; after the excess first reaction precursor is discharged from the deposition chamber, a second reaction precursor and the hydrogen-containing modified precursor are introduced into the deposition chamber at the same time, the modified precursor is suitable for modifying the sidewall surface of the opening, and the second reaction precursor reacts with the first reaction precursor; the by-product after the second reaction precursor reacts with the first reaction precursor is discharged from the deposition chamber.

2. The method of forming a semiconductor structure of claim 1, wherein, The atomic layer deposition process is a plasma enhanced atomic layer deposition process.

3. The method of forming a semiconductor structure of claim 1, wherein, The gas flow of the modified precursor is 1sccm to 5sccm.

4. The method of forming a semiconductor structure of claim 1, wherein, In the step of forming the barrier layer on the sidewall of the opening by using the atomic layer deposition process, the barrier layer further comprises a second barrier layer conformally covering the first barrier layer, the first barrier layer and the second barrier layer are formed in sequence and continuously in the same deposition chamber, and the etching resistance of the second barrier layer is greater than that of the first barrier layer.

5. The method for forming a semiconductor structure according to claim 4, wherein: In the process of the atomic layer deposition process, the same reaction precursor is used to form the first barrier layer and the second barrier layer.

6. The method of forming a semiconductor structure of claim 1, wherein, The material of the first barrier layer is silicon nitride, the first reaction precursor comprises SiH2I2 or SiH2Cl2, and the second reaction precursor comprises N2 or NH3.

7. The method of forming a semiconductor structure of claim 1, wherein, The material of the dielectric layer is silicon oxide, and the material of the first barrier layer is silicon nitride.

8. The method of forming a semiconductor structure of claim 1, wherein, The parameters of the atomic layer deposition process comprise: the gas flow of the first reaction precursor is 0.001sccm to 1sccm, the gas flow of the second reaction precursor is 1sccm to 1000sccm, the source radio frequency power is 500W to 1000W, the chamber pressure is 10torr to 30torr, and the process temperature is 300℃ to 400℃.

9. The method of forming a semiconductor structure of claim 4, wherein, The thickness of the first barrier layer is 2nm to 2.5nm.

10. The method of forming a semiconductor structure of claim 1, wherein, The step of providing a substrate, a gate structure is formed on the substrate, and source-drain doped regions are formed in the substrate on both sides of the gate structure, and the dielectric layer covers the source-drain doped regions; The step of forming an opening in the dielectric layer, the opening is located on both sides of the gate structure and penetrates the dielectric layer above the source-drain doped regions; After forming the barrier layer on the sidewall of the opening, the semiconductor structure further comprises: forming a contact hole plug in the opening exposed by the barrier layer, and the contact hole plug is electrically connected to the source-drain doped regions.

11. The method of forming a semiconductor structure of claim 1, wherein, The step of providing a substrate, the substrate comprises a plurality of adjacent device unit regions and isolation regions between adjacent device unit regions, and a gate structure is formed on the substrate of the device unit regions and the isolation regions; The dielectric layer is located on the substrate exposed by the gate structure, and the dielectric layer covers the sidewall of the gate structure; The step of forming an opening in the dielectric layer comprises: removing the gate structure located in the isolation region to form an initial opening in the dielectric layer; and performing lateral etching on the sidewall of the initial opening in a direction parallel to the surface of the substrate to form an opening from the initial opening, and the opening is a top blocking trench; After forming the barrier layer on the sidewall of the opening, the semiconductor structure further comprises: etching a portion of the thickness of the substrate at the bottom of the top blocking trench using the barrier layer as a mask to form a bottom blocking trench in the substrate, the bottom blocking trench being in communication with the top blocking trench; and forming a blocking structure in the top blocking trench and the bottom blocking trench.

12. A semiconductor structure formed using the method of claims 1-11. The semiconductor structure comprises: a substrate; a dielectric layer located on the substrate, the material of the dielectric layer being an oxygen-containing material; an opening located in the dielectric layer; a barrier layer located on the sidewall of the opening, the barrier layer being formed by an atomic layer deposition process, and the barrier layer at least comprises a first barrier layer covering the surface of the sidewall of the opening, and in the process of forming the first barrier layer, the atomic layer deposition process uses a modified precursor containing hydrogen.

13. The semiconductor structure of claim 12, wherein, The barrier layer further comprises a second barrier layer conformally covering the first barrier layer, and the etching resistance of the second barrier layer is greater than that of the first barrier layer.

14. The semiconductor structure of claim 13, wherein, The material of the second barrier layer is the same as that of the first barrier layer.

15. The semiconductor structure of claim 13, wherein, The thickness of the first barrier layer is 2 nm to 2.5 nm.

16. The semiconductor structure of claim 12, wherein, The material of the dielectric layer is silicon oxide, and the material of the first barrier layer is silicon nitride.

17. The semiconductor structure of claim 12, wherein, The semiconductor structure further comprises: a gate structure located on the substrate; and source-drain doped regions located in the substrate on both sides of the gate structure; The dielectric layer covers the source-drain doped regions; The opening is located on both sides of the gate structure and penetrates the dielectric layer above the source-drain doped regions; The semiconductor structure further comprises: a contact hole plug located in the opening exposed by the first barrier layer and electrically connected to the source-drain doped regions.

18. The semiconductor structure of claim 12, wherein, The substrate comprises a plurality of adjacent device unit regions and isolation regions between adjacent device unit regions; The semiconductor structure further comprises: a gate structure located on the substrate of the device unit regions; The dielectric layer is located on the substrate exposed by the gate structure, and the dielectric layer covers the sidewall of the gate structure; The opening is located in the dielectric layer of the isolation region, and the opening serves as a top blocking groove; the semiconductor structure further comprises: a bottom blocking groove located in the substrate of the isolation region, the bottom blocking groove being in communication with the top blocking groove, and a side wall of the bottom blocking groove being flush with a side wall of the blocking layer; and a blocking structure located in the top blocking groove and the bottom blocking groove.

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