Thin film transistor array substrate for digital X-ray detector device, digital X-ray detector device and manufacturing method thereof

Abstract

This disclosure relates to a thin-film transistor array substrate for a digital X-ray detector device, the digital X-ray detector device, and a method for manufacturing the same. The thin-film transistor array substrate includes: a base substrate comprising a driving region and a non-driving region; at least one PIN diode disposed in the driving region of the base substrate and including a lower electrode, a PIN layer, and an upper electrode; and at least one alignment mark disposed in the non-driving region of the base substrate, wherein the alignment mark includes a first alignment mark layer, an alignment PIN layer, and a second alignment mark layer.

Description

Technical Field

[0001] The present disclosure relates to a thin film transistor array substrate for a digital X-ray detector device, and the digital X-ray detector device and a method for manufacturing the same capable of minimizing incorrect recognition of an alignment mark. Background Art

[0002] Since the wavelength of X-rays is short, X-rays may easily pass through an object. The transmittance of X-rays depends on the internal density of the object. Therefore, the internal structure of the object can be observed by detecting the amount of X-rays transmitted through the object.

[0003] One of the X-ray-based inspection methods used in the medical field is a film printing scheme. However, in the film printing scheme, in order to check the result, an image is taken and then a film is printed. Therefore, it takes a long time to check the result. In particular, in the film printing scheme, there are some difficulties in storing and preserving the printed film.

[0004] Digital X-ray detector (DXD) devices using thin film transistors have been developed and widely used in the medical field.

[0005] The DXD apparatus detects the transmittance of X-rays transmitted through an object, and displays the internal state of the object on a display based on the transmittance.

[0006] Therefore, the digital X-ray detector device can display the internal structure of the object without using additional film and printing paper. In addition, the DXD device can verify the results in real time immediately after the X-ray shooting. Summary of the invention

[0007] Components such as a driving thin film transistor or a PIN diode of a digital X-ray detector device may be formed by repeatedly depositing and patterning a plurality of layers using a plurality of masks.

[0008] In this case, one or more alignment marks are used to align the mask to minimize misalignment of each layer stacked sequentially.

[0009] The alignment marks are identified using a device such as a microscope or camera to determine and adjust the alignment of the mask to accurately form the layers according to the desired design.

[0010] The digital X-ray detector device detects current inside a digital X-ray detection panel to realize an image based on the current, and uses a photo PIN (P-type semiconductor-intrinsic semiconductor-N-type semiconductor) diode that responds to light.

[0011] The PIN diode includes a PIN layer which is a high deposition film having a thickness of 1 μm or more and which is formed using a dry etching gas.

[0012] In this case, due to the thick thickness of the PIN layer at a region where the PIN layer may be completely etched, the PIN layer may not be completely etched, and a PIN residual film may remain as an etching residue of the PIN layer.

[0013] If the PIN residual film covers at least a portion of the alignment mark, incorrect recognition of the alignment mark may occur, thereby reducing process accuracy after forming the PIN layer and preventing proper inspection of the digital X-ray detector panel.

[0014] Therefore, the inventors of the present disclosure have invented a thin film transistor array substrate for a digital X-ray detector device and a digital X-ray detector device capable of minimizing incorrect recognition of an alignment mark and a method of manufacturing the same.

[0015] The present disclosure provides a thin film transistor array substrate for a digital X-ray substrate and a digital X-ray detector device capable of minimizing the formation of a PIN residual film in an alignment mark and a method of manufacturing the same.

[0016] The present disclosure also provides a thin film transistor array substrate for a digital X-ray substrate and a digital X-ray detector device capable of minimizing incorrect recognition of an alignment mark after forming a PIN layer and a method of manufacturing the same.

[0017] The purpose of the present disclosure is not limited to the above-mentioned purpose, and other purposes and advantages of the present disclosure that are not mentioned can be understood by the following description, and can be more clearly understood by the embodiments of the present disclosure. It is also easy to understand that the purposes and advantages of the present disclosure can be achieved by the features described in the attached claims and their combinations.

[0018] According to an embodiment of the present disclosure, a thin film transistor array substrate for a digital X-ray detector device and a digital X-ray detector device capable of minimizing the formation of a PIN residual film in an alignment mark after forming a PIN layer and incorrect recognition of the alignment mark and a method for manufacturing the same are provided.

[0019] According to an embodiment of the present disclosure, a thin film transistor array substrate for a digital X-ray detector device and a digital X-ray detector device include: a base substrate including a driving area and a non-driving area; at least one PIN diode, arranged in the driving area of ​​the base substrate and including a lower electrode, a PIN layer and an upper electrode; and at least one alignment mark, arranged in the non-driving area of ​​the base substrate, and the alignment mark includes a first alignment mark layer, an alignment PIN layer, and a second alignment mark layer.

[0020] In this case, the first alignment mark layer, the alignment PIN layer, and the second alignment mark layer may be sequentially stacked on the base substrate.

[0021] The driving thin film transistor is disposed in a driving region of the base substrate, connected to the PIN diode, and includes an active layer, a first electrode, a second electrode, and a gate electrode, and the first alignment mark layer may be made of the same material as the gate electrode.

[0022] In addition, the PIN layer may be made of the same material as the alignment PIN layer, the bias electrode may be disposed on the PIN layer, and the second alignment mark layer may be made of the same material as the bias electrode.

[0023] In addition, according to an embodiment of the present disclosure, a method for manufacturing a thin film transistor array substrate for a digital X-ray detector device includes: i) forming a driving thin film transistor in at least one pixel in a driving area of ​​a base substrate, the driving thin film transistor including an active layer, a first electrode, a second electrode and a gate electrode, and forming a first alignment mark layer in at least one alignment mark in a non-driving area; ii) forming a lower electrode on the driving thin film transistor; iii) forming a PIN film over the entire surface of the base substrate, and forming an upper electrode film on the PIN layer; iv) forming a photoresist on the upper electrode film to correspond to each of the alignment marks and pixels; v) forming an alignment PIN layer and an alignment upper electrode layer in the alignment mark, and forming a PIN diode including a lower electrode, a PIN layer and an upper electrode in the pixel by patterning the upper electrode film and the PIN film; and vi) forming a second alignment mark layer above the alignment upper electrode layer, and forming a bias electrode above the upper electrode.

[0024] In this case, the gate electrode and the first alignment mark layer may be formed by the same patterning process, the PIN layer and the alignment PIN layer may be formed by the same patterning process, and the bias electrode and the second alignment mark layer may be formed by the same patterning process.

[0025] According to the present disclosure, an alignment PIN layer is formed over the first alignment mark layer by the same patterning process as the patterning process using the photoresist used to form the PIN layer in the pixel. Therefore, the formation of an undesirable PIN residual film can be minimized by the patterning process in the alignment mark.

[0026] Furthermore, according to the present disclosure, an alignment PIN layer is formed on the first alignment mark layer, and a second alignment mark layer is also formed, and the second alignment mark layer can be used as an alignment mark after the PIN layer is formed to minimize incorrect recognition of the alignment mark after the PIN layer is formed.

[0027] In addition to the above-described effects, specific effects of the present disclosure will be described together with specific matters for implementing the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic block diagram showing a digital X-ray detector device.

[0029] Figure 2 is a schematic plan view showing an example digital X-ray detector device.

[0030] Figure 3 is a plan view showing an example area taken along line II' of the digital X-ray detector device.

[0031] Figure 4 2 are cross-sectional views showing example regions taken along lines II-II′ and III-III′ of the digital X-ray detector device.

[0032] Figure 5A-5C A main active region of the dry etching gas and a weak region of the dry etching gas formed above the base substrate are shown.

[0033] Figure 6 A PIN (P-type semiconductor-intrinsic semiconductor-N-type semiconductor) remaining film is shown.

[0034] Fig. 7A and Figure 7B is a process diagram illustrating a PIN residual film that may be formed during a PIN layer forming process.

[0035] Fig. 8A Some areas of the alignment mark covered by the PIN residual film are shown. Figure 8B Alignment marks not covered by the PIN residual film are shown.

[0036] 9A to 9F is a process diagram illustrating an example method for manufacturing a thin film transistor array substrate for a digital X-ray detector device. DETAILED DESCRIPTION

[0037] Some embodiments of the present disclosure are described in detail with reference to the accompanying drawings. Therefore, a person skilled in the art to which the present disclosure belongs can easily implement the technical idea of ​​the present disclosure. In the description of the present disclosure, if it is determined that a detailed description of well-known technologies related to the present disclosure does not necessarily make the subject matter of the present disclosure unclear, the detailed description may be omitted. One or more embodiments of the present disclosure are described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals may be used to refer to the same or similar components.

[0038] In this document, the terms "upper", "lower", "on", "under", etc. are used, so that when a first component is arranged at the "upper portion" or "lower portion" of a second component, the first component may be arranged in contact with the upper surface (or lower surface) of the second component, or another component may be provided between the first component and the second component. Similarly, when a first component is arranged on or under a second component, the first component may be arranged directly on or under the second component (in contact with the second component), or one or more other components may be provided between the first component and the second component.

[0039] In addition, the terms "connected", "coupled", etc. are used, so that when a first component is connected or coupled to a second component, the first component can be directly connected or connectable to the second component, or one or more additional components can be set between the first and second components, or the first and second components can be connected or coupled through one or more additional components.

[0040] Hereinafter, a thin film transistor array substrate for a digital X-ray detector device, the digital X-ray detector device, and a method for manufacturing the same according to some embodiments of the present disclosure are described.

[0041] Figure 1 is a schematic block diagram showing a digital X-ray detector device. The digital X-ray detector device may include a thin film transistor array 110 , a gate driver 120 , a bias power supply 130 , a readout circuit 140 , and a timing controller 150 .

[0042] The thin film transistor array 110 may include a plurality of cell areas defined by a plurality of gate lines GL arranged along a first direction and a plurality of data lines DL arranged along a second direction orthogonal to the first direction.

[0043] The unit areas are arranged in a matrix configuration. Each unit area may include a pixel area in which a photosensitive pixel Ps is formed. The thin film transistor array 110 may detect X-rays emitted from an X-ray source, may convert the detected X-rays into electrical signals, and may output the electrical signals.

[0044] Each photosensitive pixel may include: a PIN (P-type semiconductor-intrinsic semiconductor-N-type semiconductor) diode, which converts light in the visible light region converted from X-rays by a scintillator into an electronic signal and outputs the electronic signal; and a thin film transistor TFT, which transmits the detection signal output from the PIN diode to the readout circuit 140. A first end of the PIN diode may be connected to the thin film transistor, and a second end thereof may be connected to a bias line BL.

[0045] The gate electrode of the thin film transistor can be connected to the gate line GL carrying the scan signal. The source / drain electrodes of the thin film transistor can be respectively connected to the PIN diode and the data line DL carrying the detection signal output from the PIN diode. Each bias line BL can extend to each data line DL in a parallel manner.

[0046] The gate driver 120 may sequentially apply gate signals to the thin film transistors of the light-sensitive pixels through the gate lines GL. The thin film transistors of the light-sensitive pixels may be turned on in response to the gate signals having a gate-on voltage level.

[0047] The bias power supply 130 may apply a driving voltage to the photosensitive pixel through the bias line BL. The bias power supply 130 may selectively apply a reverse bias or a forward bias to the PIN diode.

[0048] The readout circuit 140 may read out a detection signal received from a thin film transistor turned on in response to a gate signal of a gate driver. For example, a detection signal output from a PIN diode may be input to the readout circuit 140 through a thin film transistor and a data line DL.

[0049] The readout circuit 140 may have an offset readout period for reading out an offset image and an X-ray readout period for reading out a detection signal after X-ray exposure, and may read out the detection signal output from the photosensitive pixel during the X-ray readout period.

[0050] The readout circuit 140 may include a signal detector and a multiplexer. The signal detector includes a plurality of amplifying circuits corresponding to the data lines DL, respectively. Each amplifying circuit may include an amplifier, a capacitor, and a reset element.

[0051] The timing controller 150 may control the operation of the gate driver 120 by generating a start signal and a clock signal and providing each of the start signal and the clock signal to the gate driver 120. In addition, the timing controller 150 may control the operation of the readout circuit 140 by generating a readout control signal and a readout clock signal and providing each of the readout control signal and the readout clock signal to the readout circuit 140.

[0052] In the following, reference Figure 2 A digital X-ray detector device according to an embodiment of the present disclosure is described in detail.

[0053] According to one embodiment of the present disclosure, a thin film transistor array substrate for a digital X-ray detector device and the digital X-ray detector device include a base substrate having a driving area AA and a non-driving area NAA.

[0054] The driving area AA includes a plurality of pixels P, and each pixel P includes a photosensitive pixel having a driving thin film transistor and a PIN diode.

[0055] The non-driving area NAA surrounds the driving area AA.

[0056] At least one readout circuit 140 may be disposed at one side of the non-driving area NAA, for example, above the driving area AA. For example, a readout integrated circuit (ROIC) pad may be disposed.

[0057] In addition, the gate driver 120 may be disposed at one or more other sides of the non-driving area NAA where the readout circuit 140 is not disposed. For example, the gate driver 120 may be disposed on the left or right side, or both sides of the driving area.

[0058] In this case, the gate driver 120 may be arranged using a gate-in-panel (GAP) method.

[0059] The alignment mark AM may be disposed at each of a plurality of corners of the non-driving area NAA, and preferably, the alignment mark AM may be disposed at four corners of the non-driving area NAA for accuracy of alignment mark recognition and alignment mark adjustment.

[0060] In addition, at least one test element group TEG pattern may be provided in the non-driving area NAA, and the characteristics of the elements in the driving area may be determined based on the TEG pattern. Therefore, the TEG pattern may have the same pattern as each element in the pixel of the driving area.

[0061] For example, the TEG pattern may be formed in the same pattern as the photosensitive pixels in the pixel. Therefore, the TEG pattern may include a pattern for each of the driving thin film transistor and the PIN diode.

[0062] Reference below Figure 3 and Figure 4 Pixels and alignment marks of a digital X-ray detector device according to an embodiment of the present disclosure are described in detail.

[0063] According to an embodiment of the present disclosure, the digital X-ray detector 200 includes a base substrate 210 .

[0064] The base substrate 210 may be embodied as a glass substrate made of glass, but is not limited thereto. In some cases where the base substrate 210 is used for a flexible digital X-ray detector device, a substrate made of a polyimide material and having a flexible property may be used as an example of the base substrate 210 .

[0065] On the base substrate 210 , a plurality of pixels are defined by a plurality of gate lines 223 and a plurality of data lines 225 that cross each other in an orthogonal manner.

[0066] Each pixel includes a thin film transistor 220 and a PIN diode 230. A plurality of thin film transistors 220 and a plurality of PIN diodes 230 may be disposed on an array substrate having a plurality of pixels. The thin film transistor 220 and the PIN diode 230 of a pixel are described below, and unless otherwise specified, the configuration may also be applied to adjacent pixels.

[0067] The thin film transistor 220 including a first electrode 225 a , a second electrode 225 b , a gate electrode 223 a , and an active layer 221 is disposed in the driving region of the base substrate 210 .

[0068] The buffer layer 211 may be disposed between the base substrate 210 and the thin film transistor 220. In this case, the buffer layer 211 may be made of an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx), and may be provided as a multi-buffer layer consisting of a plurality of sub-layers.

[0069] The active layer 221 is disposed over the base substrate 210. The active layer 221 may be made of an oxide semiconductor material such as indium gallium zinc oxide (IGZO), but is not limited thereto, and may be made of low temperature polysilicon (LTPS) or amorphous silicon (a-Si).

[0070] The active layer 221 may include, for example, a channel region and a conductive region, wherein the channel region is disposed between the two conductive regions. In some examples, the conductive region may be divided into a first conductive region directly contacting the first electrode 225a and a second conductive region directly contacting the second electrode 225b.

[0071] The conductive region of the active layer 221 may be formed by making both ends of the active layer 221 conductive, and various types of methods such as a dry etching method, hydrogen plasma treatment, helium plasma treatment, etc. may be used as examples of a conductive treatment method.

[0072] The gate electrode 223 a is disposed over the active layer 221 , and the gate insulating layer 222 is disposed between the active layer 221 and the gate electrode 223 a to insulate the active layer 221 from the gate electrode 223 a .

[0073] For example, the gate electrode 223a may be disposed on the gate insulating layer 222 to correspond to the channel region of the active layer 221. The gate electrode 223a may be made of, but not limited to, one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), copper (Cu), and alloys thereof, and may include a single layer or a plurality of layers.

[0074] The gate electrode 223a may extend from the gate line 223. The gate line 223 and the gate electrode 223a may be integrated with each other such that the gate electrode 223a is disposed in the gate line 223. Therefore, the gate line 223 and the gate electrode 223a may be disposed on the same layer.

[0075] The gate insulating layer 222 made of an inorganic material is disposed under the gate electrode 223 a and may have an area the same as or larger than that of the gate electrode 223 a for effective insulation.

[0076] The gate electrode 223a and the gate insulating layer 222 may be disposed at the central region of the active layer 221. In this example, a first region of the active layer 221 that is exposed and not covered by the gate electrode 223a, such as a first end of the active layer 221 excluding the channel region, may be a first conductive region, and a second region of the active layer 221 that is exposed and not covered by the gate electrode 223a, such as a second end of the active layer 221 excluding the channel region, may be a second conductive region.

[0077] In this case, the first conductive region may be a drain region, and the second conductive region may be a source region.

[0078] The source region of the active layer 221 may be disposed closer to the PIN diode 230 than the drain region, but is not limited thereto, and the positions of the source region and the drain region may be interchanged.

[0079] An interlayer insulating layer 224 made of an inorganic material may be disposed on the gate electrode 223 a to cover the base substrate 210 . A first electrode 225 a and a second electrode 225 b may each be disposed on the interlayer insulating layer 224 .

[0080] The first electrode 225a may be disposed at a first side of the active layer 221, and the second electrode 225b may be disposed at a second side of the active layer 221. Thus, the gate electrode 223a may be disposed between the first electrode 225a and the second electrode 225b. A first contact hole 224a may be disposed at a region in the interlayer insulating layer 224 where the active layer 221 overlaps with the first electrode 225a, and a second contact hole 224b may be disposed at a region in the interlayer insulating layer 224 where the active layer 221 overlaps with the second electrode 225b.

[0081] In some examples, the first contact hole 224a may be disposed on the drain region of the active layer 221, and the second contact hole 224b may be disposed on the source region. Thus, the first electrode 225a is connected to the drain region of the active layer 221 through the first contact hole 224a, and the second electrode 225b is connected to the source region of the active layer 221 through the second contact hole 224b.

[0082] Therefore, the first electrode 225 a connected to the drain region may be a drain electrode, and the second electrode 225 b connected to the source region may be a source electrode.

[0083] The first electrode 225 a and the second electrode 225 b may each extend from the data line 225 , and may each be disposed on the same layer as the data line 225 .

[0084] The data line 225 may be made of, but is not limited to, one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), copper (Cu), and alloys thereof.

[0085] The first passivation layer 226 may be disposed on or above the thin film transistor 220 to cover the entire surface of the base substrate. The first passivation layer 226 may be made of an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. The first passivation layer 226 may protect the lower thin film transistor 220, for example, the active layer 221.

[0086] The PIN diode 230 is disposed on the first passivation layer 226 to be connected to the lower thin film transistor 220. The PIN diode 230 may be disposed in the pixel region.

[0087] The PIN diode 230 may include a lower electrode 231 connected to the thin film transistor 220 , a PIN layer 232 on the lower electrode 231 , and an upper electrode 233 on the PIN layer 232 .

[0088] The lower electrode 231 may be used as a pixel electrode in the PIN diode 230. Depending on the characteristics of the PIN diode 230, the lower electrode 231 may be made of an opaque metal such as molybdenum Mo or at least one of transparent oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO).

[0089] The lower electrode 231 may be connected to the second electrode 225b of the thin film transistor 220 via a third contact hole 226b which is a contact hole in the first passivation layer 226. Thus, the thin film transistor 220 may be connected to the PIN diode 230.

[0090] The PIN layer 232 may be disposed on the lower electrode 231 to convert the visible light that has been converted from the X-ray into an electrical signal. In this connection, the scintillator may convert the X-ray into the visible light.

[0091] The PIN layer 232 may be formed by sequentially stacking an N (negative) type semiconductor layer 232 n including N type impurities, an I (intrinsic) type semiconductor layer 232 i , and a P (positive) type semiconductor layer 232 p including P type impurities on the lower electrode 231 .

[0092] The I-type semiconductor layer may be relatively thicker than each of the N-type semiconductor layer and the P-type semiconductor layer. The PIN layer 232 may be made of a material capable of converting visible light converted from X-rays emitted from the X-ray source into an electrical signal, such as a-Se, HgI 2 、CdTe、PbO、PbI 2 ,BiI 3 , GaAs and Ge.

[0093] The upper electrode 233 may be disposed on the PIN layer 232. The upper electrode 233 may be made of at least one of transparent oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO), and may improve a fill factor of the PIN diode 230.

[0094] The second passivation layer 235 may be disposed above the PIN diode 230. The second passivation layer 235 may be made of an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. The second passivation layer 235 may cover up to the side surface of the PIN diode 230 to protect the side surface of the PIN diode 230 from moisture or other foreign substances.

[0095] The bias electrode 243 may be disposed on the second passivation layer 235 on the PIN diode 230. The bias electrode 243 may be connected to the upper electrode 233 of the PIN diode 230 via a fourth contact hole 235a as a contact hole in the second passivation layer 235 and may apply a bias voltage to the PIN diode 230.

[0096] The bias electrode 243 may be branched from a bias line 241 arranged parallel to the data line 225 .

[0097] In this case, the first planarization layer 237 is disposed between the second passivation layer 235 and the bias electrode 243 to cover the entire surface of the base substrate 210 including the PIN diode 230 .

[0098] The first planarization layer 237 may be made of an organic material such as PAC (Photo Acryl), but is not limited thereto.

[0099] In this case, a fifth contact hole 237a may be provided in the first planarization layer 237 to expose the upper electrode 233 to a position of the second passivation layer 235 corresponding to the fourth contact hole 235a. The bias electrode 243 may be electrically connected to the upper electrode 233 through the fourth contact hole 235a and the fifth contact hole 237a.

[0100] The second planarization layer 245 may be disposed on the bias electrode 243 to cover the entire surface of the base substrate 210 .

[0101] The second planarization layer 245 may be made of an organic material such as PAC (photo acryl), but is not limited thereto.

[0102] The scintillator layer 250 may be disposed on the second planarization layer 245 to cover the PIN diode 230 above the base substrate.

[0103] In some examples, the scintillator layer 250 is disposed over each of the thin film transistor 220 and the PIN diode 230 to cover each of the thin film transistor 220 and the PIN diode 230 .

[0104] Since the scintillator layer 250 may be directly deposited on the array substrate 201, it may be necessary to planarize the lower surface of the scintillator layer 250. Therefore, the second planarization layer 245 is formed to planarize the lower surface of the scintillator layer 250 to facilitate the formation of the scintillator layer 250 by depositing the scintillator.

[0105] The scintillator layer 250 may grow in a vertical direction to have a plurality of columnar crystal phases so that a plurality of scintillator columnar crystals may be arranged in a side-by-side manner, but is not limited thereto. The scintillator may be made of a material such as cesium iodide (CsI), but is not limited thereto.

[0106] In some examples, at least one alignment mark AM is disposed in the non-driving area NAA of the base substrate 210 , and the alignment mark AM includes a first alignment mark layer 223 ′, an alignment PIN layer 232 ′, and a second alignment mark layer 243 ′.

[0107] In this case, the first alignment mark layer 223 ′, the alignment PIN layer 232 ′, and the second alignment mark layer 243 ′ are sequentially stacked on the base substrate 210 .

[0108] In the case of the alignment mark AM, various layers may be formed between layers according to processes in addition to the first alignment mark layer 223 ′, the alignment PIN layer 232 ′, and the second alignment mark layer 243 ′, and this configuration is described in detail below.

[0109] The first alignment mark layer 223 ′ is disposed on the base substrate 210 .

[0110] The first alignment mark layer 223 ′ is a layer in which an alignment mark is recognized by the alignment mark recognition device and may have a cross-shaped pattern, but is not limited thereto.

[0111] The first alignment mark layer 223 ′ may be made of the same material as the gate electrode 223 a of the driving area AA, and may be formed through the same patterning process as the gate electrode 223 a of the driving area AA.

[0112] When the first alignment mark layer 223 ′ is formed through the same patterning process as the gate electrode 223 a , processes after the mask process for forming the gate electrode 223 a may be accurately performed by minimizing deviation with the first alignment mark layer 223 ′.

[0113] An alignment interlayer insulating layer 224 ′ may be disposed on the first alignment mark layer 223 ′, and a first alignment passivation layer 226 ′ may be disposed over the first alignment mark layer 223 ′.

[0114] The alignment interlayer insulating layer 224' may be made of the same material as the interlayer insulating layer 224 of the driving area AA, and may be formed by the same patterning process as the interlayer insulating layer 224 of the driving area AA. The first alignment passivation layer 226' may be made of the same material as the first passivation layer 226 of the driving area AA, and may be formed by the same patterning process as the first passivation layer 226 of the driving area AA.

[0115] The alignment interlayer insulating layer 224' and the first alignment passivation layer 226' may be made of a transparent inorganic material so as not to hinder recognition of the first alignment mark layer 223' even though the alignment interlayer insulating layer 224' and the first alignment passivation layer 226' may be disposed on or over the first alignment mark layer 223'.

[0116] The alignment PIN layer 232 ′ may be disposed on the first alignment passivation layer 226 ′.

[0117] The alignment PIN layer 232 ′ may be made of the same material as the PIN layer 232 in the driving area AA, and may be formed by the same patterning process as the PIN layer 232 in the driving area AA.

[0118] Therefore, the incomplete PIN residual film is not disposed in the alignment mark AM, but a complete alignment PIN layer 232' may be disposed in the alignment mark AM. Specifically, the alignment PIN layer 232' may have the same stacking structure and may be made of the same material as the PIN layer 232 including the n-type semiconductor layer 232n, the intrinsic semiconductor layer 232i, and the p-type semiconductor layer 232p in the driving area AA.

[0119] The alignment PIN layer 232 ′ is physically spaced apart from the PIN layer 232 in the driving area AA and has an island shape, such that the alignment PIN layer 232 ′ is not electrically connected to the PIN layer 232 in the driving area AA.

[0120] The alignment upper electrode layer 233 ′ may be disposed on the alignment PIN layer 232 ′.

[0121] The alignment upper electrode layer 233 ′ may be made of the same material as the upper electrode 233 in the driving area AA, and may be formed by the same patterning process as the upper electrode 233 in the driving area AA.

[0122] The alignment upper electrode layer 233 ′ is also physically spaced apart from the upper electrode 233 in the driving area AA and has an island shape such that the alignment upper electrode layer 233 ′ is not electrically connected to the upper electrode 233 in the driving area AA.

[0123] The second alignment passivation layer 235' may be disposed on the alignment upper electrode layer 233'. The second alignment passivation layer 235' may be made of the same material as the second passivation layer 235 in the driving area AA and may be formed by the same patterning process as the second passivation layer 235 in the driving area AA.

[0124] The second alignment mark layer 243 ′ may be disposed on the second alignment passivation layer 235 ′.

[0125] Similar to the first alignment mark layer 223 ′, the second alignment mark layer 243 ′ is a layer in which an alignment mark is recognized by an alignment mark recognition device, and may have a cross-shaped pattern, but is not limited thereto.

[0126] The second alignment mark layer 243 ′ may be made of the same material as the bias electrode 243 of the driving area AA, and may be formed through the same patterning process as the bias electrode 243 of the driving area AA.

[0127] Since the second alignment mark layer 243 ′ is made of the same material and formed through the same patterning process as the bias electrode 243 , processes after the mask process for forming the bias electrode 243 may be accurately performed by minimizing deviation with the second alignment mark layer 243 ′.

[0128] In particular, according to the present invention, even if the first alignment mark layer 223' is not recognized by the alignment PIN layer 232' disposed above the first alignment mark layer 223', the alignment mark can be clearly recognized by the second alignment mark layer 243' formed above the alignment PIN layer 232'. Therefore, the process after the second alignment mark layer 243' formation process can be accurately performed by minimizing the deviation by the second alignment mark layer 243'.

[0129] For example, the second alignment mark layer 243 ′ may be used as an alignment mark in a layer forming process after the PIN layer 232 forming process, after the bias electrode 243 forming process, and in an additional process such as attaching an upper substrate to the base substrate 210 .

[0130] According to an embodiment of the present invention, a thin film transistor array substrate for a digital X-ray detector device and the digital X-ray detector device are provided, which can minimize the formation of a PIN residual film in an alignment mark after a PIN layer formation process and minimize incorrect recognition of the alignment mark.

[0131] The digital X-ray detector 200 according to the present disclosure operates as follows.

[0132] X-rays are irradiated to the digital X-ray detector 200. The scintillator layer 250 converts the X-rays into visible light. The PIN layer 232 of the PIN diode 230 converts light in the visible region into an electronic signal.

[0133] For example, when light in the visible region is irradiated to the PIN layer 232, the I-type semiconductor layer is depleted by each of the N-type semiconductor layer and the P-type semiconductor layer, thereby generating an electric field therein. Then, holes and electrons generated by the light drift based on the electric field and are collected in the P-type semiconductor layer and the N-type semiconductor layer, respectively.

[0134] The PIN diode 230 converts light in the visible region into an electric signal and transmits the electric signal to the thin film transistor 220. The electric signal thus transmitted is displayed as an image signal via the data line 225 connected to the thin film transistor 220.

[0135] The effects of the present disclosure, by which the formation of the PIN residual film can be minimized, and the reasons why the PIN residual film is formed, are described in more detail below.

[0136] The PIN diode of the digital X-ray detector device includes a single-layer film having a thickness greater than that of each other element of the other display device. For example, the PIN diode of the digital X-ray detector device is formed by depositing a PIN layer including a single-layer film having a thickness of 1 μm or more.

[0137] After the PIN layer is deposited, a patterning process is performed using a mask such as a photoresist PR. The remaining area of ​​the PIN layer except for the patterned area PTA patterned by the patterning process is removed by dry etching.

[0138] In this case, the patterned area PTA may refer to an area where a mask is disposed, and may refer to a remaining area that is not etched during an etching process such as dry etching.

[0139] In some examples, the non-patterned area NPTA may refer to an area where no mask is disposed, and may refer to an area that is etched to be removed during an etching process such as dry etching.

[0140] The etching substrate is inserted into the dry etching chamber to perform a dry etching process.

[0141] In this case, if voltage is applied to both the upper and lower parts of the chamber after the dry etching gas EG is injected into the chamber, the dry etching gas EG in a plasma state is not uniformly distributed over the entire surface of the substrate but has a uniform distribution as shown in FIG. Figure 5A and Figure 5B The elliptical distribution shown in .

[0142] In this example, Figure 5A and Figure 5B In the plan view of the substrate shown, the main active area of ​​the etching gas may have an elliptical shape relative to the center of the substrate. The area outside the main active area may be a vulnerable area for the etching gas.

[0143] For example, Figure 5A The four corners of the edge area of ​​the substrate shown and Figure 5B The outer rim areas of the substrate shown below the main active area of ​​the etching gas can all be vulnerable areas of the etching gas, and the vulnerable areas of the etching gas have a low distribution density compared to the distribution density of the central area of ​​the etching gas.

[0144] Therefore, the edge of the chamber, for example, the edge of the substrate relative to the center of the substrate, may be a vulnerable area of ​​the etching gas where the influence of the etching gas is small.

[0145] Figure 5C The activation degree of the etching gas according to the patterning is shown in detail for each region.

[0146] like Figure 5C As shown, the driving thin film transistor 220, the lower electrode 231, the PIN layer 232 and the upper electrode 233 are stacked on the patterned area PTA of the base substrate 210. To this end, the PIN film 232" in the non-patterned area NPTA but not in the patterned area PTA is etched by dry etching gas EG using a mask.

[0147] When the dry etching gas EG has an elliptical density distribution, the density of the etching gas decreases relatively toward the bottom, and the density of the etching gas in the middle active region of the etching gas decreases relative to the density of the etching gas in the main active region of the etching gas, and the density of the etching gas in the fragile region of the etching gas decreases relative to the density of the etching gas in the middle active region of the etching gas.

[0148] Therefore, when etching the PIN film 232", etching can be correctly performed in the main active area of ​​the etching gas, but etching cannot be correctly performed in the intermediate active area of ​​the etching gas and the etching gas fragile area, which prevents the PIN film 232" in the non-patterned area NPTA from being completely removed and retained as a PIN residual film.

[0149] For example, to completely etch and remove the PIN film 232'', a large amount of the PIN film 232'' in the fragile area of ​​the etching gas in the non-patterned area NPTA where the etching performance is reduced can be removed more than the patterned area PTA. However, due to the low density of the etching gas, the PIN film 232'' may not be completely removed, and the PIN residual film remains.

[0150] The PIN residual film is an accidental remainder of the PIN film 232″ and may be mainly disposed on the substrate except for Figure 6 In the non-driving area NAA outside the driving area AA shown.

[0151] Fig. 7A and Figure 7B A process diagram showing a PIN residual film formed in the alignment mark AM during the formation of the PIN layer.

[0152] In the base substrate 210 , at least one driving thin film transistor 220 and a lower electrode 231 may be formed in the pixel P in the driving area AA, and a first alignment mark layer 223 ′ may be formed in the alignment mark AM in the non-driving area NAA.

[0153] The PIN film 232 ″ covers each of the lower electrode 231 and the first alignment mark layer 223 ′, and the upper electrode 233 and the photoresist PR may be formed in the pixel P in the driving area AA.

[0154] For example, a mask such as a photoresist (PR) is provided in the driving area AA, and thus the driving area corresponds to the patterned area PTA, and the PIN film 232" in the alignment mark AM in the non-patterned area NPTA is preferably completely removed.

[0155] Therefore, if Fig. 7A As shown, a larger amount of dry etching gas EG is required to completely remove the PIN film 232" in the non-patterned area NPTA compared to the patterned area PTA.

[0156] In particular, since the PIN film 232 ″ has a thick thickness of 1 to 2 μm, a large amount of dry etching gas EG is required to completely remove the PIN film 232 ″ from the non-patterned area NPTA.

[0157] For example, a method of increasing the activation time period of the dry etching gas EG may be used as a method of completely removing the PIN film 232 ″, but in this case, other metal layers in which etching is not desired may also be etched as well as the PIN film 232 ″, which may cause defects.

[0158] Therefore, it is preferred to control the density of the etching gas in a specific area rather than the activation period of the etching gas to remove the PIN film 232" while minimizing etching of other metal layers.

[0159] like Figure 7B As shown, since the alignment mark AM in the non-patterned area NPTA is disposed in a vulnerable area of ​​the etching gas, the PIN film 232 ″ is not completely etched and a PIN residual film remains.

[0160] For example, when a PIN residual film is formed on the first alignment mark layer 223 ′ in the alignment mark AM, a defect may occur because the first alignment mark layer 223 ′ cannot be correctly recognized.

[0161] Fig. 8A It is shown that a PIN residual film is formed on a portion of the region on the alignment mark layer, and the PIN residual film cannot correctly identify the alignment mark layer.

[0162] Figure 8B The PIN residual film is shown completely removed from the alignment mark layer, and the cross shape of the alignment mark layer is clearly recognized.

[0163] Reference Figure 7B , some areas of the boundary portion between the patterned area PTA and the non-patterned area NPTA may be a 'completely etched area TEA' in which etching is completely performed and the PIN film 232' is removed.

[0164] The fully etched area TEA is an area in which the etching gas that does not react in the patterned area PTA in which a small amount of etching gas reacts is concentrated on the boundary between the patterned area PTA and the non-patterned area NPTA, and the PIN residual film can be completely removed from the fully etched area TEA.

[0165] According to the present disclosure, a process may be performed as follows to minimize a phenomenon in which an alignment mark layer of the alignment mark AM in the non-patterned area NPTA is covered by a PIN residual film and is not recognized.

[0166] Figures 9A to 9F is a process diagram illustrating an example method of manufacturing a thin film transistor array substrate for a digital X-ray detector device.

[0167] like Fig. 9AAs shown, a driving thin film transistor 220 including an active layer 221, a first electrode 225a, a second electrode 225b and a gate electrode 223a is formed in each of one or more pixels P in the driving area AA of the base substrate 210. A first alignment mark layer 223' is formed in at least one alignment mark AM in the non-driving area NAA.

[0168] In this case, the gate electrode 223 a and the first alignment key layer 223 ′ are formed through the same patterning process.

[0169] like Fig. 9B As shown, a lower electrode 231 is formed on each driving thin film transistor 220 in the pixel P.

[0170] like Fig. 9C As shown, a PIN film 232 ″ is formed on the entire surface of the base substrate 210 , and an upper electrode film 233 ″ is formed on the PIN film 232 ″ to cover the first alignment mark layer 223 ′ of the alignment mark AM and the lower electrode 231 of the pixel P.

[0171] A photoresist PR is formed on the upper electrode film 233 ′ to be disposed in each of the alignment mark AM and the pixel P.

[0172] Since the photoresist PR formed as described above is used as a mask in the patterning process, a region where the photoresist PR is provided is a patterned region PTA, and a region where the photoresist PR is not provided is a non-patterned region NPTA.

[0173] like Fig.9D As shown, the upper electrode layer 233' is etched using a mask to form an alignment upper electrode film 233' in the alignment mark AM and form an upper electrode 233 in the pixel P. A wet etching method may be used together with an etching liquid to etch the upper electrode film 233', but is not limited thereto.

[0174] After etching the upper electrode film 233″, as Fig.9D As shown, the PIN film 232 ″ is patterned using a dry etching gas EG.

[0175] like Fig.9E As shown, the PIN film 232 ″ is patterned by using a dry etching gas EG, an alignment PIN layer 232 ′ is formed in the alignment mark AM, and a PIN layer 232 is formed in the pixel P. For example, the PIN layer 232 and the alignment PIN layer 232 ′ are formed by the same patterning process.

[0176] In this case, the alignment mark AM corresponds to the patterned area PTA in which the photoresist PR is formed and the PIN residual film is not disposed, and an additional alignment PIN layer 232 ′ may be formed.

[0177] In some examples, a PIN residual film can be formed in some areas (i.e., non-patterned areas NPTA) of the remaining areas of the base substrate 210 except the alignment mark AM and the pixel P, and the area between the alignment mark AM and the PIN residual film and the area between the pixel P and the PIN residual film are both fully etched areas TEA, and the boundaries of the PIN residual film can be clearly determined.

[0178] In particular, since the alignment mark AM also becomes the patterned area PTA, the dry etching gas EG that does not react in the alignment mark AM reacts at the boundary area between the alignment mark AM and the PIN residual film, and thus the boundary area between the alignment mark AM and the PIN residual film can be a fully etched area TEA to minimize the influence of the PIN residual film on the alignment mark AM.

[0179] like Fig.9F As shown, the alignment mark AM and the photoresist PR in the pixel P are removed, a second alignment mark layer 243 ′ is formed on the alignment upper electrode layer 233 ′, and a bias electrode 243 is formed on the upper electrode 233 .

[0180] In this case, the bias electrode 243 and the second alignment key layer 243 ′ are formed through the same patterning process.

[0181] The first alignment mark layer 223' may be used to adjust alignment before forming the alignment PIN layer 232', and the second alignment mark layer 243' may be used to adjust alignment by forming the second alignment mark layer 243' over the alignment PIN layer 232' of the alignment mark AM after forming the alignment PIN layer 232'.

[0182] For example, according to the present disclosure, an alignment PIN layer is formed over the first alignment mark layer by the same patterning process as that of forming a PIN layer in a pixel using a photoresist. Through the patterning process, the formation of an unwanted PIN residual film in the alignment mark can be minimized.

[0183] In addition, according to the present disclosure, an alignment PIN layer is formed on the first alignment mark layer, and then a second alignment mark layer is further formed after forming the PIN layer to use the second alignment mark layer as an alignment mark, thereby minimizing incorrect recognition of the alignment mark even after forming the PIN layer.

[0184] According to the present disclosure, in order to minimize incorrect alignment of a digital X-ray detector device, incorrect recognition of an alignment mark by a PIN residual film can be minimized, thereby obtaining high-quality images and improving the yield of digital X-ray detector panels.

[0185] According to the present disclosure, a thin film transistor array substrate for a digital X-ray detector device and the digital X-ray detector device include: a base substrate including a driving area and a non-driving area; at least one PIN diode, which is arranged in the driving area of ​​the base substrate and includes a lower electrode, a PIN layer and an upper electrode; and at least one alignment mark, which is arranged in the non-driving area of ​​the base substrate, and the alignment mark includes: a first alignment mark layer; an alignment PIN layer; and a second alignment mark layer.

[0186] In this case, the first alignment mark layer, the alignment PIN layer, and the second alignment mark layer may be sequentially stacked on the base substrate.

[0187] The non-driving region may surround the driving region, and the alignment mark may be disposed at one or more corners of the non-driving region.

[0188] The driving region of the base substrate includes an active layer, a first electrode, a second electrode, a gate electrode, and a driving thin film transistor connected to the PIN diode, and the first alignment mark layer may be made of the same material as the gate electrode.

[0189] In addition, the PIN layer may be made of the same material as the alignment PIN layer, the bias electrode is disposed over the PIN layer, and the second alignment mark layer may be made of the same material as the bias electrode.

[0190] The alignment electrode layer is disposed between the alignment PIN layer and the second alignment mark layer, and the alignment upper electrode layer may be made of the same material as the upper electrode.

[0191] The bias electrode is disposed over the PIN layer, and the second alignment mark layer may be made of the same material as the bias electrode.

[0192] In addition, according to an embodiment of the present disclosure, a method for manufacturing a thin film transistor array substrate for a digital X-ray detector device includes: i) forming a driving thin film transistor including an active layer, a first electrode, a second electrode and a gate electrode in at least one pixel in a driving area of ​​a base substrate, and setting a first alignment mark layer in at least one alignment mark in a non-driving area of ​​the base substrate; ii) forming a lower electrode on the driving thin film transistor; iii) forming a PIN film over the entire surface of the base substrate, and forming an upper electrode film on the PIN layer; iv) forming a photoresist corresponding to the alignment mark and the pixel on the upper electrode film; v) forming an alignment PIN layer and an alignment upper electrode in the alignment mark, and forming a PIN diode including a lower electrode, a PIN layer and an upper electrode in the pixel by patterning the upper electrode film and the PIN film; and vi) forming a second alignment mark layer on the alignment upper electrode, and forming a bias electrode on the upper electrode.

[0193] In this case, the gate electrode and the first alignment mark layer may be formed by the same patterning process, the PIN layer and the alignment PIN layer may be formed by the same patterning process, and the bias electrode and the second alignment mark layer may be formed by the same patterning process.

[0194] The PIN film can also be patterned using dry etching gases.

[0195] Although the present disclosure has been described with reference to the exemplary drawings, the present disclosure is not limited to the embodiments and drawings disclosed herein, and those skilled in the art may make various modifications within the scope of the technical concept of the present disclosure. In addition, even if the working effect obtained based on the configuration of the present disclosure is not explicitly described in the description of the embodiments of the present disclosure, it must be recognized that the effect can be predicted based on the corresponding configuration.

Claims

1. A thin film transistor array substrate for a digital X-ray detector device, comprising: A base substrate including a driving region and a non-driving region; At least one PIN diode is disposed in the driving region having a pixel region of the base substrate and includes a lower electrode, a PIN layer and an upper electrode; as well as at least one alignment mark disposed in the non-driving area of ​​the base substrate, The at least one alignment mark comprises a first alignment mark layer, an alignment PIN layer, and a second alignment mark layer. The completely etched area where the PIN layer is removed is arranged between the pixel area and the at least one alignment mark.

2. The thin film transistor array substrate for a digital X-ray detector device according to claim 1, wherein: The first alignment mark layer, the alignment PIN layer, and the second alignment mark layer are sequentially stacked on the base substrate.

3. The thin film transistor array substrate for a digital X-ray detector device according to claim 1, in, The non-driving area is configured to surround the driving area, and Wherein, the at least one alignment mark is arranged in at least one corner of the non-driving area.

4. The thin film transistor array substrate for a digital X-ray detector device according to claim 2, wherein: An active layer, a first electrode, a second electrode, a gate electrode, and a driving thin film transistor connected to the PIN diode are disposed in the driving region of the base substrate, and Wherein, the first alignment mark layer is made of the same material as the gate electrode.

5. The thin film transistor array substrate for a digital X-ray detector device according to claim 2, wherein: The PIN layer is made of the same material as the alignment PIN layer.

6. The thin film transistor array substrate for a digital X-ray detector device according to claim 2, in, An alignment upper electrode layer is provided between the alignment PIN layer and the second alignment mark layer, and Wherein, the alignment upper electrode layer is made of the same material as the upper electrode.

7. The thin film transistor array substrate for a digital X-ray detector device according to claim 2, in, A bias electrode is provided on the PIN layer, and Wherein, the second alignment mark layer is made of the same material as the bias electrode.

8. A digital X-ray detector device, comprising: The thin film transistor array substrate for a digital X-ray detector device according to claim 1; as well as A scintillator layer is disposed above the thin film transistor array substrate for the digital X-ray detector device.

9. A method for manufacturing a thin film transistor array substrate for a digital X-ray detector device, comprising: Forming a driving thin film transistor in at least one pixel disposed in a driving region of the base substrate, the driving thin film transistor comprising an active layer, a first electrode, a second electrode and a gate electrode, and forming a first alignment mark layer in at least one alignment mark disposed in a non-driving region; forming a lower electrode on the driving thin film transistor; forming a PIN film over the entire surface of the base substrate, and forming an upper electrode film on the PIN film; forming a photoresist on the upper electrode film to correspond to the at least one alignment mark and each of the pixels; forming an alignment PIN film and an alignment upper electrode layer in the at least one alignment mark, and forming a PIN diode including the lower electrode, the PIN layer and the upper electrode in the pixel by patterning the upper electrode film and the PIN film; as well as forming a second alignment mark layer above the alignment upper electrode layer, and forming a bias electrode above the upper electrode, The completely etched area where the PIN layer is removed is arranged between the PIN diode and the at least one alignment mark.

10. The method for manufacturing a thin film transistor array substrate for a digital X-ray detector device according to claim 9, comprising: The gate electrode and the first alignment mark layer are formed by a same patterning process. 11 . The method for manufacturing a thin film transistor array substrate for a digital X-ray detector device according to claim 9 , comprising forming the PIN layer and the alignment PIN layer by a same patterning process. 12 . The method for manufacturing a thin film transistor array substrate for a digital X-ray detector device according to claim 9 , comprising patterning the PIN film using a dry etching gas. 13 . The method for manufacturing a thin film transistor array substrate for a digital X-ray detector device according to claim 9 , comprising forming the bias electrode and the second alignment mark layer by a same patterning process.

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