TVS Diode and Component with Asymmetric Breakdown Voltage

Abstract

In one embodiment, an asymmetric TVS device may include: a semiconductor substrate including an internal region having a first polarity; and a first surface region disposed on a first surface of the semiconductor substrate, the first surface region including a second polarity opposite to the first polarity. The asymmetric TVS device may further include a second surface region including the second polarity and disposed on a second surface of the semiconductor substrate opposite to the first surface, wherein the first surface region includes a first dopant concentration and wherein the second surface region includes a second dopant concentration greater than the first dopant concentration.

Description

Technical Field

[0001] Multiple embodiments relate to the field of surge protection devices, and more particularly to overvoltage protection devices and resettable fuses. Background Art

[0002] Surge protection devices include overvoltage protection devices for protecting components, equipment, or systems from damage due to overvoltage fault conditions, and fuses for protecting components, equipment, or systems from excessive current. In the field of overvoltage protection devices, diodes (such as transient voltage suppressor (TVS) diodes) can be used for unidirectional TVS, which are most suitable for protecting circuit nodes whose signals are unidirectional or always higher or lower than a reference voltage (usually ground).

[0003] In the field of automotive circuits, protection requirements may include different breakdown voltage requirements. For example, a jump start requirement may need to maintain the voltage below a certain voltage threshold, while reverse polarity protection may require the voltage not to exceed a different voltage threshold.

[0004] In view of these and other considerations, the present disclosure is provided. Summary of the Invention

[0005] Multiple exemplary embodiments relate to improved protection devices. In one embodiment, an asymmetric transient voltage suppressor (TVS) device is provided. The asymmetric TVS device may include: a semiconductor substrate including an internal region having a first polarity; and a first surface region disposed on a first surface of the semiconductor substrate, the first surface region including a second polarity opposite to the first polarity. The asymmetric TVS device may further include: a second surface region including the second polarity and disposed on a second surface of the semiconductor substrate opposite to the first surface, wherein the first surface region includes a first dopant concentration, and wherein the second surface region includes a second dopant concentration greater than the first dopant concentration.

[0006] In yet another embodiment, a method of forming an asymmetric transient voltage suppression (TVS) device is provided. The method may include: providing a semiconductor substrate that includes a first dopant of a first polarity and defines a first surface and a second surface opposite the first surface. The method may further include: performing a first oxidation process on the semiconductor substrate, wherein a first oxide layer is formed on the first surface and a second oxide layer is formed on the second surface. The method may further include: removing the first oxide layer from at least a first region of the first surface of the semiconductor substrate; and performing a first doping process, wherein the first doping process generates a first surface region on the first surface having a first concentration of a second dopant of a second polarity opposite the first polarity. The method may additionally include: performing a second oxidation process on the semiconductor substrate, wherein a third oxide layer is formed over a first region on the first surface; and removing the second oxide layer from at least a second region of the second surface. The method may additionally include: performing a second doping process, wherein the second doping process generates a second surface region on the second surface having a second concentration of the second dopant of the second polarity that is greater than the first concentration.

[0007] In an additional embodiment, an asymmetric transient voltage suppression (TVS) device may include a semiconductor substrate that includes an internal region having a first polarity. The semiconductor substrate may include: a first surface region that is disposed on a first surface of the semiconductor substrate and includes a second polarity; and a second surface region that includes the second polarity and is disposed on a second surface of the semiconductor substrate opposite the first surface. Thus, the first surface region and the internal region define a first TVS diode having the first polarity and a first breakdown voltage, wherein the second surface region and the internal region define a second TVS diode having the second polarity and a second breakdown voltage greater than the first breakdown voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A side cross-sectional view of a protection device in accordance with multiple embodiments of the present disclosure is shown;

[0009] Figure 2A - 2I Exemplary stages of synthesis of a protection device in accordance with an embodiment of the present disclosure are shown;

[0010] Figure 3 Exemplary breakdown voltage data is provided;

[0011] Figure 4 Exemplary process flows are shown;

[0012] Figure 5 The overall structure of a mesa-type TVS embodiment is shown; and

[0013] Figure 6 Shows the overall structure of a planar TVS embodiment. Detailed implementation

[0014] This embodiment will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown. These embodiments should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope thereof to those skilled in the art. In the drawings, like reference numerals always refer to like elements.

[0015] In the following description and / or claims, the terms "on", "covering", "disposed on", and "above" may be used in the following description and claims. "On", "covering", "disposed on", and "above" may be used to indicate that two or more elements are in direct physical contact with each other. In addition, the terms "on", "covering", "disposed on", and "above" may mean that two or more elements are not in direct contact with each other. For example, "above" may mean that one element is above another element without contacting each other, and there may be another element or elements between the two elements. Further, the term "and / or" may mean "and", it may mean "or", it may mean "exclusive - or", it may mean "one", it may mean "some, but not all", it may mean "either of the two", and / or it may mean "both", although the scope of the claimed subject matter is not limited thereto.

[0016] In multiple embodiments, a protection device and component are provided for protecting electrical components, systems, or wires, such as communication lines. Multiple embodiments may include a protection device that is arranged as a double - sided transient voltage suppression (TVS) diode.

[0017] Refer to Figure 5 and Figure 6 , according to this embodiment, the double - sided transient voltage suppression (TVS) diode device may be arranged as a mesa - type device 500 or a planar device 600. Generally, in either device, a single - crystal substrate, such as silicon, may be used. As Figure 5 shown, the internal region 502 of the mesa - type device 500 may be doped as an N - type region, while the surface region 504 on the first face may be a P - type region, and the surface region 506 on the second face may also be a P - type region. As Figure 6As shown, the internal region 602 of the planar device 600 may be doped with a first dopant, such as an N-type region, while the surface region 604 on the first surface may be doped with a second dopant to form, for example, a P-type region, and the surface region 606 on the second surface may also be a P-type region. As is known in the art, the isolation structure 508 in the mesa-type device 500 may be formed differently from the isolation structure 608 in the planar device 600. As discussed below, in a double-sided mesa-type TVS device or a planar TVS device, the breakdown voltage may be designed to have different dopants on different surfaces, for example, by adjusting the dopant concentration in the surface regions.

[0018] Figure 1 A side cross-sectional view of a protection device 100 according to various embodiments of the present disclosure is shown. The protection device 100 may be formed in a substrate 102, such as single-crystalline silicon or a similar suitable semiconductor material. The protection device 100 may include a first TVS diode 140 and a second TVS diode 142, where the first TVS diode 140 and the second TVS diode 142 are integrated into a common die, i.e., the substrate 102. According to various embodiments of the present disclosure, the first TVS diode 140 may be characterized by a first breakdown voltage, and the second TVS diode may be characterized by a second breakdown voltage different from the first breakdown voltage. Thus, the protection device 100 may form an asymmetric TVS device characterized by two different breakdown voltages for voltage surges of opposite polarities.

[0019] According to various embodiments of the present disclosure, the protection device 100 includes an internal region 104, where the internal region 104 has a first polarity, such as an N-type polarity. The protection device 100 may also include a first surface region 106 disposed on a first surface 108 of the substrate 102, where the first surface region 106 includes a second polarity, such as a P-type polarity. The protection device 100 may also include a second surface region 110, which includes the second polarity and is disposed on a second surface 112 of the substrate 102 opposite to the first surface 108. Specifically, as Figure 1 shown, the internal region 104 and the first surface region 106 include a first TVS diode 140 having a first breakdown voltage, while the internal region 104 and the second surface region 110 include a second TVS diode 142 having a polarity opposite to that of the first TVS diode 140 and a second breakdown voltage different from the first breakdown voltage.

[0020] According to some non-limiting embodiments, the first breakdown voltage may be in the range of 15V - 20V, and the second breakdown voltage may be in the range of 30V - 35V. In a particular embodiment, the first breakdown voltage may be approximately 18V, and the second breakdown voltage may be approximately 33V.

[0021] Of course, depending on the application, other voltage ranges may also be used. To generate different breakdown voltages for the first TVS diode 140 and the second TVS diode 142, the first surface region 106 may have a first dopant concentration, while the second surface region 110 may have a second dopant concentration greater than the first dopant concentration. In various embodiments, the first dopant concentration may be within a suitable concentration range to generate a breakdown voltage of approximately 15V - 20V, and this concentration range will depend on the doping level of the internal region of the substrate. Similarly, the second dopant concentration may be within a suitable concentration range to generate a breakdown voltage of approximately 30V - 35V, and this concentration range will depend on the doping level of the internal region of the substrate. In a non-limiting example, the concentration of one P-type layer exhibits a maximum dopant concentration of 2E19 / cm 3 , and may exhibit a relatively deep junction depth to generate a relatively high breakdown voltage, while the other P-type layer may exhibit a maximum dopant concentration of 8E19 / cm 3 , and may exhibit a relatively shallow junction depth to generate a relatively low breakdown voltage.

[0022] Generally speaking, as will be understood by those of ordinary skill in the art, also taking into account the dopant concentration of the internal region 104, the first dopant concentration and the second dopant concentration can be adjusted to generate the target breakdown voltages of the first TVS diode and the second TVS diode.

[0023] In a given substrate, such as substrate 102, a given diode can be defined as a planar diode, where the area of the planar diode can be defined by electrically isolating components, such as isolation trenches 120 provided on the first surface 108 and isolation trenches 122 provided on the second surface 112. According to various embodiments of the present disclosure, the first surface region 106 may have a first surface area, where the second surface region 110 has a second surface area that is the same as the first surface area.

[0024] Figure 2A - 2I Exemplary stages of synthesizing a protection device according to an embodiment of the present disclosure are shown. In Figure 2A , a substrate 102, such as a single-crystalline silicon substrate, is provided. However, various embodiments are not limited thereto. The substrate 102 can be doped according to the target dopant polarity (e.g., N-type dopant) and the target level of dopant concentration. In Figure 2B , the substrate 102 is shown after an oxidation process has been performed to form an oxide layer 150. In various embodiments, the oxide layer 150 may be formed on the first surface 108 and the second surface 112.

[0025] In Figure 2C, a subsequent stage is shown in which the oxide layer 150 has been removed from the first surface 108. In different embodiments, the oxide layer 150 may be removed from the entire first surface 108 or only a portion of the first surface 108. In Figure 2D , a subsequent stage is shown in which the dopant layer 152 is formed on the first surface 108. The dopant layer 152 generally may have a polarity opposite to the polarity of the substrate 102.

[0026] In Figure 2E , a subsequent example is shown in which the first surface region 154 has been formed. The first surface region 154 may be formed of dopants having a polarity opposite to the polarity of the substrate 102 (such as a P-type polarity). The first surface region 154 may be formed by performing a drive-in anneal to drive the dopants of the dopant layer 152 into the substrate 102 to form a dopant. Thus, the layer thickness of the first surface region 154 (see D1 in Figure 1 ) may be determined in part by the layer thickness of the dopant layer 152 and the annealing scheme (one or more annealing temperatures, one or more annealing times) for the drive-in anneal. Additionally, the dopant concentration of the first surface region 154 may be determined by the layer thickness of the dopant layer 152 or the total amount of dopants in the dopant layer 152 and the annealing scheme for the drive-in anneal.

[0027] Although Figure 2D and Figure 2E do not explicitly describe forming a dopant layer on the second surface 112, in some embodiments, the formation of the dopant layer 152 may employ a process in which at least some of the dopants may be deposited on the lower surface. However, the lower surface is protected by the oxide layer 150 to prevent dopants from being driven into the substrate 102 from the second surface 112.

[0028] In Figure 2F , a second oxide layer 156 has been formed on the substrate 102. As shown, the second oxide layer 156 may cover the first surface region 154. In Figure 2G , a subsequent operation is shown in which the oxides (such as the oxide layer 150 and the second oxide layer 156) are removed from the second surface 112.

[0029] In Figure 2H , a subsequent example is shown in which the second dopant layer 158 has been deposited on the second surface 112.

[0030] In Figure 2I, a subsequent example is shown in which the second surface region 160 has been formed. The second surface region 160 can be formed of dopants having a polarity opposite to that of the substrate 102 (such as P-type polarity). The second surface region 160 can be formed by performing a push-pit annealing to drive the dopants of the dopant layer 158 into the substrate 102 to form dopant dopants. Thus, the layer thickness of the second surface region 160 (see Figure 1 D2) can be determined in part by the thickness of the dopant layer 158 and the annealing scheme for the push-pit annealing (one or more annealing temperatures, one or more annealing times). Additionally, the dopant concentration of the second surface region 160 can be determined by the thickness of the dopant layer 158 or the total amount of dopants in the dopant layer 158 and the annealing scheme for the push-pit annealing. In Figure 2I the example, the second oxide layer 156 has also been removed from the first surface 108, thereby forming a device 180 having an asymmetric breakdown voltage. A non-limiting example of a suitable annealing procedure for forming a surface region of P-type polarity (relatively high voltage layer or relatively low voltage layer) involves annealing at 1150 °C for 4 hours in a gas atmosphere. The nitrogen flow rate can be 28 S LPM (standard liters per minute), where O2 is 70 standard cubic centimeters per minute (sccm). The BBr3 material can be used as a doping source flowing at 380 sccm. Note that it may be necessary to first generate the higher voltage layer. Additionally, the basic annealing procedure outlined above can be slightly modified to generate different dopant concentrations. For example, the volumes of N2, O2, and source gas can be adjusted differently to generate different dopant concentrations and thus different breakdown voltages.

[0031] In a particular embodiment, the asymmetric TVS diode device can be arranged with a breakdown voltage suitable for automotive applications. As an example, a first diode formed on the first surface of a silicon die can be arranged with a breakdown voltage in the range of 32.8 V, while a second diode arranged on the second surface of the silicon die has a breakdown voltage of 18 V. Figure 3 Shows the breakdown voltage behavior of a semiconductor die arranged according to the above embodiment, where the opposing diodes have nominal breakdown voltages of 32.8 V and 18 V. As shown, multiple die measurements show uniform breakdown voltage values for both diodes. Additionally, it was also found that the surge capabilities meet the product specifications for this set of die.

[0032] In this example, one P-type layer has a peak dopant concentration of approximately 8E19 / cm 3 and extends to a thickness of less than 30 mm, while the other P-type layer has a peak dopant concentration of approximately 2E19 / cm 3 and extends to a greater thickness (depth).

[0033] Figure 4Illustrates process flow 400 according to an embodiment of the present disclosure. At block 410, a semiconductor substrate, such as a silicon substrate, is provided. The semiconductor substrate may be doped at a suitable doping concentration to form a breakdown diode. As an example, the semiconductor substrate may be doped to have an N-type polarity. In one example, the doping level may be such that both polar doping ranges result in a sheet resistance of 1.0 - 1.5 ohm / sq.

[0034] At block 420, a first oxidation process is performed to form an oxide layer on the semiconductor substrate. The first oxidation process may be performed by any suitable method, and in some examples, an oxide layer may be formed on the second surface and the first surface of the semiconductor substrate.

[0035] At block 430, the first oxide layer (if present) is removed from the first surface of the semiconductor substrate. In some examples, in the case where the first oxide layer initially coats the entire first surface, all or at least a portion of the first oxide layer is removed from the first surface.

[0036] At block 440, a first doping process is performed to generate a first surface region on the first surface. Thus, the first surface region is formed with a second polarity opposite to the first polarity of the substrate. In some embodiments, a suitable dopant concentration for a P-type surface region is in the range of 2E20 / cm 3 or slightly lower.

[0037] At block 450, a second oxidation process is performed to form a third oxide layer on the first surface of the semiconductor substrate. The second oxidation process may be performed by any suitable method, and in some examples, an oxide layer may be formed on the second oxide layer that already exists on the second surface of the semiconductor substrate.

[0038] At block 460, the second oxide layer is removed from the second surface of the semiconductor substrate. To the extent that the third oxide layer is present on the second oxide layer, the third oxide layer is also removed from the second surface.

[0039] At block 470, a second doping process is performed to generate a second surface region having the second polarity on the second surface. According to various embodiments, the second doping process differs from the first doping process in that the first surface region and the second surface region differ in the concentration of the dopant species of the second polarity. According to some embodiments, the depth of the first surface region may also be different from the depth of the second surface region. Thus, the first surface region and the second surface region may combine with the semiconductor substrate to form two different TVS diodes, characterized by different breakdown voltages.

[0040] Although the present embodiment has been disclosed with reference to certain embodiments, many modifications, variations, and alterations to the described embodiments are possible without departing from the scope and range of the present disclosure as defined in the appended claims. Accordingly, the present embodiment is not limited to the described embodiments, but rather has the full scope defined by the language of the appended claims and their equivalents.

Claims

1. A method of forming an asymmetric transient voltage suppression (TVS) device, comprising: Providing a semiconductor substrate, the semiconductor substrate including a first dopant of a first polarity and defining a first surface and a second surface opposite the first surface; Performing a first oxidation process on the semiconductor substrate, wherein a first oxide layer is formed on the first surface and a second oxide layer is formed on the second surface; Removing the first oxide layer from at least a first region of the first surface of the semiconductor substrate while not removing the second oxide layer from the second surface; Performing a first doping process, wherein the first doping process generates a first surface region on the first surface having a first concentration of a second dopant of a second polarity opposite to the first polarity; Performing a second oxidation process on the semiconductor substrate, wherein a third oxide layer is formed over a first region on the first surface and wherein a fourth oxide layer is formed over the second oxide layer; Removing the second oxide layer and the fourth oxide layer from at least a second region of the second surface while not removing the third oxide layer from the first surface; And Performing a second doping process, wherein the second doping process generates a second surface region on the second surface having a second concentration of the second dopant of the second polarity greater than the first concentration.

2. The method according to claim 1, wherein, The semiconductor substrate includes an N-type polarity, and wherein the first surface region and the second surface region include a P-type polarity.

3. The method according to claim 2, wherein, The semiconductor substrate includes an N-type internal region characterized by an N-type polarity after performing the first doping process and performing the second doping process.

4. The method according to claim 3, wherein The N-type internal region and the first surface region include a first TVS diode having a first breakdown voltage, and wherein the N-type internal region and the second surface region include a second TVS diode having a polarity opposite to the first TVS diode and having a second breakdown voltage different from the first breakdown voltage.

5. The method according to claim 4, wherein the first breakdown voltage is in the range of 15V to 20V and the second breakdown voltage is in the range of 30V to 35V.

6. The method according to claim 1, wherein the maximum value of the first concentration is 2E19 / cm 3 , and the maximum value of the second concentration is 8E19 / cm 3 .

7. The method according to claim 1, wherein the first surface region includes a first surface area and the second surface region includes a second surface area equal to the first surface area.

8. The method according to claim 1, wherein, Performing the first doping process includes depositing a first dopant layer having a first layer thickness and performing a first push-in annealing, and wherein performing the second doping process includes depositing a second dopant layer having a second layer thickness and performing a second push-in annealing, wherein during the first doping process, the first dopant layer is formed on the second oxide layer, and wherein removing the second oxide layer and the fourth oxide layer further includes removing the first dopant layer from at least a second region of the second surface.

9. The method according to claim 8, wherein The first layer thickness is different from the second layer thickness.

10. The method according to claim 8, wherein, The first push-in annealing is different from the second push-in annealing.

Images