A staggered stacked DDR module and thermal analysis method thereof

Abstract

The present invention provides a staggered stacked DDR module, comprising: a substrate; a multi-chip staggered stacking structure, which is formed by staggered stacking of multiple chips, wherein the multi-chip staggered stacking structure is connected to the substrate through a first adhesive layer, and each chip of the multi-chip staggered stacking structure is connected through a second adhesive layer; and a package body, which covers the multi-chip staggered stacking structure. The present invention also provides a thermal analysis method for a staggered stacked DDR module, which changes the thermal resistance of the overlapping contact area by changing the overlapping length between the stacked chips, thereby improving the heat dissipation capacity on the heat transfer path, reducing the chip junction temperature, and improving the heat dissipation reliability of the three-dimensional package.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductors, and in particular to a thermal analysis method of a staggered stacked DDR module and a heat dissipation structure thereof. Background Art

[0002] There is a common "10°C rule" in the electronics industry, which means that the failure rate of a device will increase by an order of magnitude for every 10°C increase in the ambient temperature of the device. Therefore, for the heat dissipation design of integrated circuit packaging, even if the chip junction temperature is reduced by only 1°C, it is possible to improve the overall reliability of the chip.

[0003] The rapid increase in chip packaging density has made it difficult for traditional packaging technology to meet high-performance requirements. System-in-Package (SiP) has emerged as the times require. SiP is a comprehensive reflection of the continuous innovation of packaging technology and architecture, achieving the goal of light, thin, small, high-performance and high-reliability systems. Three-dimensional stacking packaging is a common assembly form for system-level packaging. For stacked chips, the heat generated by each layer of chips will couple with each other, which can easily cause the chip to overheat and fail. Therefore, the junction temperature optimization design for three-dimensional stacking packaging is of great significance. Taking stacked DDR modules as an example, bare chips are only bonded to each other by adhesive, and the thermal coupling effect is serious, which causes the junction temperature to rise further. In severe cases, the chip will overheat and fail.

[0004] Commonly used three-dimensional stacked packaging forms include pyramid-type stacked packaging, cantilever stacked packaging, etc. Figure 1 , Figure 2 As shown. Among them, Figure 1 It is a pyramid-shaped stacked package. The size of the upper chip is smaller than that of the lower chip. The signal of the chip (die1, die2) is transmitted to the substrate through the bonding wires on the side, and finally transmitted to the PCB through the solder balls. The chips are bonded together with adhesive and wrapped with plastic packaging material to prevent interference from the external environment. Figure 2 It is a cantilever stacked package. Different from the pyramid stacked package, the chips (die1, die2) in the package are of the same size, and a silicon interposer (Si interpose) is added between the chips to make room for chip bonding.

[0005] The pyramid-type stacked package has certain requirements for the placement of chips of different sizes, and the heat dissipation channel is relatively fixed; the cantilever-type stacked package requires a silicon interposer to be added between every two layers of chips, which increases the length of the heat dissipation channel in the vertical direction. The present invention proposes a multi-layer staggered three-dimensional stacked package, which has no strict requirements on the chip size and reduces the use of silicon interposers. By optimizing the overlap length between chips, the thermal resistance is further reduced, and the chip junction temperature is lowered. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a staggered stacked DDR module and a thermal analysis method thereof, which is provided for one or more of the above-mentioned technical problems.

[0007] To achieve the above objectives, on one hand, the present invention provides a staggered stacked DDR module, comprising:

[0008] a substrate;

[0009] a multi-chip staggered stacking structure, which is formed by staggered stacking of a plurality of chips, and the multi-chip staggered stacking structure is configured on the substrate; and

[0010] A package body covers the multi-chip staggered stacking structure.

[0011] In some embodiments, the multi-chip staggered stacking structure is connected to the substrate via a first adhesive layer, and the chips in the multi-chip staggered stacking structure are connected via a second adhesive layer.

[0012] In some embodiments, the multi-chip staggered stacking structure is formed by alternately staggering a plurality of first chips and a plurality of second chips and stacking them with an offset, and the offsets of adjacent first chips and second chips are the same.

[0013] In some embodiments, the chip has a width of 5 mm, a length of 10 mm, and a thickness of 0.1 mm, the first adhesive layer has a width of 5 mm, a length of 10 mm, and a thickness of 0.02 mm, the second adhesive layer has a width of 4.5 mm, a length of 10 mm, and a thickness of 0.02 mm, the offset X between the adjacent first chip and the second chip is 2.5 mm, and the thickness of the packaging medium is 0.9 mm.

[0014] In another aspect, the present invention provides a thermal analysis method for heat dissipation of staggered stacked DDR modules, comprising:

[0015] The staggered stacked DDR modules are divided into regions, which are respectively recorded as region 1, region 2, region 3 and region 4;

[0016] Wherein, the region 1 is the packaging portion extending upward from the multi-chip staggered stacking structure, the region 2 is the chip overlapping portion of the multi-chip staggered stacking structure, and the regions 3 and 4 are respectively the chip non-overlapping portions of the multi-chip staggered stacking structure;

[0017] Obtain the thickness of the component in each area, the thermal conductivity of the component, and the cross-sectional area of ​​the heat flow path, and obtain the conduction thermal resistance of the area, which are R 区域1 , R 区域2 , R 区域3 and R 区域4 ;

[0018] By using formula I, we can get the total area thermal resistance R 区域总 ;

[0019] Wherein, formula I is: R 区域总 =R 区域1 +R 区域2 / / R 区域3 / / R 区域4 .

[0020] Among them, R 区域2 / / R 区域3 / / R 区域4 is the parallel summation formula, that is

[0021] R 区域2 / / R 区域3 / / R 区域4 =(R 区域2 ·R 区域3 ·R 区域4 ) / (R 区域3 ·R 区域4 +R 区域2 ·R 区域4 +R 区域2 ·R 区域3 ).

[0022] In some embodiments, a multi-chip staggered stacking structure is connected to the substrate via a first adhesive layer, and each chip of the multi-chip staggered stacking structure is connected via a second adhesive layer. The multi-chip staggered stacking structure is formed by a plurality of first chips and a plurality of second chips being staggered and stacked with an offset, and the offsets of adjacent first chips and second chips are the same.

[0023] In some embodiments, the components in region 1 include packaging media, the components in region 2 include overlapping portions of the chips, a first adhesive layer between the chips corresponding to the overlapping portions and the substrate, and a second adhesive layer between the chips, the components in region 3 include non-overlapping portions of the chips, a first adhesive layer between the chips corresponding to the non-overlapping portions and the substrate, and packaging media between adjacent first chips, and the components in region 4 include non-overlapping portions of the chips and packaging media between adjacent second chips.

[0024] In some embodiments, the method further includes: obtaining the thickness, length, and width of the chip, the offset between the first and second adjacent chips, the thickness, length, and width of the first adhesive layer, the thickness, length, and width of the second adhesive layer, and the thickness of the packaging medium, to obtain the thickness of the components in each area and the cross-sectional area of ​​the heat flow path.

[0025] In some embodiments, the method further includes: acquiring the thermal conductivity of the chip, the thermal conductivity of the first adhesive layer, the thermal conductivity of the second adhesive layer, and the thermal conductivity of the packaging medium to obtain the thermal conductivity of the components in each region. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic diagram of pyramid-type stacked packaging;

[0027] Figure 2 It is a schematic diagram of cantilever stacked package;

[0028] Figure 3 is an isometric view of a DDR module according to an embodiment of the present invention;

[0029] Figure 4 is a side view of a DDR module according to an embodiment of the present invention;

[0030] Figure 5 is an explanatory diagram of a DDR module according to an embodiment of the present invention;

[0031] Figure 6 is a schematic diagram of area division according to an embodiment of the present invention;

[0032] Figure 7 is a graph showing the variation trend of the total regional thermal resistance with the chip overlap length according to an embodiment of the present invention;

[0033] Figure 8 It is a three-dimensional packaging model of a DDR module with five groups of chips overlapping length according to an embodiment of the present invention;

[0034] Fig. 9 is a thermal spectrum diagram of die5 in a DDR module when the overlap length is 0.5 mm according to an embodiment of the present invention;

[0035] Fig.10 FIG. 1 is a graph showing a trend of a DDR module junction temperature changing with chip overlap length according to an embodiment of the present invention. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] This specific embodiment discloses a staggered stacked DDR module, including: a substrate; a multi-chip staggered stacking structure, which is formed by staggered stacking of multiple chips, wherein the multi-chip staggered stacking structure is connected to the substrate through a first adhesive layer, and each chip of the multi-chip staggered stacking structure is connected through a second adhesive layer; and a package body, covering the multi-chip staggered stacking structure.

[0038] It should be pointed out that:

[0039] The substrate of the embodiment of the present invention refers to but is not limited to a copper-clad laminate. The chip of the embodiment of the present invention refers to but is not limited to a bare chip, which is a chip that has not been packaged after the wafer has been cut and tested, and only has solder joints for packaging. The package of the embodiment of the present invention refers to but is not limited to epoxy molding compound, and the plastic encapsulation process is to extrude the epoxy molding compound into the mold cavity by transfer molding, and embed the semiconductor chip therein, and cross-link and cure it to form a semiconductor device with a certain structural appearance. The first adhesive layer and the second adhesive layer of the embodiment of the present invention refer to but are not limited to epoxy adhesive layers. Among them, the realization of multi-layer staggered stacking three-dimensional assembly can use single-piece sequential assembly or multiple pieces at a time assembly.

[0040] Further, in various embodiments of the multi-chip staggered stacking structure provided in the present application, the multi-chip staggered stacking structure is formed by a plurality of first chips and a plurality of second chips being staggered and stacked with an offset, and the offsets of adjacent first chips and second chips are the same.

[0041] Furthermore, in the most preferred embodiment of the staggered stacked DDR module provided in the present application, the chip has a width of 5 mm, a length of 10 mm, and a thickness of 0.1 mm, the first adhesive layer has a width of 5 mm, a length of 10 mm, and a thickness of 0.02 mm, the second adhesive layer has a width of 4.5 mm, a length of 10 mm, and a thickness of 0.02 mm, the offset X between the adjacent first chip and the second chip is 2.5 mm, and the thickness of the packaging medium is 0.9 mm.

[0042] As the most preferred embodiment of the present invention, the thermal analysis method is as follows:

[0043] like Figures 3 to 5 As shown,

[0044] The present invention takes a DDR module including 5 chips as an example (but not limited to 5 chips), and the chips in each layer are stacked alternately, and the chips are bonded together by adhesive.

[0045] Figure 3 and Figure 4 These are the isometric view and side view of the DDR module. The top chip (die5) is the IPD chip, and the remaining four layers (die1 to die4) are DDR chips. Figure 5 This is an illustration of a DDR module. The parts extending from both sides are called overlap areas. The width of the overlap area is called the chip overlap length. The part of the module consisting of bare chips and adhesive is called the contact area. adh1 to adh5 represent chip adhesive. Table 1 shows the dimensions and material parameters of each component in the DDR module. In the initial model, the length of the staggered stacking adhesive (adh1) between the bottom chip and the package substrate is 5mm, the length of the adhesive between chips (adh2 to adh5) is set to 4.5mm, and the chip overlap length is 0.5mm. Modeling was performed according to the data in Table 1, where the power consumption of the IPD chip was set to 0.1W, and the power consumption of the remaining DDR chips was set to 0.5W.

[0046]

[0047]

[0048] Table 1 Dimensions and material parameters of components in the DDR module (initial model)

[0049] Different from pyramid-type stacked packaging and cantilever-type stacked packaging, staggered stacked DDR modules use the method of stacking chips alternately. The change of the overlap length between chips will change the thermal resistance of the plastic encapsulation material in the overlap area and the thermal resistance in the contact area, thereby changing the heat flow on different heat transfer paths. The theoretical analysis model is as follows: Figure 6 shown.

[0050] Among them, the oblique line area 1 is the packaging part extending upward of the multi-chip staggered stacking structure, the oblique line area 2 is the chip overlapping part of the multi-chip staggered stacking structure, and the oblique line area 3 and the oblique line area 4 are the chip non-overlapping parts of the multi-chip staggered stacking structure respectively.

[0051] Set the chip overlap length to x (mm), then the length in area 2 is 5-x (mm). According to the calculation formula of conduction thermal resistance R = d / (λ*A), where R represents conduction thermal resistance, d is the thickness of the plate, λ is the thermal conductivity of the component, and A is the cross-sectional area of ​​the heat flow path. The change law of conduction thermal resistance of areas 1 to 4 with the chip overlap length x can be approximately obtained. Take the conduction thermal resistance calculation of areas 1 and 2 as an example:

[0052]

[0053]

[0054] The calculation methods of thermal resistance in area 3 and area 4 are similar, so the calculation results are given directly:

[0055]

[0056]

[0057] The total regional thermal resistance can be expressed as:

[0058] R 区域总 =R 区域1 +R 区域2 / / R 区域3 / / R 区域4

[0059] Substitute the calculated results of the thermal resistance of each region into the functional expression of the total thermal resistance of the region, where:

[0060] R 区域2 / / R 区域3 / / R 区域4 =(R 区域2 ·R 区域3 ·R 区域4 ) / (R 区域3 ·R 区域4 +R 区域2 ·R 区域4 +R 区域2 ·R 区域3 )

[0061] We can get:

[0062]

[0063] Convert the function expression into a function graph, such as Figure 7 shown.

[0064] Depend on Figure 7 It can be seen that when the chip overlap length increases from 0.5mm to 2.5mm, the total regional thermal resistance will continue to decrease, and the thermal coupling effect between chips will continue to decrease with the increase of chip overlap length. The combined effect of the two causes the junction temperature to continue to decrease.

[0065] Next, a 3D stacked package model of the DDR module was established in the simulation software. In the initial model, the overlap length was set to 0.5 mm and the step length was 0.5 mm (not limited to 0.5 mm). Considering the reliability of the package structure, five overlap lengths of 0.5 mm, 1 mm, 1.5 mm, 2 mm and 2.5 mm were selected for verification. Figure 8 shown.

[0066] Fig. 9 This is the thermal spectrum of the top layer (die5) in the 3D packaging model of the DDR module when the chip overlap length is 0.5mm. It can be seen from the figure that the maximum junction temperature of die5 is 74.87℃.

[0067] Table 2 gives the junction temperature values ​​of die5 in the DDR module under five groups of chip overlap lengths. In order to more clearly observe the variation trend of junction temperature with chip overlap length, the data in Table 4.3 are plotted into a two-dimensional image, as shown in Figure 8 shown.

[0068] Chip overlap length (mm) 0.5 1 1.5 2 2.5 DDR module junction temperature (℃) 74.87 74.21 73.53 72.85 72.17

[0069] Table 2 Statistics of junction temperature of top chip die5 of DDR module at different chip overlap lengths

[0070] Depend on Fig.10 It can be seen that when the chip overlap length increases from 0.5mm to 2.5mm, the temperature of the DDR module continues to decrease. When the chip overlap length is 0.5mm, the DDR module junction temperature reaches a maximum of 74.87℃. When the chip overlap length is 2.5mm, the DDR module junction temperature reaches a minimum of 72.17℃, which indicates that appropriately increasing the chip overlap length within a certain range is beneficial to the heat dissipation of stacked multi-chip packages.

[0071] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. For those skilled in the art, various changes, modifications, substitutions and variations of these embodiments are made without departing from the principles and spirit of the present invention, and still fall within the scope of protection of the present invention.

Claims

1. A thermal analysis method for staggered stacked DDR modules, characterized in that: include: The staggered stacked DDR modules are divided into regions, which are respectively recorded as region 1, region 2, region 3 and region 4; Wherein, the region 1 is the packaging portion extending upward from the multi-chip staggered stacking structure, the region 2 is the chip overlapping portion of the multi-chip staggered stacking structure, and the regions 3 and 4 are respectively the chip non-overlapping portions of the multi-chip staggered stacking structure; Obtain the thickness of the component in each area, the thermal conductivity of the component, and the cross-sectional area of ​​the heat flow path, and obtain the conduction thermal resistance of the area, which are R 区域1 , R 区域2 , R 区域3 and R 区域4 ; By using formula I, we can get the total area thermal resistance R 区域总 ; Among them, formula I is: ; Wherein, the staggered stacked DDR module comprises: a substrate; a multi-chip staggered stacking structure, which is formed by alternately staggering a plurality of first chips and a plurality of second chips and stacking them with an offset, wherein the offsets of adjacent first chips and second chips are the same, wherein the multi-chip staggered stacking structure is connected to the substrate via a first adhesive layer, and wherein the chips in the multi-chip staggered stacking structure are connected to each other via a second adhesive layer; and A packaging body, covering the multi-chip staggered stacking structure; The chip has a width of 5 mm, a length of 10 mm, and a thickness of 0.1 mm; the first adhesive layer has a width of 5 mm, a length of 10 mm, and a thickness of 0.02 mm; the second adhesive layer has a width of 4.5 mm, a length of 10 mm, and a thickness of 0.02 mm; the offset X between the adjacent first chip and the second chip is 2.5 mm; and the thickness of the packaging medium is 0.9 mm.

2. The thermal analysis method according to claim 1, characterized in that The components in area 1 include packaging media, the components in area 2 include overlapping portions of the chips, a first adhesive layer between the chips corresponding to the overlapping portions and a substrate, and a second adhesive layer between the chips, the components in area 3 include non-overlapping portions of the chips, a first adhesive layer between the chips corresponding to the non-overlapping portions and a substrate, and packaging media between adjacent first chips, and the components in area 4 include non-overlapping portions of the chips and packaging media between adjacent second chips.

3. The thermal analysis method according to claim 2, characterized in that: Also includes: The thickness, length, and width of the chip, the offset between the first and second adjacent chips, the thickness, length, and width of the first adhesive layer, the thickness, length, and width of the second adhesive layer, and the thickness of the packaging medium are obtained to obtain the thickness of the components in each area and the cross-sectional area of ​​the heat flow path.

4. The thermal analysis method according to claim 2, characterized in that: Also includes: The thermal conductivity of the chip, the thermal conductivity of the first adhesive layer, the thermal conductivity of the second adhesive layer and the thermal conductivity of the packaging medium are obtained to obtain the thermal conductivity of the components in each area.

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