Semiconductor device

Abstract

A semiconductor device includes a lower structure, a stack structure on the lower structure and extending from a memory cell region into a connection region, a gate contact plug in the connection region on the stack structure, and a memory vertical structure in the memory cell region through the stack structure, wherein the stack structure includes alternately stacked interlayer insulating layers and horizontal layers, wherein, in the connection region, the stack structure includes a stepped region and a flat region, wherein the stepped region includes a lowered pad, wherein the flat region includes a flat pad region, a flat edge region, and a flat dummy region between the flat pad region and the flat edge region, and wherein the gate contact plug includes a first gate contact plug on the pad, a flat contact plug on the flat pad region, and a flat edge contact plug on the flat edge region.

Description

TECHNICAL FIELD

[0001] Example embodiments relate to semiconductor devices, and more particularly, to semiconductor devices including a stack structure having a flat region in a connection region adjacent to a memory cell array region. BACKGROUND

[0002] A semiconductor device can include gate electrodes stacked in a vertical direction from a surface of a semiconductor substrate. To achieve a high integration density of such a semiconductor device, the number of stacked gate electrodes can be increased. SUMMARY

[0003] According to an example embodiment, a semiconductor device includes a lower structure, a stack structure disposed in a memory cell array region on the lower structure and extending from the memory cell array region into a connection region, an upper insulating layer on the stack structure, a gate contact plug in the connection region, and a memory vertical structure through the stack structure in the memory cell array region, wherein the stack structure includes a plurality of interlayer insulating layers and a plurality of horizontal layers, wherein the plurality of interlayer insulating layers and the plurality of horizontal layers are alternately stacked on the lower structure in the memory cell array region and extend into the connection region on the lower structure adjacent to the memory cell array region, wherein, in the connection region, a first cross-sectional structure of the stack structure includes a first gate staircase region and a first gate flat region adjacent to the first gate staircase region, wherein the first gate staircase region includes first gate pads lowered in a first horizontal direction with a first height therebetween, wherein the first horizontal direction points to the connection region in the memory cell array region, wherein the first gate flat region includes a first gate flat pad region, a first gate flat edge region, and a first gate flat dummy region disposed between the first gate flat pad region and the first gate flat edge region, and wherein the gate contact plug includes a plurality of first gate contact plugs in contact with the first gate pads on the first gate pads, a plurality of flat contact plugs in contact with the first gate flat pad region on the first gate flat pad region, and an edge flat contact plug in contact with the first gate flat edge region on the first gate flat edge region.

[0004] According to an example embodiment, a semiconductor device includes a lower structure; a stack structure disposed in a memory cell array region on the lower structure and extending from the memory cell array region into a connection region; a gate contact plug in the connection region on the stack structure; and a memory vertical structure through the stack structure in the memory cell array region, wherein the stack structure includes a plurality of interlayer dielectric layers and a plurality of horizontal layers stacked alternately, wherein, in the connection region, the stack structure includes a stepped region and a flat region adjacent to the stepped region, wherein the stepped region includes pads lowered in a first horizontal direction, wherein the flat region includes a flat pad region, a flat edge region, and a flat dummy region disposed between the flat pad region and the flat edge region, and wherein the gate contact plug includes first gate contact plugs on the pads, a plurality of flat contact plugs on the flat pad region, and a flat edge contact plug on the flat edge region.

[0005] According to an example embodiment, a semiconductor device includes a lower structure; a stack structure disposed in a memory cell array region on the lower structure and extending from the memory cell array region into a connection region; a gate contact plug in the connection region on the stack structure; and a memory vertical structure through the stack structure in the memory cell array region, wherein the stack structure includes a plurality of interlayer dielectric layers and a plurality of horizontal layers stacked alternately, wherein, in the connection region, the stack structure includes a stepped region and a flat region adjacent to the stepped region, wherein the stepped region includes pads lowered in a first horizontal direction, wherein the flat region includes a flat pad region, a flat edge region, and a flat dummy region disposed between the flat pad region and the flat edge region, and wherein the gate contact plug includes first gate contact plugs on the pads, a plurality of flat contact plugs on the flat pad region, and a flat edge contact plug on the flat edge region. BRIEF DESCRIPTION OF DRAWINGS

[0006] The features will become apparent to one skilled in the art upon examination of the detailed description of the exemplary embodiments taken in connection with the accompanying drawings, in which:

[0007] FIGS. 1A-5B is a diagram illustrating a semiconductor device according to an example embodiment;

[0008] FIG. 6 is a cross-sectional view illustrating an example of a part of elements of a semiconductor device according to an example embodiment;

[0009] FIG. 7A and FIG. 7B is an enlarged cross-sectional view illustrating a modified example of a semiconductor device according to an example embodiment;

[0010] FIG. 8 is a plan view illustrating a modified example of a semiconductor device according to an example embodiment;

[0011] FIGS. 9-10B is a diagram illustrating a modified example of a semiconductor device according to an example embodiment; and

[0012] FIGS. 11A-12C is a diagram illustrating an example of a stage in a method of manufacturing a semiconductor device according to an example embodiment. DETAILED DESCRIPTION

[0013] Hereinafter, the embodiments will be described below with reference to the accompanying drawings.

[0014] In the following description, reference will be made to FIG. 1A and FIG. 1B a planar structure of a semiconductor device will be described. FIG. 1A and FIG. 1B is a plan view illustrating a semiconductor device according to an example embodiment, FIG. 1A illustrates a plan view which illustrates FIG. 1B a part of elements illustrated in

[0015] With reference to FIG. 1A and FIG. 1B , a memory cell array region MA and a connection region EA, for example, adjacent to the memory cell array region MA along a first horizontal direction X, can be provided. A stack structure ST' can be provided in the memory cell array region MA and can extend into the connection region EA. The stack structure ST' can include a gate region GA and an insulating region IA. An inner region indicated by a broken line in FIG. 1A and FIG. 1B relates to the insulating region IA, for example, in FIG. 1A and FIG. 1BThe portion of the broken line indicated as "IA" and facing the gate region GA can be understood as a boundary with the gate region GA. The insulating region IA can be provided in the connection region EA. The insulating region IA can be spaced apart from the memory cell array region MA.

[0016] A plurality of separation structures 62B, 62S1, and 62S2 can be provided. The plurality of separation structures 62B, 62S1, and 62S2 can include a block separation structure 62B, a first auxiliary separation structure 62S1, and a second auxiliary separation structure 62S2. The plurality of separation structures 62B, 62S1, and 62S2 can be formed of the same material.

[0017] For example, each of the plurality of separation structures 62B, 62S1, and 62S2 can be formed of an insulating material such as silicon oxide or the like. In another example embodiment, each of the plurality of separation structures 62B, 62S1, and 62S2 can be configured to include a conductive material and an insulating material between the conductive material and the stack structure ST'.

[0018] The block separation structure 62B can continuously span, for example, the memory cell array region MA and the connection region EA in a first horizontal direction X, and can separate, for example, each of the memory cell array region MA and the connection region EA in a second horizontal direction Y perpendicular to the first horizontal direction X.

[0019] The first auxiliary separation structure 62S1 can span the memory cell array region MA, and can extend, for example, partially into the connection region EA. The second auxiliary separation structure 62S2 can be spaced apart from the memory cell array region MA, and can be provided in the connection region EA. The first auxiliary separation structure 62S1 and the second auxiliary separation structure 62S2 can be provided between, for example, adjacent block separation structures among the block separation structures 62B.

[0020] The block separation structure 62B can include a first block separation structure 62B1, a second block separation structure 62B2, and a third block separation structure 62B3 arranged in order (e.g., sequentially) in the second horizontal direction Y.

[0021] The first auxiliary separation structure 62S1 can be provided between the first block separation structure 62B1 and the second block separation structure 62B2, and can be provided between the second block separation structure 62B2 and the third block separation structure 62B3. In an example embodiment, the second auxiliary separation structure 62S2 can not be provided between the first block separation structure 62B1 and the second block separation structure 62B2, and can be provided between the second block separation structure 62B2 and the third block separation structure 62B3.

[0022] In an example embodiment, the insulating separation pattern 34 (in FIG. 1BThe insulating region IA can be provided between the second block separation structure 62B2 and the first auxiliary separation structure 62S1, which are adjacent to each other in the second horizontal direction Y. The insulating separation pattern 34 (in FIG. 1B The insulating region IA can span the memory cell array region MA and can extend into the connection region EA.

[0023] The insulating region IA can be provided, for example, only in the connection region EA, for example, among the memory cell array region MA and the connection region EA. In the stack structure ST', a region other than the insulating region IA can be defined as a gate region GA. For example, in the connection region EA, a region other than the insulating region IA (for example, a portion of the connection region EA between adjacent dashed-line boxes) is a portion of the gate region GA. FIG. 1A and FIG. 1B A region other than the insulating region IA (indicated by a dashed-line box in

[0024] In an example embodiment, the insulating region IA can be provided between the first block separation structure 62B1 and the second block separation structure 62B2, and can not be provided between the second block separation structure 62B2 and the third block separation structure 62B3. The insulating region IA can be spaced apart from the first auxiliary separation structure 62S1 and the insulating separation pattern 34 (in FIG. 1B In an example embodiment, each block separation structure 62B can be provided between the insulating region IA and the second auxiliary separation structure 62S2 adjacent to each other in the second horizontal direction Y.

[0025] In the connection region EA, the stack structure ST' can have a stepped structure. In the connection region EA, the stack structure ST' can include a plurality of flat regions FAa, FAb, and FAc. For example, the stack structure ST' can include an upper flat region FAa, one or more intermediate flat regions FAb, and a lower flat region FAc provided in order (for example, sequentially) in a direction away from the memory cell array region MA in the first horizontal direction X.

[0026] In the following description, a semiconductor device will be described with reference to FIG. 1C , FIG. 1D and FIGS. 2A-3B together with FIG. 1A and FIG. 1B . FIG. 1C is an enlarged plan view of a portion "A" in FIG. 1B , FIG. 1D is an enlarged plan view of a portion "B" in FIG. 1B , FIG. 2A is a cross-sectional view along line I-I in FIG. 1B , FIG. 2B is an enlarged view of a portion "C" in FIG. 2A ,FIG. 3A is a cross-sectional view along the line II-II in FIG. 1B FIG. 3B is a plan view of the portion "D" shown in FIG. 3A

[0027] Referring to FIGS. 1A-3B , an integrated circuit region 7 can be provided on a lower substrate 5. The lower substrate 5 can be configured as a semiconductor substrate (e.g., a single-crystal silicon substrate). The integrated circuit region 7 can include circuit wiring 8 and a lower insulating layer 9 covering the circuit wiring 8. The circuit wiring 8 can include a peripheral contact pad 8P. An upper substrate 12 can be provided on the integrated circuit region 7. The upper substrate 12 can include, for example, polysilicon. A gap-filling insulating layer 13 can be provided through the upper substrate 12. In an example embodiment, the gap-filling insulating layer 13 can be formed of an insulating material such as silicon oxide. The lower structure 3 can include the lower substrate 5, the integrated circuit region 7, the upper substrate 12, and the gap-filling insulating layer 13.

[0028] For example, a plurality of gap-filling insulating layers 13 can be provided under the insulating region IA provided between a pair of block separation structures 62B adjacent to each other. In another example, the gap-filling insulating layer 13 can be configured to have a linear shape extending in the first horizontal direction X under the insulating region IA provided between a pair of block separation structures 62B adjacent to each other.

[0029] A memory cell array region MA and a connection region EA can be defined on the upper substrate 12. A stacked structure ST' can be provided in the memory cell array region MA on the upper substrate 12 and can extend into the connection region EA on the upper substrate 12. The first horizontal direction X can be parallel to an upper surface of the upper substrate 12.

[0030] A first upper insulating layer 33 can be provided on the stacked structure ST'. A memory vertical structure 36 can be provided through the first upper insulating layer 33 and the stacked structure ST'. A second upper insulating layer 53 can be provided on the first upper insulating layer 33. A plurality of separation structures 62B, 62S1, and 62S2 can penetrate the second upper insulating layer 53, the first upper insulating layer 33, and the stacked structure ST'. A third upper insulating layer 65 can be provided on the second upper insulating layer 53. A bit line contact plug 72 can be provided through the second upper insulating layer 53 and the third upper insulating layer 65 and electrically connected to the memory vertical structure 36. A bit line 74b can be provided on the bit line contact plug 72. The first to third upper insulating layers 33, 53, and 65 can be formed of an insulating material such as silicon oxide.

[0031] ​​The stack structure ST' can include the interlayer insulating layers 20 and the horizontal layers 23 which are alternately stacked. The interlayer insulating layers 20 and the horizontal layers 23 can be alternately stacked in the vertical direction Z in the memory cell array region MA and can extend from the memory cell array region MA into the connection region EA. The vertical direction Z can be perpendicular to an upper surface of the lower structure 3. The horizontal layers 23 can include pad regions which are formed in a stepped shape in the connection region EA.

[0032] The stack structure ST' can include a lower stack structure ST1' and an upper stack structure ST2' disposed on the lower stack structure ST1'.

[0033] The lower stack structure ST1' can include the first interlayer insulating layers 20a and the lower horizontal layers 23Ga and 23Ia which are alternately stacked. The lowermost layer among the first interlayer insulating layers 20a and the lower horizontal layers 23Ga and 23Ia can be a lower interlayer insulating layer, and the uppermost layer can be a lower horizontal layer. The lower stack structure ST1' can further include the second interlayer insulating layer 20b which covers the first interlayer insulating layers 20a and the lower horizontal layers 23Ga and 23Ia.

[0034] The upper stack structure ST2' can include a plurality of horizontal layers 23G and 23I which are stacked in the vertical direction Z and spaced apart from each other. The upper stack structure ST2' can further include a plurality of third interlayer insulating layers 20c which are alternately stacked with the plurality of horizontal layers 23G and 23I. The interlayer insulating layers 20 can include the first to third interlayer insulating layers 20a, 20b, and 20c. The interlayer insulating layers 20 can be formed of an insulating material such as silicon oxide.

[0035] The plurality of horizontal layers 23G and 23I can include a plurality of intermediate horizontal layers 23Gb and 23Ib, an upper horizontal layer 23Gc disposed on the plurality of intermediate horizontal layers 23Gb and 23Ib, and floating horizontal layers 23Gf and 23If disposed on the plurality of intermediate horizontal layers 23Gb and 23Ib. The horizontal layers 23 can include the lower horizontal layers 23Ga and 23Ia, the intermediate horizontal layers 23Gb and 23Ib, the upper horizontal layer 23Gc, and the floating horizontal layers 23Gf and 23If.

[0036] The intermediate horizontal layers 23Gb and 23Ib can be stacked in the vertical direction Z and spaced apart from each other in the memory cell array region MA and can extend into the connection region EA. The upper horizontal layer 23Gc can be stacked in the vertical direction Z and spaced apart from each other in the memory cell array region MA and can extend into the connection region EA.

[0037] Each of the upper horizontal layers 23Gc can have a length shorter than that of each of the middle horizontal layers 23Gb and 23Ib in the first horizontal direction X. The floating horizontal layers 23Gf and 23If can be stacked along the vertical direction Z in the connection region EA and spaced apart from each other. The floating horizontal layers 23Gf and 23If can face the upper horizontal layers 23Gc, for example, each of the floating horizontal layers 23Gf and 23If can be at the same level as and face a corresponding one of the upper horizontal layers 23Gc with a predetermined distance therebetween.

[0038] In the stacked structure ST', the horizontal layers 23 provided in the gate regions GA can be gate horizontal layers 23G, and the horizontal layers 23 provided in the insulating regions IA can be insulating horizontal layers 23I. Thus, the gate horizontal layers 23G and the insulating horizontal layers 23I can contact each other at the boundaries between the gate regions GA and the insulating regions IA provided in the connection region EA, for example, each insulating horizontal layer 23I can directly contact a corresponding one of the gate horizontal layers 23G at the boundary between the gate region GA and the insulating region IA and extend from the corresponding gate horizontal layer in the first horizontal direction X in the insulating region IA. For example, referring to FIG. 1B 、 FIG. 2A and FIG. 3A , the insulating horizontal layers 23I can directly extend from a corresponding one of the gate horizontal layers 23G only at the insulating regions IA of the connection region EA in both the lower stacked structure ST1' and the upper stacked structure ST2', for example, the gate horizontal layers 23G can extend in the connection region EA parallel to the insulating horizontal layers 23I between adjacent insulating regions IA (e.g., between the dashed regions of FIG. 1A .

[0039] A lower one of the horizontal layers 23 provided in the gate regions GA can be a lower gate horizontal layer 23Ga, and a lower one of the horizontal layers 23 provided in the insulating regions IA can be a lower insulating horizontal layer 23Ia. Similarly, a middle one of the horizontal layers 23 provided in the gate regions GA can be a middle gate horizontal layer 23Gb, and a middle one of the horizontal layers 23 provided in the insulating regions IA can be a middle insulating horizontal layer 23Ib. An upper one of the horizontal layers 23 can be provided in the gate regions GA and can be an upper gate horizontal layer. In the following description, the upper horizontal layer 23Gc is referred to as the upper gate horizontal layer. The floating horizontal layers among the horizontal layers 23 can include floating gate horizontal layers 23Gf FIG. 2A provided in the gate regions GA and floating insulating horizontal layers 23If FIG. 3A provided in the insulating regions 1A.

[0040] The horizontal layer 23 can include a gate horizontal layer 23G and an insulating horizontal layer 23I. The gate horizontal layer 23G can include a lower gate horizontal layer 23Ga, an intermediate gate horizontal layer 23Gb, an upper gate horizontal layer 23Gc, and a floating gate horizontal layer 23Gf. The insulating horizontal layer 23I (in FIG. 3A the middle) can include a lower insulating horizontal layer 23Ia, an intermediate insulating horizontal layer 23Ib, and a floating insulating horizontal layer 23If.

[0041] In an example embodiment, the insulating horizontal layer 23I can be formed of an insulating material having etching selectivity with respect to the interlayer insulating layer 20, for example, by silicon nitride. In an example embodiment, the gate horizontal layer 23G can include a conductive material.

[0042] Referring to FIG. 2A , the gate horizontal layer 23G can include pad regions formed in a stepped shape in the connection region EA.

[0043] The intermediate gate horizontal layer 23Gb can include an intermediate gate pad GPb lowered in the first horizontal direction X with a first difference in height therebetween, and a first lower gate pad GPc1 lowered in the first horizontal direction X with a second difference in height therebetween. The second height can be smaller than the first height.

[0044] The upper gate horizontal layer 23Gc can include upper gate pads GPa lowered in the first horizontal direction X with a difference in the second height in order, and the floating gate horizontal layer 23Gf can include floating gate pads GPf lowered in the first horizontal direction X with a difference in the second height in order. The lower gate horizontal layer 23Ga can include a second lower gate pad GPc2 lowered in the first horizontal direction X with a difference in the second height in order. Accordingly, the first height between the intermediate gate pads GPb adjacent to each other can be greater than the second height between the second lower gate pads GPc2 adjacent to each other.

[0045] A region in which the upper gate pad GPa is formed can be defined as an upper gate stepped region GSA, a region in which the floating gate pad GPf is formed can be defined as a floating gate stepped region GSf, a region in which the intermediate gate pad GPb is formed can be defined as an intermediate gate stepped region GSb, a region in which the first lower gate pad GPc1 is formed can be defined as a first lower gate stepped region GSc1, and a region in which the second lower gate pad GPc2 is formed can be defined as a second lower gate stepped region GSc2.

[0046] The gate region GA of the stacked structure ST' can include gate flat regions GFa, GFb, and GFc. The gate flat regions GFa, GFb, and GFc can include an upper gate flat region GFa, an intermediate gate flat region GFb, and a lower gate flat region GFc, which are sequentially arranged in the first horizontal direction X.

[0047] The upper gate flat region GFa can be arranged between the floating gate step region GSf and the intermediate gate step region GSb. The upper gate flat region GFa (in FIG. 1C and FIG. 2A ) can include an upper gate flat dummy region GFd1 (in FIG. 1C and FIG. 2A ) and an upper gate flat edge region GFe1 (in FIG. 1C and FIG. 2A ). The lower gate flat region GFc can be arranged between a first lower gate step region GSc1 and a second lower gate step region GSc2.

[0048] In an example embodiment, a first dummy pattern 24dc can be arranged between the lower gate flat region GFc and the first lower gate step region GScl. The first dummy pattern 24dc can be arranged on the second interlayer insulating layer 20b. In an example embodiment, the first dummy pattern 24dc can be formed of a conductive material.

[0049] A plurality of intermediate gate step regions GSb can be arranged. In an example embodiment, a plurality of intermediate gate flat regions GFb can be arranged. One of the intermediate gate flat regions GFb can be arranged between intermediate gate step regions GSb adjacent to each other among the intermediate gate step regions GSb. Thus, one or more intermediate gate flat regions GFb can be arranged. The intermediate gate step regions GSb can be sequentially arranged in the first horizontal direction X and can include a first gate step region GSb and a second gate step region GSb, which are sequentially arranged in the first horizontal direction X and have substantially the same cross-sectional structure, and one of the intermediate gate flat regions GFb can be arranged between the first gate step region GSb and the second gate step region GSb.

[0050] In the following description, the intermediate gate flat region GFb will be described with reference to FIG. 1D and FIG. 2B .

[0051] With reference to FIG. 1D and FIG. 2BEach of the intermediate gate pads GPb can have a first length La in the first horizontal direction X. The intermediate gate flat region GFb can include an intermediate gate flat pad region GFp2, an intermediate gate flat edge region GFe2, and an intermediate gate flat dummy region GFd2 disposed between the intermediate gate flat pad region GFp2 and the intermediate gate flat edge region GFe2. The intermediate gate flat pad region GFp2, the intermediate gate flat dummy region GFd2, and the intermediate gate flat edge region GFe2 can be sequentially (e.g., sequentially) disposed in the first horizontal direction X.

[0052] The intermediate gate flat pad region GFp2 can have a second length Lp in the first horizontal direction X that is greater than the first length La. The intermediate gate flat edge region GFe2 can have a third length Lc in the first horizontal direction X that is greater than the first length La. The intermediate gate flat dummy region GFd2 can have a fourth length Ld in the first horizontal direction X that is greater than each of the second length Lp and the third length Lc.

[0053] In an example embodiment, the second length Lp of the intermediate gate flat pad region GFp2 can be greater than the third length Lc of the intermediate gate flat edge region GFe2. In another example embodiment, the third length Lc of the intermediate gate flat edge region GFe2 can be the same as the second length Lp of the intermediate gate flat pad region GFp2. Thus, the second length Lp of the intermediate gate flat pad region GFp2 can be equal to or greater than the third length Lc of the intermediate gate flat edge region GFe2.

[0054] In an example embodiment, the fourth length Ld of the intermediate gate flat dummy region GFd2 can be greater than a sum of the second length Lp of the intermediate gate flat pad region GFp2 and the third length Lc of the intermediate gate flat edge region GFe2. In another example embodiment, the fourth length Ld of the intermediate gate flat dummy region GFd2 can be the same as the sum of the second length Lp of the intermediate gate flat pad region GFp2 and the third length Lc of the intermediate gate flat edge region GFe2. Thus, the fourth length Ld can be equal to or greater than the sum of the second length Lp and the third length Lc.

[0055] Each of the gate horizontal layers 23G can have a first thickness t1. Each of the intermediate gate flat pad region GFp2, the intermediate gate flat edge region GFe2, and the intermediate gate flat dummy region GFd2 can have a second maximum thickness t2 that is greater than the first thickness t1.

[0056] The gate horizontal layer 23G can include an electrically conductive material. The middle gate flat pad region GFp2 and the middle gate flat edge region GFe2 can include an electrically conductive material. The middle gate flat dummy region GFd2 can not include an electrically conductive material and can be filled with an insulating material. For example, the middle gate flat pad region GFp2 can include a first electrically conductive layer, the middle gate flat edge region GFe2 can include a second electrically conductive layer, the middle gate flat dummy region GFd2 can include an insulating material, and the insulating material of the middle gate flat dummy region GFd2 can separate the first electrically conductive layer of the middle gate flat pad region GFp2 and the second electrically conductive layer of the middle gate flat edge region GFe2 from each other in the first horizontal direction X, such that the first electrically conductive layer and the second electrically conductive layer can be spaced apart from each other in the first horizontal direction X. The first electrically conductive layer and the second electrically conductive layer can include the same electrically conductive material.

[0057] The insulating material of the middle gate flat dummy region GFd2 can be part of the first upper insulating layer 33. Thus, the portion of the first upper insulating layer 33 extending to the region between the middle gate flat pad region GFp2 and the middle gate flat edge region GFe2 can be defined as the middle gate flat dummy region GFd2.

[0058] The gate contact plugs 70g1, 70g2, 70d1, and 70d2 can be disposed in the connection region EA. In an example embodiment, the gate contact plugs can include first gate contact plugs 70g1 on the upper gate pad GPa (in the FIG. 2A The gate contact plugs 70g1, 70g2, 70d1, and 70d2 can be disposed in the connection region EA. In an example embodiment, the gate contact plugs can include first gate contact plugs 70g1 on the upper gate pad GPa (in the

[0059] In an example embodiment, the gate contact plugs can further include a plurality of flat contact plugs 70g2 and 70d1 in contact with the middle gate flat pad region GFp2 on the middle gate flat pad region GFp2. The plurality of flat contact plugs 70g2 and 70d1 can include a second middle gate contact plug 70g2 and a first dummy gate contact plug 70d1 disposed in sequence in the first horizontal direction X.

[0060] In an example embodiment, the gate contact plug can further include an edge flat contact plug 70d2 in contact with the middle gate flat edge region GFe2 on the middle gate flat edge region GFe2. The edge flat contact plug 70d2 can be referred to as a second dummy gate contact plug 70d2. The first dummy gate contact plug 70dl can prevent deformation or defects of the second middle gate contact plug 70g2. The edge flat contact plug 70d2 can prevent deformation or defects of the first middle gate contact plug 70gl adjacent to the second dummy gate contact plug 70d2. For example, when the gate contact holes for forming the first middle gate contact plug 70gl and the second middle gate contact plug 70g2 and the dummy contact holes for forming the first dummy contact plug 70dl and the second dummy contact plug 70d2 are formed simultaneously, etching gas of an etching process for forming the dummy contact holes and the gate contact holes can be stably supplied into the gate contact holes, for example, particularly directed toward the middle gate contact plugs, while being unstably supplied into the dummy contact holes. Thus, the first middle gate contact plug 70gl and the second middle gate contact plug 70g2 formed in the gate contact holes can be stably formed without defects, for example, due to the formation of the first dummy contact plug 70dl and the second dummy contact plug 70d2. Accordingly, the first dummy contact plug 70dl and the second dummy contact plug 70d2 can improve reliability and / or productivity of the semiconductor device.

[0061] The gate contact plugs 70gl and 70g2 and the dummy contact plugs 70dl and 70d2 can be formed of the same conductive material, such as doped silicon, metal nitride (e.g., TiN, WN, etc.), or metal (e.g., tungsten, etc.). However, note that while the dummy contact plugs 70dl and 70d2 can have the same or similar structure and shape as the gate contact plugs 70gl and 70g2, electrical signals are not applied to the dummy contact plugs 70dl and 70d2.

[0062] For example, along the first horizontal direction X, a separation distance between the second middle gate contact plug 70g2 and the first dummy gate contact plug 70dl can be smaller than a separation distance between the first dummy gate contact plug 70dl and the middle gate flat dummy region GFd2. For example, when the second middle gate contact plug 70g2 is between the first middle gate contact plug 70gl and the first dummy gate contact plug 70dl (e.g., as shown in FIG. 1), the separation distance between the second middle gate contact plug 70g2 and the first dummy gate contact plug 70dl can be smaller than the separation distance between the first dummy gate contact plug 70dl and the middle gate flat dummy region GFd2. FIG. 2BWhen the first dummy gate contact plug 70d1 is adjacent to the second intermediate gate contact plug 70g2 (i.e., on the left side), the spacing between the second intermediate gate contact plug 70g2 and the first dummy gate contact plug 70d1 can be substantially the same as the spacing between the first intermediate gate contact plug 70g1 and the second intermediate gate contact plug 70g2. For example, along the first horizontal direction X, the spacing between the second intermediate gate contact plug 70g2 and the first dummy gate contact plug 70d1 can be substantially the same as the spacing between the second dummy gate contact plug 70d2 and the first intermediate gate contact plug 70g1. In order to distinguish the first intermediate gate contact plug 70g1 adjacent to the second intermediate gate contact plug 70g2 (i.e., on the left side), FIG. 2B (on the left side) and the first intermediate gate contact plug 70g1 adjacent to the second dummy gate contact plug 70d2 (i.e., FIG. 2B (on the right side), the first intermediate gate contact plug 70g1, which is adjacent to the second dummy gate contact plug 70d2, can also be referred to as the "third intermediate gate contact plug".

[0063] In one example implementation, the upper gate flat region GFa (in) FIG. 1C and 2A The upper gate flat dummy region GFd1 (in the middle) FIG. 1C and FIG. 2A The length of the upper gate flat region GFa in the first horizontal direction X can be greater than the length of the middle gate flat dummy region GFd2 in the first horizontal direction X. In an example embodiment, the upper gate flat region GFa (in FIG. 1C and FIG. 2A The length of the upper gate flat edge region GFe1 in the first horizontal direction X can be substantially the same as the length of the middle gate flat edge region GFe2 in the first horizontal direction X of the middle gate flat region GFb. The middle gate flat region GFb can be referred to as the first gate flat region. The upper gate flat region GFa can be referred to as the second gate flat region.

[0064] The intermediate gate flat pad region GFp2 can be referred to as the first gate flat pad region, and the intermediate gate flat edge region GFe2 can be referred to as the first gate flat edge region. The intermediate gate flat dummy region GFd2 can be referred to as the first gate flat dummy region. The upper gate flat dummy region GFd1 (in FIG. 1C and FIG. 2A The middle region can be referred to as the second gate flat dummy region, and the upper gate flat edge region GFe1 (in) FIG. 1C and FIG. 2A The middle section can be referred to as the second gate flat edge region.

[0065] In the following description, reference will be made to FIG. 3AThe insulating horizontal layer 23I is described including a lower insulating horizontal layer 23Ia, an intermediate insulating horizontal layer 23Ib, and a floating insulating horizontal layer 23If.

[0066] Referring to FIG. 1C , the insulating horizontal layer 23I can include pad regions formed in a stepped shape in the connection region EA. The floating insulating horizontal layer 23If can include floating insulating pads IPf raised in a difference of a second height therebetween in the first horizontal direction X. The intermediate insulating horizontal layer 23Ib can include: intermediate insulating pads IPb sequentially lowered in a difference of a first height greater than the second height in the first horizontal direction X; and first lower insulating pads IPc1 sequentially lowered in a difference of the second height in the first horizontal direction X. The lower insulating horizontal layer 23Ia can include second lower insulating pads IPc2 sequentially lowered in a difference of the second height in the first horizontal direction X.

[0067] The region in which the floating insulating pads IPf are formed can be defined as a floating insulating stepped region ISf, the region in which the intermediate insulating pads IPb are formed can be defined as an intermediate insulating stepped region ISb, the region in which the first lower insulating pads IPc1 are formed can be defined as a first lower insulating stepped region ISc1, and the region in which the second lower insulating pads IPc2 are formed can be defined as a second lower insulating stepped region ISc2. The insulating region IA of the stack structure ST' can include insulating flat regions IFa, IFb, and IFc. The insulating flat regions IFa, IFb, and IFc can include an upper insulating flat region IFa, an intermediate insulating flat region IFb, and a lower insulating flat region IFc sequentially disposed in the first horizontal direction X.

[0068] The upper insulating flat region IFa can be disposed between the floating insulating stepped region ISf and the intermediate insulating stepped region ISb. The upper insulating flat region IFa (in FIG. 3A and FIG. 1C ) can include an upper insulating flat dummy region IFd1 (in FIG. 3A and FIG. 1C ) and an upper insulating flat edge region IFe1 (in FIG. 3A and FIG. 2B ). The lower insulating flat region IFc can be disposed between the first lower insulating stepped region ISc1 and the second lower insulating stepped region ISc2.

[0069] In an example embodiment, a second dummy pattern 24di can be disposed between the lower insulating flat region IFc and the first lower insulating stepped region IScl. The second dummy pattern 24di can be disposed on the second interlayer insulating layer 20b. In an example embodiment, the second dummy pattern 24di can be formed of an insulating material such as silicon nitride.

[0070] In an example embodiment, a plurality of intermediate insulating stepped regions ISb can be provided. In an example embodiment, a plurality of intermediate insulating flat regions IFb can be provided. One of the plurality of intermediate insulating flat regions IFb can be provided between intermediate insulating stepped regions that are adjacent to each other among the plurality of intermediate insulating stepped regions ISb. Thus, one or more intermediate insulating flat regions IFb can be provided.

[0071] A peripheral contact plug 71 can be provided, which extends downward through the first, second, and third upper insulating layers 33, 53, 65, the stack structure ST', and the gap filling insulating layer 13, and is electrically connected to the peripheral contact pad 8P. A gate connection wiring 74gl can be provided on the peripheral contact plug 71. The upper flat region FAa can include upper gate flat regions GFa and upper insulating flat regions IFa that are adjacent to each other in the second horizontal direction Y. One or more intermediate flat regions FAb can include one or more intermediate gate flat regions GFb and one or more intermediate insulating flat regions IFb that are adjacent to each other in the second horizontal direction Y. The lower flat region FAC can include lower gate flat regions GFc and lower insulating flat regions IFc that are adjacent to each other in the second horizontal direction Y.

[0072] The one or more intermediate gate flat regions GFb can be referred to as a first flat region, the lower flat region FAC can be referred to as a second flat region, and the upper flat region FAa can be referred to as a third flat region. The gate contact plugs 70gl, 70g2, 70dl, and 70d2 (in FIG. 1D The one or more intermediate gate flat regions GFb can be referred to as a first flat region, the lower flat region FAC can be referred to as a second flat region, and the upper flat region FAa can be referred to as a third flat region. The gate contact plugs 70gl, 70g2, 70dl, and 70d2 (in

[0073] In the following description, reference will be made to FIG. 3B and FIG. 1D The intermediate insulating flat region IFb will be described.

[0074] Referring to FIG. 3B and FIG. 1D Each of the intermediate insulating pads IPb can have a first length La in the first horizontal direction X. The intermediate insulating flat region IFb can include an intermediate insulating flat pad region IFp2, an intermediate insulating flat edge region IFe2, and an insulating flat dummy region IFd2 provided between the intermediate insulating flat pad region IFp2 and the intermediate insulating flat edge region IFe2. The intermediate insulating flat pad region IFp2, the insulating flat dummy region IFd2, and the intermediate insulating flat edge region IFe2 can be provided in order in the first horizontal direction X.

[0075] Similar to the intermediate gate flat pad region GFp2 (inFIG. 2B and FIG. 1D In the middle, the intermediate insulating flat pad region IFp2 can have a second length Lp in the first horizontal direction X. Similar to the intermediate gate flat edge region GFe2 (in... FIG. 2B and FIG. 1D In the middle, the intermediate insulating flat edge region IFe2 can have a third length Lc in the first horizontal direction X. Similar to the intermediate gate flat dummy region GFd2 (in... FIG. 2B and FIG. 1C In the middle), the insulating flat dummy region IFd2 can have a fourth length Ld in the first horizontal direction X.

[0076] Similar to the intermediate gate flat region GFb (in FIG. 3A and FIG. 1C In the middle section, the second length Lp of the intermediate insulating flat pad region IFp2 can be equal to or greater than the third length Lc of the intermediate insulating flat edge region IFe2. The fourth length Ld can be greater than each of the second length Lp and the third length Lc. The fourth length Ld can be equal to or greater than the sum of the second length Lp and the third length Lc.

[0077] In one example implementation, the upper insulating flat region IFa (in) FIG. 3A and FIG. 1C The upper insulation flat dummy region IFd1 (in the middle) FIG. 3A and FIG. 2B The length of the middle insulating flat region IFb in the first horizontal direction X can be greater than the length of the insulating flat dummy region IFd2 in the first horizontal direction X.

[0078] In one example implementation, the upper insulating flat region IFa (in) FIG. 1B and FIG. 2A The length of the upper insulating flat edge region IFe1 in the first horizontal direction X of the middle insulating flat region IFb can be basically the same as the length of the middle insulating flat edge region IFe2 in the first horizontal direction X.

[0079] Each insulating horizontal layer 23I may be formed of a first insulating material layer 24a. Each of the intermediate insulating flat pad region IFp2, the intermediate insulating flat edge region IFe2, and the intermediate insulating pad IPb may include the first insulating material layer 24a and a second insulating material layer 24b disposed on the first insulating material layer 24a. The second insulating material layer 24b may have a thickness smaller than that of the first insulating layer 24a. The first insulating material layer 24a may be formed of a first silicon nitride, and the second insulating layer 24b may be formed of a second silicon nitride, the second silicon nitride being etched at a higher rate than the etching rate of the first silicon nitride.

[0080] In an example embodiment, the insulating flat dummy region IFd2 can be formed of a material different from that of the first and second insulating material layers 24a and 24b, for example, silicon oxide. The insulating flat dummy region IFd2 can be formed of the same material as that of the intermediate gate flat dummy region GFd2 (in FIG. 1B ). The insulating flat dummy region IFd2 can separate the first and second insulating material layers of the intermediate insulating flat pad region IFp2 from the first and second insulating material layers of the intermediate insulating flat edge region IFe2, so that the intermediate insulating flat pad region IFp2 can be spaced apart from the intermediate insulating flat edge region IFe2.

[0081] In an example embodiment, each of the lower gate flat regions GFc (in FIG. 3A and FIG. 1B ) and the lower insulating flat regions IFc (in FIG. 2A and FIG. 1B ) can have a length larger than a first length La of each of the intermediate gate pads GPb in the first horizontal direction X. In an example embodiment, each of the lower gate flat regions GFc (in FIG. 2A and FIG. 1B ) and the lower insulating flat regions IFc (in FIG. 2A and FIG. 1B ) can have a length larger than a third length Lc of each of the intermediate insulating flat edge regions IFe2 and the intermediate gate flat edge regions GFe2 (in FIG. 2A and FIG. 1B ) in the first horizontal direction X. In an example embodiment, each of the lower gate flat regions GFc (in FIG. 3A and FIG. 1B ) and the lower insulating flat regions IFc (in FIG. 2A and FIGS. 4A-5B ) can have a length larger than a second length Lp of each of the intermediate insulating flat pad regions IFp2 and the intermediate gate flat pad regions GFp2 (in FIG. 4A and FIG. 1D ) in the first horizontal direction X.

[0082] A cross-sectional structure of a semiconductor device including the stack structure ST' in the connection region EA will be described with reference to FIG. 4B . FIG. 4A is a cross-sectional view along the line III-III' in FIG. 5A , FIG. 1D is an enlarged view of the portion "E" in FIG. 5B , FIG. 5A is a cross-sectional view along the line IV-IV' in FIG. 1D , FIG. 4A is an enlarged view of the portion "E" in FIG. 5BAn enlarged view of a portion "F" in FIG. 6.

[0083] Referring to FIG. 2A , FIG. 1A and FIG. 1B , the block separation structure 62B can include first to third block separation structures 62B1, 62B2 and 62B3. The upper surface of the stack structure ST' can be flat between the first block separation structure 62B1 and the second block separation structure 62B2. The insulating region IA can be disposed between the first block separation structure 62B1 and the second block separation structure 62B2 and can be spaced apart from the first and second block separation structures 62B1 and 62B2. The stack structure ST' can be configured to have a stepped structure that decreases in the second horizontal direction Y between the second block separation structure 62B2 and the third block separation structure 62B3. For example, the intermediate gate pad GPb (in FIG. 1A ) can decrease in the first horizontal direction X with a difference in first height therebetween, and can decrease in the second horizontal direction Y with a difference in second height therebetween that is less than the first height.

[0084] The second auxiliary separation structure 62S2 can be disposed through the stack structure ST' between the second block separation structure 62B2 and the third block separation structure 62B3.

[0085] The block separation structure 62B, the second auxiliary separation structure 62S2 and the first auxiliary separation structure 62S1 (in FIG. 1B and FIG. 5B ) can have the same cross-sectional structure. The block separation structure 62B, the second auxiliary separation structure 62S2 and the first auxiliary separation structure 62S1 (in FIG. 1D and FIG. 3B ) can be sequentially disposed through the second upper insulating layer 53, the first upper insulating layer 33 and the stack structure ST'.

[0086] A cross-sectional structure in FIG. 6 obtained by cutting the intermediate insulating flat pad region IFp2 and the intermediate gate flat pad region GFp2 in the second horizontal direction Y will be described.

[0087] The intermediate insulating flat pad region IFp2 can include a first insulating material layer 24a and a second insulating material layer 24b on the first insulating material layer 24a, as in the example embodiment described with reference to FIG. 2A and FIG. 3A .

[0088] In the region in which the intermediate insulating flat pad region IFp2 is provided, the intermediate gate horizontal layer 23Gb in the intermediate gate horizontal layer 23Gb adjacent to the intermediate insulating flat pad region IFp2 can further include a gate extension portion 25 that extends to an upper surface of the first insulating material layer 24a included in the intermediate insulating flat pad region IFp2 and contacts the second insulating material layer 24b of the intermediate insulating flat pad region IFp2. The gate extension portion 25 can be formed of a conductive material.

[0089] Reference will be made to FIG. 6 the memory vertical structure 36 (in FIG. 1B and FIG. 6 ) in the memory cell array region MA will be described. FIG. 3B is a cross-sectional structure taken in the second horizontal direction Y of the insulating separation pattern 34 (in FIG. 3B ) in the memory cell array region MA.

[0090] Reference will be made to FIG. 7A , the insulating separation pattern 34 can penetrate the first upper insulating layer 33, can extend downward, and can penetrate the gate horizontal layer 23G. The memory vertical structure 36 can include a core region 48, a pad pattern 50 on the core region 48, a channel layer 46 covering side surfaces and a bottom surface of the core region 48 and contacting the pad pattern 50, and a dielectric structure 38 surrounding an outer side surface of the channel layer 46.

[0091] The channel layer 46 can be formed of a semiconductor material. The channel layer 46 can be formed of, for example, polysilicon. For example, the pad pattern 50 can be formed of, for example, doped polysilicon, polysilicon having N-type conductivity. The pad pattern 50 can contact the contact plug 72. The core region 48 can include an insulating material or an insulating material having a void formed therein.

[0092] The dielectric structure 38 can include a first dielectric layer 40, a second dielectric layer 44, and a data storage material layer 42 provided between the first dielectric layer 40 and the second dielectric layer 44. The first dielectric layer 40 can be provided between the data storage material layer 42 and the stack structure ST', and the second dielectric layer 44 can be provided between the data storage material layer 42 and the channel layer 46.

[0093] In an example embodiment, the data storage material layer 42 can be configured as a charge-trapping layer, such as silicon nitride. The data storage material layer 42 can include a region in which data can be stored in a semiconductor device, such as a vertical type NAND flash memory device.

[0094] In an example embodiment, at least a lowermost gate layer of the lower gate horizontal layers 23Ga can be a gate layer of an erase transistor for an erase operation of the vertical NAND flash memory device that utilizes a gate-induced drain leakage (GIDL) phenomenon. The gate layers of the lower gate horizontal layers 23Ga disposed on the erase transistor gate layer for the erase operation can be ground select gate layers of ground select transistors.

[0095] In an example embodiment, a portion of the middle gate horizontal layers 23Gb can be word lines of the vertical NAND flash memory device included in the memory cells.

[0096] In an example embodiment, at least an uppermost gate layer of the upper gate horizontal layers 23Gc can be a gate layer of an erase transistor for an erase operation of the vertical NAND flash memory device that utilizes a gate-induced drain leakage (GIDL) phenomenon.

[0097] In an example embodiment, one or more gate layers of the upper gate horizontal layers 23Gc disposed in a lower portion of the gate layer of the erase transistor can be gate layers of string select transistors of the vertical NAND flash memory device.

[0098] In an example embodiment, each gate horizontal layer 23G can include a first layer 23G1 and a second layer 23G2. The first layer 23G1 can be interposed between the second layer 23G2 and the memory vertical structure 36 and can cover an upper surface and a lower surface of the second layer 23G2.

[0099] In an example embodiment, the first layer 23G1 and the second layer 23G2 can be formed of different materials. For example, the second layer 23G2 can be formed of a conductive material, such as doped silicon, metal nitride (e.g., TiN, WN, etc.), metal-semiconductor compound (e.g., TiSi, WSi, etc.), or metal (e.g., W, etc.), and the first layer 23G1 can be formed of an insulating material. The first layer 23G1 can be formed of a high-k dielectric, such as aluminum oxide, etc. In another example embodiment, the first layer 23G1 can be formed of a metal nitride (e.g., TiN, WN, etc.), and the second layer 23G2 can be formed of a metal (e.g., W, etc.). In yet another example embodiment, each gate horizontal layer 23G can be formed of a single conductive material, such as doped silicon, metal nitride (e.g., TiN, WN, etc.), metal-semiconductor compound (e.g., TiSi, WSi, etc.), or metal (e.g., W, etc.).

[0100] In one example embodiment, the dielectric structure 38 can include a data storage material layer 42 that includes regions in which data of a vertical type NAND flash memory device can be stored, although example embodiments are not limited thereto. For example, the dielectric structure 38 can include a data storage material layer in which data of a resistive random access memory (ReRAM) device can be stored or a data storage material layer in which data of a PRAM device can be stored, instead of the data storage material layer 42.

[0101] Referring back to FIG. 7A As described above, the intermediate insulating planar dummy region IFd2 can not include the first insulating material layer 24a and the second insulating material layer 24b. However, the intermediate insulating planar dummy region IFd2 (in FIG. 3B ) can be modified to form an intermediate insulating planar dummy region IFd2' as in FIG. 7A . FIG. 3B is an enlarged view illustrating a modified example of the intermediate insulating planar dummy region IFd2 shown in FIG. 7A .

[0102] In this modified example embodiment, referring back to FIG. 2B , the intermediate insulating planar dummy region IFd2 (in FIG. 2B ) can be replaced with an intermediate insulating planar dummy region IFd2' shown in FIG. 7B . The intermediate insulating planar dummy region IFd2' can have a reduced thickness, and can extend from the first insulating material layer 24a of the intermediate insulating planar plug region IFp2 and the first insulating material layer 24a of the intermediate insulating planar edge region IFe2. Thus, the intermediate insulating planar dummy region IFd2' can include, for example, a first insulating material layer 24a' that is continuous and integral with the first insulating material layer 24a, which has a thickness that is reduced, for example, along the vertical direction Z, with respect to the first insulating material layer 24a.

[0103] For example, along the vertical direction Z, the minimum thickness of the first insulating material layer 24a' of the intermediate insulating planar dummy region IFd2' can be less than the maximum thickness of the intermediate insulating planar pad region IFp2 and the maximum thickness of the first insulating material layer 24a. The intermediate insulating planar dummy region IFd2' can not include the second insulating material layer 24b.

[0104] Referring back to FIG. 7B As described above, the intermediate gate planar dummy region GFd2 can not include a conductive material, and can be formed of an insulating material. The intermediate gate planar dummy region GFd2 (in FIG. 2B ) can be modified to form an intermediate gate planar dummy region GFd2' as in FIG. 2B . FIG. 7B is an enlarged view illustrating a modified example of the intermediate gate planar dummy region GFd2 shown in FIG. 2BAn enlarged view of the portion shown, showing a modified example of the middle gate flat dummy region GFd2 (in FIG. 7B ).

[0105] In this modified example embodiment, with reference to FIG. 7B , the middle gate flat dummy region GFd2 (in FIG. 1A ) can be replaced with FIG. 8 the middle gate flat dummy region GFd2' shown in .

[0106] As shown in FIG. 8 , the middle gate flat pad region GFp2 can include a first conductive layer, and the middle gate flat edge region GFe2 can include a second conductive layer. The middle gate flat dummy region GFd2' can include a third conductive layer having a reduced thickness and extending from the first conductive layer of the middle gate flat pad region GFp2 and the second conductive layer of the middle gate flat edge region GFe2. The first conductive layer, the third conductive layer, and the second conductive layer can continuously extend without a boundary surface therebetween, e.g., can be integral as a single and uniform layer with each other. The first conductive layer of the gate flat pad region GFp2 and the second conductive layer of the gate flat edge region GFe2 can have the same maximum thickness. For example, in the vertical direction Z, the maximum thickness of each of the first conductive layer and the second conductive layer can be greater than the minimum thickness of the third conductive layer of the middle gate flat dummy region GFd2'.

[0107] With reference to FIG. 1A , each second auxiliary separation structure 62S2 can have a linear shape connected to each other continuously in the first horizontal direction X, but example embodiments thereof are not limited thereto. Each second auxiliary separation structure 62S2 can be modified to form FIG. 8 the second auxiliary separation structure 62S2' shown in FIG. 1A . is a plan view showing a modified example of the second auxiliary separation structure 62S2 shown in FIG. 8 .

[0108] With reference to FIG. 9 , the second auxiliary separation structure 62S2 (in FIGS. 10A-10B ) can be replaced with FIG. 9 the second auxiliary separation structure 62S2' shown in. Each second auxiliary separation structure 62S2' can include a plurality of linear patterns spaced apart from each other in the first horizontal direction X.

[0109] In the following description, modified examples of a semiconductor device will be described with reference to FIG. 10A and FIG. 9 . FIG. 10B is a plan view showing a modified example of a semiconductor device according to an example embodiment, FIG. 9 is a cross-sectional view taken alongFIG. 9 a cross-sectional view along the line Ia-Ia' in FIG. 1A, FIG. 10A is along the FIG. 10B a cross-sectional view along the line IIa-IIa' in FIG. 1B. Repetitive description will not be provided, and only the modified portions will be described.

[0110] Referring to FIGS. 1A-5B , FIGS. 1A-5B and FIGS. 1A-5B , a substantially same memory cell array region MA and a substantially same connection region EA described with reference to FIG. 1A may be provided. A stacked structure ST” can be provided, which is provided in the same memory cell array region MA and extends into the connection region EA. The stacked structure ST” can include a substantially same gate region GA and a substantially same insulating region IA described with reference to FIG. 1B . A plurality of separation structures 62B, 62S1, and 62S2 substantially same as in the example embodiment described with reference to FIG. 8 may be provided. The second auxiliary separation structure 62S2 among the plurality of separation structures 62B, 62S1, and 62S2, which is provided in the connection region EA, can be configured to have a linear shape extending in the first horizontal direction X as in FIGS. 1A-5B and FIG. 1B , or a bar shape spaced apart from each other in the first horizontal direction X as in FIG. 1B .

[0111] A lower structure 3 described with reference to FIG. 1B may be provided. A lower stacked structure ST1’ having a substantially same shape as the shape in the foregoing example embodiment can be provided on the lower structure 3. For example, the lower stacked structure ST1’ can include a lower flat region FAc’ corresponding to the lower flat region FAc (in FIG. 1B ), and the lower flat region FAc’ can include a lower gate flat region GFc’ and a lower insulating flat region IFc’ corresponding to the lower gate flat region GFc (in FIG. 10A ) and the lower insulating flat region IFc (in FIG. 1B ), respectively. The lower stacked structure ST1’ can include a second lower gate step region GSc2 in which a second lower gate pad GPc2 is formed, and a second lower insulating step region ISc2 in which a second lower insulating pad IPc2 is formed.

[0112] A first upper stacked structure ST2a having a substantially same shape as the shape of the upper stacked structure ST2’ described with reference to FIG. 1B may be provided on the lower stacked structure ST1’. A first upper insulating layer 33 same as in the foregoing example embodiment can be provided on the lower stacked structure ST1’ and the first upper stacked structure ST2a.

[0113] The first upper stacked structure ST2a may include one or more intermediate flat regions FAb as described in the foregoing example embodiments. FIGS. 1A-3B (middle), and the upper flat region FAa (in) FIG. 1B The first intermediate flat region FAba and the first upper flat region FAaa correspond to one or more first intermediate flat regions FAba. The one or more first intermediate flat regions FAba may include one or more intermediate gate flat regions GFb (in the middle). FIG. 1B (in the middle) and with one or more intermediate insulating flat regions IFb (in FIG. 1B One or more intermediate gate flat regions GFba (in) corresponding to the middle) FIG. 1B (in the middle). The first upper flat region FAaa may include the upper gate flat region GFa (in the middle). FIG. 1B (middle) and upper insulating flat area IFa (in) FIG. 1B The first upper gate flat region GFaa and the first upper insulating flat region IFaaa correspond to the middle region.

[0114] With reference FIG. 10A A second upper stacked structure ST2b, having a shape substantially the same as the described upper stacked structure ST2', can be disposed on the first upper insulating layer 33. An additional upper insulating layer 133 can be disposed on the first upper insulating layer 33 and the second upper stacked structure ST2b.

[0115] The second upper stacked structure ST2b may include one or more intermediate flat regions FAb (in... FIG. 10B (middle), and the upper flat region FAa (in) FIG. 10B The second intermediate flat region FAbb and the second upper flat region FAab correspond to the first or second intermediate flat region FAbb. The first or second intermediate flat region FAbb may include the first or second intermediate gate flat region GFb described in the foregoing example embodiments. FIG. 3A (in the middle), and one or more intermediate insulating flat regions IFb (in FIG. 6 One or more second intermediate gate flat regions GFbb and one or more second intermediate insulating flat regions IFbb corresponding to the upper gate flat region GFbb. The second upper flat region FAab may include one or more second intermediate gate flat regions GFbb and one or more second intermediate insulating flat regions IFbb corresponding to the upper gate flat region GFbb. FIGS. 11A-12C (middle) and upper insulating flat area IFa (in) FIG. 11A The second upper gate flat region GFab and the second upper insulating flat region IFab correspond to the middle region.

[0116] exist FIG. 12AIn the cross-sectional structure shown, each of the first upper stacked structure ST2a and the second upper stacked structure ST2b may include an intermediate gate step region GSb on which an intermediate gate pad GPb is formed, a floating gate step region GSf on which a floating gate pad GPf is formed, and an upper gate step region GSa on which an upper gate pad GPa is formed.

[0117] exist FIG. 1B In the cross-sectional structures shown, each of the first upper stacked structure ST2a and the second upper stacked structure ST2b may include an intermediate insulating step region ISb in which an intermediate insulating pad IPb is formed and a floating insulating step region ISf in which a floating insulating pad IPf is formed. FIG. 11B In the cross-sectional structure shown, the first upper stacked structure ST2a may further include an upper insulating step region ISa in which an upper insulating pad IPa is formed, each upper insulating pad IPa having a cross-sectional shape substantially the same as the cross-sectional shape of the upper gate step region GSa including the upper gate pad GPa. The second upper stacked structure ST2b may further include an upper gate step region GSa in which an upper gate pad GPa is disposed, such as... FIG. 12B Like in China.

[0118] The stacked structure ST can include a lower stacked structure ST', a first upper stacked structure ST2a, and a second upper stacked structure ST2b.

[0119] A memory vertical structure 136 can be configured to sequentially penetrate the additional upper insulating layer 133, the second upper stacked structure ST2b, the first upper stacked structure ST2a, and the first stacked region ST1'. The memory vertical structure 136 may include a reference... FIG. 1B The components included in the described vertical memory structure 36 are substantially the same.

[0120] The second upper insulating layer 53 and the third upper insulating layer 65 described in the foregoing example embodiments can be disposed on the additional upper insulating layer 133. Furthermore, peripheral contact plugs 171 and gate connection wiring 174g1 corresponding to peripheral contact plugs 71 and gate connection wiring 74g1, respectively, can be disposed.

[0121] In the following description, reference will be made to FIG. 11C Describe the methods for forming semiconductor devices. FIG. 12C and FIG. 1D It is along FIGS. 11A-12C A cross-sectional view of line I-I' in the diagram. FIGS. 1A-5B and FIGS. 1A-5B It is along FIG. 1B The cross-sectional view of line II-II' in the middle. FIG. 1D and FIGS. 11A-11C It is along FIG. 1Bcross-sectional view of the line III-III' in FIG. 3B.

[0122] In the description of the method of forming a semiconductor device described with reference to FIG. 1D In the description of the structure of the semiconductor device described with reference to FIGS. 12A-12C In the description of the method of forming a semiconductor device described with reference to FIGS. 1A-5B In the description of the structure of the semiconductor device described with reference to

[0123] In the description of the method of forming a semiconductor device described with reference to FIG. 1A 、 FIG. 5B and FIG. 2A An integrated circuit region 7 can be formed on a lower substrate 5. The lower substrate 5 can be configured as a semiconductor substrate. For example, the lower substrate 5 can be configured as a single-crystal silicon substrate. The integrated circuit region 7 can include circuit wiring 8 and a lower insulating layer 9 covering the circuit wiring 8. The circuit wiring 8 can include a peripheral contact pad 8P. An upper substrate 12 can be provided on the integrated circuit region 7. The upper substrate 12 can be configured as a polysilicon substrate. A gap-fill insulating layer 13 can be provided through the upper substrate 12.

[0124] A preliminary stack structure ST can be provided on the upper substrate 12. The preliminary stack structure ST can be provided in a memory cell array region MA and a connection region EA on the upper substrate 12. Formation of the preliminary stack structure ST can include forming a preliminary lower stack structure ST1 on the upper substrate 12, and forming a preliminary upper stack structure ST2 on the preliminary lower stack structure ST1.

[0125] Formation of the preliminary lower stack structure ST1 can include forming first and second interlayer insulating layers 20a and 20b alternately stacked, patterning the first and second interlayer insulating layers 20a and 20b, forming a lower pad region of lower horizontal layers 22L, and forming a third interlayer insulating layer 20c covering the lower horizontal layers 22L. The preliminary upper stack structure ST2 can be provided on the preliminary lower stack structure ST1.

[0126] Formation of the preliminary upper stack structure ST2 can include forming third interlayer insulating layers 20c and horizontal layers 22M, 22U, and 23F alternately stacked, patterning the third interlayer insulating layers 20c and the horizontal layers 22M, 22U, and 23F, forming pad regions Pa, Pb, P1, and P2 arranged in a stepped structure in the connection region EA, and forming a pad cap layer 23R on the pad regions Pa, Pb, P1, and P2. The stack structure ST can be formed to include flat regions FAa, FAb, and FAC, each of which has a length greater than that of each of the pad regions Pa, Pb, P1, and P2 and is configured to be flat in a first horizontal direction X.

[0127] In one example embodiment, the pad cap layer 23R can not be provided on the uppermost horizontal layer among the horizontal layers 22M, 22U, and 23F. In another example embodiment, the pad cap layer 23R can be provided on the uppermost horizontal layer among the horizontal layers 22M, 22U, and 23F.

[0128] The photoresist pattern 30 can be formed. The photoresist pattern 30 can have an opening for exposing a portion of each of the flat areas FAa, FAb, and FAc. The photoresist pattern 30 can expose the pad region of the lower horizontal layer 22L.

[0129] Referring to FIG. 2B , FIG. 3A and FIG. 3B , the pad cap layer 23R not covered by the photoresist pattern 30 can be etched using the photoresist pattern 30. For example, only the pad cap layer 23R can be selectively etched. In another example, while the pad cap layer 23R is etched, the preliminary horizontal layer 22 in contact with the pad cap layer 23R can be partially etched. In yet another example, while the pad cap layer 23R is etched, the preliminary horizontal layer 22 in contact with the pad cap layer 23R can be completely etched. In still another example, while the pad cap layer 23R is etched, the preliminary horizontal layer 22 in contact with the pad cap layer 23R can be etched, and one of the interlayer insulation layers 20 exposed while the preliminary horizontal layer 22 is etched can be etched.

[0130] The photoresist pattern 30 can be removed. The first upper insulation layer 33 can be formed on the stack structure ST'.

[0131] The memory vertical structure 36 can be formed through the first upper insulation layer 33 and the stack structure ST'. The memory vertical structure 36 can be formed in the memory cell array region MA. The second upper insulation layer 53 can be provided on the first upper insulation layer 33.

[0132] The separation trenches 61B and 61C can be formed through the second upper insulation layer 53, the first upper insulation layer 33, and the stack structure ST'. The separation trenches 61B and 61C can be provided at positions corresponding to positions of the separation structures 62B, 62S1, and 62S2 shown in FIG. 6B. FIG. 2A

[0133] A portion of the preliminary horizontal layer 22 and a portion of the pad cap layer 23R can be replaced with the gate horizontal layer 23G. Accordingly, the preliminary horizontal layer 22 among the preliminary horizontal layers not replaced with the gate horizontal layer 23G and the pad cap layer can be defined as the insulating horizontal layer 23I. Accordingly, the horizontal layer including the insulating horizontal layer 23I and the gate horizontal layer 23G can be provided.

[0134] ​In one example implementation, replacing a portion of the initial horizontal layer 22 and a portion of the capping layer 23R with the gate horizontal layer 23G may include forming empty spaces by partially etching the initial horizontal layer 22 and the capping layer 23R exposed via the separating trenches 61B and 61S, and filling the empty spaces with the gate horizontal layer 23G. Thus, a reference can be formed. FIG. 2B and FIG. 3A The description includes a stacked structure ST' comprising horizontal layers 23G and 23I and an interlayer insulating layer 20.

[0135] In the semiconductor device of the foregoing example embodiments, the stacked structure ST' may include a plurality of interlayer insulating layers 20 and a plurality of horizontal layers 23G and 23I, and the plurality of interlayer insulating layers 20 and the plurality of horizontal layers 23G and 23I may be alternately stacked in the memory cell array region MA and may extend into the connection region EA adjacent to the memory cell array region MA. In the connection region EA, the stacked structure ST' may include a stepped region and a flat region adjacent to the stepped region. The stepped region may include a pad that decreases in a first horizontal direction, each pad may have a first length in the first horizontal direction, and the flat region may include a flat pad region having a second length greater than the first length in the first horizontal direction, a flat edge region having a third length greater than the first length in the first horizontal direction, and a flat dummy region disposed between the flat pad region and the flat edge region. The fourth length of the flat dummy region in the first horizontal direction may be greater than each of the second length and the third length.

[0136] The stepped area can be configured as follows FIG. 3B and FIG. 2B The intermediate gate step region GSb shown FIG. 3B and FIG. 2B The intermediate insulating stepped region ISb is shown, and the flat region can be configured as follows: FIG. 3B and ​ The intermediate gate flat region GFb shown is ​ and ​ The intermediate insulating flat region IFb is shown. The flat pad region can be configured as follows: ​ The gate flat pad region GFp2 or shown ​ The insulating flat pad region IFp2 is shown. The flat dummy region can be configured as follows: ​ The gate flat dummy region GFd2 or shown ​ The insulating flat dummy region IFd2 is shown. By providing a stacked structure ST' including the flat region as described above, the integration density of semiconductor devices can be increased.

[0137] According to the foregoing example embodiment, by providing a stack structure including a gate region and an insulating region on a lower structure including a peripheral circuit region, the integration density of the semiconductor device can be improved. Further, by providing a stack structure including a flat region on a lower structure including a peripheral circuit region and a contact plug that crosses the flat region and penetrates the stack structure, the integration density of the semiconductor device can be improved.

[0138] As a summary and review, as the number of gate electrodes stacked in a direction perpendicular to the surface of the semiconductor substrate increases, the difficulty of electrically connecting the gate electrodes to the peripheral circuit increases, and unexpected defects can occur. In contrast, the example embodiments provide a semiconductor device that can improve the integration density.

[0139] That is, in order to achieve a high integration density, the semiconductor device according to the example embodiments includes a stack structure, in which a portion of the stack structure above the peripheral circuit is configured as an insulating region so that a peripheral contact plug penetrates the insulating region of the stack structure. In this case, a molding layer for forming a word line is left in the insulating region to prevent the insulating region from being reduced when the word line is formed, and a method of patterning a portion of the molding layer formed in the insulating region can be suggested.

[0140] Example embodiments have been disclosed herein and, although a specific terminology is employed, they will only be used in a generic and descriptive sense and not for purposes of limitation. In some instances, features, characteristics, and / or elements described in connection with a particular embodiment can be used singly or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless expressly indicated otherwise. Accordingly, one of ordinary skill in the art will recognize that the various features, characteristics, and / or elements described in connection with a particular embodiment can be used in a variety of combinations, unless expressly indicated otherwise. Accordingly, the skilled artisan will appreciate that various modifications can be made to the described embodiments without departing from the spirit and scope of the present invention as set forth in the appended claims.

[0141] Korean Patent Application No. 10-2019-0163653, filed on December 10, 2019, in the Korean Intellectual Property Office and entitled “Semiconductor Device,” is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor device, comprising: Substructure; The stacked structure on the lower structure is in the memory cell array region and extends into the connection region, and the stacked structure includes interlayer insulating layers and horizontal layers that are alternately stacked in the memory cell array region and extend into the connection region; The upper insulating layer on the stacked structure; Gate contact plug in the connection area; as well as A vertical memory structure that runs through the stacked structure in the memory cell array region. In the connection region, the first cross-sectional structure of the stacked structure includes a first gate step region and a first gate flat region adjacent to the first gate step region. The first gate step region includes a first gate pad, which decreases in height along a first horizontal direction, the first horizontal direction being oriented from the memory cell array region toward the connection region. The first gate flat region includes a first gate flat pad region, a first gate flat edge region, and a first gate flat dummy region between the first gate flat pad region and the first gate flat edge region. The gate contact plug includes a first gate contact plug that contacts the first gate pad on the first gate pad, a flat contact plug that contacts the first gate flat pad region on the first gate flat pad region, and an edge flat contact plug that contacts the first gate flat edge region on the first gate flat edge region.

2. The semiconductor device according to claim 1, wherein: Each of the first gate pads has a first length in the first horizontal direction. The first gate flat pad region has a second length in the first horizontal direction that is greater than the first length. The first gate flat edge region has a third length in the first horizontal direction that is greater than the first length. The first gate flat dummy region has a fourth length greater than each of the second and third lengths, and The second length is equal to or greater than the third length.

3. The semiconductor device according to claim 1, wherein: Each of the first gate pads has a first length in the first horizontal direction. The first gate flat pad region has a second length in the first horizontal direction that is greater than the first length. The first gate flat edge region has a third length in the first horizontal direction that is greater than the first length. The first gate flat dummy region has a fourth length greater than each of the second and third lengths, and The fourth length is equal to or greater than the sum of the second length and the third length.

4. The semiconductor device according to claim 1, wherein: The stacked structure includes a gate region and an insulating region. The horizontal layer includes a horizontal gate layer in the gate region and a horizontal insulating layer in the insulating region. The first cross-sectional structure of the stacked structure passes through the gate region of the stacked structure in the first horizontal direction. The first gate stepped region and the first gate flat region are arranged sequentially in the first horizontal direction, and The level of the lowest first gate pad in the first gate pad of the first gate step region differs from the level of the first gate flat pad region by the first height.

5. The semiconductor device according to claim 4, wherein: Each of the first gate pads has a first length in the first horizontal direction. The first gate flat pad region has a second length in the first horizontal direction that is greater than the first length. The first gate flat edge region has a third length in the first horizontal direction that is greater than the first length. The first gate flat dummy region has a fourth length greater than each of the second and third lengths. The second cross-sectional structure passing through the insulating region of the stacked structure in the first horizontal direction includes a first insulating stepped region and a first insulating flat region adjacent to the first insulating stepped region. The first insulating stepped area includes a first insulating pad, which decreases in height along the first horizontal direction. Each of the first insulating pads has the first length in the first horizontal direction, and The first insulating flat region includes a first insulating flat pad region having the second length, a first insulating flat edge region having the third length, and a first insulating flat dummy region having the fourth length between the first insulating flat pad region and the first insulating flat edge region.

6. The semiconductor device according to claim 5 further includes peripheral contact plugs. The lower structure includes a lower substrate, an integrated circuit region on the lower substrate, an upper substrate on the integrated circuit region, and a gap-filling insulating layer penetrating the upper substrate. The peripheral contact plug penetrates the upper insulating layer, the stacked structure, and the gap-filling insulating layer, and is electrically connected to the peripheral contact pad of the integrated circuit region. The peripheral contact plug penetrates the first insulated flat dummy area.

7. The semiconductor device according to claim 5, wherein: The first insulating flat pad region and the first insulating flat edge region are at the same level. Each of the first insulating flat pad region and the first insulating flat edge region includes a first insulating material layer and a second insulating material layer on the first insulating layer. The second insulating material layer in the first insulating flat pad region and the second insulating material layer in the first insulating flat edge region are spaced apart from each other in the first horizontal direction. Each of the horizontal insulating layers includes the first insulating material layer, and The maximum thickness of each of the first insulating flat pad region and the first insulating flat edge region is greater than the thickness of each of the horizontal layers in the memory cell array region.

8. The semiconductor device of claim 7, wherein the first insulating flat dummy region comprises an insulating material different from the first insulating material layer and the second insulating material layer.

9. The semiconductor device according to claim 5, wherein: The first insulating flat pad region and the first insulating flat edge region are at the same level. Each of the first insulating flat pad region and the first insulating flat edge region includes a first insulating material layer and a second insulating material layer on the first insulating layer. The first insulating material layer in the first insulating flat pad region and the first insulating material layer in the first insulating flat edge region extend into the first insulating flat dummy region, and The minimum thickness of the first insulating material layer extending from the first insulating flat pad region and the first insulating flat edge region to the first insulating flat dummy region is less than the maximum thickness of the first insulating material layer in the first insulating flat pad region.

10. The semiconductor device according to claim 4, wherein: The first cross-sectional structure of the stacked structure further includes a second gate flat region adjacent to the first gate stepped region. The second gate flat region, the first gate stepped region, and the first gate flat region are arranged sequentially in the first horizontal direction. The second gate flat region includes a second gate flat dummy region and a second gate flat edge region adjacent to the second gate flat dummy region. The second gate flat edge region has the same cross-sectional structure as the first gate flat edge region. The second gate flat dummy region has the same cross-sectional structure as the first gate flat dummy region, and The length of the second gate flat dummy region in the first horizontal direction is greater than the length of the first gate flat dummy region in the first horizontal direction.

11. The semiconductor device according to claim 10, wherein: The stacking structure includes a lower stacking structure, a first upper stacking structure on the lower stacking structure, and a second upper stacking structure on the first upper stacking structure. Each of the first upper stack structure and the second upper stack structure includes a first gate flat region and a second gate flat region.

12. The semiconductor device according to claim 1, wherein: The first gate flat pad region and the first gate flat edge region are at the same level. The first gate planar pad region includes a first conductive layer. The first gate flat edge region includes a second conductive layer. The first gate flat dummy region includes an insulating material, and The insulating material of the first gate flat dummy region separates the first conductive layer of the first gate flat pad region from the second conductive layer of the first gate flat edge region in the first horizontal direction, such that the first conductive layer and the second conductive layer are spaced apart from each other in the first horizontal direction.

13. The semiconductor device of claim 1, wherein the maximum thickness of each of the first gate flat pad region and the first gate flat edge region is greater than the thickness of each of the horizontal layers in the memory cell array region.

14. The semiconductor device according to claim 1, wherein: The first gate flat pad region and the first gate flat edge region are at the same level. The first gate planar pad region includes a first conductive layer. The first gate flat edge region includes a second conductive layer. The first gate flat dummy region includes a third conductive layer extending from the first conductive layer and the second conductive layer, and The maximum thickness of each of the first conductive layer and the second conductive layer is greater than the minimum thickness of the third conductive layer.

15. The semiconductor device according to claim 1, wherein: In the connection region, the first cross-sectional structure of the stacked structure further includes an upper stepped region, a second gate stepped region, a lower gate flat region, and a lower stepped region. The upper stepped region, the first gate stepped region, the first gate flat region, the second gate stepped region, the lower gate flat region, and the lower stepped region are arranged sequentially in the first horizontal direction. The upper stepped area includes an upper pad. The lower stepped area includes a lower pad. The second gate step region includes a second gate pad. The upper pad is lowered in the first horizontal direction by a second height, the second height being smaller than the first height. The lower pad is lowered in the first horizontal direction by the second height therebetween. The second gate pad decreases in the first horizontal direction by the first height therebetween. The first gate pad and the second gate pad decrease in height in a second horizontal direction perpendicular to the first horizontal direction, with the second height being less than the first height. The length of the lower gate flat region in the first horizontal direction is greater than the length of each of the first gate pads in the first horizontal direction.

16. A semiconductor device, comprising: Substructure; A stacked structure, located on the lower structure in the memory cell array region and extending from the memory cell array region to the connection region; Gate contact plug, on the stacked structure in the connection region; as well as A vertical memory structure extends through the stacked structure in the memory cell array region. The stacked structure includes alternating stacked interlayer insulating layers and horizontal layers. In the connection region, the stacking structure includes a stepped region and a flat region adjacent to the stepped region. The stepped region includes a pad that decreases in the first horizontal direction. The flat region includes a flat pad region, a flat edge region, and a flat dummy region between the flat pad region and the flat edge region. The gate contact plug includes a first gate contact plug on the pad, a flat contact plug on the flat pad region, and a flat edge contact plug on the flat edge region.

17. The semiconductor device according to claim 16, wherein: Each of the pads has a first length in the first horizontal direction. The flat pad region has a second length in the first horizontal direction that is greater than the first length; The flat edge region has a third length in the first horizontal direction that is greater than the first length, and The flat dummy region has a fourth length in the first horizontal direction that is greater than each of the second and third lengths, and The flat pad region, the flat edge region, and each of the pads have a maximum thickness greater than the thickness of each of the horizontal layers in the memory cell array region.

18. The semiconductor device of claim 16, further comprising a peripheral contact plug penetrating the stacked structure in the connection region. The stacked structure also includes gate regions and insulating regions that are adjacent to each other. The gate contact plug is located on the gate region of the stacked structure. The lower structure includes a peripheral contact pad, and The peripheral contact plug penetrates the insulating region of the stacked structure, extends into the stacked structure, and contacts the peripheral contact pad.

19. A semiconductor device, comprising: Substructure; A stacked structure, located on the lower structure in the memory cell array region and extending from the memory cell array region to the connection region; Gate contact plugs are located on the stacked structure. as well as A vertical memory structure extends through the stacked structure in the memory cell array region. The stacking structure includes a lower stacking structure and an upper stacking structure on the lower stacking structure. The lower stacked structure includes lower horizontal layers that are stacked vertically and spaced apart from each other. The vertical direction is perpendicular to the upper surface of the lower structure. The upper stacked structure includes upper horizontal layers that are stacked and spaced apart from each other in the vertical direction. The upper horizontal layer includes a first stepped region, the first stepped region including a first pad, the first pad decreasing in height in the connecting region by a first height. The lower horizontal layer includes a second stepped region, the second stepped region including a second pad, the second pad being lowered at a second height less than the first height. The upper stacked structure includes a first flat region adjacent to the first stepped region. The lower stacked structure includes a second flat region adjacent to the second stepped region. Each of the first pads has a first length. The first flat region includes a flat pad region having a second length greater than the first length in the first horizontal direction, a flat edge region having a third length greater than the first length in the first horizontal direction, and a flat dummy region between the flat pad region and the flat edge region. The fourth length of the flat dummy region in the first horizontal direction is greater than each of the second length and the third length. The second flat region has a length greater than the first length in the first horizontal direction, and The gate contact plugs include a first gate contact plug on a first pad and a second pad, a second gate contact plug and a dummy contact plug spaced apart from each other on the flat pad region, and a flat edge contact plug on the flat edge region.

20. The semiconductor device of claim 19, further comprising a peripheral contact plug penetrating the stacked structure in the connection region. The stacked structure includes a gate region and an insulating region. The gate contact plug is located on the gate region of the stacked structure. The peripheral contact plug penetrates the insulating region of the stacked structure. The lower structure includes a peripheral contact pad. A portion of the peripheral contact plug extends through the flat dummy area in the insulating region of the stacked structure, into the lower structure, and contacts a portion of the peripheral contact pad. Another portion of the peripheral contact plug passes through the second flat region in the insulating region of the stacked structure, penetrates the stacked structure, extends into the lower structure, and contacts another portion of the peripheral contact pad. The length of the first flat region in the first horizontal direction is greater than the length of the second flat region in the first horizontal direction.

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