A high-power flip-chip high-voltage chip and its manufacturing method

Abstract

The present invention relates to the technical field of LED chips, and discloses a high-power flip-chip high-voltage chip, which includes a substrate and a plurality of serially connected GaN-based epitaxial layer units disposed on the substrate. The GaN-based epitaxial layer unit includes an N-type GaN layer and a P-type GaN layer. A P-type electrode layer is plated on the P-type GaN layer, and an N-type electrode layer is plated on the N-type GaN layer. Among two adjacent GaN-based epitaxial layer units, the N-type electrode layer of the upper GaN-based epitaxial layer unit is connected to the P-type electrode layer of the lower GaN-based epitaxial layer unit through a connecting electrode layer. The P-type electrode layer, the connecting electrode layer, and the N-type electrode layer all include an AuSn layer, an Au layer, a Ni layer, a first Ti layer, a first AlCu layer, a second Ti layer, a second AlCu layer, and a Cr layer sequentially arranged from top to bottom. The present invention also discloses a manufacturing method of the high-power flip-chip high-voltage chip. Using the present invention can reduce the number of electrode layers, improve production efficiency, reduce production costs, and at the same time reduce the height difference between the positive and negative electrodes, which is beneficial to subsequent welding and heat dissipation of the chip.

Description

Technical Field

[0001] The present invention relates to the technical field of LED chips, and particularly to a high-power flip-chip high-voltage chip and a manufacturing method thereof. Background Art

[0002] The voltage of a blue LED is generally between 2.5V and 3.5V, while the mains voltage is 220V. Therefore, for a high-voltage chip, after the LED chips are connected in series and parallel, the chip voltage is increased, the loss caused by voltage conversion is reduced, and at the same time, chip integration is carried out at the chip end to improve reliability. The chips are arranged more densely and the light intensity is more concentrated.

[0003] Existing flip-chip high-voltage chips generally require a three-layer electrode structure, as Figure 1 shown. One layer is a contact layer a, whose function is to form a good ohmic contact with the epitaxial layer; one layer is a connection layer b, whose function is to perform series and parallel connections between chips; and the last layer is a welding layer c used for welding and heat dissipation. The three-layer electrode structure will cause a height difference between the electrodes, resulting in poor contact during welding and heat dissipation, affecting the effect. In addition, the production cost of the three-layer electrode structure is high. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a high-power flip-chip high-voltage chip with reduced number of electrode layers and a manufacturing method thereof.

[0005] To solve the above technical problem, the present invention provides a high-power flip-chip high-voltage chip, including a substrate and a plurality of serially connected GaN-based epitaxial layer units disposed on the substrate. The GaN-based epitaxial layer unit includes an N-type GaN layer disposed on the substrate and a P-type GaN layer disposed on the N-type GaN layer. A P-type electrode layer is plated on the P-type GaN layer, and an N-type electrode layer is plated on the N-type GaN layer. Among two adjacent GaN-based epitaxial layer units, the N-type electrode layer of the upper GaN-based epitaxial layer unit is connected to the P-type electrode layer of the lower GaN-based epitaxial layer unit through a connection electrode layer. The P-type electrode layer, the connection electrode layer, and the N-type electrode layer all include an AuSn layer, an Au layer, a Ni layer, a first Ti layer, a first AlCu layer, a second Ti layer, a second AlCu layer, and a Cr layer sequentially arranged from top to bottom.

[0006] As a preferred solution of the present invention, the P-type electrode layer, the N-type electrode layer, and the connection electrode layer are all formed in the same evaporation process.

[0007] As a preferred solution of the present invention, an isolation trench is provided between adjacent GaN-based epitaxial layer units, and a first protective layer is deposited in the isolation trench.

[0008] As a preferred embodiment of the present invention, the connecting electrode layer covers the top surface of the first protective layer, and both ends of the connecting electrode layer are respectively connected to the P-type electrode layer and the N-type electrode layer.

[0009] As a preferred embodiment of the present invention, an ITO layer is plated on the top surface of the P-type GaN layer, and an Ag layer is plated on the ITO layer.

[0010] As a preferred embodiment of the present invention, it further includes a second protective layer covering the GaN-based epitaxial layer unit, and the second protective layer is respectively provided with a P-type conductive hole for exposing the P-type electrode layer and an N-type conductive hole for exposing the last N-type electrode layer in series.

[0011] Meanwhile, the present invention also provides a method for manufacturing the high-power flip-chip high-voltage chip, including the following steps:

[0012] (1) Fabricate an epitaxial layer, and use MOCVD equipment to sequentially grow an N-type GaN layer, a light-emitting quantum well, and a P-type GaN layer on a substrate to complete the fabrication of the GaN-based epitaxial layer;

[0013] (2) Plate an ITO layer on the GaN-based epitaxial layer, and then etch the ITO layer and the GaN-based epitaxial layer to expose the N-type GaN layer and form a plurality of isolated GaN-based epitaxial layer units on the GaN-based epitaxial layer;

[0014] (3) Plate an Ag layer on the surface of the ITO layer;

[0015] (4) Deposit a first protective layer in the gap between adjacent GaN-based epitaxial layer units;

[0016] (5) Evaporate and deposit an electrode layer, evaporate and deposit a P-type electrode layer on the ITO layer, an N-type electrode layer on the N-type GaN layer, and a connecting electrode layer on the first protective layer, wherein both ends of the connecting electrode layer are respectively connected to the P-type electrode layer and the N-type electrode layer;

[0017] (6) Deposit a second protective layer on the GaN-based epitaxial layer, and etch P-type conductive holes for exposing the P-type electrode layer and N-type conductive holes for exposing the last N-type electrode layer in series on the second protective layer.

[0018] As a preferred embodiment of the present invention, in step (2), first etch an N-type step on the GaN-based epitaxial layer to expose the N-type GaN layer, and then etch isolation trenches on the GaN-based epitaxial layer to divide the entire GaN-based epitaxial layer into a plurality of isolated GaN-based epitaxial layer units.

[0019] As a preferred embodiment of the present invention, in step (4), the first protective layer is deposited in the isolation trench.

[0020] As a preferred embodiment of the present invention, the materials of the first protective layer and the second protective layer are SiO2.

[0021] Implementing a high-power flip-chip high-voltage chip and its manufacturing method provided by the present invention, compared with the prior art, the beneficial effects are as follows: The P-type electrode layer, the connection electrode layer, and the N-type electrode layer all include an AuSn layer, an Au layer, a Ni layer, a first Ti layer, a first AlCu layer, a second Ti layer, a second AlCu layer, and a Cr layer arranged in sequence from top to bottom; the Cr layer can well contact the GaN-based epitaxial layer unit, and the cooperation of the Ti layer and the AlCu layer has the effects of high reflectivity and slowdown of Al migration. The cooperation of the Cr layer, the Ti layer, and the AlCu layer makes the electrode layer better contact with the GaN-based epitaxial layer unit, effectively improving the brightness at the same time. Finally, the AuSn layer serves as a welding layer, and the addition of the Ni layer in the middle effectively blocks the penetration of Sn under the electrode; this electrode layer structure enables the P-type electrode layer, the connection-type electrode layer, and the N-type electrode layer to effectively act as contact layers and welding layer electrodes at the same time. The entire high-power flip-chip high-voltage chip only needs to deposit a P-type electrode layer, a connection electrode layer, and an N-type electrode layer respectively to achieve the series connection of the GaN-based epitaxial layer units, thereby reducing the setting of electrode layers. Since the number of electrode layers is reduced, the production steps are reduced, the cost is reduced, the manufacturing process is accelerated, and at the same time, the height difference between the positive and negative electrodes is reduced, which is beneficial to subsequent welding and chip heat dissipation. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Schematic structural diagram of a current high-power flip-chip;

[0023] Figure 2 Schematic structural diagram of the present invention;

[0024] Figure 3 Schematic structural diagram of the P-type electrode layer, the connection electrode layer, and the N-type electrode layer;

[0025] In the figure, 1, substrate; 2, GaN-based epitaxial layer unit; 21, N-type GaN layer; 22, P-type GaN layer; 23, P-type electrode layer; 231, AuSn layer; 232, Au layer; 233, Ni layer; 234, first Ti layer; 235, first AlCu layer; 236, second Ti layer; 237, second AlCu layer; 238, Cr layer; 24, connection electrode layer; 25, N-type electrode layer; 26, ITO layer; 27, Ag layer; 3, isolation trench; 4, first protective layer; 5, second protective layer; 51, P-type conductive hole; 52, N-type conductive hole; a, contact layer; b, connection layer; c, welding layer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. The following embodiments are used to illustrate the present invention, but are not used to limit the scope of the present invention.

[0027] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. in the present invention is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0028] In the description of the present invention, it should be understood that unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" used in the present invention should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0029] As Figure 2 As shown in FIG. -3, a high-power flip-chip high-voltage chip according to a preferred embodiment of an embodiment of the present invention includes a substrate 1 and a plurality of serially connected GaN-based epitaxial layer units 2 provided on the substrate 1. The GaN-based epitaxial layer unit 2 includes an N-type GaN layer 21 provided on the substrate 1 and a P-type GaN layer 22 provided on the N-type GaN layer 21. A P-type electrode layer 23 is plated on the P-type GaN layer 22, and an N-type electrode layer 25 is plated on the N-type GaN layer 21. Among two adjacent GaN-based epitaxial layer units 2, the N-type electrode layer 25 of the upper GaN-based epitaxial layer unit 2 is connected to the P-type electrode layer 23 of the lower GaN-based epitaxial layer unit 2 through a connection electrode layer 24. The P-type electrode layer 23, the connection electrode layer 24, and the N-type electrode layer 25 all include an AuSn layer 231, an Au layer 232, a Ni layer 233, a first Ti layer 234, a first AlCu layer 235, a second Ti layer 236, a second AlCu layer 237, and a Cr layer 238 provided in sequence from top to bottom.

[0030] The working principle of the present invention is as follows: In two adjacent GaN-based epitaxial layer units 2, the N-type electrode layer 25 of the previous GaN-based epitaxial layer unit 2 is connected to the P-type electrode layer 23 of the next GaN-based epitaxial layer unit 2 through the connecting electrode layer 24, realizing the series connection of the GaN-based epitaxial layer units 2. The P-type electrode layer 23, the connecting electrode layer 24, and the N-type electrode layer 25 all include an AuSn layer 231, an Au layer 232, a Ni layer 233, a first Ti layer 234, a first AlCu layer 235, a second Ti layer 236, a second AlCu layer 237, and a Cr layer 238 arranged in sequence from top to bottom. The Cr layer 238 can contact the GaN-based epitaxial layer unit 2 well. The cooperation of the Ti layer and the AlCu layer has the effects of high reflectivity and slowing down the migration of Al. The cooperation of the Cr layer 238, the Ti layer, and the AlCu layer makes the electrode layer contact the GaN-based epitaxial layer unit 2 better, and effectively improves the brightness. Finally, the AuSn layer 231 serves as a welding layer, and the Ni layer 233 in the middle effectively blocks the penetration of Sn under the electrode. This electrode layer structure enables the P-type electrode layer 23, the connecting electrode layer, and the N-type electrode layer 25 to effectively act as contact layers and welding layer electrodes at the same time. The entire high-power flip-chip high-voltage chip only needs to deposit a layer of P-type electrode layer 23, connecting electrode layer 24, and N-type electrode layer 25 respectively to realize the series connection of the GaN-based epitaxial layer units 2, thereby reducing the setting of electrode layers. Since the number of electrode layers is reduced, the production steps are reduced, the cost is reduced, the manufacturing process is accelerated, and at the same time, the height difference between the positive and negative electrodes is reduced, which is beneficial to subsequent welding and the heat dissipation of the chip.

[0031] Exemplarily, the P-type electrode layer 23, the N-type electrode layer 25, and the connecting electrode layer 24 are all formed in the same evaporation process. Since the structures of the P-type electrode layer 23, the N-type electrode layer 25, and the connecting electrode layer 24 are the same, forming them in the same evaporation process helps to improve production efficiency.

[0032] Exemplarily, an isolation trench 3 is provided between adjacent GaN-based epitaxial layer units 2. A first protective layer 4 is deposited in the isolation trench 3. The connecting electrode layer 24 covers the top surface of the first protective layer 4. The two ends of the connecting electrode layer 24 are respectively connected to the P-type electrode layer 23 and the N-type electrode layer 25, facilitating the deposition of the connecting electrode layer 24. The first protective layer 4 plays an insulating role to prevent the connecting electrode layer 24 from conducting the N-type GaN layer 21 of adjacent GaN-based epitaxial layer units 2.

[0033] Exemplarily, an ITO layer 26 is deposited on the top surface of the P-type GaN layer 22, and an Ag layer 27 is deposited on the ITO layer 26. Since the flip-chip high-voltage chip emits light from the back, adding the Ag layer 27 with high reflectivity can improve the brightness and also enhance the connection reliability.

[0034] Exemplarily, the present invention further includes a second protective layer 5 covering the GaN-based epitaxial layer unit 2 to protect the GaN-based epitaxial layer unit 2. The second protective layer 5 is respectively provided with a P-type conductive hole 51 for exposing the P-type electrode layer 23 and an N-type conductive hole 52 for exposing the last N-type electrode layer 25 in series, facilitating the connection of the P-type electrode layer 23 and the N-type electrode layer 25 to the power supply, and at the same time contributing to the heat dissipation of the GaN-based epitaxial layer unit 2.

[0035] A method for manufacturing a high-power flip-chip high-voltage chip based on the above contents includes the following steps:

[0036] (1) Fabricate an epitaxial layer, and sequentially grow an N-type GaN layer 21, a light-emitting quantum well, and a P-type GaN layer 22 on the substrate 1 by using MOCVD equipment to complete the fabrication of the GaN-based epitaxial layer.

[0037] (2) Deposit an ITO layer 26 on the GaN-based epitaxial layer, and then etch the GaN-based epitaxial layer to expose the N-type GaN layer 21 and form multiple isolated GaN-based epitaxial layer units 2 in the GaN-based epitaxial layer.

[0038] (3) Deposit an Ag layer 27 on the surface of the ITO layer 26.

[0039] (4) Deposit a first protective layer 4 in the gap between adjacent GaN-based epitaxial layer units 2.

[0040] (5) Evaporate electrode layers, evaporate a P-type electrode layer 23 on the ITO layer 26, evaporate an N-type electrode layer 25 on the N-type GaN layer 21, and evaporate a connection electrode layer 24 on the first protective layer 4, wherein both ends of the connection electrode layer 24 are respectively connected to the P-type electrode layer 23 and the N-type electrode layer 25.

[0041] (6) Deposit a second protective layer 5 on the GaN-based epitaxial layer, and etch P-type conductive holes 51 for exposing the P-type electrode layer 23 and N-type conductive holes 52 for exposing the last N-type electrode layer 25 in series on the second protective layer 5.

[0042] Exemplarily, in step (2), first etch an N-type step on the GaN-based epitaxial layer to expose the N-type GaN layer 21, and then etch isolation trenches 3 on the GaN-based epitaxial layer to divide the entire GaN-based epitaxial layer into multiple isolated GaN-based epitaxial layer units 2.

[0043] Exemplarily, in step (4), the first protective layer 4 is deposited in the isolation trenches 3, facilitating the deposition of the first protective layer 3.

[0044] Exemplarily, the materials of the first protective layer 3 and the second protective layer 5 are SiO2, with good stability.

[0045] In summary, the high-power flip-chip high-voltage chip of the present invention can reduce the number of electrode layers, thereby reducing the production process, improving efficiency, and reducing costs. At the same time, it can reduce the height difference between the governing electrodes, which is beneficial to subsequent welding and chip heat dissipation.

[0046] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the technical principle of the present invention, several improvements and substitutions can be made, and these improvements and substitutions should also be regarded as the protection scope of the present invention.

Claims

1. A manufacturing method of a high-power flip-chip high-voltage chip, characterized in that: The high-power flip-chip high-voltage chip includes a substrate and a plurality of serially connected GaN-based epitaxial layer units disposed on the substrate. The GaN-based epitaxial layer unit includes an N-type GaN layer disposed on the substrate and a P-type GaN layer disposed on the N-type GaN layer. The P-type GaN layer is plated with a P-type electrode layer, and the N-type GaN layer is plated with an N-type electrode layer. Among two adjacent GaN-based epitaxial layer units, the N-type electrode layer of the previous GaN-based epitaxial layer unit is connected to the P-type electrode layer of the next GaN-based epitaxial layer unit through a connecting electrode layer. The P-type electrode layer, the connecting electrode layer, and the N-type electrode layer each include an AuSn layer, an Au layer, a Ni layer, a first Ti layer, a first AlCu layer, a second Ti layer, a second AlCu layer, and a Cr layer sequentially arranged from top to bottom. The P-type electrode layer, the N-type electrode layer, and the connecting electrode layer are all formed in the same evaporation process; The manufacturing method of the high-power flip-chip high-voltage chip includes the following steps: (1) Fabricate the epitaxial layer. Use MOCVD equipment to sequentially grow an N-type GaN layer, a light-emitting quantum well, and a P-type GaN layer on the substrate to complete the fabrication of the GaN-based epitaxial layer; (2) Deposit an ITO layer on the GaN-based epitaxial layer, and then etch the ITO layer and the GaN-based epitaxial layer to expose the N-type GaN layer and form a plurality of isolated GaN-based epitaxial layer units on the GaN-based epitaxial layer; (3) Deposit an Ag layer on the surface of the ITO layer; (4) Deposit a first protective layer in the gap between adjacent GaN-based epitaxial layer units; (5) Evaporate the electrode layer. Evaporate a P-type electrode layer on the ITO layer, an N-type electrode layer on the N-type GaN layer, and a connecting electrode layer on the first protective layer, wherein both ends of the connecting electrode layer are respectively connected to the P-type electrode layer and the N-type electrode layer; (6) Deposit a second protective layer on the GaN-based epitaxial layer, and etch the second protective layer to form a P-type conductive hole exposing the P-type electrode layer and an N-type conductive hole exposing the last N-type electrode layer in series; 2. The manufacturing method of the high-power flip-chip high-voltage chip according to claim 1, characterized in that: In step (2), first etch an N-type step on the GaN-based epitaxial layer to expose the N-type GaN layer, and then etch isolation trenches on the GaN-based epitaxial layer to divide the entire GaN-based epitaxial layer into a plurality of isolated GaN-based epitaxial layer units.

3. The manufacturing method of the high-power flip-chip high-voltage chip according to claim 2, characterized in that: In step (4), the first protective layer is deposited in the isolation trenches.

4. The manufacturing method of the high-power flip-chip high-voltage chip according to claim 1, characterized in that: The materials of the first protective layer and the second protective layer are SiO2.

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