Integrated multi-path power amplifier

Abstract

The present disclosure relates to integrated multi-path power amplifiers. A multi-path amplifier (e.g., a Doherty amplifier) includes first and second transistors (e.g., a main transistor and a peaking transistor) each having a first output and a second output, all of which are integrally formed with a semiconductor die. A signal path through the second transistor extends in a second direction from a control terminal of the second transistor to the second output, where the second output corresponds to or is closely electrically coupled to a combining node. The amplifier also includes an integrated phase delay circuit configured to impart an overall phase delay (e.g., 90 degrees) to a signal carried between the first and second outputs. The integrated phase delay circuit includes a delay circuit bond wire coupled between the first and second outputs, and the delay circuit bond wire extends in a third direction that is angularly offset (e.g., perpendicular) from the second direction.

Description

TECHNICAL FIELD

[0001] Embodiments of the subject matter described herein relate generally to multi-path power amplifiers, and more particularly to multi-path power amplifiers having output combining circuitry. BACKGROUND

[0002] Doherty power amplifiers (PAs) have been one of the most popular amplifiers in cellular infrastructure applications for many years. Doherty PAs are expected to continue to be used heavily for upcoming 5G infrastructure deployments due to their suitability for amplifying signals with high peak-to-average power ratio (PAPR). However, despite the use of Doherty PAs for many years, conventional Doherty PA configurations are unable to address some new challenges associated with 5G deployments. These challenges include supporting communications over increasingly wide bandwidths using low-cost and increasingly compact amplifier devices, while meeting stringent RF performance requirements regarding linearity, efficiency, and power gain. SUMMARY

[0003] According to one aspect of the present disclosure, a multi-path amplifier is provided, comprising:

[0004] a semiconductor die;

[0005] a first transistor integrally formed with the semiconductor die and having a first output, wherein a first signal path through the first transistor extends in a first direction from a control terminal of the first transistor to the first output;

[0006] a second transistor integrally formed with the semiconductor die and having a second output and a combining node, wherein the second output corresponds to or is closely electrically coupled to the combining node, and wherein a second signal path through the second transistor extends in a second direction from a control terminal of the second transistor to the second output; and

[0007] an integrated phase delay circuit configured to impart an overall phase delay to a signal carried between the first output and the second output, wherein the integrated phase delay circuit includes a delay circuit bond wire coupled between the first output and the second output, and wherein the delay circuit bond wire extends in a third direction angularly offset from the second direction.

[0008] According to one or more embodiments, the overall phase delay is 90 degrees, and the delay circuit bond wire is configured to impart 30 degrees to 80 degrees of the overall phase delay.

[0009] According to one or more embodiments, the first output has an elongated first bond pad having a first length extending parallel to the first direction of the first signal path, and the delay circuit bond wire is connected in parallel along the first length of the elongated first bond pad.

[0010] According to one or more embodiments, the first output further includes an elongated conductive structure electrically coupled to the elongated first bond pad, wherein the elongated conductive structure has a second length extending perpendicular to the first direction, and the elongated conductive structure is tightly electrically coupled to a drain manifold of the first transistor.

[0011] According to one or more embodiments, the second output has an elongated second bond pad having a second length extending parallel to the second direction of the second signal path, and the delay circuit bond wire is connected in parallel along the second length of the elongated second bond pad.

[0012] According to one or more embodiments, the elongated first bond pad and the elongated second bond pad are arranged in parallel.

[0013] According to one or more embodiments, the second output further includes an elongated third bond pad electrically coupled to the elongated second bond pad, wherein the elongated third bond pad has a third length extending perpendicular to the second direction, and the elongated third bond pad is tightly electrically coupled to a drain manifold of the second transistor.

[0014] According to one or more embodiments, the multi-path amplifier additionally includes a set of output signal bond wires connected to the elongated third bond pad and extending in the second direction.

[0015] According to one or more embodiments, the multi-path amplifier additionally includes a shunt inductive circuit electrically coupled between the combined node and a ground reference node, wherein the shunt inductive circuit includes a shunt inductance integrated with the semiconductor die.

[0016] According to one or more embodiments, the shunt inductive circuit includes a first integrated inductance including a set of bond wires, and a second integrated inductance including one or more spiral inductors formed integral with the semiconductor die, wherein the first integrated inductance and the second integrated inductance are coupled in series between the combined node structure and the ground reference node.

[0017] According to one or more embodiments, the multi-path amplifier additionally includes: a video bandwidth circuit electrically coupled between the second output terminal and a ground reference node.

[0018] According to one or more embodiments, the semiconductor die includes a base semiconductor substrate having a bulk resistivity in a range from about 1,000 Ohm / cm to about 100,000 Ohm / cm or more.

[0019] According to one or more embodiments, the multi-path amplifier is a Doherty power amplifier, and wherein: the first transistor is a main amplifier transistor; and the second transistor is a peaking amplifier transistor.

[0020] According to one or more embodiments, the multi-path amplifier additionally includes: a signal divider integrated with the semiconductor die, wherein the signal divider is configured to divide power of an input radio frequency (RF) signal into a main input signal provided to the main amplifier transistor and a peaking input signal provided to the peaking amplifier transistor.

[0021] According to a second aspect of the present invention, there is provided a method of manufacturing a multi-path amplifier, the method comprising:

[0022] integrating a first transistor with a semiconductor die, wherein the first transistor has a first output terminal, and wherein a first signal path through the first transistor extends in a first direction from a control terminal of the first transistor to the first output terminal;

[0023] integrating a second transistor with the semiconductor die, wherein the second transistor has a second output terminal and a combining node, wherein the second output terminal corresponds to or is closely electrically coupled to the combining node, and wherein a second signal path through the second transistor extends in a second direction from a control terminal of the second transistor to the second output terminal; and

[0024] forming an integrated phase delay circuit by coupling a delay circuit bond wire between the first output terminal and the second output terminal, wherein the delay circuit bond wire extends in a third direction angularly offset from the second direction, and wherein the integrated phase delay circuit is configured to impart an overall phase delay to a signal carried between the first output terminal and the second output terminal. BRIEF DESCRIPTION OF DRAWINGS

[0025] A more complete understanding of the subject matter can be obtained by referring to the specific embodiments and to the detailed description that follows, taken in connection with the drawings, where like reference characters indicate like elements throughout the several views.

[0026] Figure 1 is a simplified schematic diagram of an integrated Doherty power amplifier according to example embodiments;

[0027] Figure 2 is a top view of a Doherty power amplifier die according to example embodiments;

[0028] Figure 3 is a Doherty amplifier die according to example embodiments Figure 2 is a cross-sectional side view of the Doherty amplifier die of

[0029] Figure 4 is a top view of a Doherty amplifier device packaged in a high power package according to example embodiments;

[0030] Figure 5 is a top view of a packaged Doherty amplifier device coupled to a printed circuit board substrate according to example embodiments; and

[0031] Figure 6 is a flowchart of a method of manufacturing a Doherty power amplifier die and a packaged Doherty amplifier device according to example embodiments. DETAILED DESCRIPTION

[0032] An embodiment of a multi-path amplifier includes a semiconductor die, a first transistor formed integral with the semiconductor die and having a first output, a second transistor formed integral with the semiconductor die and having a second output and a combination node, and an integrated phase delay circuit. A first signal path through the first transistor extends in a first direction from a control terminal of the first transistor to the first output, and a second signal path through the second transistor extends in a second direction from a control terminal of the second transistor to the second output. The second output corresponds to or is in close electrical coupling to the combination node. The integrated phase delay circuit is configured to impart an overall phase delay to a signal carried between the first output and the second output. The integrated phase delay circuit includes a delay circuit bond wire coupled between the first output and the second output, and the delay circuit bond wire extends in a third direction angularly offset from the second direction.

[0033] According to other embodiments, the overall phase delay is 90 degrees, and the delay circuit bond wires are configured to impart 30 degrees to 80 degrees of the overall phase delay. According to another other embodiment, the integrated phase delay circuit additionally includes a first output terminal and a second output terminal. According to another other embodiment, the first output terminal has an elongated first bond pad having a first length extending parallel to a first direction of the first signal path, and the delay circuit bond wires are connected in parallel along the first length of the elongated first bond pad. According to another other embodiment, the first output terminal further includes an elongated conductive structure electrically coupled to the elongated first bond pad, wherein the elongated conductive structure has a second length extending perpendicular to the first direction, and the elongated conductive structure is in close electrical coupling to a drain manifold of the first transistor. According to another other embodiment, the second output terminal has an elongated second bond pad having a second length extending parallel to a second direction of the second signal path, and the delay circuit bond wires are connected in parallel along the second length of the elongated second bond pad. According to another other embodiment, the elongated first bond pad and the elongated second bond pad are arranged in parallel. According to another other embodiment, the second output terminal further includes an elongated third bond pad electrically coupled to the elongated second bond pad, wherein the elongated third bond pad has a third length extending perpendicular to the second direction, and the elongated third bond pad is in close electrical coupling to a drain manifold of the second transistor. According to another other embodiment, the first length and the second length are in a range between 200 micrometers and 400 micrometers, and the third length is in a range between 800 micrometers and 1800 micrometers.

[0034] According to another other embodiment, the set of output signal bond wires are connected to the elongated third bond pad and extend in the second direction. According to another other embodiment, the multi-path amplifier further includes a shunt inductive circuit electrically coupled between the combination node and a ground reference node, wherein the shunt inductive circuit includes a shunt inductance integrated with the semiconductor die. According to another other embodiment, the shunt inductive circuit includes a first integrated inductance including the set of bond wires and a second integrated inductance including one or more spiral inductors formed integral with the semiconductor die, wherein the first integrated inductance and the second integrated inductance are coupled in series between the combination node structure and the ground reference node. According to another other embodiment, the shunt inductive circuit additionally includes a capacitor electrically connected in series with the first integrated inductance and the second integrated inductance. According to another other embodiment, a video bandwidth circuit is electrically coupled between the second output terminal and the ground reference node. According to another other embodiment, the semiconductor die includes a base semiconductor substrate having a bulk resistivity in a range of about 1000 ohms per centimeter (cm) to about 100,000 ohms / cm or greater.

[0035] According to another other embodiment, the multi-path amplifier is a Doherty power amplifier, and the first transistor is a main amplifier transistor and the second transistor is a peaking amplifier transistor. According to another other embodiment, the signal divider is integrated with the semiconductor die, wherein the signal divider is configured to divide power of an input radio frequency (RF) signal into a main input signal provided to the main amplifier transistor and a peaking input signal provided to the peaking amplifier transistor.

[0036] An embodiment of a method of manufacturing a multi-path amplifier includes forming a first transistor and a second transistor integral with a semiconductor die. The first transistor has a first output, and a first signal path through the first transistor extends in a first direction from a control terminal of the first transistor to the first output. The second transistor has a second output and a combining node, wherein the second output corresponds to or is in close electrical coupling to the combining node. A second signal path through the second transistor extends in a second direction from a control terminal of the second transistor to the second output. The method further includes forming an integrated phase delay circuit by coupling a delay circuit bond wire between the first output and the second output, wherein the delay circuit bond wire extends in a third direction angularly offset from the second direction, and the integrated phase delay circuit is configured to impart an overall phase delay to a signal carried between the first output and the second output.

[0037] According to other embodiments, forming the first transistor integral includes forming the first output to include an elongated first bond pad, and forming the second transistor integral includes forming the second output to include an elongated second bond pad having a length extending parallel to the second direction of the second signal path. The elongated first bond pad and the elongated second bond pad are arranged in parallel. According to another other embodiment, forming the integrated phase delay circuit includes a delay circuit bond wire connected between the elongated first bond pad and the elongated second bond pad.

[0038] In some typical conventional Doherty amplifiers, different semiconductor die for the main amplifier and the peaking amplifier are packaged in a discrete power amplifier device, and the discrete power amplifier device is coupled to a printed circuit board (PCB) that includes other parts of the Doherty amplifier. For example, an input splitter on the PCB is used to divide an input radio frequency (RF) signal into a main input signal and a peaking input signal, and the main input signal and the peaking input signal are supplied to the main amplifier and the peaking amplifier through input leads of the power amplifier device. On the output side of the Doherty amplifier, the amplified main signal and the peaking signal are provided by the power amplifier device through separate output leads. Depending on whether the Doherty amplifier has a non-inverting configuration or an inverting configuration, a phase delay and impedance inverter circuit (simply referred to as a "phase delay circuit") is coupled to the PCB along the main output path or the peaking output path. At the output of the phase delay circuit, the amplified main signal and the peaking signal are combined together by a Doherty combiner implemented on the PCB. In a high volume production environment, various performance issues can arise with conventional Doherty amplifiers due to placement tolerances of the main power amplifier die and the peaking power amplifier die, variations in the length and height of the bond wires within the device, and variations in the structure for implementing the phase delay circuit and the combiner at the PCB level.

[0039] Embodiments of the inventive subject matter include monolithic multi-path amplifiers, and in more particular embodiments, monolithic Doherty power amplifiers having integrated first and second power transistors (e.g., main and peaking power transistors), an integrated phase delay and impedance inverter circuit, and an integrated signal combiner connected between the output terminals (e.g., drain terminals) of the first and second power transistors. More specifically, the phase delay circuit and the signal combiner are implemented by conductive structures and bond wires that are integrated in the same die as the first and second power transistors. As used herein, the term "monolithic" means integrated with or within a single semiconductor die (e.g., die 201, Figure 2 , 3 ). When a component is referred to herein as being "monolithically formed" with a die (e.g., die 201, Figure 2 , 3 ), this means that the component structure forms part of the die itself (e.g., the component is produced during the die fabrication process and is physically located between the top and bottom surfaces of the die). For example, simply referring to Figure 2 and 3In contrast, when a component is said to be "integrated" with a die, this means that the component structure is "monolithically formed" with the die, or the component is attached to the die in a standalone manner (e.g., attached to a surface of the die 201). For example, a set of bond wires 262, 282 (where "set" means one or more) is considered to be "integrated" with the die 201, as each bond wire in the set of bond wires 262, 282 begins and lands on the top surface of the die 201 (i.e., both ends of each bond wire are bonded to different bond pads on the die top surface, and thus each bond wire is "standalone" within the die 201). In contrast, a set of bond wires 219, 290 is not considered to be "integrated" with the die 201, as the bond wires in the set of bond wires 219, 290 do not begin and land on the die 201 (i.e., only one end of each bond wire is bonded to a bond pad on the die top surface). Further, a discrete component that is coupled to the top surface of the die is also considered to be "integrated" with the die (e.g., a passive or active component is packaged separately from the input and output terminals, which are physically and electrically attached to bond pads exposed on the die surface, such as by solder or conductive adhesive).

[0040] As mentioned above, embodiments of Doherty amplifiers include an integrated signal combiner (or combining node structure) connected between the outputs of the main and peaking power transistors. In some embodiments, the signal combiner is tightly electrically coupled to the drain terminal of the peaking transistor, where "tightly electrically coupled" as used herein means directly connected or electrically coupled by one or more electrically conductive components (e.g., integrated electrically conductive traces or vias) that form an electrically conductive path having a total electrical resistance that is negligible (e.g., less than 5.0 ohms - 20 ohms) and free of passive or active electrical components (e.g., discrete or integrated resistors, inductors, capacitors, or transistors). Because the signal combiner can be implemented in close proximity to the drain of the peaking amplifier, a 90-0 Doherty amplifier can be achieved. The 90 degree phase difference between the main amplifier output and the peaking amplifier output is provided by an analog quarter wavelength transmission line having a capacitor-inductor-capacitor (CLC) topology. The CLC topology includes the drain-source capacitances of the main and peaking transistors, as well as a tightly controlled inductance implemented between the main amplifier output and the Doherty combining structure. Further, according to various embodiments, implementation of a shunt inductor (or shunt-L) circuit on-die can effectively compensate for additional parasitic drain-source capacitances of the peaking amplifier transistor that can otherwise limit performance.

[0041] In addition, various embodiments can significantly reduce or eliminate inter-device production variations associated with die placement, and can also reduce variations in bondwire length and height. Thus, implementation of various embodiments can enable Doherty amplifiers to have more consistent RF performance.

[0042] The following description of a Doherty amplifier die and the illustrated embodiments corresponds to a two-way Doherty amplifier including a main amplifier and one peaking amplifier. Although not explicitly illustrated, other embodiments can include an "N-way" Doherty power amplifier, where N > 2, and where the number of peaking amplifiers is equal to N-1. In addition, although the example embodiments described below specifically relate to embodiments of Doherty power amplifiers, the inventive subject matter can be more generally applicable to any type of multi-path amplifier that can benefit from implementation of the inventive circuitry and structures described herein. Thus, the inventive subject matter is not limited to application in Doherty power amplifiers only.

[0043] Figure 1 is a simplified schematic diagram of a multi-path Doherty power amplifier 100 according to example embodiments. The Doherty amplifier 100 includes an input node 102, an output node 194, a power divider 104 (or splitter), a main amplification path 110, a peaking amplification path 111, an integrated phase delay and impedance inverter circuit 160 (hereinafter, simply "phase delay circuit"), a combining node structure 164, and an output shunt-L circuit 180. A load 196 can be coupled (e.g., through an inductor 190 and the output node 194) to the combining node structure 164 to receive an amplified RF signal from the amplifier 100.

[0044] According to embodiments, at least the main amplification path 110, the peaking amplification path 111, the phase delay circuit 160, and the combining node structure 164 are integrated with or within a single integrated circuit die 101 (i.e., the circuitry is monolithic). In some other embodiments, the output shunt-L circuit 180 is also integrated with the die 101. In various embodiments, the power divider 104 can be implemented on-die or off-die. Off-die implementations are indicated by the solid rectangular box that does not include the power divider 104, but encloses the amplification paths 110, 111, the phase delay circuit 160, and the combining node structure 164. In off-die embodiments, the outputs 106, 108 of the power divider 104 can be electrically connected to the main path input 121 and the peaking path input 141, respectively. In other embodiments, and as discussed later, the power divider 104 (e.g., the power divider 204, Figure 2 Figure 2 ​) Alternatively integrated with die 101 having amplification paths 110, 111, phase delay circuit 160, and combiner node structure 164, as shown by the dashed rectangular box surrounding power divider 104.

[0045] Doherty power amplifier 100 is considered a "two-way" Doherty power amplifier, which includes one main amplifier 120 and one peaking amplifier 140. Main amplifier 120 provides amplification along main amplification path 110, and peaking amplifier 140 provides amplification along peaking amplification path 111. In other embodiments, more than one peaking amplifier can be implemented in parallel with first peaking amplifier 140 to produce an N-way Doherty power amplifier, where N > 2, and the number of peaking amplifiers is equal to N - 1.

[0046] Although main amplifier 120 and peaking amplifier 140 can be of equal size (e.g., in a symmetric Doherty configuration having a 1 : 1 main-to-peak size ratio), main amplifier 120 and peaking amplifier 140 can also be of unequal size (e.g., in various asymmetric Doherty configurations). In asymmetric two-way Doherty amplifier configurations, peaking power amplifier 140 is typically larger than main power amplifier 120 by some multiple. For example, peaking power amplifier 140 can be twice the size of main power amplifier 120, such that peaking power amplifier 140 has twice the current carrying capability of main power amplifier 120. Asymmetric main-to-peak amplifier size ratios other than the 1 :2 ratio can also be implemented.

[0047] Power divider 104 is configured to divide the power of an input RF signal received at input node 102 into a main portion and a peaking portion of the input signal. The main input signal is provided at power divider output 106 to main amplification path 110, and the peaking input signal is provided at power divider output 108 to peaking amplification path 111. During operation in a low power mode, when only main amplifier 120 supplies current to load 196, power divider 104 provides input signal power only to main amplification path 110. During operation in a full power mode, when both main amplifier 120 and peaking amplifier 140 supply current to load 196, power divider 104 divides input signal power between amplification paths 110, 111.

[0048] The power divider 104 can divide the power of the input RF signal equally or unequally. For example, when the Doherty amplifier 100 has an asymmetric Doherty amplifier configuration in which the size of the peaking amplifier 140 is approximately twice the size of the main amplifier 120 (i.e., the Doherty amplifier 100 has an asymmetric configuration with a 1 :2 main-to-peak size ratio), the power divider 104 can divide the power such that approximately one-third of the input signal power is provided to the main amplification path 110 and approximately two-thirds of the input signal power is provided to the peaking amplification path 111. In other words, with a 1 :2 main-to-peak size ratio, the size of the peaking amplifier 140 is approximately twice the size of the main amplifier 120, and the power divider 104 is configured to produce a peaking input signal that is approximately twice the power of the main input signal.

[0049] Alternatively, with a symmetric Doherty amplifier configuration (i.e., a main-to-peak size ratio of approximately 1 : 1), the power divider 104 can divide the power such that approximately half of the input signal power is provided to the main amplification path 110 at the power divider output 106 and approximately half of the input signal power is provided to the peaking amplification path 111 at the power divider output 108.

[0050] In essence, the power divider 104 divides the input RF signal supplied at the input node 102, and the divided signals are amplified along the main amplification path 110 and the peaking amplification path 111, respectively. The amplified signals are then combined in phase at the combining node structure 164. It is important to maintain phase coherence between the main amplification path 110 and the peaking amplification path 111 over the frequency band of interest (or operating frequency band) to ensure that the amplified main signal and peaking signal arrive in phase at the combining node structure 164, thereby ensuring proper operation of the Doherty amplifier. In the Doherty amplifier configuration depicted in FIG. 1 (i.e., a non-symmetrical Doherty configuration), the main amplification path 110 and the peaking amplification path 111 are configured to maintain phase coherence over the frequency band of interest. Figure 1 In the Doherty amplifier configuration depicted in FIG. 1 (i.e., a non-symmetrical Doherty configuration), the main amplification path 110 and the peaking amplification path 111 are configured to maintain phase coherence over the frequency band of interest.

[0051] Each of the main amplifier 120 and the peaking amplifier 140 includes a single power transistor or multiple cascaded power transistors for amplifying RF signals conducted through the amplifier 120, 140. As used herein, the term "transistor" refers to a field effect transistor (FET) or another type of suitable transistor. For example, the "FET" can be a metal oxide semiconductor FET (MOSFET), a lateral diffusion MOSFET (LDMOS FET), an enhancement or depletion mode high electron mobility transistor (HEMT), or another type of FET. According to various embodiments, each of the power transistors in the main amplifier 120 and the peaking amplifier 140 can be implemented, for example, using a silicon-based FET (e.g., LDMOS FET), a silicon germanium (SiGe)-based FET, or a III-V FET (e.g., HEMT), such as a gallium nitride (GaN) FET (or another type of III-V transistor, including a gallium arsenide (GaAs) FET, a gallium phosphide (GaP) FET, an indium phosphide (InP) FET, or an indium antimonide (InSb) FET).

[0052] According to embodiments, the main amplifier 120 is a two-stage amplifier that includes a relatively lower power preamplifier 126 and a relatively higher power final amplifier 130 connected in a cascaded arrangement between the main amplifier input 121 and the main amplifier output 134. In the main amplifier cascaded arrangement, the output 127 of the preamplifier 126 is electrically coupled to the input 129 of the final amplifier 130. Similarly, the peaking amplifier 140 is a two-stage amplifier that includes a relatively lower power preamplifier 146 and a relatively higher power final amplifier 150 connected in a cascaded arrangement between the peaking amplifier input 141 and the peaking amplifier output 154. In the peaking amplifier cascaded arrangement, the output 147 of the preamplifier 146 is electrically coupled to the input 149 of the final amplifier 150. In other embodiments, each of the main amplifier 120 and the peaking amplifier 140 can be a single-stage amplifier, or can include more than two cascaded coupled amplification stages. At the input 125, 145 of each preamplifier 126, 146 and between each preamplifier 126, 146 and each final amplifier 130, 150, an input impedance matching network 122, 142 (IMN) and an inter-stage impedance matching network 128, 148 (ISMN) can be implemented, respectively. In each case, the matching networks 122, 142, 128, 148 can incrementally increase the circuit impedance toward the load impedance.

[0053] During operation of the Doherty amplifier 100, the main amplifier 120 is biased to operate in an AB class mode, and the peaking amplifier 140 is typically biased to operate in a class C mode. In some configurations, the peaking amplifier 140 can be biased to operate in a class B or deep class B mode. At low power levels, where the power of the input signal at the node 102 is lower than the turn-on threshold level of the peaking amplifier 140, the amplifier 100 operates in a low power mode, in which the main amplifier 120 is the only amplifier supplying current to the load 196. When the power of the input signal exceeds the threshold level of the peaking amplifier 140, the amplifier 100 operates in a high power mode, in which both the main amplifier 120 and the peaking amplifier 140 supply current to the load 196. At this time, the peaking amplifier 140 provides active load modulation at the combined node structure 164 to allow the current of the main amplifier 120 to continue to increase linearly.

[0054] As will be explained in greater detail in connection with Figure 2 later, in embodiments, one or more resistor- divider gate bias circuits 170, 170' (e.g., resistor- divider gate bias circuits 270, 270', 270', 270' of FIGS. 2A and 2B, respectively, Figure 2 ) can be used to perform the gate biasing of the main amplifier 120 and the peaking amplifier 140, where each resistor- divider gate bias circuit 170, 170' includes at least one resistor 173, 174, 173', 174' electrically coupled between a gate bias voltage input 171, 171' and an input 125, 129, 145, 149 (e.g., a gate terminal) of each amplifier 126, 130, 146, 150. Drain biasing of the preamplifiers 126, 146 can also be performed using drain bias circuits (not shown in FIGS. 1A and 1B, but shown as circuit 277 in FIG. 2B). Figure 1 Figure 2

[0055] In embodiments, a shunt-L circuit 180 is coupled between the output 154 of the peaking amplifier 140 and a ground reference (or ground reference node). As previously mentioned, the shunt-L circuit 180 is configured to compensate for the drain-source capacitance at the output 151 of the peaking final amplifier 150. In embodiments, the shunt-L circuit 180 includes an inductance 182 and a capacitance 184 coupled in series between the output 154 of the peaking amplifier 140 and the ground reference.

[0056] ​​Furthermore, embodiments of the present subject matter can include a video bandwidth (VBW) circuit 186 coupled between the output 154 of the peaking amplifier 140 and a ground reference. In more particular embodiments, the VBW circuit 186 is coupled to a node between the inductor 182 and the capacitor 184 of the shunt-L circuit 180 (e.g., the "RF cold spot" node or some other node). As used herein, the "RF cold spot" node is a conductive node that can act as a virtual ground reference voltage for RF electrical signals. In various embodiments, components of the VBW circuit 186 can be integrated with the die 101, or components of the VBW circuit 186 can be implemented off-chip. Either way, the VBW circuit 186 is configured to improve the low frequency resonance (LFR) of the amplifier 100 caused by interactions between various circuitry and structures of the amplifier 100 by presenting a low impedance at the envelope frequency and / or a high impedance at the RF frequency. From an RF matching perspective, the VBW circuit 186 can be essentially "invisible" in that it primarily affects the impedance at the envelope frequency (i.e., the VBW circuit 186 provides termination for the signal energy of the amplifier 100 at the envelope frequency).

[0057] The VBW circuit 186 can have any of a number of configurations. In some embodiments, the VBW circuit 186 includes a series circuit of a resistor, an inductor, and a capacitor coupled between the peaking amplifier output 154 (or some other point along the amplification path 110, 111) and a ground reference. Although Figure 1 Although the VBW circuit 186 is shown coupled to a particular node, the VBW circuit 186 can be coupled to another node, or multiple VBW circuits can be coupled to multiple points along each amplification path 110, 111. For example, the VBW circuit 186 can be coupled between any output 127, 147 of the preamplifier 126, 146 and a ground reference, or the VBW circuit 186 can be coupled between any output 131, 151 of the final stage amplifier 130, 150 and a ground reference, or the VBW circuit 186 can be coupled between any input 125, 145 of the preamplifier 126, 146 and a ground reference.

[0058] The Doherty amplifier 100 has a "in-phase" load network configuration. In the in-phase configuration, the input circuit is configured such that the input signal supplied to the peaking amplifier 140 is delayed by 90 degrees relative to the input signal supplied to the main amplifier 120 at the center operating frequency fo of the amplifier 100. To ensure that the main input RF signal and the peaking input RF signal arrive at the main amplifier 120 and the peaking amplifier 140 with a phase difference of approximately 90 degrees, as is proper for the basic operation of a Doherty amplifier, as described above, an input phase delay circuit 109 applies a phase delay of approximately 90 degrees to the peaking input signal before it is provided to the peaking amplifier 140.

[0059] At the input to the amplifiers 120, 140, the 90 degree phase delay difference between the main amplification path 110 and the peaking amplification path 111 compensates for the 90 degree phase delay applied by the phase delay circuit 160 to the signal between the output of the main amplifier 120 and the combining node structure 164. In addition, the phase delay circuit 160 applies an impedance inversion to the amplified RF signal along the main amplification path 110. The phase delay circuit 160 includes a plurality of components 161, 162, 163 connected in series. According to embodiments, as will be discussed in more detail below, the components 161-163 include a combination of specially configured amplifier outputs 161, 163 connected by a bond wire 162. Figure 2 and Figure 3 As will be discussed in more detail below, the components 161-163 include a combination of specially configured amplifier outputs 161, 163 connected by a bond wire 162.

[0060] An alternative embodiment of a Doherty amplifier can have an "anti-phase" load network configuration. In this configuration, the amplifier is configured such that the input signal supplied to the main amplifier 120 is delayed by approximately 90 degrees relative to the input signal supplied to the peaking amplifier 140 at the center operating frequency fo of the amplifier 100, and the output phase delay circuit is configured to apply an approximately 90 degree phase delay and impedance inversion to the signal between the output of the peaking amplifier 140 and the combining node structure.

[0061] As the term is used herein, the Doherty amplifier 100 is "integrated" in that at least the main amplifier 120 (e.g., including the preamplifier 126 and the final amplifier 130), the peaking amplifier 140 (including the preamplifier 146 and the final amplifier 150), the phase delay circuit 160, and the combining node structure 164 are integrated with or within a single IC die 101 (e.g., the die 201, Figure 2 , 3), so it can be referred to herein as an "integrated Doherty amplifier die." According to embodiments, all or portions of the input and inter-stage impedance matching networks 122, 142, 128, 148 can also be integrated with or within the same IC die 101 (e.g., die 201, Figure 2 , 3 ). Additionally, the distributor 104 can be integrated with or within the same IC die 101 (e.g., die 201, Figure 2 ). Alternatively, the distributor 104 and / or all or portions of the input impedance matching networks 122, 142 can be implemented in one or more components different from the IC die that includes the main amplifier 120 and the peaking amplifier 140. According to another other embodiment, the resistor- voltage divider bias circuit 170, 170' is also integrated with or within the same IC die 101 (e.g., die 201, Figure 2 , 3 ) as the main amplifier 120 and the peaking amplifier 140, but in other embodiments the biasing can be performed by non-integrated circuits and structures. According to yet another other embodiment, the VBW circuit 186 is also integrated with or within the same IC die 101 (e.g., die 201, Figure 2 , 3 ) as the main amplifier 120 and the peaking amplifier 140, but in other embodiments the VBW circuit 186 can be implemented using non-integrated circuits and structures.

[0062] Figure 2 is a top view of an example embodiment of a Doherty power amplifier die 200 (or "Doherty IC"). For enhanced understanding, Figure 2 and Figure 3 should be viewed in conjunction with one another, Figure 3 is Figure 2 is a cross-sectional side view of the Doherty IC 200 of Figure 2 and 3 along line 3-3. It should be noted that the same reference numbers are used to indicate the same elements in

[0063] The Doherty IC 200 includes an entire Doherty amplifier (e.g., Doherty amplifier 100, Figure 1of the semiconductor die has a substantially rectangular periphery defined by opposite input and output sides 210 / 211 (e.g., the bottom side and the top side in the orientation of Figure 2 Fig. 2A) and opposite left and right sides 212 / 213 extending between the input and output sides. With reference to Figure 2 the coordinate legend at the top, the left and right sides 212, 213 are parallel to the direction 298, and the input and output sides 210, 211 are parallel to the direction 299. The overall direction of the signal path through the die 201 is parallel to the direction 298 (i.e., in the direction between the input terminal 202 and the output lead 298). In addition, the direction of the signal path through the transistors 226, 230, 246, 250 is also parallel to the direction 298 (i.e., in the direction between each respective gate terminal 225, 229, 245, 249 and drain terminal 227, 231, 247, 251). Circuitry within the die 201 is electrically connected to external circuitry by leads (e.g., leads 214, 216, 217, 218, 287, 294) located adjacent to the input and output sides 210 / 211 of the die 201, and by bonding wires (e.g., bonding wires 219, 290) between leads and bonding pads (e.g., bonding pads 202, 271, 271', 278, 285) connected on the die 201.

[0064] In the specific embodiment shown in Figure 2 Fig. 2A, the Doherty amplifier die 200 includes the following circuitry integrated with or within the semiconductor die 201: a two-stage main amplifier 220 (e.g., the main amplifier 120, Figure 1 ), a two-stage peaking amplifier 240 (e.g., the peaking amplifier 140, Figure 1 ), a phase shift / impedance inverter circuit 260 (e.g., the phase shift / impedance inverter 160, Figure 1 ), a combining node structure 264 (e.g., the combining node structure 164, Figure 1 ), resistor-divider bias circuits 270, 270' (e.g., the resistor-divider bias circuits 170, 170', Figure 1 ), a drain bias circuit 277, and a shunt-L circuit 280 (e.g., the shunt-L circuit 180, Figure 1 ). Figure 2 The Doherty IC 200 of Fig. 2A additionally includes a power divider 204 (e.g., the power divider 104, Figure 1 ) and an input phase delay circuit 209 (e.g., the input phase delay circuit 109, Figure 1 ).

[0065] As in Figure 3As best seen in FIG. 3, the semiconductor die 201 includes a base semiconductor substrate 310 and a plurality of build-up layers 312 over a top surface of the base semiconductor substrate 310. In particular example embodiments, the base semiconductor substrate 310 is a high resistivity silicon substrate (e.g., a silicon substrate having a bulk resistivity in a range of about 1000 ohm / cm to about 100,000 ohm / cm or greater). Alternatively, the base semiconductor substrate 310 can be a semi-insulating gallium arsenide (GaAs) substrate (e.g., a GaAs substrate having a bulk resistivity of up to 10 8 ohm / cm), or another suitable high resistivity substrate. In still other alternative embodiments, the base semiconductor substrate 310 can be a GaN substrate or any of a variety of other III-V semiconductor substrates. An advantage of using a high resistivity substrate is that such a substrate can cause various on-die circuitry (e.g., the on-die combiner node structure 264 and other circuitry) to exhibit relatively low losses as compared to an amplifier die that does not use a high resistivity substrate.

[0066] The plurality of build-up layers 312 can include, for example, a plurality of interleaved dielectric layers, patterned conductive layers, and other conductive structures (e.g., conductive polysilicon structures). Portions of different patterned conductive layers and structures in the build-up layers 312 are electrically coupled with conductive vias. Additionally, conductive through-substrate vias (TSVs) (e.g., TSVs 348) can provide conductive paths between the top and bottom surfaces of the base semiconductor substrate 310. The TSVs can or can not be lined with dielectric material to insulate the TSVs from the base semiconductor substrate 310. According to embodiments, a conductive layer 328 on or over the bottom surface of the base semiconductor substrate 310 acts as a ground reference node for the Doherty IC 200. As used herein, a “ground reference node” refers to a conductive component that is integrally formed with the semiconductor die 201 and is configured to be electrically coupled to an external conductive component, which in turn can be electrically coupled to a ground reference voltage source. Thus, although not shown in FIG. 3, the conductive layer 328 can be physically and electrically coupled to a ground node of a package substrate (e.g., a flange 430, Figure 2 、 3 ) when the Doherty IC 200 is finally packaged. In other embodiments, the “ground reference node” can be a conductive component of the die 201 that is integrally formed other than the conductive layer 328 (e.g., the ground reference node can be a bond pad, an end of one or more conductive vias, or other integrally formed conductive component). Figure 4

[0067] ​In the following description of the Doherty IC 200, reference will be made to various circuits including capacitors, inductors, and / or resistors. For example, in various embodiments, the capacitor may be an integrated metal-insulator-metal (MIM) capacitor (e.g., capacitor 284) formed within a building layer (e.g., layer 312). Figure 2 Discrete capacitors and / or other types of capacitors coupled to the top surface of die 201. For example, resistors may be integrated resistors (e.g., formed from polysilicon within building layer 312) or discrete resistors coupled to the top surface of die 201. Inductors may be integrally formed spiral inductors (e.g., spiral inductors 282', 282") from patterned conductive layers and vias within building layer (e.g., layer 312). Figure 2 ), or they can be made of bonding wires (e.g., bonding wires 262, 290, Figure 2 , 3 Patterned conductive components (e.g., bonding pads 261, 263), Figure 2 Discrete inductors or inductors formed from other inductor components.

[0068] exist Figure 2 , 3 In each embodiment, the main amplifier 220 and the peaking amplifier 240 include a cascaded arrangement of two power transistors, including relatively low-power preamplifier transistors 226, 246 (e.g., preamplifiers 126, 146). Figure 1 ) and relatively high-power final-stage amplifier transistors 230, 250 (e.g., final-stage amplifiers 130, 150, ) Figure 1 The description herein refers to each transistor including a control terminal and two current-conducting terminals. For example, using the terminology associated with FETs, "control terminal" refers to the gate terminal of the transistor, and the first and second current-conducting terminals refer to the drain and source terminals of the transistor (and vice versa). Although the following description may use terminology commonly used in conjunction with FET devices, the various embodiments are not limited to implementations using FET devices and, rather, are intended to apply to implementations using bipolar junction transistor (BJT) devices or other suitable types of transistors.

[0069] Each transistor 226, 230, 246, 250 includes gate terminals 225, 229, 245, 249 (or control terminals), drain terminals 227, 231, 247, 251 (or output terminals), and an unnumbered source terminal. In a specific embodiment, each transistor 226, 230, 246, 250 is an LDMOS FET, which includes an active region disposed between the gate terminal and the drain terminal. (Refer to...) Figure 3The cross-sections shown indicate that the active regions of FETs 230 and 250 each include multiple elongated, parallel, and staggered drain regions 332 and 352 (in... Figure 3 (shown as an unfilled box in the cross-section) and source regions 334, 354 (in) Figure 3 (Seen as a shaded outline in a cross-section), where each drain region and each source region are doped semiconductor regions formed in a base semiconductor substrate (e.g., substrate 310). The drain region 332 of FET 230 is electrically coupled to a first drain manifold, and similarly, the drain region 352 of FET 250 is electrically coupled to a second drain manifold. Each of the drain manifolds of FETs 230, 250 is tightly electrically coupled to its corresponding drain terminal 231, 251 (or output terminal, or current conduction terminal). Due to their elongated shape, each set of adjacent drain and source regions and the gate structures 336, 356 covering the channel region between adjacent drain and source regions can be referred to as "transistor fingers". Each transistor 226, 230, 246, 250 includes a plurality of parallel transistor fingers (in the active region of the transistor) in the active region of the transistor. Figure 2 (Used as vertical lines in the middle). For example... Figure 2 As shown by the vertical line, the transistor finger has the longest dimension parallel to direction 298.

[0070] A variable conductivity channel region (and, in some embodiments, a drain drift region) exists between adjacent source regions 334, 354 and drain regions 332, 352. Conductive (e.g., polysilicon or metal) gate structures 336, 356 formed in the build layer 312 above the base semiconductor substrate 310 extend over and along the elongated channel regions, and the gate structures 336, 356 are coupled to each gate terminal 229, 249. Similarly, additional conductive (e.g., polysilicon or metal) drain contacts are formed on the base semiconductor substrate 310. Figure 3 (Not depicted) Extending along elongated drain regions 332, 352 to conduct current between drain regions 332, 352 and corresponding drain manifolds. As mentioned above, the drain manifolds are tightly electrically coupled to each drain terminal 231, 251 having additional conductive structures (simply indicated by vias 338, 358). The source regions are electrically coupled to conductive (e.g., polysilicon or metal) source contacts (e.g., contacts 339, 359), which in turn are coupled to conductive TSVs (e.g., TSV 348, ...). Figure 3), which extends through the base semiconductor substrate 310 to connect with the conductive layer 328 on the bottom surface of the base semiconductor substrate. Voltages applied to the gate terminals 225, 229, 245, 249 during operation modulate the conductivity of the variable conductive channel, enabling current to flow between the source and drain regions (or ultimately between the conductive layer 328 and each of the drain terminals 227, 231, 247, 251).

[0071] The circuitry integrated within and coupled to the Doherty IC 200 will now be described in greater detail. The Doherty IC 200 includes an integrated power divider 204 (e.g., power divider 104, Figure 1 ). More specifically, an input 202 (e.g., input node 102, Figure 1 ) configured to receive an input RF signal for amplification is electrically connected with a divider input 205 (e.g., input 105, Figure 1 ) of the power divider 204 through a conductive path implemented in the build layer of the Doherty IC 200. The input 202 can include, for example, a conductive bond pad exposed at a top surface of the die 201, and the conductive bond pad is configured for attachment of one or more bond wires 219. Alternatively, the die 201 can be a flip-chip die or can expose an input at a bottom surface of the die 201, in which case the input 202 can be comprised of a conductive bond pad or other type of connection. These alternative configurations can also apply to other terminals (e.g., terminals 271, 271', 278) of the Doherty IC 200.

[0072] The power divider 204 (e.g., power divider 104, Figure 1 ) is configured to divide the power of the input RF signal received at the input 202 into a main portion of the input signal and a peaking portion of the input signal. As described in connection with Figure 1 , the power divider 204 is configured to divide the power of the input RF signal received at the input 202 into one main portion (or "main input signal") of the input signal and one peaking portion (or "peaking input signal") of the input signal. The main input signal is produced at a power divider output 206 (e.g., output 106, Figure 1 ), and the peaking input signal is produced at a power divider output 208 (e.g., output 108, Figure 1 ). As previously discussed, the power divider 204 can divide the power equally or unequally depending on the relative sizes of the main amplifier 220 and the peaking amplifier portion 240. In Figure 2 and Figure 3In embodiments, main amplifier 220 is approximately half the size of peaking amplifier 240 (i.e., the final amplifiers FET 230, 250 have a 1 :2 size relationship, and the Doherty amplifier is an asymmetric amplifier with a 1 :2 main-to-peak ratio), so power divider 204 divides the input RF signal such that approximately one-third of the input signal power is produced at power divider output 206, and approximately two-thirds of the input signal power is produced at power divider output 208. In other embodiments, main amplifier 220 and peaking amplifier 240 can have different asymmetric size relationships. In still other embodiments, main amplifier 220 and peaking amplifier 240 can be equal in size (i.e., the final amplifiers FET 230, 250 have a 1 : 1 size relationship, and the Doherty amplifier is a symmetric amplifier with a 1 : 1 main-to-peak ratio), in which case power divider 204 can divide the power of the RF input signal into equal portions.

[0073] In embodiments, input 205 has a 50 ohm input impedance, although the input impedance can be less than or greater than 50 ohms. According to embodiments, power divider 204 has a Wilkinson-based design that essentially divides the power of the input signal received at input 205 into two signals (i.e., a main input signal and a peaking input signal) having equal phase at outputs 206 and 208. In alternative embodiments, power divider 204 can divide the power of the input signal received at input 205 into two signals that are out of phase with each other (e.g., 90 degrees out of phase).

[0074] Output 206 of power divider 204 is electrically connected to the input of main amplifier 220 through a conductive path implemented in the build-up layers of die 201. According to embodiments, output 208 of power divider 204 is electrically connected to the input of peaking amplifier 240 through input phase delay circuit 209 (e.g., input phase delay circuit 109, Figure 1) and additional conductive paths implemented in the build layers of the die 201 are electrically connected to the input of the peaking amplifier 240. The input phase delay circuit 209 is configured to apply a delay to the peaking input signal to ensure that the peaking input signal at the input of the peaking amplifier 240 has approximately 90 degrees of phase difference from the main input signal at the input of the main amplifier 220. According to embodiments, the input phase delay circuit 209, which is implemented with integrated components as shown in the circuit schematic next to the circuit 209, can include a pi-configured phase delay circuit. For example, the phase delay circuit 209 can include an integrated inductor having a first end coupled to the output 208 of the distributor 204, a second end coupled to the input of the peaking amplifier 240, and an integrated shunt capacitor coupled between each inductor end and a ground reference. In alternative embodiments, the input phase delay circuit 209 can be implemented using a transmission line (or bond wire) having an appropriate electrical length (e.g., approximately 90 degrees or a lesser amount sufficient to produce the desired phase delay) or using some other delay circuit structure or configuration.

[0075] In embodiments, each of the main amplifier 220 and the peaking amplifier 240 can have substantially similar configurations. According to embodiments, each amplifier 220, 240 is a two-stage amplifier that includes a relatively low power preamplifier 226, 246 (or preamplifier FET) and a relatively higher power final amplifier transistor 230, 250 (or final amplifier FET) connected in a cascaded arrangement between an amplifier input 221, 241 and a combined node structure 264.

[0076] In the main amplifier 220, the input 221 of the amplifier 220 is coupled through an input impedance matching network 222 (e.g., the IMN 122, Figure 1 ) to an input terminal 225 (e.g., a gate terminal) of the preamplifier FET 226, and an output 227 (e.g., a drain terminal) of the preamplifier FET 226 is electrically coupled through an inter-stage impedance matching network 228 (e.g., the ISMN 128, Figure 1 ) to an input terminal 229 (e.g., a gate terminal) of the final amplifier FET 230. Similarly, in the peaking amplifier 240, the input 241 of the amplifier 240 is coupled through an input impedance matching network 242 (e.g., the IMN 142, Figure 1 ) to an input terminal 245 (e.g., a gate terminal) of the preamplifier FET 246, and an output 247 (e.g., a drain terminal) of the preamplifier FET 246 is electrically coupled through an inter-stage impedance matching network 248 (e.g., the ISMN 148, Figure 1) electrically coupled to an input 249 (e.g., a gate terminal) of the final amplifier FET 250. The source terminal of each of the FETs 226, 230, 246, 250 is electrically coupled to a ground reference (e.g., through the base semiconductor substrate 310 to the bottom conductive layer 328 using a TSV 348, Figure 3 ).

[0077] In embodiments, the pre-amplifier FETs 226, 246 can be equal in size and can be configured to apply a gain in a range of about 15 decibels (dB) to about 25 dB to the respective input RF signal when the Doherty IC 200 is operating in a high power mode (e.g., near compression), but only the pre-amplifier FET 226 provides gain for its input signal when the Doherty IC 200 is operating in a low power mode. The final amplifier FETs 230, 250 are significantly larger than the pre-amplifier FETs 226, 246 (e.g., at least twice as large to apply at least twice the gain). In asymmetric configurations, as shown in FIGS. 2A and 2B, the final amplifier FETs 230, 250 are different in size. Specifically, the final amplifier FET 250 of the peaking amplifier 240 is about twice as large as the final amplifier FET 230 of the main amplifier 220, but the size ratio can be different. Either way, each final amplifier FET 230, 250 can be configured to apply a gain in a range of about 15 dB to about 25 dB to the respective input RF signal when the Doherty IC 200 is operating in a high power mode (e.g., near compression), but only the final amplifier FET 230 provides gain for its input signal when the Doherty IC 200 is operating in a low power mode. Figure 2 and 3

[0078] The output (i.e., the drain manifold and drain terminal 231, 251) of each of the final amplifier FETs 230, 250 is electrically connected to a combining node structure 264 (e.g., the combining node structure 164, Figure 1 ) that functions to combine the amplified RF signals produced by each of the final amplifier FETs 230, 250 into a single amplified output RF signal. More specifically, the drain manifold and drain terminal 231 of the final main amplifier FET 230 is electrically coupled to the combining node structure 264 (as well as the drain terminal 251 of the final peaking amplifier FET 250) through a phase delay circuit 260 (e.g., the phase delay circuit 160, Figure 1 ) in accordance with embodiments. The phase delay circuit 260 essentially includes the drain terminals 231, 251 and a set of bond wires 262 coupled between the drain terminals 231, 251.

[0079] ​According to an embodiment, the drain terminal 231 of the final-stage main amplifier FET 230 is uniquely configured such that a first set of bonding lines 262 (referred to as “delay circuit bonding lines”) can be coupled parallel to each other to the drain terminal 231, such that the delay circuit bonding lines 262 extend in a direction (e.g., direction 299) that is angularly offset (e.g., perpendicular or orthogonal to the direction of the signal path through the die 201), and more specifically, in the direction of the signal path through the final-stage main amplifier FET 230. During operation of the device 200, the vertical (or otherwise angularly offset) orientation of the delay circuit bonding lines 262 relative to the direction of the signal path through the die 201 and the transistor 230 can reduce electromagnetic coupling between the signal transmitted through the delay circuit bonding lines 262 and the signal transmitted through the transistor 230.

[0080] In order for the delay circuit bonding wire 262 to be connected to the drain terminal 231 as described above, the drain terminal 231 has a sufficiently large depth (i.e., Figure 2 (the vertical dimension in the text) so that the delay circuit bond line 262 can couple to the drain terminal 231 in the orthogonal orientation explained above. Figure 2 In the depicted embodiment, drain terminal 231 includes an elongated first conductive structure 265 (i.e., extending along a dimension parallel to direction 299) directly connected to the drain region of the final-stage main amplifier FET 230 (or tightly electrically coupled to a drain manifold), and an elongated bonding pad 261 exposed on the top surface of die 201, large enough to allow a plurality of delay circuit bonding lines 262 to be connected in parallel to each other along the length of bonding pad 261 (a dimension parallel to direction 298). The conductive structure 265 and bonding pad 261 may be formed from the same conductive layer (including integrally formed from the same conductive layer), or they may be tightly electrically coupled different conductive components. In the embodiment, the long dimension of the first conductive structure 265 is perpendicular to the direction of the signal path through die 201 and transistor 230 and parallel to the direction of the delay circuit bonding lines 262. Conversely, the long dimension of the bonding pad 261 is parallel to the direction of the signal path passing through the die 201 and the transistor 230, and perpendicular to the direction of the delay circuit bonding line 262.

[0081] The drain terminal 251 of the final stage peaking amplifier FET 250 also includes a bond pad exposed at the top surface of the die 201. According to embodiments, the drain terminal 251 is uniquely configured to enable the second array or plurality of bond wires 290 (referred to as “output signal bond wires”) to be coupled to the drain terminal 251 parallel to one another, such that the output signal bond wires 290 extend in a first direction (e.g., direction 298), and further to enable the delay circuit bond wires 262 to be coupled to the drain terminal 251 parallel to one another, such that the delay circuit bond wires 262 extend in a second direction (e.g., direction 299) that is angularly offset from the first direction (e.g., perpendicular to the first direction). For example, the first and second directions can be orthogonal (i.e., offset by 90 degrees from one another), or the first and second directions can be angularly offset by an angle greater than or less than 90 degrees (e.g., an angle in a range of about 30 degrees to about 150 degrees). In one embodiment, as shown in FIG. 3, the first direction of the output signal bond wires 290 can be parallel to the direction of the signal path through the die 201, and more particularly, parallel to the direction of the signal path through the final stage peaking amplifier FET 250 (e.g., direction 298), and the second direction of the delay circuit bond wires 262 can be perpendicular to the direction of the signal path through the die 201, and more particularly, perpendicular to the direction of the signal path through the final stage peaking amplifier FET 250. Figure 2

[0082] To enable the first and second bond wires 290, 262 to be connected to the drain terminal 251 as described above, the drain terminal 251 has a width (i.e., horizontal dimension in Figure 2 ) and a depth (i.e., vertical dimension in Figure 2 ) that are large enough to enable the output signal and delay circuit bond wires 290, 262 to be coupled to the drain terminal 251 in an orthogonal manner relative to one another. In Figure 2 ​In the illustrated embodiment, the drain terminal 251 includes an elongated first bonding pad 266 that is directly connected to the drain region of the final peaking amplifier FET 250 and is large enough to enable multiple output signal bonding wires 290 to be connected to one another in parallel along the length of the first bonding pad 266 (the horizontal dimension parallel to the direction 299). The drain terminal 251 also includes an elongated second bonding pad 263 that is large enough to enable multiple delay circuit bonding wires 262 to be connected to one another in parallel along the length of the second bonding pad 263 (the vertical dimension parallel to the direction 298). The bonding pads 263, 266 can be formed from (including integrally formed from) the same conductive layer, or they can be different conductive components that are in close electrical coupling. In embodiments, the long dimension of the first bonding pad 266 is perpendicular to the direction of the signal path through the die 201 and the transistor 250, and also perpendicular to the direction of the output signal bonding wires 290. Conversely, the long dimension of the second bonding pad 263 is parallel to the direction of the signal path through the die 201 and the transistor 250, and perpendicular to the direction of the delay circuit bonding wires 262.

[0083] Accordingly, the direction of the delay circuit bonding wires 262 (i.e., the direction 299) is perpendicular to (or orthogonal to) the direction of the signal path through the die 201 and the transistor 250 (i.e., the direction 298), and also perpendicular to the direction of the output signal bonding wires 290. During operation of the device 200, the perpendicular (or otherwise angularly offset) orientation of the delay circuit bonding wires 262 relative to the direction of the signal path through the die 201 and the transistor 250, and also relative to the direction of the output signal bonding wires 290, can reduce electromagnetic coupling between signals that are conveyed through the delay circuit bonding wires 262 and signals that are conveyed through the output signal bonding wires 290, and also can reduce electromagnetic coupling between signals that are conveyed through the delay circuit bonding wires 262 and signals that are conveyed through the transistor 250.

[0084] According to embodiments, the length (horizontal dimension) of the drain terminals 231, 251 is in the range of about 800 microns to about 1800 microns, although the length of the drain terminals 231, 251 can be smaller or larger. Further, the length (vertical dimension) of the bonding pads 261, 263 can be in the range of about 200 microns to about 400 microns, although the length of the bonding pads 261, 263 can be smaller or larger. As Figure 2As shown, bond pads 261, 263 are arranged parallel to each other and aligned with the left edges of drain terminals 231, 251 (and aligned with the left edges of final FETs 230, 250). In other embodiments, one or both of bond pads 261, 263 can be positioned at other locations along the width of their respective drain terminals 231, 251 (or more specifically, along portions 265, 266 of drain terminals 231, 251) rather than aligned with the left edges of drain terminals 231, 251. Additionally, while both bond pads 261, 263 extend in direction 298 away from the FET 230, 250 to which they are coupled, in other embodiments one or both of bond pads 261, 263 can extend in other directions (including toward the FET input terminals 229, 249). In other words, while in Figure 2 In some embodiments, the two drain terminals 231, 251 (or "output terminals") are shown as having an "L" shape, but in other embodiments the drain terminals 231, 251 can have other suitable shapes (e.g., a "T" shape, a triangle, a taper, etc.).

[0085] In some embodiments, the combination node structure 264 and the bond pad 266 associated with the drain terminal 251 of the final peaking amplifier FET 250 are the same conductive structure. In other words, the combination node structure 264 can substantially correspond to the drain terminal 251 (or more specifically, to the bond pad 266). In effect, the combination node structure 264 can be implemented with the conductive structure that is electrically coupled to the drain terminal 251 of the final peaking amplifier FET 250. It is desirable that the drain terminal 251 be connected to the combination node structure 264 through a conductive path that has a negligible phase delay (i.e., a phase delay as close to zero degrees as possible, such as a phase delay of 10 degrees or less), and in some embodiments the drain terminal 251 can be an integrally formed part of the combination node structure 264. In other words, in some embodiments the drain terminal 251 of the final peaking amplifier final FET 250 can form part of the combination node structure 264.

[0086] As indicated above, the drain terminal 231 of the final main amplifier FET 230 is electrically coupled to the combination node structure 264 through a phase delay circuit 260. Specifically, the phase delay circuit 260 includes an integrated conductive structure between the drain region of the FET 230 (or the drain manifold of the FET 230) and the conductive structure 265, the conductive structure 265, the bond pad 261, the delay circuit bond wire 262, the bond pad 263, and the bond pad 266. The phase delay circuit 260 imposes a phase delay of approximately 90 degrees to the signal communicated between the drain region of the final main amplifier FET 230 (or the drain manifold) and the combination node structure 264. In addition, the phase delay circuit 260 imposes an impedance inversion between the final main amplifier FET 230 and the combination node structure 264. As previously described, there is a 90 degree phase difference between the main amplification path and the peaking amplification path at the inputs of the amplifiers 220, 240, and the overall phase delay of approximately 90 degrees imposed by the phase delay circuit 260 enables the amplified main and peaking signals to be combined substantially in phase (or coherently) at the combination node structure 264.

[0087] Each of the series-coupled conductive structures between the drain of the FET 230 and the combination node structure 264 contributes to the 90 degree delay imposed by the phase delay circuit 260. In addition, the parasitic drain-source capacitances of the final main and peaking FETs 230, 250 affect the overall phase delay imposed by the phase delay circuit 260. According to embodiments, the number, length, and shape of the bond wires 262 are selected to achieve a 90 degree overall electrical length of the phase / delay / impedance inverter circuit 260. For example, according to one embodiment, the bond wires 262 can be configured to have an electrical length (and impose a phase delay) of approximately 30 degrees to approximately 80 degrees for RF signals carried through the bond wires 262. The remaining portion of the 90 degree electrical length / phase delay is provided by other conductive components of the phase delay circuit 260, as affected by the parasitic drain-source capacitances of the final main and peaking FETs 230, 250. It should be noted that, although the phase delay circuit 260 is shown as being implemented using bond wires 262, other conductive structures can be used to implement the phase delay circuit 260, such as conductive traces, conductive vias, and the like. Figure 3 While four bond wires 262 are shown connected in parallel with each other between the drain terminals 231 and 251, in alternative embodiments, fewer (e.g., as few as two) or more (e.g., 10 or more) bond wires can be connected in parallel between the drain terminals 231 and 251.

[0088] According to embodiments, the phase delay circuit 260 has a CLC (capacitor-inductor-capacitor) topology between the drain terminal 231 and the drain terminal 251. The first (shunt) capacitor of the CLC topology includes the drain-source capacitance C dsMIn some embodiments, this first (shunt) capacitance can be augmented with additional capacitance provided by one or more additional shunt capacitors (e.g., MIM capacitors, not shown) coupled in parallel with C Figure 2 between the main amplifier final FET drain terminal 231 and the die ground reference (e.g., conductive layer 328, dsM Desirably, for a symmetric Doherty amplifier, the capacitance of the additional shunt capacitors is selected so that the combined capacitance of C dsM and the additional shunt capacitors is approximately equal to the drain-source capacitance C dsP of the final peaking amplifier FET 250. For asymmetric Doherty amplifiers, such as shown in Figure 1 and 3 , the drain-source capacitance C dsM of the final main amplifier FET 230 can be designed to be lower than the drain-source capacitance C dsP of the final peaking amplifier FET 250. In asymmetric Doherty amplifier embodiments, if a combined capacitance of C dsM and the additional shunt capacitors is included, it should be designed so that the transmission path (or “pseudo transmission line”) between the final main amplifier FET 230 and the final peaking amplifier FET 250 provides approximately 90 degrees of phase shift at the center operating frequency. Additionally, if a combined capacitance of C dsM and the additional shunt capacitors is included, it should be designed so that:

[0089]

[0090]

[0091] where freq is the center operating frequency (f0), L D is the inductance of the conductive path between the drain terminal 231 of the main amplifier final FET 230 and the drain terminal 251 of the final peaking amplifier FET 250, C DS is the output capacitance of the final main amplifier FET 230 and / or the final peaking amplifier FET 250, and Z C is the characteristic impedance of the pseudo transmission line between the drain terminal 231 of the final main amplifier FET 230 and the drain terminal 251 of the final peaking amplifier FET 250. For example, in embodiments, the parallel combination of C dsM and the additional shunt capacitors can have a combined capacitance value in a range of about 3 picofarads (pF) to about 10 pF (e.g., about 5 pF to about 6 pF) at a center operating frequency of about 2.0 gigahertz (GHz), although the center operating frequency and / or the combined capacitance can be lower or higher.

[0092] The inductance in the CLC topology of phase delay circuit 260 is primarily provided by delay circuit bond wires 262, with sub-components of inductance also provided by bond pads 261, 263. Delay circuit bond wires 262 each have a first end connected to bond pad 261 (which in turn is tightly electrically coupled to the final stage main amplifier FET drain (or drain manifold) through portion 265 of drain terminal 231), and a second end connected to bond pad 263. Bond pad 263 is electrically coupled to the combination node structure 264 (and / or to portion 266 of drain terminal 251). According to embodiments, the series combination of drain pad portion 265, bond pad 261, bond wires 262, bond pad 263, and drain pad portion 266 has a combined inductance in a range of about 0.8 nano henries (nH) to about 1.2 nH at a center operating frequency of about 2.0 GHz, although the center frequency and / or combined inductance can be lower or higher.

[0093] Finally, as explained below, the second (shunt) capacitance in the CLC topology of phase delay circuit 260 is approximately equal to the drain-source capacitance C dsP of final stage peaking amplifier FET 250, less a portion of C dsP compensated by the shunt inductance (of shunt inductors 282, 282', 282", for example). In other words, the second shunt capacitance can be represented as A x C dsP , where A < 1.0, and (1.0 - A) x C dsP is equivalent to the negative capacitance provided by the compensating shunt inductance (of shunt inductors 282, 282', 282", for example). In embodiments, C dsP has a capacitance value in a range of about 5 pF to about 10 pF (e.g., about 7 pF to about 8 pF) at a center operating frequency of about 2.0 GHz, although the center frequency and / or capacitance can be lower or higher.

[0094] In summary, the 90 degree phase difference between drain terminal 231 and drain terminal 251 (or combination node 264) is provided by phase delay circuit 260 having a CLC topology that includes a first shunt capacitance (e.g., provided by C dsM and possibly by additional shunt capacitors), a series inductance circuit (e.g., provided by drain pad portion 265, bond pad 261, delay circuit bond wires 262, bond pad 263, and drain pad portion 266), and a second shunt capacitance (e.g., provided by A x C dsP , where A < 1.0, when including compensating shunt inductance, as described below).

[0095] As previously mentioned, the RF signals amplified by the main amplification path and the peaking amplification path are combined in phase at the combining node 264 to produce an amplified output RF signal. In embodiments, the combining node 264 is electrically connected to the output lead 294 (e.g., the output node 194, Figure 1 ) by a plurality of output signal bond wires 290 (e.g., inductances 190, Figure 1 ). Thus, the amplified output RF signal is transferred from the combining node 264 to the output lead 294 by the bond wires 290. According to embodiments, the output signal bond wires 290 are configured to have a relatively low inductance, such as an inductance value in a range of about 20 picohenries (pH) to about 70 pH (e.g., about 60 pH), although the inductance value can be smaller or larger. It is desirable that the bond wires 290 are designed such that the inductance value of the bond wires 290 is as low as possible.

[0096] According to embodiments, in embodiments, the shunt-L circuit 280 (e.g., the shunt-L circuit 180, Figure 3 ) is coupled between the final peaking amplifier drain terminal 251 (or the combining node 264) and a die ground reference (e.g., the conductive layer 328, Figure 1 ). As previously mentioned, the shunt-L circuit 280 is configured to compensate (e.g., resonate) for the drain-source capacitance at the drain terminal 251 of the final peaking amplifier FET 250. In embodiments, the shunt-L circuit 280 includes a shunt inductance (e.g., the inductance 182, Figure 1 ) and a shunt capacitance (e.g., the capacitance 184, Figure 3 ) coupled in series between the drain terminal 251 of the final peaking amplifier FET 250 and the ground reference. The shunt capacitance is configured to provide a low impedance path to ground for very low frequency signal energy (e.g., near DC signal energy), and to provide a high impedance path to ground for signal energy at the operating frequency band of the amplifier 200. In alternative embodiments, the shunt-L circuit can be coupled between the final main amplifier drain terminal 231 and the die ground reference, or the shunt-L circuit can be coupled between both drain terminals 231, 251 and the die ground reference.

[0097] According to embodiments, the shunt inductance of the shunt-L circuit 280 is implemented by a set of one or more bondwires 282 coupled in series with one or more inductors 282', 282" formed in the body. The bondwires 282 representing the first integrated inductance each have a first end connected to a bondpad 266 of the drain terminal 251 (corresponding to or closely electrically coupled to the combined node 264) and a second end connected to a bondpad 283 (hereinafter referred to as the "inter-inductor node"), where both bondpads 266, 283 are integrally formed with and exposed on the top surface of the die 201. In essence, the set of bondwires 282 can be viewed as an inductor, where the first ends of the bondwires 282 correspond to the first end of the inductor and the second ends of the bondwires 282 correspond to the second end of the inductor. In alternative embodiments, more or less than two bondwires can be used to implement the first inductance. In still other alternative embodiments, the set of bondwires 282 can be replaced with one or more discrete inductors, with the first and second ends of the discrete inductors connected to different bondpads exposed on the top surface of the die 201.

[0098] The integrated inductors 282', 282" collectively representing the second inductance are coupled in parallel between the inter-inductor node 283 and a second conductive node 285, which in one embodiment can be the RF cold spot node. More specifically, each of the integrated inductors 282', 282" includes an integrally formed spiral inductor formed from portions of one or more layers of the build structure of the die 201 (e.g., build layers 312, Figure 3 ), with a first end (or end portion) of each spiral inductor coupled to the inter-inductor node 283 and a second end (or end portion) of each spiral inductor coupled to the node 285. In alternative embodiments, the two parallel coupled integrated inductors 282', 282" can be replaced with a single integrated inductor, more than two parallel coupled integrated inductors, or one or more discrete inductors coupled to the top surface of the die 201.

[0099] As used herein, the "band of operation" or "operational band" of an amplifier 200, 300 refers to a range of frequencies defined by a lower and upper -3db cutoff frequency. According to embodiments, the shunt inductance of the shunt-L circuit has an inductance value selected such that the shunt inductance and the drain-source capacitance C dsP resonate at frequencies below the operational band of the amplifier 200. For example, the shunt inductance and C dsP may resonate at frequencies at least 300 megahertz (MHz) below the operational band of the amplifier 200 (e.g., the shunt inductance and C dsPThe resonant frequency can be 300-500 MHz below the operating frequency band, but it can also be higher or lower. As a specific, non-limiting example, when the center operating frequency f0 of amplifier 200 is 2.0 GHz and has a wide operating frequency band of 400 MHz between the lower cutoff frequency of 1.8 Hz and the upper cutoff frequency of 2.2 GHz, the shunt inductor and C dsP The resonant frequency can be 300-500MHz or more below the lower cutoff frequency (e.g., the resonant frequency can be between 1.3GHz and 1.5GHz, but it can also be lower or higher). In other embodiments, the center operating frequency can be less than or greater than 2.0GHz, and the operating bandwidth can be narrower or wider; therefore, the shunt inductance value can be selected to operate at different frequencies below the corresponding operating bandwidth with C. dsP To achieve resonance.

[0100] By reducing the difference between the effective drain-source capacitances of the final-stage main amplifier transistor and the peaking amplifier transistors 230 and 250, the shunt inductance of the shunt-L circuit substantially improves the quality of the combination node structure 264 (e.g., improving Zopt and Zmod at the center operating frequency). More specifically, because amplifier 200 is an asymmetric Doherty amplifier, the drain-source capacitance C of the final-stage peaking amplifier transistor 250... dsP The drain-source capacitance C of the final stage main amplifier transistor 230 is greater than that of the transistor. dsM For example, when the ratio of the main peak size is approximately 1:2, the drain-source capacitance of the final-stage peaking amplifier transistor 250 can be greater than that of the final-stage main amplifier transistor 230 (C...). dsM Approximately 50-80% (e.g., for an asymmetric ratio of 1:2, C) dsM It is approximately 3.7 pF, and C dsP (Approximately 4.9pF). The shunt inductor of the shunt-L circuit is configured to reduce the drain-source capacitance C of the final-stage main amplifier FET 250. dsM The difference between the effective drain-source capacitance of the final stage peaking amplifier FET 230 and the effective drain-source capacitance of the final stage peaking amplifier FET 250, and in some embodiments, the shunt inductor is configured such that the effective drain-source capacitance of the final stage peaking amplifier FET 250 is approximately equal to the drain-source capacitance of the final stage main amplifier FET 230 (or, if another shunt inductor is tightly electrically coupled to the drain of the final stage main amplifier FET, it is equal to the effective capacitance of the final stage main amplifier FET).

[0101] The use of the shunt-L circuit 280 to resonate out at least some of the drain-source capacitance of the final peaking amplifier transistor 250 substantially equalizes the effective drain-source capacitance of the main final amplifier transistor and the peaking final amplifier transistor 230, 250 (or significantly reduces the difference between the two), which improves the quality of the combined node structure 264. In other words, the total shunt inductance provided by the series coupling arrangement of the bond wire 282 and the inductors 282', 282" is selected to resonate out at least some of the drain-source capacitance of the final peaking amplifier transistor 250. For example, in the above-described example of the amplifier 200 having an asymmetric ratio of 1 :2, a drain-source capacitance of approximately 3.7 pF, and a center frequency fo of approximately 2 GHz, the shunt-L circuit 280 having a total shunt inductance of approximately 5 nH can reduce the effective drain-source capacitance of the final peaking amplifier transistor 250 (i.e., the drain-source capacitance that is altered by the shunt inductance) from 4.9 pF to approximately 3.7 pF (i.e., substantially equal to the value of the drain-source capacitance of the main final amplifier transistor 230). dsM dsP In the above-described example of the amplifier 200 having an asymmetric ratio of 1 :2, a drain-source capacitance of approximately 3.7 pF, and a center frequency fo of approximately 2 GHz, the shunt-L circuit 280 having a total shunt inductance of approximately 5 nH can reduce the effective drain-source capacitance of the final peaking amplifier transistor 250 (i.e., the drain-source capacitance that is altered by the shunt inductance) from 4.9 pF to approximately 3.7 pF (i.e., substantially equal to the value of the drain-source capacitance of the main final amplifier transistor 230).

[0102] Factors that affect the selection of the total shunt inductance include, for example, the asymmetric ratio between the main amplifier transistor 230 and the peaking amplifier transistor 250 (and, as a result, the difference in drain-source capacitance between the transistors 230, 250), the power level of the amplifier 200, and the center operating frequency of the amplifier 200. Generally, as the asymmetric ratio, the center operating frequency, and / or the power level increase, the selected total shunt inductance decreases, and, conversely, as the asymmetric ratio, the center operating frequency, and / or the power level decrease, the selected total shunt inductance increases. For example, for a 30 watt amplifier 200 having an asymmetric ratio of 1 :2 and a center frequency fo of approximately 2 GHz, the total shunt inductance provided by the series coupling arrangement of the bond wire 282 and the inductors 282', 282" can be in the range of approximately 1 nH to approximately 10 nH (e.g., approximately 5 nH), but the total shunt inductance can also be lower or higher. If the center operating frequency is increased to 4 GHz, the selected total shunt inductance can be reduced to approximately one-half of the value for the 2 GHz amplifier. Alternatively, if the power level is reduced to 15 watts, with all other conditions being the same, the selected total shunt inductance can be approximately doubled for the 2 GHz amplifier.

[0103] ​According to embodiments, a portion of the total shunt inductance of the shunt-L circuit 280 is provided by the bondwire 282, while another portion of the total shunt inductance is provided by the integrated inductors 282', 282". In some embodiments, the portion of the total shunt inductance provided by the bondwire 282 can be between about 20% to about 80% of the total shunt inductance of the shunt-L circuit 280. For example, for an amplifier 200 having a center operating frequency of about 2 GHz, the first inductance provided by the bondwire 282 can have an inductance value in the range of about 0.5 nH to about 9.5 nH, and the second inductance provided by the parallel coupled integrated inductors 282', 282" can be in the range of about 0.5 nH to about 9.5 nH. Although specific example ranges and values are provided above, in other embodiments, the inductance value of any one of the elements 282, 282', 282" and / or the total inductance value of all of the elements 282, 282', 282" can be less than or greater than the ranges given above.

[0104] In embodiments, the shunt capacitance of the shunt-L circuit 280 is implemented using an integrally formed capacitor 284. In embodiments, the capacitor 284 has a first end (or plate) electrically coupled to the node 285, and a second end (or plate) electrically coupled to a die ground reference (e.g., the conductive layer 328, Figure 3 ) of the die 201. According to embodiments, for example, the capacitor 284 can include one or more MIM capacitors formed within a build-up layer (e.g., the layer 312, Figure 3 ) of the die 201. Alternatively, the capacitor 284 can be integrally formed within a base semiconductor substrate (e.g., the substrate 310, Figure 2 ) with vertical and / or horizontal conductive layers (e.g., polysilicon) spaced apart by a dielectric material. In still other embodiments, the capacitor 284 can be a discrete capacitor coupled to a surface of the die 201. In still other alternative embodiments, the node 285 can be coupled to a bond pad, the capacitor 284 can be an "off-die" capacitor connected to a substrate other than the die 201, and a bondwire can be used to electrically couple the bond pad (or the node 285) to the off-die capacitor 284. Regardless, according to embodiments, the capacitor 284 has a capacitance value in the range of about 500 pF to about 2000 pF, although the capacitor 284 can have a lower or higher capacitance value.

[0105] Although Figure 1The embodiment of the shunt-L circuit 280 shown includes a series-coupled circuit that includes specific components (i.e., bond wire 282, integrated inductors 282', 282" and integrated capacitor 284) in a specific series sequence. However, other embodiments may include different implementations of the shunt-L circuit 280, including different series arrangements of components, components of different physical types, additional components or fewer components. By way of non-limiting examples, different series arrangements may include one or more integrated inductors (e.g., inductors 282' and / or 282) having a first end directly electrically connected to the drain terminal 251 and a second end coupled to bond pads (e.g., bond pad 283) between the inductors, and may additionally include bond wires (e.g., bond wire 282) having a first end coupled to bond pads between the inductors and a second end coupled to node 285. Other embodiments of the shunt-L circuit 280 may include only bond wires or only integrated inductors. Additionally, the physical components of the inductor in the shunt-L circuit 280 may include any combination of inductor components selected from one or more integrally formed inductors, one or more bond wire sets, and / or one or more discrete inductors. Furthermore, any series and / or parallel arrangement may be used to interconnect the inductor components of the shunt-L circuit 280 to obtain the desired total inductance value for the shunt inductor of the shunt-L circuit 280. Similarly, the physical components of the capacitor in the shunt-L circuit may include any combination of capacitor components selected from one or more integrally formed capacitors and / or one or more discrete capacitors. Furthermore, any series and / or parallel arrangement may be used to interconnect the capacitor components of the shunt-L circuit 280 to obtain the desired total capacitance value for the shunt capacitor of the shunt-L circuit 280.

[0106] As previously indicated, embodiments of the Doherty amplifier die 200 may also include one or more video bandwidth (VBW) circuits 286 (e.g., VBW circuit 186) coupled between the combined node structure 264 and the ground reference. Figure 2 ).exist Figure 3 In the illustrated embodiment, VBW circuit 286 is electrically coupled to node 285 in shunt-L circuit 280. According to the embodiment, and as indicated by the circuit diagram of VBW circuit 286 above, VBW circuit 286 may include a series circuit comprising multiple components, more specifically, the series circuit comprising components coupled in series in any order to node 285 and a ground reference (e.g., layer 328). Figure 1resistor (or resistance), an inductor (or inductance), and a capacitor (or capacitance) between the nodes. In other embodiments, one or more VBW circuits 286 can be coupled to one or more different nodes (e.g., to the drain terminal 231, 251, to the gate terminal 225, 245, or elsewhere). Multiple VBW circuits can also be coupled along multiple points of each amplification path.

[0107] In some embodiments, some or all of the components of the VBW circuit 286 can be integrally formed with the die 201, and / or some or all of the components of the VBW circuit 286 can be discrete components connected to a top surface of the die 201. Alternatively, only some of the components of the VBW circuit 286 (e.g., the resistors and / or inductors) can be integrally formed with or connected to the die 201, while other components (e.g., the capacitors) can be implemented off-chip and electrically connected through conductive connections (e.g., bond wires). In other embodiments, substantially all of the VBW circuit can be implemented off-chip (i.e., all or part of the VBW circuit 286 can be provided with circuitry that is not integrated with the die 201). For example, in alternative embodiments, the node 285 can be electrically connected to the lead 287 (e.g., as shown by a bond wire), and all or part of the VBW circuit 286 (i.e., at least one of the resistance, inductance, and / or capacitance of the VBW circuit) can be implemented through external circuitry coupled to the lead 287.

[0108] According to embodiments, the resistor-divider gate bias circuit 270, 270' (e.g., the resistor-divider gate bias circuit 170, 170', Figure 4 ) provides a gate bias voltage for each of the FETs 226, 230, 246, 250. As previously indicated, for proper operation of the Doherty amplifier die 200, the main amplifier 220 is biased to operate in AB class mode, and the peaking amplifier 240 is typically biased to operate in C class mode. Because the main amplifier 220 is biased differently than the peaking amplifier 240, the main amplifier resistor-divider gate bias circuit 270 is different from (and not electrically connected to) the peaking amplifier resistor-divider gate bias circuit 270'.

[0109] In the illustrated embodiment, the main amplifier resistor-divider gate bias circuit 270 includes a bias input 271, resistors 273, 274, and RF isolation circuits 275, 276. Similarly, the peaking amplifier resistor-divider gate bias circuit 270' includes a bias input 271', resistors 273', 274', and RF isolation circuits 275', 276'.

[0110] Terminals 271 and 271' can each include a conductive bond pad exposed at the top surface of the die 201 and configured to attach one or more bond wires. The input terminals 271, 271' enable supply of a main amplifier gate bias voltage through a first bias lead 216 (e.g., lead 416, Figure 4 ) and enable supply of a peaking amplifier gate bias voltage through a second bias lead 217 (e.g., lead 417, Figure 4 ).

[0111] The resistors 273, 274 or 273', 274' are electrically connected in series between the input terminals 271, 271' and a ground reference. The first resistors 273, 273' have a first end electrically coupled to the input terminals 271, 271' and to the gate terminals 225, 245 of the preamplifier FETs 226, 246. A node between the input terminals 271, 271' and the resistors 273, 273' is electrically connected to the gate terminals 225, 245 of the preamplifier FETs 226, 246, and an intermediate node (between resistors 273 / 273', 274 / 274') is electrically connected to the gate terminals 229, 249 of the final amplifier FETs 230, 250. The resistance values of the resistors 273, 273', 274, 274' are selected to divide the main preamplifier gate bias DC voltage or the peaking preamplifier gate bias DC voltage supplied at the input terminals 271, 271' (or at the gate terminals 225, 245) into portions in order to provide the desired DC bias voltage at the gate terminals 229, 249. For example, the resistors 273 / 273', 274 / 274' can have equal or unequal resistance values in the range of about 500 ohms to about 10,000 ohms, but the resistors 273 / 273', 274 / 274' can also have lower or higher resistance values.

[0112] To ensure that large amounts of RF power do not dissipate into the bias circuit 270, 270', the main amplifier and peaking amplifier 220, 240 are decoupled (or isolated) from the bias circuit 270, 270' by RF isolation circuits 275 / 275', 276 / 276'. More specifically, the RF isolation circuits 275, 275' are electrically coupled between the bias input 271, 271' and the gate terminal 225, 245, and the RF isolation circuits 276, 276' are electrically coupled between the resistors 273, 273' and the gate terminal 229, 249. According to embodiments, each RF isolation circuit 275, 275', 276, 276' includes lumped elements equivalent to a quarter wavelength (λ / 4) transmission line, and a reactive component that resonates at the center operating frequency fo of the amplifier 200. Ideally, using this configuration, the bias circuit 270, 270' is analogously an infinite impedance at frequencies near the center operating frequency, thereby isolating the bias circuit 270, 270' at those frequencies.

[0113] In addition to the gate bias circuit 270, 270', the Doherty amplifier die 200 can also include one or more drain bias circuits 277. According to embodiments, the drain bias circuit 277 includes a bias input 278 and RF isolation circuits 279, 279'. Again, the bias input 278 can include a conductive bond pad exposed at the top surface of the die 201, and the conductive bond pad is configured for attachment of one or more bond wires. The input 278 allows the supply of a drain bias voltage through the third bias lead 218 (e.g., lead 418, Figure 2 ) to each of the preamplifier FETs 226, 246.

[0114] In embodiments, the input 278 is electrically connected to the drain terminal 227, 247 of each of the preamplifier FETs 226, 246 to supply the same DC drain bias voltage to each FET 226, 246. Again, to ensure that large amounts of RF power do not dissipate into the bias circuit 277, the main amplifier 220 and peaking amplifier 240 are decoupled (or isolated) from the bias circuit 277 by RF isolation circuits 279, 279'. More specifically, each RF isolation circuit 279, 279' is electrically coupled between the input 278 and the drain terminal 227, 247 of the preamplifier FET 226, 246. Each RF isolation circuit 279, 279' can include lumped elements equivalent to a quarter wavelength (λ / 4) transmission line, and a reactive component that resonates at the center operating frequency fo. It should be noted that in embodiments, the drain bias voltage can be supplied through one or more device output leads (e.g., output leads 294, 494, Figure 4 、 4) and connections (e.g., output signal bond wires 290) between the device output leads and the combining structure 264 supply the drain bias voltage to the final amplifier FETs 230, 250.

[0115] The Doherty power amplifier die 200, and more specifically the die 201, can be packaged and / or incorporated into a larger electrical system in a variety of ways. For example, the Doherty amplifier die 201 can be packaged within an overmolded or air cavity power device package (e.g., package 404, Figure 4 ). Alternatively, the Doherty amplifier die 201 can be packaged in a surface mount package, such as a leadless package (e.g., a dual flat no-lead (DFN) or quad flat no-lead (QFN) package). In still other embodiments, the Doherty die 201 can be mounted directly to a module or PCB substrate surface.

[0116] As an example, Figure 2 is a top view of a Doherty amplifier device 400 according to an example embodiment, including a Doherty amplifier die 401 (e.g., die 201, Figure 2 ) packaged within a high power discrete device package 404. The die 401 includes the following integrated circuitry: a main amplifier (e.g., main amplifier 220, Figure 2 ), a peaking amplifier (e.g., peaking amplifier 240, Figure 2 ), a phase delay circuit (e.g., phase delay circuit 260, Figure 2 ), a combining node structure (e.g., combining node structure 264, Figure 2 ), and a shunt-L circuit (e.g., shunt-L circuit 280, Figure 2 ). In some embodiments, the die 401 can also include an integrated signal divider (e.g., signal divider 204, Figure 2 ) and / or a VBW circuit (e.g., VBW circuit 286, Figure 2 ), while in other embodiments the signal divider and / or VBW circuit can be implemented off-die and / or outside of the device 400.

[0117] The package 404 includes a plurality of conductive input signal and bias leads 414, 416, 417, 418 (e.g., leads 214, 216, 217, 218, Figure 2 ) and at least one output lead 494 (e.g., lead 294, Figure 2 ). In some embodiments, the package 404 can also include one or more additional bias or other leads. For example, the package 404 can include a VBW lead 487 (e.g., lead 287, Figure 2), which facilitates electrical connection of the die 401 to one or more components of the VBW circuit mounted to a PCB or other substrate (not shown), with the package 404 mounted on the PCB or other substrate. Input signal and bias leads 414, 416, 417, 418 are positioned on an input side of the package 404, and at least one output lead 494 and a VBW lead 487 (if included) are positioned on an output side of the package 404. In embodiments, the input side (e.g., input side 210, Figure 2 ) of the Doherty amplifier die 401 is proximate to and parallel to the input side of the device package 404.

[0118] According to embodiments, the package 404 includes a package substrate, such as a conductive flange 430, to which the Doherty amplifier die 401 is physically and electrically connected (e.g., using conductive epoxy, solder, brazing, sintering, or other conductive connection methods). Finally, the package 404 includes non-conductive structural features or materials, such as a molding compound and / or other insulating materials, that hold the leads 414, 416, 417, 418, 487, 494 and the flange 430 in fixed orientations relative to one another.

[0119] Conductive connections, such as conductive bond wires, electrically connect the input signal and bias voltage bond pads (or terminals) on the die 401 to the conductive leads 414, 416, 417, 418 on the input side of the package 404. For example, one or more first bond wires 419 can electrically connect the input RF signal lead 414 to a first bond pad corresponding to an input terminal (e.g., input terminal 202, Figure 2 ) of the Doherty amplifier die 401, and the input RF signal lead 414 can be used to deliver an input RF signal to the Doherty amplifier die 401. In alternative embodiments in which the signal distributor (e.g., distributor 204, Figure 2 ) is not implemented in the die 401, a separate lead can be used to provide the main RF signal and the peaking RF signal to two bond pads on the die 401, with the first bond pad corresponding to an input terminal of the main amplifier and the second bond pad corresponding to an input terminal of the peaking amplifier. As previously discussed in connection with Figure 2 the bias circuit (e.g., bias circuit 270, 270', 277, Figure 2 ) on the Doherty amplifier die 401 can be electrically connected to the bias leads 416-418 (e.g., bias leads 216-218, Figure 2 ) by additional bond wires (not numbered). According to embodiments, the output of the Doherty amplifier die 401 (and more specifically, the combined node structure 264, Figure 4 ) is electrically connected to the at least one output lead 494 by a plurality of bond wires (e.g., bond wires 290, Figure 5) electrically connected to the output lead 494.

[0120] In some embodiments, the leads 414, 416-518, 487, 494, and the flange 430 can form part of a leadframe. To complete an overmolded package during device fabrication, after the attachment of the die 401 and the wirebond interconnections between the leads and the die 401 are made, the die 401, the inner ends of the leads 414, 416-418, 487, 494, the wirebonds, and the top and side surfaces of the flange 430 can be encapsulated with non-conductive (e.g., plastic) molding compounds 440, 442 (only the top molding compound 440 is shown in Figure 3 part to avoid obscuring the internal components of the device 400). The molding compounds 440, 442 define the periphery of the leads 414, 416-418, 487, 494 that protrude from the device 400, and also define the top surface of the device 400. The bottom surface of the device 400 is defined in part by the molding compound 440, and in part by the bottom surface of the flange 430. Thus, when properly coupled to a system substrate (e.g., a PCB 501, Figure 4 ), the flange 430 can be used to transfer a ground reference to the die 401 (e.g., through the bottom conductive layer 328, Figure 4 ), and can also act as a heat sink for the device 400.

[0121] In similar but different embodiments, the leads 414, 416-418, 487, 494 shown in the configuration can be replaced with connection pads of a leadless package. The flange 430 and the connection pads can again form a leadframe to which the die 401 and wirebonds are attached, and the assembly can again be encapsulated by a non-conductive molding compound to form a leadless, surface mount device (e.g., a DFN or QFN device). Figure 5

[0122] In other embodiments, the package 404 can be a cavity package. In such embodiments, the flange 430 can have a larger periphery that is equal to or approximately equal to the periphery of the device 400. A non-conductive insulator (e.g., ceramic, plastic, or another material) having a frame shape can be attached to the top surface of the flange, the leads 414, 416-418, 487, 494 can be placed over the non-conductive insulator, the wirebonds are attached, and a lid (not shown) is placed over the frame opening to encapsulate the internal components of the device 400 in a cavity.

[0123] Although Figure 4 ​A Doherty amplifier device 400 is shown, comprising a single Doherty amplifier die 401 and corresponding leads. However, other embodiments of the Doherty amplifier device may include multiple Doherty amplifier dies placed side-by-side (e.g., multiple instances of dies 201, 401), with corresponding lead groups associated with each die. Using such a device, for example, a 3-dB coupler or other means (e.g., on a PCB coupling the Doherty amplifier device) can be used to combine output RF signals from multiple Doherty amplifier dies.

[0124] Ultimately, the Doherty amplifier unit 400 is integrated into a larger power system (e.g., a power transmitter line in a cellular base station). For example, as... Figure 2 As shown, the Doherty amplifier device 520 (e.g., device 400) can be coupled to a system substrate such as a single-layer or multi-layer PCB 501. Figure 2 The Doherty amplifier device 520 is incorporated into the amplifier system 500. In an embodiment, the Doherty amplifier device 520 includes a plurality of input-side leads 510 and output leads 594 (e.g., leads 294, 494, ...). Figure 4 , 4 These are configured as conductive components on PCB 501 and dies (e.g., die 201) encapsulated within device 520. Figure 4 It transmits bias voltage and RF signals between them.

[0125] In embodiments, PCB 501 may be a single-layer or multi-layer PCB, and multiple components are coupled to PCB 501. According to an embodiment, a conductive coin 502 (or other feature) is embedded within PCB 501, and the top and bottom surfaces of the conductive coin 502 are exposed to the top and bottom surfaces of PCB 501, respectively. Doherty amplifier device 520 (e.g., device 400, Figure 1 This is connected to the conductive coin 502. More specifically, the bottom surface of the Doherty amplifier device 520 (e.g., the bottom of the flange 430) is connected to the conductive coin 502. Figure 2 The conductive coin 502 can be physically and electrically connected to the top surface of the conductive coin 502. The conductive coin 502 can also be electrically connected to the system ground, and the bottom surface of the coin 502 can be physically connected to the system heat sink. Therefore, the conductive coin 502 can serve as a heat sink for the ground reference and amplifier system 500.

[0126] In a typical configuration, the amplifier system 500 includes an input RF connector 503 and an output RF connector 504 coupled to the PCB 501, which are respectively configured to receive an input RF signal from an RF signal source and to produce an amplified output RF signal for transmission to a load (e.g., the load 196, Figure 2 which can be a cellular antenna coupled to the connector 504.

[0127] The PCB 501 includes a plurality of conductive paths 505, 506, 507, 540 electrically coupled between the input and output RF connectors 503, 504 and the Doherty amplifier device 520. Additional conductive paths 516, 517, 518, 542 can be used to convey DC gate and drain bias voltages from bias voltage connectors 550, 551, 552 to the device 520. For example, the conductive paths and features 505-507, 516-518, 540, 542 can be formed by patterned portions of a top conductive layer, a bottom conductive layer, and / or an internal conductive layer (if included) of the PCB 501.

[0128] In the illustrated embodiment, the signal divider 530 (e.g., the signal divider 204, Figure 2 ) is not integrated within the device 520, but is instead implemented as a separate component coupled to the PCB 501. More specifically, a first conductive path 505 electrically connects the input RF connector 503 to an input of the signal divider 530, which is configured to split the input RF signal conveyed through the path 505 into a first RF signal and a second RF signal (e.g., corresponding to a main input RF signal and a peaking input RF signal). The first and second RF signals are produced at two outputs of the signal divider 530, and the signals are respectively conveyed through second and third conductive paths 506, 507 to first and second RF input leads 514, 515 of the Doherty amplifier device 520. According to embodiments, the signal divider 530 produces the first and second RF signals such that they have a phase difference of about 90 degrees. In other embodiments, the phase difference can be imposed by circuitry other than the signal divider 530.

[0129] As indicated in the preceding paragraph, the Doherty amplifier device 520 in the illustrated embodiment corresponds to a device that includes a Doherty amplifier die that does not include an integrated signal divider (e.g., the divider 204, Figure 2Alternatively, in the illustrated embodiment, the signal distributor 530 is used to split the input RF signal into a first RF signal and a second RF signal (e.g., a main RF signal and a peaked RF signal). In an alternative embodiment, the Doherty amplifier device 520 may include a Doherty amplifier die (e.g., Doherty die 201, Figure 2 Doherty amplifier chips do indeed include integrated signal distributors (e.g., distributor 204). Figure 2 In this case, the signal distributor 530 can be excluded from system 500, and the input RF connector 503 can be directly connected to a single input lead (e.g., leads 214, 514) that passes through the conductive path.

[0130] As discussed in detail above, the Doherty amplifier die (e.g., die 201, 401) within the Doherty amplifier assembly 520 Figure 2 , 4 Amplify the input RF signal to output lead 594 (e.g., leads 294, 494). Figure 2 , 4 An amplified output RF signal is generated at the output RF connector 504. An additional conductive path 540 on PCB 501 electrically connects the output RF signal lead 594 of the Doherty amplifier device 520 to the output RF connector 504. Therefore, during operation of system 500, the amplified RF signal generated by the Doherty amplifier device 520 is transmitted to the output RF connector 504 via conductive path 540.

[0131] As mentioned earlier, Doherty amplifier dies (e.g., dies 201, 401, ...) Figure 5 , 4 It may or may not include integrated VBW circuitry (e.g., VBW circuitry 286). Figure 2 ).exist Figure 6 In the illustrated embodiment, the Doherty amplifier die within the Doherty amplifier device 520 does not include integrated VBW circuitry. Instead, the Doherty amplifier device 520 includes VBW leads 587 (e.g., VBW leads 287, 487, ...). Figure 2 , 4 ) and VBW circuit 586 implemented on PCB 501. For example, VBW circuit 586 may include a resistor, inductor and capacitor coupled in series between VBW lead 587 and ground reference.

[0132] Figure 4This is a flowchart of a method for manufacturing a multipath amplifier according to an example embodiment, and more specifically, for manufacturing a Doherty power amplifier die (e.g., Doherty amplifier die 201, 401). Figure 5 , 4 Doherty amplifier devices in package (e.g., device 400, Figure 2 ) and Doherty amplifier systems (e.g., System 500, Figure 2 A flowchart of the method is shown. In block 602, the method can be implemented by forming amplifier dies (e.g., dies 201, 401, ...). Figure 2 , 4 The method begins by integrally forming one or more main amplifier transistors (e.g., main amplifier 220). Figure 2 ) and a semiconductor die, and integrally formed one or more peaking amplifier transistors (e.g., peaking amplifier 240, Figure 2 (and semiconductor die.) The output terminals of the main amplifier transistor and the peaking amplifier transistor can be configured as described above. Figure 2 The configuration described. The output of the peaking amplifier corresponds to an integrated combination node structure or is electrically coupled to an integrated combination node structure (e.g., combination node structure 264). Figure 2 Furthermore, the amplifier die may include an integrally formed or integrated power divider (e.g., divider 204). Figure 2 ), matching networks (e.g., IMN 222, 242; ISMN 228, 248, Figure 2 Bias circuits (e.g., bias circuits 270, 270', 277, Figure 2 ), integrated shunt-L circuit (e.g., shunt-L circuit 280, Figure 2 ), VBW circuit (e.g., VBW circuit 286, Figure 2 (and / or other integrated components.) In alternative embodiments, some of the circuitry and components described in the previous sentence may be implemented on a different substrate than the amplifier die.

[0133] In block 604, an integrated phase delay circuit (e.g., phase delay circuit 260) is formed between the outputs of the main final-stage amplifier transistor and the peaking final-stage amplifier transistor. Figure 2 To complete the Doherty amplifier die (e.g., Doherty amplifier die 201, 401, ) Figure 2 , 4 The integrated phase delay circuit includes a bonding wire (e.g., bonding wire 262) between the outputs of the main final stage amplifier transistor and the peaking final stage amplifier transistor. Figure 4). The bond wires extend in a direction that is offset at an angle from the direction of the signal path through the peaking final amplifier transistor (e.g., offset 30 degrees to 150 degrees, including perpendicular to the direction of the signal path). In addition, other discrete components can be coupled to the top surface of the die.

[0134] Then, in block 606, the Doherty amplifier die (e.g., Doherty amplifier die 201, 401, Figure 4 、 4 ) can be packaged. As previously mentioned, the Doherty amplifier die can be packaged in an overmolded or air cavity package. Alternatively, the Doherty amplifier die can be attached as a bare die to a system substrate (e.g., a module or PCB substrate). When packaged in an overmolded package (e.g., package 404, Figure 5 ), the Doherty amplifier die can be connected to the conductive flanges of the lead frame, the bond wires can be coupled between the input, output, and bias leads of the lead frame and the appropriate bond pads of the Doherty amplifier die, and the flanges, leads, and Doherty amplifier die can be packaged in a molding compound. When packaged in an air cavity package, an insulator frame can be attached to the top surface of the conductive flanges, the Doherty amplifier die can be connected to the top surface of the flanges in the frame opening, the input, output, and bias leads can be connected to the top surface of the insulator frame, the bond wires can be coupled between the input, output, and bias leads and the appropriate bond pads of the Doherty amplifier die, and a lid can be applied over the flanges, insulator frame, leads, bond wires, and Doherty amplifier die to encase the Doherty amplifier die in an air cavity.

[0135] In block 608, the amplifier system (e.g., system 500, Figure 5 ) can be completed by attaching the Doherty amplifier device (e.g., device 400, Figure 5 ) (or, in some embodiments, the bare die) to a system substrate, such as a PCB (e.g., PCB 501, Figure 5 ). More specifically, the bottom surface of the Doherty amplifier device can be connected to a conductive coin (e.g., coin 502, Figure 5 ) to provide a ground reference and heat sink to the device, and the input, output, and bias leads of the device can be connected to corresponding conductive paths (e.g., paths 505-507, 516-518, 540, Figure 5 ) of the system substrate.

[0136] According to embodiments, in block 610, additional components (e.g., a splitter 530 and / or a VBW circuit 586, ​) to a system substrate (e.g., PCB 501, ​ ) to complete the amplifier system. The method can then end.

[0137] A multi-path amplifier (e.g., a Doherty amplifier) includes first and second transistors (e.g., a main transistor and a peaking transistor) having first and second outputs, respectively, all of which are integrally formed with a semiconductor die. A signal path through the second transistor extends in a second direction from a control terminal of the second transistor to the second output, where the second output corresponds to a combining node or is in close electrical coupling to the combining node. The amplifier also includes an integrated phase delay circuit configured to impart an overall phase delay (e.g., 90 degrees) to a signal carried between the first and second outputs. The integrated phase delay circuit includes a delay circuit bond wire coupled between the first and second outputs, and the delay circuit bond wire extends in a third direction that is angularly offset (e.g., perpendicular) to the second direction.

[0138] The connecting lines shown in the various figures contained herein are intended to represent exemplary functional relationships and / or physical couplings between the various elements. It should be noted that many alternatives or additional functional relationships or physical connections can be present in a subject's embodiments, as will be apparent to those skilled in the art. Additionally, certain terminology can also be used herein for the purpose of reference only, and, thus, is not intended to be limiting, and the terms "first" and "second" and other such numerical terms referring to structures do not imply a sequence or order unless specifically so stated in the context of the description.

[0139] As used herein, a "node" means any internal or external reference point, connection point, junction point, signal line, conductive element, and the like, at which a given signal, logic level, voltage, data pattern, current, or quantity exists. Moreover, two or more nodes can be implemented by one physical element (and, although received or output at a common node, two or more signals can still be multiplexed, modulated, or otherwise distinguished).

[0140] The above description refers to elements or nodes or features being "connected" or "coupled" together. As used herein, unless otherwise clearly indicated, "connected" means that one element is directly connected to another element (or directly communicates with another element) without necessarily being mechanically connected. Also, unless otherwise clearly indicated, "coupled" means that one element is either directly or indirectly connected to (or directly or indirectly in electrical or other communication with) another element, without necessarily being mechanically connected. Thus, although the schematic diagrams shown in the figures depict one exemplary arrangement of elements, additional intervening elements, devices, features, or components can be present in embodiments of the depicted subject matter.

[0141] As used herein, the words “exemplary” and “example” mean “serving as an example, instance, or illustration.” Any implementation described herein as exemplary or as an example is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the foregoing description of implementations includes various specific details out of the interest of providing a thorough understanding of the various implementations. However, various other alternatives, modifications, and equivalents can be used. Accordingly, the foregoing description of implementations is not intended to be exhaustive or to limit the implementations to the precise forms disclosed. Instead, the preceding description of implementations is intended to be illustrative.

[0142] While at least one exemplary embodiment has been presented in the foregoing detailed description of implementations, it should be appreciated that a vast number of modifications can be made to the exemplary embodiments without departing from the scope disclosed herein. Additionally, it should be appreciated that one or more exemplary embodiments described herein are not intended to be limited to the precise configurations described herein. Rather, the preceding detailed description of implementations is meant to be illustrative only and should not be taken as limiting the scope of the disclosure. Accordingly, the exemplary embodiments described herein are not meant to be limiting but are examples of implementations.

Claims

1. A multi-path amplifier characterized by, comprising: a semiconductor die; a first transistor integral with the semiconductor die and having a first output, wherein a first signal path through the first transistor extends in a first direction from a control terminal of the first transistor to the first output; a second transistor integral with the semiconductor die and having a second output and a combination node, wherein the second output corresponds to or is directly electrically coupled to the combination node, and wherein a second signal path through the second transistor extends in a second direction from a control terminal of the second transistor to the second output; and an integrated phase delay circuit configured to impart an overall phase delay to a signal carried between the first output and the second output, wherein the integrated phase delay circuit includes a delay circuit bond wire coupled between the first output and the second output, and wherein the delay circuit bond wire extends in a third direction angularly offset from the second direction, wherein the second output has an elongated second bond pad having a second length extending parallel to the second direction of the second signal path, and the delay circuit bond wire is connected in parallel along the second length of the elongated second bond pad, wherein the second output further includes: an elongated third bond pad electrically coupled to the elongated second bond pad, wherein the elongated third bond pad has a third length extending perpendicular to the second direction, and the elongated third bond pad is directly electrically coupled to a drain manifold of the second transistor, wherein the multi-path amplifier further includes a set of output signal bond wires connected to the elongated third bond pad and extending in the second direction.

2. The multi-path amplifier of claim 1, wherein, The overall phase delay is 90 degrees, and the delay circuit bond wire is configured to impart 30 degrees to 80 degrees of the overall phase delay.

3. The multi-path amplifier of claim 1, wherein: the first output has an elongated first bond pad having a first length extending parallel to the first direction of the first signal path, and the delay circuit bond wire is connected in parallel along the first length of the elongated first bond pad.

4. The multi-path amplifier of claim 3, wherein, The first output further includes: an elongated conductive structure electrically coupled to the elongated first bond pad, wherein the elongated conductive structure has a second length extending perpendicular to the first direction, and the elongated conductive structure is directly electrically coupled to a drain manifold of the first transistor.

5. The multi-path amplifier of claim 1, wherein, The elongated first bond pad and the elongated second bond pad are arranged in parallel.

6. The multi-path amplifier of claim 1, wherein, Further comprising: a shunt inductive circuit electrically coupled between the combination node and a ground reference node, wherein the shunt inductive circuit includes a shunt inductance integrated with the semiconductor die.

7. A method of fabricating a multi-path amplifier, characterized by, The method includes: forming a first transistor integral with the semiconductor die, wherein the first transistor has a first output, and wherein a first signal path through the first transistor extends in a first direction from a control terminal of the first transistor to the first output; forming a second transistor integral with the semiconductor die, wherein the second transistor has a second output and a combination node, wherein the second output corresponds to or is directly electrically coupled to the combination node, and wherein a second signal path through the second transistor extends in a second direction from a control terminal of the second transistor to the second output; and forming an integrated phase delay circuit by coupling a delay circuit bond wire between the first output and the second output, wherein the delay circuit bond wire extends in a third direction angularly offset from the second direction, and wherein the integrated phase delay circuit is configured to impart an overall phase delay to a signal carried between the first output and the second output, wherein the second output has an elongated second bond pad having a second length extending parallel to the second direction of the second signal path, and the delay circuit bond wire is connected in parallel along the second length of the elongated second bond pad, wherein the second output further comprises: an elongated third bond pad electrically coupled to the elongated second bond pad, wherein the elongated third bond pad has a third length extending perpendicular to the second direction, and the elongated third bond pad is directly electrically coupled to a drain manifold of the second transistor, wherein the multi-path amplifier further comprises an output signal bond wire set connected to the elongated third bond pad and extending in the second direction.

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