Turbo coding method and device, electronic device and storage medium

Abstract

The present invention provides a Turbo encoding method and device, electronic device and storage medium, wherein the method comprises: encoding the serial output of the member encoder in the Turbo encoder in one dimension of the bit stream, extracting the time information, and based on the time information, converting the serial output of the member encoder into a two-dimensional generator matrix of the member encoder; based on the characteristics of the generator polynomial, converting the two-dimensional generator matrix into a plurality of partition matrices; based on each of the partition matrices and their corresponding preset lookup tables, parallel encoding the input information and then outputting it; the preset lookup table is a table listing all matching input vectors and output vectors corresponding to the partition matrices. The present invention obtains the encoding results of multiple consecutive input information at the same time through limited and few steps, greatly reducing power consumption, shortening encoding time, and using storage resources in exchange for increased encoding speed.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a Turbo coding method and system. Background Art

[0002] Compared with wired communication, wireless communication has limited bandwidth resources for data transmission and a relatively harsh transmission channel environment. In order to improve data transmission efficiency, it is usually necessary to encode the data stream in the channel during data transmission to reduce the bit error rate and thus enhance channel reliability. Turbo codes have superior performance in high-noise environments with low channel signal-to-noise ratios, and also have strong anti-fading and anti-interference capabilities. Due to time-varying fading channels and interference and noise, the reliability of wireless signals during wireless transmission is reduced. Turbo codes use convolutional codes as their member codes and introduce internal interleavers to reduce correlation. The performance of Turbo codes can theoretically approach the Shannon limit.

[0003] During the turbo coding process, the input information bits are grouped and encoded. The encoded output bits of each code group are not only related to the information bits of the group, but also to the information bits of other groups at the previous moment. Therefore, the traditional processing method is to input data in the form of a bit stream, bit by bit, and output it according to the processing rules set by the convolution encoder.

[0004] There are many ways to process turbo coding. The traditional implementation structure of turbo coding uses single-bit coding, and one input bite is processed in one clock cycle. In order to improve the throughput of communication systems, parallel turbo coding is usually used to exchange logic resources for speed. Parallel system bit streams are encoded in parallel, and each channel uses its own logic resources in parallel, which increases resources exponentially.

[0005] For example, patent CN200910151557.4 provides a device for parallel encoding of data, including: a first parallel encoder, used for parallel encoding of M-bit input data input from a first path; an inner interleaver, used for inner interleaving of M-bit input data input from a second path parallel to the first path; and a second parallel encoder, used for receiving the data processed by inner interleaving, and performing parallel encoding on the data processed by inner interleaving, wherein M=2m, m is an integer greater than 0 and less than 13, and the total number of bits of the input data can be divided by M. The above method derives the encoding formula of M consecutive moments through time expansion, and calculates the encoding formula of these M moments in parallel. The speed improvement depends on the number of parallel paths of the implementation structure, which is only M times higher than the traditional method, and the maximum value of M is 26, but the logic resources required by this method increase exponentially, and the power consumption also increases accordingly, which is not conducive to implementation. Summary of the invention

[0006] The present invention provides a Turbo coding method and device, electronic equipment and storage medium, which are used to solve the technical defects in the prior art.

[0007] The present invention provides a Turbo coding method, comprising:

[0008] Encode the serial output of the member encoder in the Turbo encoder in one dimension of the bit stream, extract the time information, and convert the serial output of the member encoder into a two-dimensional generator matrix of the member encoder based on the time information;

[0009] Based on the characteristics of the generator polynomial, the two-dimensional generator matrix is ​​converted into a plurality of partition matrices;

[0010] Based on each of the divided matrices and the corresponding preset lookup table, the input information is encoded in parallel and then output;

[0011] The preset lookup table is a table that lists all matching input vectors and output vectors corresponding to the matrix.

[0012] Preferably, the Turbo coding method includes: using a matrix to represent the coding formula of the serial output of the member encoder at n consecutive moments, wherein n is a natural number, and the serial output of the member encoder includes the coding output of the feedback part and the coding output of the forward part.

[0013] Preferably, in the Turbo coding method, the coding output of the feedback part is equal to the matrix A (n+h)x(n+h) The inverse of is multiplied by the input code, where h is the order of the generator matrix.

[0014] Preferably, in the Turbo coding method, the coding output of the forward part is equal to the forward part generation matrix multiplied by the coding output of the feedback part to obtain a matrix B ( n+h)x(n+h) , the two-dimensional generator matrix G of the member encoder (n+h)x(n+h) From the matrix B (n+h)x(n+h) Multiply by matrix A (n+h)x(n+h) The inverse of is obtained.

[0015] Preferably, in the Turbo coding method, the step of converting the two-dimensional generator matrix into a plurality of matrices based on the characteristics of the generator polynomial comprises: using the first h columns of the two-dimensional generator matrix as the initial value calculation part H0 (n+h)×h Divide into two matrices, upper and lower, and add zero elements in the rh column on the right to get Divide the last n columns equally into n / r matrices Hi (n+h)×r , each is divided into a matrix Hi (n+h)×r Divide into two matrices: upper and lower get The r-column matrix is ​​divided into two parts, where i is less than or equal to n / r.

[0016] Preferably, the Turbo coding method, wherein the step of encoding the input information in parallel based on each of the matrixes and the corresponding preset lookup table before outputting the information further comprises: Add later Row 0 element, we get All matrices are unified as Matrix with rows and columns, encoding output d k ~d k+n-1 By calculating G (n+h)x(n+h) Multiply the input information D2, D1, D0, 0, c k ~c k+n-1 , which is converted to indivual The generator matrix with rows and columns is multiplied by D2, D1, D0, 0 or c k+(i-1)×r ~c k+i×r get.

[0017] Preferably, in the Turbo coding method, matrix operations are calculated by looking up tables, and the lookup tables corresponding to each matrix are Table1, Table2 to Table3. The lookup table is configured to indivual SRAM, each SRAM result corresponds to the corresponding position of the matrix element and performs XOR to complete the encoding.

[0018] The present invention provides a Turbo coding device, characterized by comprising:

[0019] A two-dimensional generator matrix determination module, used to encode the serial output of the member encoder in the Turbo encoder in one dimension of the bit stream, extract the time information, and convert the serial output of the member encoder into a two-dimensional generator matrix of the member encoder based on the time information;

[0020] A matrix determination module is used to convert the two-dimensional generator matrix into a plurality of matrixes based on the characteristics of the generator polynomial;

[0021] A parallel encoding module, used for encoding the input information in parallel and then outputting it based on each of the divided matrices and the corresponding preset lookup table;

[0022] The preset lookup table is a table that lists all matching input vectors and output vectors corresponding to the matrix.

[0023] The present invention also provides an electronic device, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of any of the above-mentioned Turbo encoding methods are implemented.

[0024] The present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the Turbo encoding methods described above are implemented.

[0025] The present invention converts turbo member encoders into two-dimensional matrix operations after extracting time information in a serial manner according to the one-dimensional calculation of the bit stream; at the same time, according to the characteristics of the generator polynomial, the large matrix is ​​converted into a few small matrices; finally, turbo encoding is performed quickly and in parallel in the form of a lookup table; at the same time, considering that the logic and storage resources should be minimized in hardware implementation, a plurality of small-scale lookup tables are used to realize large-scale parallel encoding according to the characteristics of the generator matrix. The encoding results of multiple continuous input information are obtained at the same time through limited and few steps, which greatly reduces power consumption, shortens encoding time, and exchanges storage resources for increased encoding speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 This is one of the flow charts of the Turbo coding method provided by the present invention;

[0028] Figure 2 is a schematic diagram of the structure of a Turbo encoding device provided by the present invention;

[0029] Figure 3 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] The embodiment of the present invention discloses a Turbo coding method, see Figure 1 ,include:

[0032] S1: Encode the serial output of the member encoder in the Turbo encoder in one dimension of the bit stream, extract the time information, and based on the time information, convert the serial output of the member encoder into a two-dimensional generator matrix of the member encoder;

[0033] S2: based on the characteristics of the generator polynomial, convert the two-dimensional generator matrix into a plurality of partition matrices;

[0034] S3: Based on each of the divided matrices and the corresponding preset lookup table, the input information is encoded in parallel and then output;

[0035] The preset lookup table is a table that lists all matching input vectors and output vectors corresponding to the matrix.

[0036] Among them, a two-dimensional matrix is ​​known. This two-dimensional matrix is ​​multiplied by a one-dimensional vector (input vector). The number of elements of the one-dimensional vector is the number of columns of the two-dimensional matrix. The result is a one-dimensional vector (output vector) with the number of elements equal to the number of rows of the two-dimensional matrix. Each input vector corresponds to a result output vector. All matching input vectors and output vectors are listed in a table. This table is the preset lookup table. The input vector is used as the RAM address and the output vector is used as the storage content of the RAM. The preset lookup table can be stored in the RAM.

[0037] The present invention converts turbo member encoders into two-dimensional matrix operations after extracting time information in a serial manner according to the one-dimensional calculation of the bit stream; at the same time, according to the characteristics of the generator polynomial, the large matrix is ​​converted into a few small matrices; finally, turbo encoding is performed quickly and in parallel in the form of a lookup table; at the same time, considering that the logic and storage resources should be minimized in hardware implementation, according to the characteristics of the generator matrix, multiple small-scale lookup tables are used to achieve large-scale parallel encoding. The encoding results of multiple continuous input information are obtained at the same time through limited and few steps. The encoding time is greatly shortened, and the storage resources are exchanged for the increase in encoding speed.

[0038] Furthermore, the method includes: using a matrix to represent the encoding formula of the serial output of the member encoder at n consecutive moments, wherein n is a natural number, and the serial output of the member encoder includes the encoding output of the feedback part and the encoding output of the forward part.

[0039] The coded output of the feedback part is equal to the matrix A (n+h)x(n+h) The inverse of the input code is multiplied by h, where h is the order of the generator matrix. The encoding result of the feedback part is only related to the current input and the encoding output of the previous h (h is the order of the generator matrix) moments. For the encoding formula at each moment, the input c k+iIt is equal to the h+1 coded outputs from time k+i forward multiplied by the inverse of the generating polynomial of the feedback part (g0m k+i +g1m k+i-1 +…+g h m k+i-h ), the formula of these n moments is expressed in a matrix. Here, the inverse of the polynomial is known, and the inverse matrix of the polynomial is obtained. For the convenience of calculation, the initial value part of the matrix is ​​expanded by h rows, and the matrix A is obtained. (n+h)x(n+h) , so the feedback part encoding output is equal to the matrix A (n+h)x(n+h) The inverse of is multiplied by the input code.

[0040] The coded output of the forward part is equal to the forward part generation matrix multiplied by the coded output of the feedback part, and the matrix B is obtained. (n+h)x(n+h) , the two-dimensional generator matrix G of the member encoder (n+h)x(n+h) From the matrix B (n+h)x(n+h) Multiply by matrix A (n+h)x(n+h) The encoding result of the forward part is d k+i With the current input m k+i And the input m at the previous h (h is the order of the generating matrix) time k+i-1 ,···,m k+i-h Related, expressed as a matrix, the encoding result d k Equal to the forward part generating matrix B nx(n+h) Multiply by the feedback section's coded output m k To facilitate calculation, the initial value part of the matrix is ​​expanded by h rows, and the matrix B is obtained. (n+h)x(n+h) .

[0041] From the matrix B (n+h)x(n+h) Multiply by matrix A (n+h)x(n+h) The inverse of the member encoder is obtained by (n+h)x(n+h) The first h columns of the G matrix are the initial value calculation part H0 (n+h)×h Divide into two matrices, upper and lower, and add zero elements in the rh column on the right to get Divide the last n columns equally into n / r matrices Hi (n+h)×r , each matrix is ​​divided into two parts: upper and lower i is less than or equal to n / r; since both A and B matrices are sparse matrices, after calculation, it is found that

[0042] According to the above The r columns are divided into matrices, Add later Row 0 element, we get All matrices are unified as Matrix with rows and columns, encoding output d k ~d k+n-1 By calculating G (n+h)x(n+h)Multiply input data D2, D1, D0, 0, c k ~c k+n-1 , which is converted to indivual The rows and columns are divided into matrices and multiplied by D2, D1, D0, 0 or c k+(i-1)×r ~c k+i×r get.

[0043] Based on the characteristics of the generator polynomial, the two-dimensional generator matrix is ​​converted into a plurality of matrices, including: the first h columns of the two-dimensional generator matrix are used as the initial value calculation part H0 (n+h)×h Divide into two matrices, upper and lower, and add zero elements in the rh column on the right to get Divide the last n columns equally into n / r matrices Hi (n+h)×r , each is divided into a matrix Hi (n+h)×r Divide into two matrices: upper and lower get The r-column matrix is ​​divided into two parts, where i is less than or equal to n / r.

[0044] The method further comprises: encoding the input information in parallel based on each of the matrixes and the corresponding preset lookup table before outputting the information; Add later Row 0 element, we get All matrices are unified as Matrix with rows and columns, encoding output d k ~d k+n-1 By calculating G (n+h)x(n+h) Multiply the input information D2, D1, D0, 0, c k ~c k+n-1 , which is converted to indivual The two-dimensional generator matrix with r rows and columns is multiplied by D2, D1, D0, 0 or c k+(i-1)×r ~c k+i×r get.

[0045] Matrix operations are calculated by lookup tables. The lookup tables corresponding to each matrix are Table1, Table2 to The lookup table is configured to indivual Each SRAM result corresponds to the corresponding position of the matrix element and performs XOR to complete the encoding. When applied, the input r bit state information is used as the SRAM address query to obtain the design output. Each SRAM is equivalent to completing a small matrix multiplication. The addition and XOR of the Galois field operation are equivalent. Each lookup table SRAM result corresponds to the corresponding position of the matrix element and performs XOR to complete the member encoder operation.

[0046] Specifically, the structure of the Turbo encoder is as follows: Turbo encoder, two identical member encoders and an interleaver, wherein the member encoder is as follows:

[0047] Assume that the initial values ​​in the registers are D2, D1, and D0, and the input is c k The encoders shown in the following equations 1-3 and 1-4 can be decomposed into the following two parts:

[0048] First, we discuss the content shown in the following formula 1-3, assuming that the output of this part is m k , it is easy to get:

[0049] m k =D0+D1+c k c k =D0+D1+m k

[0050] m k+1 =D1+D2+c k+1 c k+1 =D1+D2+m k+1

[0051] m k+2 =D2+m k +c k+2 c k+2 =D2+m k +m k+2

[0052] m k+3 =m k +m k+1 +c k+3 c k+3 =m k +m k+1 +m k+3

[0053] m k+4 =m k+1 +m k+2 +c k+4 c k+4 =m k+1 +m k+2 +m k+4 .............................. ..............................

[0055] m k+n =m k+n-3 +m k+n-2 +c k+n (1-1)→ck+n =m k+n-3 +m k+n-2 +m k+n (1-2)

[0056] By simple matrix multiplication, we can easily get:

[0057]

[0058] From (1-3), we can easily get:

[0059] set up

[0060] Since A is a lower triangular matrix and all diagonal elements are non-zero, the matrix A is invertible. So:

[0061] [D0 D1 D2 m k m k+1 … m k+n ] T =A -1 ×[D0 D1 D2 c k c k+1 … c k+n ] T (1-5)

[0062] In (1-5), A is only related to the above structure, so (1-5) shows that when the above structure is known, the above structure can process any bits in parallel and the output is the mk sequence.

[0063] Then we discuss the part shown in the following formula 1-4, where the input is m k , the output is d k , it is easy to get:

[0064] d k =D0+D2+m k

[0065] d k+1 =D1+m k +m k+1

[0066] d k+2 =D2+m k+1 +m k+2

[0067] d k+3 =m k +m k+2 +m k+3

[0068] d k+4 =m k+1 +m k+3 +mk+4 ..............................

[0069] d k+n =m k+n-3 +m k+n-1 +m k+n (1-6)

[0070] By simple matrix multiplication, we can easily get:

[0071]

[0072] Therefore, when the above-mentioned partial structures are known, the above-mentioned parts can realize parallel processing of any bit. In summary, it can be concluded that the structure of the Turbo encoder is known and can realize parallel processing of any bit.

[0073] Adding redundant parts to the matrix formula (1-7) yields formula (1-8):

[0074] make

[0075] make Where 0 4×60 Represents a 4-row 60-column all-zero matrix, then:

[0076]

[0077] When the degree of parallelism is 60, n=59 in (1-5), (1-5) can be written as:

[0078] [D0 D1 D2 m k m k+1 … m k+59 ] T =A -1 ×[D0 D1 D2 c k c k+1 … c k+59 ] T (1-9)

[0079] Substituting (1-9) into (7-8) yields (1-10) as follows:

[0080]

[0081] Pick Divide G into columns:

[0082]

[0083] Among them, H1~H16, R1~R8 are all 32×4 matrices. 0 is a 32×4 all-zero matrix.

[0084] [D0 D1 D2 c k c k+1 c k+2 … c k+59 ] T The rows are divided into one 3×1 matrix and 15 4×1 matrices. According to the matrix decomposition and multiplication principle (1-10), it can be written as follows:

[0085]

[0086] Note that the final form of (1-11) is F1 32×4 ×P1 4×1 +F2 32×4 ×P2 4×1 +F3 32×4 ×P3 4×1 +…, the next step is to connect with Chapter 0 and understand the mapping of these 23 matrix multiplications to 23 SRAMs. By the way, we can also obtain the corresponding Table1, Table2, ...Table23.

[0087] In addition, note that the first matrix multiplication in (1-11) does not satisfy the form F 32×4 ×P 4×1 , so do the following:

[0088] Let M1′ 32×4 =[M1 32×3 0 32×1 ], M2′ 32×4 =[M2 32×2 0 32×1 ],

[0089] Table 24 can be obtained by using M1' to multiply the 16 linearly independent column vectors [0 0 0 0]T, [0 0 0 1]T, [0 0 1 0]T, [0 0 1 1]T, [0 1 0 0]T, ..., [1 1 1 1]T respectively and transposing the results in order.

[0090] Table 25 can be obtained by using M2' to multiply the 16 linearly independent column vectors [0 0 0 0]T, [0 0 0 1]T, [0 0 1 0]T, [0 0 1 1]T, [0 1 0 0]T, ..., [1 1 1 1]T respectively and transposing the results in order.

[0091] It should be pointed out here that the above operation on M1 and M2 is equivalent to Substitute into Chapter 0, and again notice that the last four digits on the left side of the equal sign (output) of (1-10) are m k+57 、m k+58 、m k+59 , 0, where the first three bits correspond to the first three initial values ​​used in the next loop, and the last bit is fixed to 0. Then, in the architecture of 7.3, it can be found that m k+57 、m k+58 、m k+59 , 0 enters MUX and is used to query Table 24 and Table 25 except for the first round. That is to say, in actual use, D3=0 above is a fixed value, and a column of all-zero matrices is added to M1 and M2. These two points will ensure and The results are completely consistent.

[0092] These 25 tables are configured to 25 16×32 SRAMs. When applied, the input 4-bit status information is used as the SRAM address query to obtain the design output. Each SRAM is equivalent to completing a matrix multiplication in (1-11). The addition and XOR of the Galois field operation are equivalent, so it is only necessary to map the addition items in (1-11) to the corresponding SRAM results and design the corresponding XOR to complete the operation of (1-11). The calculation process is shown in formula 1-5 above.

[0093] MUX: Selects the initial value at the beginning (the standard defines that the initial value is fixed to 0). Otherwise, it selects the output of the TXOR0 module (the last four bits).

[0094] TXOR1: XOR the 9 32-bit input data and output the XOR result (32 bits)

[0095] TXOR0: XOR the 16 32-bit data input, and output the first 28 bits of the XOR result (32 bits), and input the last 4 bits into MUX as the initial value of the next cycle;

[0096] Note: In the above formula, each LUT is divided into 8 areas to represent 8 SRAMs. Each area table has T1, ..., T25, which means that the SRAM is equipped with Table1, ..., Table25. "Empty" or blank means that the SRAM is not equipped with any table (the SRAM area will not be used in the encoding process of this algorithm).

[0097] The Turbo coding device provided by the present invention is described below. The Turbo coding device described below and the Turbo coding method described above can be referred to each other.

[0098] The embodiment of the present invention discloses a Turbo encoding device, see Figure 2 ,include:

[0099] A two-dimensional generator matrix determination module 10 is used to encode the serial output of the member encoder in the Turbo encoder in one dimension of the bit stream, extract the time information, and convert the serial output of the member encoder into a two-dimensional generator matrix of the member encoder based on the time information;

[0100] A matrix determination module 20, configured to convert the two-dimensional generator matrix into a plurality of matrixes based on the characteristics of the generator polynomial;

[0101] A parallel encoding module 30, for performing parallel encoding on the input information and then outputting the information based on each of the divided matrices and the corresponding preset lookup table;

[0102] The preset lookup table is a table that lists all matching input vectors and output vectors corresponding to the matrix.

[0103] Figure 3 An example of a physical structure diagram of an electronic device is shown, and the electronic device may include: a processor 310, a communication interface 320, a memory 330, and a communication bus 340, wherein the processor 310, the communication interface 320, and the memory 330 communicate with each other through the communication bus 340. The processor 310 may call the logic instructions in the memory 330 to execute a Turbo coding method, which includes:

[0104] S1: Encode the serial output of the member encoder in the Turbo encoder in one dimension of the bit stream, extract the time information, and based on the time information, convert the serial output of the member encoder into a two-dimensional generator matrix of the member encoder;

[0105] S2: based on the characteristics of the generator polynomial, convert the two-dimensional generator matrix into a plurality of partition matrices;

[0106] S3: Based on each of the divided matrices and the corresponding preset lookup table, the input information is encoded in parallel and then output;

[0107] The preset lookup table is a table that lists all matching input vectors and output vectors corresponding to the matrix.

[0108] In addition, the logic instructions in the above-mentioned memory 330 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0109] On the other hand, the present invention further provides a computer program product, the computer program product comprising a computer program stored on a non-transitory computer-readable storage medium, the computer program comprising program instructions, and when the program instructions are executed by a computer, the computer can perform a Turbo coding method, the method comprising:

[0110] S1: Encode the serial output of the member encoder in the Turbo encoder in one dimension of the bit stream, extract the time information, and based on the time information, convert the serial output of the member encoder into a two-dimensional generator matrix of the member encoder;

[0111] S2: based on the characteristics of the generator polynomial, convert the two-dimensional generator matrix into a plurality of partition matrices;

[0112] S3: Based on each of the divided matrices and the corresponding preset lookup table, the input information is encoded in parallel and then output;

[0113] The preset lookup table is a table that lists all matching input vectors and output vectors corresponding to the matrix.

[0114] In another aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, a Turbo coding method is implemented, the method comprising:

[0115] S1: Encode the serial output of the member encoder in the Turbo encoder in one dimension of the bit stream, extract the time information, and based on the time information, convert the serial output of the member encoder into a two-dimensional generator matrix of the member encoder;

[0116] S2: based on the characteristics of the generator polynomial, convert the two-dimensional generator matrix into a plurality of partition matrices;

[0117] S3: Based on each of the divided matrices and the corresponding preset lookup table, the input information is encoded in parallel and then output;

[0118] The preset lookup table is a table that lists all matching input vectors and output vectors corresponding to the matrix.

[0119] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0120] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0121] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A Turbo coding method, characterized in that: include: Encode the serial output of the member encoder in the Turbo encoder in one dimension of the bit stream, extract the time information, and convert the serial output of the member encoder into a two-dimensional generator matrix of the member encoder based on the time information; Based on the characteristics of the generator polynomial, the two-dimensional generator matrix is ​​converted into a plurality of partition matrices; Based on each of the divided matrices and the corresponding preset lookup table, the input information is encoded in parallel and then output; The preset lookup table is a table that lists all matching input vectors and output vectors corresponding to the matrix.

2. The Turbo encoding method according to claim 1, characterized in that: include: The encoding formulas of the serial outputs of the member encoders at n consecutive moments are respectively represented by matrices, wherein n is a natural number, and the serial outputs of the member encoders include the encoding outputs of the feedback part and the encoding outputs of the forward part.

3. The Turbo encoding method according to claim 2, characterized in that: The coded output of the feedback part is equal to the matrix A (n+h)x(n+h) The inverse of is multiplied by the input code, where h is the order of the generator matrix.

4. The Turbo encoding method according to claim 3, characterized in that: The coded output of the forward part is equal to the forward part generation matrix multiplied by the coded output of the feedback part, and the matrix B is obtained. (n+h)x(n+h) , the two-dimensional generator matrix G of the member encoder (n+h)x(n+h) From the matrix B (n+h)x(n+h) Multiply by matrix A (n+h)x(n+h) The inverse of is obtained.

5. The Turbo encoding method according to claim 4, characterized in that: Based on the characteristics of the generator polynomial, the two-dimensional generator matrix is ​​converted into a plurality of matrices, including: the first h columns of the two-dimensional generator matrix are used as the initial value calculation part H0 (n+h)×h Divide into two matrices, upper and lower, and add zero elements in the rh column on the right to get Divide the last n columns equally into n / r matrices Hi (n+h)×r , each is divided into a matrix Hi (n+h)×r Divide into two matrices: upper and lower get The r-column matrix is ​​divided into two parts, where i is less than or equal to n / r.

6. The Turbo encoding method according to claim 5, characterized in that: The method further comprises: encoding the input information in parallel based on each of the matrixes and the corresponding preset lookup table before outputting the information; Add later Row 0 element, we get All matrices are unified as Matrix with rows and columns, encoding output d k ~d k+n-1 By calculating G (n+h)x(n+h) Multiply the input information D2, D1, D0, 0, c k ~c k+n-1 , which is converted to indivual The generator matrix with rows and columns is multiplied by D2, D1, D0, 0 or c k+(i-1)×r ~c k+i×r get.

7. The Turbo encoding method according to claim 1, characterized in that: Matrix operations are calculated by lookup tables. The lookup tables corresponding to each matrix are Table1, Table2 to The lookup table is configured to indivual SRAM, each SRAM result corresponds to the corresponding position of the matrix element and performs XOR to complete the encoding.

8. A Turbo encoding device, characterized in that: include: A two-dimensional generator matrix determination module is used to encode the serial output of the member encoder in the Turbo encoder in one dimension of the bit stream, extract the time information, and convert the serial output of the member encoder into a two-dimensional generator matrix of the member encoder based on the time information; A matrix determination module is used to convert the two-dimensional generator matrix into a plurality of matrixes based on the characteristics of the generator polynomial; A parallel encoding module, used for encoding the input information in parallel and then outputting it based on each of the divided matrices and the corresponding preset lookup table; The preset lookup table is a table that lists all matching input vectors and output vectors corresponding to the matrix.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps of the Turbo encoding method according to any one of claims 1 to 7 are implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the Turbo encoding method according to any one of claims 1 to 7 are implemented.

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