Method and device for implementing matrix operations

Abstract

Method for implementing a matrix operation, wherein for the matrix operation a first digital result is determined according to a first analog addition by means of a first memristor arrangement (102), wherein a second digital result is determined according to a second analog addition by means of a second memristor arrangement (102), and wherein the first result and the second result are digitally added. Device (100) for implementing a matrix operation, wherein the device (100) comprises at least a first memristor arrangement (102) and a second memristor arrangement (102), wherein the device (100) comprises a first analog-to-digital converter (106, 116) and a second analog-to-digital converter (106, 116), and wherein the device (100) is designed to determine, for the matrix operation, a first digital result according to a first analog addition by means of the first memristor arrangement (102) and the first analog-to-digital converter (106, 116), and to determine a second digital result according to a second analog addition by means of the second memristor arrangement (102) and the second analog-to-digital converter (106, 116).

Description

Background Art

[0001] Mathematically determining the scalar product from a vector and a matrix of matching dimensions by computer requires a large number of additions and multiplications and therefore a large amount of memory space in the computer. In contrast, computing the scalar product with the aid of a matrix of corresponding dimensions by in-memory calculations requires less memory space. The same applies to the solution of systems of differential equations.

[0002] Use specialized hardware, such as a dot product engine, for such applications.

[0003] It would be desirable to implement a more efficient possibility to perform such calculations relative to dedicated hardware. Summary of the invention

[0004] This is achieved by the subject matter of the independent claims.

[0005] A related method for implementing a matrix operation provides that for the matrix operation a first digital result is determined according to a first analog addition by means of a first memristor arrangement, wherein a second digital result is determined according to a second analog addition by means of a second memristor arrangement, and wherein the first result and the second result are digitally added. The analog addition in the various memristor arrangements allows the analog results to be calculated quickly. The matrix operation is completed by digitally adding the analog results and the matrix operation is provided digitally for further processing.

[0006] Preferably, provision is made for the first digital result to be determined as a function of a first simulation result, wherein the second digital result is determined as a function of a second simulation result, wherein the simulation results are determined at least partially overlapping in time. This parallelization speeds up the calculation.

[0007] Preferably, it is provided that a first voltage is applied to a first memristor of the first memristor arrangement, wherein a second voltage is applied to a second memristor of the first memristor arrangement at least partially overlapping in time, wherein a first sum current is detected at a first output of the first memristor arrangement, the first sum current representing a current flowing through the first memristor and the second memristor, wherein the first voltage is applied to a third memristor of the second memristor arrangement at least partially overlapping in time, wherein the second voltage or a third voltage is applied to a fourth memristor of the second memristor arrangement at least partially overlapping in time, wherein a second sum current is detected at a second output of the second memristor arrangement, the second sum current representing a current flowing through the third memristor and the fourth memristor, wherein the result is determined based on the first sum current and the second sum current. The calculation of matrix multiplication is accelerated by high parallelization.

[0008] Preferably, provision is made that the first voltage is defined according to a first element of a first matrix, wherein the second voltage is defined according to a second element of the first matrix, wherein a first resistance value of the first memristor is defined according to a first element of the second matrix, wherein a second resistance value of the second memristor is defined according to a second element of the second matrix, and wherein the result represents a scalar product of matrices. The calculation of the scalar product can be performed very quickly by a high degree of parallelization.

[0009] Preferably, provision is made for at least one resistance value of the memristor to be programmed as a function of an element of the second matrix. This allows the arrangement to be initialized in a simple manner for a new calculation.

[0010] Preferably, it is provided that the resistance values ​​of at least two memristors are defined or programmed as a function of the elements of the second matrix. For parallelization, the same matrix is ​​used multiple times in the device. This further speeds up the calculation.

[0011] Preferably, provision is made for arranging a plurality of memristors in a matrix arrangement, wherein the second matrix or the plurality of second matrices define a resistance value arrangement of the plurality of memristors, and wherein the memristors in the matrix arrangement have resistance values ​​or are programmed with resistance values ​​which in the resistance value arrangement, in particular with respect to their index, correspond to their positions in the matrix arrangement. This correspondence is particularly clear.

[0012] Preferably, provision is made for at least two groups of memristors to have resistance values ​​or to be programmed with resistance values, which are defined according to elements of the same second matrix. Such a grouping makes the assignment significantly easier.

[0013] Preferably, provision is made for at least some of the memristors of at least two groups of memristors in the matrix arrangement to be used for determining the same sum current. The matrices are mapped one below the other in the same row. This allows the use of analog-to-digital converters with low resolution.

[0014] Preferably, provision is made that at least one memristor from one of the at least two groups of memristors in the matrix arrangement is not taken into account when determining the sum current of the memristors of the other of the at least two groups of memristors. This allows full utilization of analog-to-digital converters with high resolution.

[0015] Preferably, it is provided that the first voltage is an analog signal generated by a digital-to-analog converter according to a digital signal defined by a first element of the first matrix, and / or the second voltage is an analog signal generated by a digital-to-analog converter according to a digital signal defined by a second element of the first matrix. Thus, the input variables for the calculation can be generated very skillfully.

[0016] Preferably, it is provided that the first voltage and the second voltage differ by a factor, in particular a power of 2, which factor is defined in particular as a function of the resolution of the analog-to-digital converter or as a function of the bit factorization on which the matrix operation is based. Thus, in particular the resolution of the signal can be influenced as a function of the resolution of the analog-to-digital converter. The factor can also be differentiated as a function of whether the underlying matrix operation is a 1-bit or 2-bit factorization.

[0017] It is preferably provided that the first sum current includes at least a first current and a second current, wherein the first current flows through the first memristor when the first voltage is applied to the first memristor, and wherein the second current flows through the second memristor when the second voltage is applied to the second memristor. This is a particularly advantageous consideration for the individual currents.

[0018] Preferably, provision is made that the first voltage is applied simultaneously to the first memristor and the third memristor, or wherein the second voltage is applied simultaneously to at least the second memristor and the fourth memristor, wherein a first sum current of the currents flowing through the first memristor and the second memristor is detected, wherein a second sum current of the currents flowing through the third memristor and / or the fourth memristor is detected, and wherein the result is determined as a function of the first sum current and the second sum current. This makes it possible to evaluate a plurality of calculations in parallel.

[0019] Preferably, provision is made for the analog-to-digital converter to determine a digital signal defining the value of at least one bit as a function of the sum current. The value of the register of the memory is thereby determined particularly easily.

[0020] Preferably, it is provided that a plurality of sum currents are determined, wherein a plurality of bits are determined from the plurality of sum currents, wherein at least one bit defined from one of the sum currents is added to at least one bit defined from another sum current. By adding a bit to another bit or by adding a plurality of bits to a plurality of bits simultaneously, the resolution can be varied.

[0021] Preferably, provision is made that at least one bit in a register is arranged shifted relative to the least significant bit of the result in the direction of the most significant bit of the result before being added to another bit from another register. As a result, the individual memristors can be driven with an increased voltage, so that the resolution of the analog-to-digital converter can be reduced.

[0022] Preferably, provision is made for at least one bit in a register to be arranged adjacent to another bit from another register before being added to the other bit relative to the least significant bit of the result. This results in particularly efficient use of the space in the register.

[0023] Preferably, provision is made for the plurality of memristors to be arranged in a matrix arrangement, wherein a second matrix or a plurality of second matrices define a resistance value arrangement of the plurality of memristors, and wherein the memristors in the matrix arrangement have a resistance or are programmed with a resistance value which in the resistance value arrangement, in particular with respect to its index, corresponds to its position in the matrix arrangement. Such an assignment can be displayed particularly easily.

[0024] The device for implementing a matrix operation comprises a first memristor arrangement and a second memristor arrangement, wherein the device comprises a first analog-to-digital converter and a second analog-to-digital converter, and wherein the device is configured to determine a first digital result from a first analog addition performed by means of the first memristor arrangement and the first analog-to-digital converter, and to determine a second digital result from a second analog addition performed by means of the second memristor arrangement and the second analog-to-digital converter for the matrix operation. The device enables the matrix operation to be calculated quickly.

[0025] Preferably, it is provided that a first voltage is applied to a first memristor of a memristor arrangement, wherein a second voltage can be applied to a second memristor of the memristor arrangement at least partially overlapping in time, wherein a first total current can be detected at a first output of the memristor arrangement, the first total current representing the current flowing through the first memristor and the second memristor, wherein the first voltage can be applied to a third memristor of the memristor arrangement at least partially overlapping in time, wherein the second voltage can be applied to a fourth memristor of the memristor arrangement at least partially overlapping in time, wherein a second total current can be detected at a second output of the memristor arrangement, the second total current representing the current flowing through the third memristor and the fourth memristor.

[0026] Preferably, provision is made for a plurality of memristors to be arranged in a matrix arrangement. This can be displayed particularly effectively.

[0027] It is preferably provided that the digital-to-analog converter is designed to detect information about at least one sum current.

[0028] Preferably, it is provided that the device comprises a first analog-to-digital converter for generating the first voltage and a second analog-to-digital converter for generating the second voltage. This allows for better control of the device.

[0029] It is preferably provided that the device provides a memristor arrangement, wherein two memristors are arranged at nodes of a row and a column of the matrix arrangement, the two memristors being variable in opposite directions with respect to their charge-dependent resistance value.

[0030] A device is provided which has a microprocessor, a switching device and a memory, in particular with registers which are designed to control the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Further advantageous embodiments emerge from the following description and the accompanying drawings. In the drawings:

[0032] Figure 1 Schematically showing the matrix arrangement,

[0033] Figure 2 The memristor arrangement is schematically shown,

[0034] Figure 3 A first calculation scheme is shown,

[0035] Figure 4 The circuit is schematically shown,

[0036] Figure 5 shows the steps in the method for calculating,

[0037] Figure 6 A second calculation scheme is shown,

[0038] Figure 7 shows the matrix allocation in the memristor arrangement,

[0039] Figure 8 A third calculation scheme is shown,

[0040] Fig. 9 Schematically showing a memristor arrangement with lead-out wires,

[0041] Fig.10 A fourth calculation scheme is shown,

[0042] Fig.11 Schematically showing a memristor arrangement with other pinouts,

[0043] Fig.12 A fifth calculation scheme is shown,

[0044] Fig.13 Other memristor arrangements are shown schematically,

[0045] Fig.14 A sixth calculation scheme is shown,

[0046] Fig.15 Other memristor arrangements are shown schematically,

[0047] Fig.16 A seventh calculation scheme is shown. DETAILED DESCRIPTION

[0048] In the following description, a memristor is an electronic component whose resistance can be changed by a current flowing through it when a voltage applied to the memristor exceeds a threshold value. A memristor is programmed to a specific resistance value, for example, by an iterative algorithm that applies voltage pulses of defined size, duration and shape to the memristor. After each voltage pulse, it is preferably checked by calculation whether the memristor has reached the target value of its resistance value.

[0049] With such an algorithm, the memristor can only be programmed with sufficient accuracy to a small number of discrete resistance values. To this end, the digitally encoded resistance value is converted into a corresponding voltage pulse, for example, by a digital-to-analog converter. In order to calculate the resistance value after each voltage pulse, the analog current signal is detected as an analog result and digitized by an analog-to-digital converter. The accuracy of the digitized result depends on the quality of the analog-to-digital converter, with which the analog result is converted back into the digital range after the calculation. Due to the conversion of values ​​from digital to analog and back again from analog to digital, it can be assumed that these calculations are affected by a certain degree of unclearness. The reasons for this are conversion errors such as digital residual errors or nonlinearities of the converter. Noise may also affect the result, especially in the case of a high resolution of the converter.

[0050] Memristors can be used for a variety of effects. One physical system that uses this effect has a variable resistance that is affected by the current that has flowed through one or more memristors in the past.

[0051] The memristors can be arranged in the physical system in the form of a matrix of dimension n × m and used as coefficients or weights of a mathematical matrix of the same dimension n × m. In such a physical system, the memristors form a memory for the coefficients or weights.

[0052] Memristors can represent inexpensive physical systems, since they require very little space. Analog-to-digital converters and digital-to-analog converters do not have these advantages. The accuracy of the physical system depends primarily on the achievable resolution of the memristor values, the quality of the analog-to-digital converter and the digital-to-analog converter, and thus also on the price of the analog-to-digital converter and the digital-to-analog converter.

[0053] exist Figure 1 Schematically, a matrix arrangement 100 is shown in FIG. 1 , exemplarily for an apparatus for implementing a matrix operation (eg, matrix multiplication).

[0054] The matrix device 100 includes a plurality of memristor arrangements 102, the structures of which are Figure 2 Detailed description is given in FIG. 1 by taking the memristor arrangement 102 as an example.

[0055] The memristors form a memristor array, wherein first ones of the memristors are arranged on a common row line.

[0056] In this example, Figure 2 As shown, the memristor arrangement 102 includes nine memristors a, ..., i. The first memristor a is arranged between the first row line ji and the first column line mz. The second memristor b is arranged between the second row line ki and the first column line mz. The third memristor c is arranged between the third row line li and the first column line mz. The fourth memristor d is arranged between the first row line ji and the second column line nz. The fifth memristor e is arranged between the second row line ki and the second column line nz. The sixth memristor f is arranged between the third row line li and the second column line nz. The seventh memristor g is arranged between the first row line ji and the third column line oz. The eighth memristor h is arranged between the second row line ki and the third column line oz. The ninth memristor i is arranged between the third row line li and the third column line oz.

[0057] In this example, the memristor arrangement 102 forms a symmetric memristor matrix of dimension 3 x 3. The dimension may be larger or smaller. The memristor matrix may be asymmetric.

[0058] In this example, the matrix arrangement 100 includes fifteen memristor arrangements 102 arranged in three rows and five columns. The memristors arranged in the same row of the memristor matrix of the first row of the matrix arrangement 100 use the same first row line and are connected to the first input terminal j0. The memristors arranged in the same row of the memristor matrix of the second row of the matrix arrangement 100 use the same second row line and are connected to the first input terminal k0. The memristors arranged in the same row of the memristor matrix of the third row of the matrix arrangement 100 use the same third row line and are connected to the first input terminal l0. The memristors arranged in the same column of the memristor matrix of the first column of the matrix arrangement 100 use the same first column line and are connected to the first output terminal m5. The memristors arranged in the same column of the memristor matrix of the memristor arrangement 102 of the second column of the matrix arrangement 100 use the same second column line and are connected to the second output terminal n5. The memristors arranged in the same column of the memristor matrix of the memristor arrangement 102 of the third column of the matrix arrangement 100 use the same third column line and are connected to the second output terminal o5.

[0059] According to the circuit diagram, the remaining memristor arrangements 102 of the matrix arrangement 100 are connected to input terminals j1, k1, 11, j2, k2, 12 and output terminals m4, n4, o4, m3, n3, o3, m2, n2, o2, m1, n1, o1.

[0060] generally, Figure 2The index i of the memristor arrangement 102 shown in indicates the row in which the memristor arrangement 102 is arranged in the matrix device 100. For a memristor arrangement 102, Figure 2 The index z shown in represents the column in which the memristor arrangement 102 in the matrix device 100 is arranged. In this example, the first column of the matrix arrangement 100 is assigned to the most significant bit MSB of the calculation result. In this example, the last column of the matrix arrangement 100 is assigned to the least significant bit LSB of the calculation result. Figure 1 Adjacent output terminals are shown grouped into columns. From the first column on the left to the last column on the right, the columns are assigned factors 16, 8, 4, 2, 1. These factors indicate the power of 2 with which the result of the analog summation of the columns is taken into account in the digital summation of the result. For example, the factors are defined according to the bit factorization on which the matrix operation is based.

[0061] In this example, a digital-to-analog converter 104 is arranged on each row line, which supplies an input voltage to the memristor array. If the calculation is performed in binary, the digital-to-analog converter 104 is omitted. The digital-to-analog converter 104 must be able to map the column current. The column current represents the sum of the maximum weights in a column. It should be taken into account that in some designs, the row voltage of the column is already equipped with a factor. A digital-to-analog converter 106 is arranged on each column line. The analog-to-digital converter 106 that reads out the analog result requires a resolution that is adapted to the size of the memristor matrix and to the bit width of the input variable in order to digitally output the output value at its output with sufficient resolution. In the case of a 4×4 matrix, for example, four values ​​are added to each column, so that in this case the digital-to-analog converter 106 must cover a value range that is at least 4 times larger. If a factor has been assigned to the row voltage, the value range must be increased accordingly. This corresponds to a value range that is 2 bits larger. The factors assigned to the columns can also be defined according to the resolution of the digital-to-analog converter. This may require the input voltage adaptation described below.

[0062] In this example, as described below, the input terminals of the digital-to-analog converter 104 and the output terminals of the analog-to-digital converter 106 are combined in row or column groups and are configured to perform the following calculations.

[0063] Through this process, calculations related to the matrix can be calculated with arbitrary accuracy. As described below, the input values ​​and weights of the matrix are decomposed into individual bits. In this example, the input value 0×03 is decomposed into 1-bit factors, which then correspond to 0*2^2+1*2^1+1*2^0.

[0064] According to this scheme, the entire matrix operation is formulated. For example, a matrix operation with a 3-bit wide input value and a 3-bit weight can be decomposed into 81 matrix operations of 1 bit each, where all matrix operations are performed simultaneously.

[0065] 81 memristors are needed simultaneously for this purpose. The digital-to-analog converters and analog-to-digital converters used only need to resolve a small number of levels.

[0066] The matrix can be designed flexibly with regard to the resolution of the components. This means:

[0067] The resolution of the digital-to-analog converter and the analog-to-digital converter is scalable. For example, the dimensions of the matrix can be determined so that a number of analog-to-digital converters operating at a lower resolution or vice versa are used.

[0068] If the speed of the analog-to-digital converters used is chosen to be faster than the reaction speed of the matrix (i.e. its components or elements), or if the analog-to-digital converters used and the matrix used allow this, it is provided on the one hand that the analog-to-digital converters are multiplexed. This multiplexing can be carried out within the matrix or on other matrices in the memory.

[0069] Since the number of states can be reduced, the memristor can operate stably and independently of temperature.

[0070] In binary operation, the digital-to-analog converter is eliminated. In binary operation, the analog-to-digital converter only needs n levels of resolution for a matrix of dimension n×n. In binary operation, the memristor only needs two states, i.e. 1 bit each. In binary operation, the memristor can be programmed very quickly, in particular without repetitive algorithms.

[0071] The matrix arrangement 100 can be arbitrarily scalable. The number of matrices depends linearly on the resolution of the weights. In this example, one matrix is ​​used for each bit. For example, for a matrix of dimension 3×3 with 3-bit input values ​​and 3-bit output values, a circuit arrangement with three matrices is suitable, each matrix being used for calculation three times. The number of additional iterations depends on the resolution of the input values. In this example, one iteration step is set for each bit. Memristors with higher resolution can also be used. If the memristor can be programmed with a resolution of more than one bit, the number of matrices will be reduced accordingly.

[0072] In order to manipulate the matrix arrangement, the matrix operation is decomposed into binary components. This is described below based on matrices of dimension 3×3 and vectors of dimension 3×1.

[0073] First, decompose the desired matrix operation into its individual bits

[0074] .

[0075] The base 2 factor is then placed outside the brackets, yielding the parsed value for 3 bits, for example:

[0076] .

[0077] By replacing the following matrix with E0, ...

[0078] ,

[0079] get

[0080] .

[0081] exist Figure 1 The manipulation of the matrix arrangement 100 for calculating this product is shown in FIG. More precisely, first Figure 1 The memristors are assigned values ​​from the matrices E0, E1, E2 at the nodes shown, i.e., the memristors are programmed accordingly. In this example, the values ​​from the rows of the corresponding matrices E0, E1, E2 are programmed as the resistance values ​​or conductance values ​​in the columns of the memristor arrangement 102, such as Figure 2 As shown. Figure 1 In , the same index is used to represent the allocation of the corresponding matrices E0, E1, E2 to the hardware of the matrix arrangement 100. Then Figure 1 The input values ​​of the input terminals denoted by j0, j1, j2, k0, k1, k2, l0, l1, l2 in FIG. 1 are assigned the values ​​of the vectors A0, A1, A2 of the same index. This means that the digital-to-analog converters 104 of these input terminals apply corresponding voltages. More precisely, in this example, no voltage is applied due to the bit decomposition of the logic 0. On the contrary, a higher voltage is applied for the logic 1.

[0082] This matrix arrangement 100 is a memory consisting of memristors. If an arithmetic operation is performed with the memory, i.e. a calculation is performed in memory, the memory location (i.e. the memristor) is first written accordingly. A voltage is then applied to a row of the matrix. At least partially superimposed on this in time, a column is grounded. The current flowing through the memristor at the node of the row and the column to the ground point depends on the resistance value R of the memristor. Knoten :I=U / R Knoten .

[0083] If voltage is applied to multiple rows simultaneously and only one row is grounded, the current flowing through each memristor in the column is U Zeile *1 / R Knoten In this example, multiple rows in the groups [j0, k0, l0], [j1, k1, l1], and [j2, k2, l2] are manipulated in combination.

[0084] These currents are then added at the ground point, i.e. in this example on the column line near the analog-to-digital converter 106 of the column connected to ground, so that for the memristors arranged at the nodes of the row and the column with resistance values ​​Ra, Rb, ..., when a voltage U is applied to each of these rows Zeile The following total current is generated:

[0085] .

[0086] These terms are sums of divisions. If the corresponding conductance values ​​are used instead of this representation, the sum of products is evaluated. If it is also assumed that the voltage U applied to a line Zeile is the same across the row and multiple columns are grounded simultaneously, then multiple of these operations can be performed simultaneously.

[0087] The resulting sum current represents the analog result of the calculation for the column line under consideration and is detected in this example by a corresponding analog-to-digital converter 106. The analog-to-digital converter 106 preferably has a virtual zero point. This means that the columns are not actually grounded. The ground potential is provided by the virtual zero point. The analog-to-digital converter 106 is, for example, a transimpedance amplifier. The digital result of this calculation is in the example of length 8 bits, according to Figure 3 The calculation scheme 300 shown by way of example for a scalar j in FIG. 1 determines the sum for each of the scalars j, k, l. .

[0088] In this example, the digitized results of the column lines assigned to the scalar j are denoted by m5, m4, m3, m2, and m1 starting from the first column on the left side of the matrix arrangement 100. These digitized results are shown in Figure 3 In this example, the sum of of Figure 3 The MSB shown on the left is the same as the sum of Figure 3 There is 8 bits of space between the LSBs shown on the right. For example, corresponding registers are provided in a memory, into which the corresponding digitized results are written. The first digitized result m1 of the last column of the matrix arrangement 100 is arranged in the first row. The first digitized result m1 provides two bits and is arranged in the sum The second digitized result m2 of the second-to-last column provides three bits, whose LSB is relative to the sum The LSB of the sum The MSB of the third column is shifted by 4 bits. The third digitized result m3 of the third column provides four bits, whose LSB is relative to the sum The LSB of the sum The MSB of the second column is shifted by two bits. The fourth digitized result m4 of the second column provides three bits, whose LSB is relative to the sum The LSB sum of The MSB of the first column is shifted by three bits. The fifth digitized result m1m5 of the first column provides two bits, whose LSB is relative to the sum The LSB of the sum The MSB of is shifted by four bits. By forming the sum of the columns of the first calculation scheme 300, the calculation result is determined as an 8-bit sum .

[0089] Figure 4 Schematically shown is a circuit 400 for controlling a digital-to-analog converter 104 to apply a voltage to a row line and for controlling an analog-to-digital converter 106 to detect a current generated on a column line. In this example, at least one electrical switching device 402 is implemented, which can be switched by a microprocessor 404 via at least one signal line 406. For example, a junction field effect transistor is used as an electrical switch in the switching device 402. The matrix arrangement 100 is connected to the switching device 402 via at least one corresponding current source 408. A memory 410 with registers for calculations is connected to the microprocessor 404 via a data bus 412.

[0090] Microprocessor 404 is designed to control matrix arrangement 100 according to the described method in order to perform the calculations.

[0091] The process of this method is Figure 5 In step 502, the equation to be solved for the matrix operation is decomposed. The matrices E0, E1, E2 can be determined more accurately.

[0092] Then execute step 504.

[0093] In step 504, the memristor arrangement 102 of the matrix arrangement 100 is programmed for the calculation. In this example, the memristors are programmed according to values ​​from matrices E0, E1, E2. For a matrix of dimension 3×3 with 3-bit input values ​​and 3-bit output values, a circuit arrangement with three matrices is suitable, each matrix being used for the calculation three times. Figure 1 A possible implementation is shown in FIG. 1 , where the assignment of the memristor arrangement 102 to the matrices E0, E1, E2 is represented by E0, E1, E2. In this example, all matrix multiplications by the same factor are arranged one below the other, i.e. the memristors are selected and programmed by corresponding manipulations. A high resistance value represents, for example, a logical 1, while a relatively low resistance value represents, for example, a logical 0.

[0094] Then execute step 506.

[0095] In step 506, the input values ​​of the input terminals denoted by j0, j1, j2, k0, k1, k2, l0, l1, l2 are assigned voltages according to the input values ​​of j0, j1, j2, k0, k1, k2, l0, l1, l2. This means that the digital-to-analog converters 104 of these input terminals apply corresponding voltages.

[0096] The resulting sum current is determined at least partially overlapping in time as an analog result of the calculation on the corresponding column line. In this example, the sum current of the column line under consideration is detected by the corresponding analog-to-digital converter 106. In this example, the digital result is written to the corresponding position in the register according to the first calculation method 300 to determine the sum current. .

[0097] In this example, the groups [j0, k0, l0], [j1, k1, l1], and [j2, k2, l2] are manipulated in combination and the digital results are determined for the corresponding column lines.

[0098] Then execute step 508.

[0099] In step 508, an 8-bit sum is determined for each of the scalars j, k, l As a result of the calculation.

[0100] According to this scheme, the entire matrix operation is formulated. For example, a matrix operation with a 3-bit wide input value and a 3-bit weight can be decomposed into 81 matrix operations of 1 bit each, where all matrix operations are performed simultaneously.

[0101] Figure 6 A second calculation scheme 600 is shown. The calculation implementation according to the second calculation scheme 600 further optimizes the above process by reducing the number of required registers. Unlike the first calculation scheme 300, the first digitized result m1 and the third digitized result m3 are arranged in the same row. Unlike the first calculation scheme 300, the second digitized result m2 and the fifth digitized result m1m5 are arranged in the same row. The rest of the process is as described in the first calculation scheme 300.

[0102] Some memristors in the otherwise regular matrix arrangement 100 are not used in these calculations. These calculations place uneven demands on the used digital-to-analog converters 106. The digital-to-analog converter 106 used to determine the output value m3 is configured to resolve four bits, and the digital-to-analog converters 106 used to determine the output values ​​m4 and m2 are configured to resolve three bits in this example. In this example, the other digital-to-analog converters 106 are configured to resolve only two bits.

[0103] If, in the allocation of the matrices E0, E1, E2, a shift is made for programming the memristor arrangements 102 in the rows of the matrix arrangement 100, such that the matrices E0, E1, E2 are such that Figure 7 This can be avoided if one is shown below the other.

[0104] In this case, the change of allocation is corrected by the voltage through adaptation. For all participating matrices, shifting the allocation in a row to the right will produce an error of factor 2. This is compensated by increasing the input voltage on the row to 2 times by shifting a memristor arrangement 102 to the right each time. Instead of multiplying the factor by multiple times, division can be performed simply from the supply voltage by means of a voltage divider. Shifting one position is corrected once, and shifting two positions is corrected twice. This leads to the manipulation of groups with input values ​​[j0, k0, l0], 2*[j1, k1, l1] and 4*[j2, k2, l2].

[0105] For the value of the factor X at the input, the required resolution of the analog-to-digital converter is calculated as follows:

[0106]

[0107] Where Y and Z are the maximum values ​​of the memristor state, that is, for n-bit resolution: Y, Z = 2n-1.

[0108] In the example with a 1-bit memristor, Z = 1. The input value on the row also has 1 bit, so Y = 1.

[0109] For a matrix of dimension 3×3 with 1-bit memristors and 3-bit input values ​​(i.e. 1 bit per row), the number of states that the analog-to-digital converter must resolve is 21.

[0110] Figure 8 A third calculation scheme 800 is shown. The calculation implementation according to the third calculation scheme 800 further optimizes the above process. Unlike the first calculation scheme 300, only the first digitized result m1, the second digitized result m2 and the third digitized result m3 are arranged. Unlike the first calculation scheme 300, these digitized results have the same bit length. The remaining process is as described in the first calculation scheme 300.

[0111] The required resolution of the analog-to-digital converter is essentially derived from the digital range that can be achieved during matrix operations.

[0112] In one aspect, provision is made for intermediate sums to be derived. If the digital range required for the matrix operation is greater than the resolution of the available analog-to-digital converter, intermediate sums can be derived, for example.

[0113] Here, the number of analog-to-digital converters required increases and the resolution decreases. Fig. 9 See an exemplary implementation in .

[0114] Based on the above Figure 7 Unlike the described implementation, a tap for the analog-to-digital converter 106 is arranged on each column line between the second and third rows of the matrix arrangement 100. The order in which the column lines are grounded and the voltage is applied to the row lines can be selected so that for each column line the current flows only through one of the taps arranged on the column line. The column line can then be constructed to be continuous without affecting the calculation of the sum current. The column line can be preferably permanently electrically interrupted at the location of the lead-out line between the memristor arrangement of the third row and the second row to determine the sum current analogously. The analog intermediate sum thus produced is detected by the taps and then digitally added.

[0115] The group having the output values ​​of the simulated intermediate sums describing the third row is represented by [m5, n5, o5], [m4, n4, o4], [m3, n3, o3], [m2, n2, o2], [m1, n1, o1]. The group having the output values ​​of the simulated intermediate sums describing the first and second rows is represented by [r5, s5, t5], [r4, s4, t4], [r3, s3, t3], [r2, s2, t2], [r1, s1, t1].

[0116] The rest of the process is the same as above, where Fig.10 The calculation scheme 1000 shown by way of example for the scalar j in FIG. 1 is used for calculating the scalars j, k, l.

[0117] The output values ​​r1, r2, and r3 assigned to scalar j are obtained in this order from the sum The output value r1 is arranged row by row starting with its LSB. The subsequent output values ​​are shifted one position further toward the MSB with their LSB in the following row. The output values ​​m1, m2 and m3 assigned to the scalar j are arranged starting from the output value m1, which is relative to the sum The LSB of the sum The MSB of the output is shifted by two bits. The subsequent output values ​​have their LSBs shifted one position further towards the MSB in the following rows. As mentioned above, the sum of the results is calculated column by column.

[0118] In this example, the analog-to-digital converter considering the third row requires a resolution of 2 bits. The analog-to-digital converter not considering the third row requires a resolution of 4 bits.

[0119] Such simulated intermediate sums can be derived at different locations. Fig.11Another division is shown in , in which each intermediate sum is derived. If necessary, the voltage factor can be adapted to the row or can be omitted if it is to be taken into account in the further digital calculation of the intermediate sums.

[0120] Based on the above Fig. 9 The depicted arrangement differs in that only nine memristor arrangements 102 are arranged in a matrix arrangement having a dimension of 3×3. Additionally, an analog-to-digital converter 106 is arranged in a lead-out line between the first and second column of the matrix arrangement 100 .

[0121] The group having the output value indicating the intermediate sum of the third row is represented by [m3, n3, o3], [m2, n2, o2], [m1, n1, o1]. The group having the output value considering the second row but not the first and third rows is represented by [r3, s3, t3], [r2, s2, t2], [r1, s1, t1]. The group having the output value considering only the first row is represented by [u3, u3, u3], [u2, v2, w2], [u1, v1, w1]. Output terminals represented by j, r and u, by k, s and v, and by l, r and w are assigned to the same column line.

[0122] The order of grounding the column lines and applying voltage to the row lines can be chosen so that for each column line current flows through only one tap. The column line at this tap can then be constructed to be continuous without affecting the calculation of the sum current. The column line can be permanently electrically interrupted at the location of the lead-out between the memristor arrangements of the third and second rows to determine the sum current.

[0123] The rest of the process is the same as above, where Fig.12 The calculation scheme 1200 shown by way of example for the scalar j in FIG. 1 is used for calculating the scalars j, k, l.

[0124] When a voltage is applied to the row line, the row voltage is always the same. By presenting the result of the analog-to-digital converter on different bit positions in the register, the previously required factor, in this example 2 or 4, can be achieved.

[0125] The output value between the first and second rows is obtained from the sum The output values ​​of u1 are arranged starting from the LSB of u2. The output values ​​of u2 and u3 are summed up in the following rows. The MSB of is further shifted one position.

[0126] The output values ​​between the second and third rows are arranged starting from the LSB of the output value r1, which is relative to the sum The LSB has been added to the sum The MSB of is shifted by one position. The output values ​​r2 and r3 contribute to the sum in the following rows. The MSB of is further shifted one position.

[0127] The output values ​​after the third row are arranged starting from the LSB of the output value m1, which is the LSB of the output value m1 relative to the sum The LSB has been added to the sum The MSB of M2 and M3 are shifted by two positions in the next row. The MSB of is further shifted one position.

[0128] In the case of the first and third rows, both analog-to-digital converters can even display their results in the same center sum.

[0129] As described above, the summation of the results is performed column by column.

[0130] In this arrangement, only analog-to-digital converters with a resolution of 2 bits are required. These analog-to-digital converters can consist of only two comparators. These analog-to-digital converters can operate in the range of up to GHz.

[0131] Another aspect involves increasing the resolution of the memristor to 2 bits. This means programming multiple states into one memristor. This is taken into account when factoring the matrix similar to the matrix operation described with 1-bit factorization.

[0132] This means that a 2-bit value is represented such that every two bits, in this example bits 0 and 1, bits 2 and 3, .. are grouped together. By replacing the variables in the matrix operation with the following equation

[0133] ,

[0134] get

[0135] .

[0136] Similar to the process of 1-bit decomposition, for a 2-bit matrix we get

[0137]

[0138] .

[0139] Implementing these equation terms as a memristor matrix is ​​also similar to the matrix arrangement 100 for 1-bit matrix operations.

[0140] exist Fig.13 An implementation starting from the description of a matrix arrangement 100 is shown in FIG. Figure 7In particular, the arrangement of the matrices E0, E1, E2 and the factor 2 in the case of input values ​​j1, k1, l1 and the factor 4 in the case of input values ​​j2, k2, l2 is as described above.

[0141] and Figure 7 The arrangement shown is different, in that the varying factors are taken into account before these terms. The output values ​​m1, ... o5 of the three right columns of the matrix used in this example are correspondingly characterized. This arrangement places higher demands on the resolution achieved in the analog-to-digital converter 116.

[0142] As in this example for a 2-bit memristor with Z=4 and Y=1, the required resolution of the analog-to-digital converter 116 is calculated for the value X:

[0143]

[0144] For a matrix of dimension 3×3, with 2-bit memristors and 3-bit input values ​​(ie, only 1 bit per row of the matrix arrangement 100 ), the number of states that the analog-to-digital converter 116 must resolve is 84.

[0145] exist Fig.14 The calculation scheme 1400 shown in FIG. 1 is exemplarily performed by a 12-bit sum for all scalars j, k, l. To account for these changes, the 12-bit sum The first output variable m1, the second output variable m3 and the third output variable m5 are determined. The second output variable m3 is arranged from the LSB of The MSB is shifted by two positions and the LSB is arranged in another row. The third output variable m5 is shifted from the sum The MSB is shifted four positions and the LSB begins to be arranged in another row. The determination is done column by column.

[0146] Use corresponding methods to improve the resolution and input value of the memristor.

[0147] To do this, we have a factor of 2 0 , 2 2 , 2 4 and the vector decomposition with the following substitutions

[0148]

[0149] Change the decomposition used previously to the following:

[0150] .

[0151] Implementing these equations as a memristor matrix is ​​similar to Fig.13 The implementation described is carried out.

[0152] The resulting matrix arrangement 100 is Fig.15 . Unlike the previous implementation, the voltage at the input terminals j1, k1, l1 is now applied using a factor of 4. Unlike the previous implementation, the voltage at the input terminals j2, k2, l2 is now applied using a factor of 16.

[0153] The factors of change in front of these terms result in the resolution requirements for the analog-to-digital converter 116. In a 1-bit matrix with a 1-bit memristor and 3-bit input values, Z=1 and Y=1. In this example, a 2-bit memristor and 6-bit input values ​​(i.e., Z=2 and Y=2) are used to calculate the required resolution of the analog-to-digital converter 116. For the matrix shown in this example with dimensions of 3×3 and with 2-bit memristors and 6-bit input values ​​(these input values ​​have 2 bits per row), the number of states that the analog-to-digital converter 116 must resolve is 1008.

[0154] exist Fig.16 The calculation scheme 1600 shown in FIG. 1 is exemplarily performed for all scalars j, k, l by a 12-bit sum To account for these changes, the 12-bit sum The first output variable m1, the second output variable m3 and the third output variable m5 are determined. The second output variable m3 is arranged from the LSB of The MSB is shifted by two positions and the LSB is arranged in another row. The third output variable m5 is shifted from the sum The MSB is shifted four positions and the LSB begins to be arranged in another row. The determination is done column by column.

[0155] Classical computation of n*n matrices requires n 2 times multiplication and n 2 -n additions. In the case of an 8×8 matrix, this would be 64 multiplications and 56 additions with 8-bit input values ​​(ie, with a width of 16 bits). This would require approximately 118 clocks.

[0156] The proposed method requires 3*8 shift operations of input values ​​and 8*8 additions of output values ​​and 64 AD conversions with 3-bit resolution. However, through high parallelization, only about 10 clocks are required.

[0157] The method can be applied to matrices of other variables and resolutions.

[0158] In one aspect, a memristor arrangement is provided, wherein two memristors are arranged at the nodes of the rows and columns of the matrix arrangement 100, which two memristors can change in opposite directions in terms of their charge-dependent resistance values. The two memristors can be programmed with the same voltage and with inverted weights at the same time. Thus, two current value calculations can be performed simultaneously. However, one of the two calculations uses inverted weights. As a result, the analog-to-digital converter counts zero, which can be taken into account when interpreting the result or in the algorithm. For example, this redundancy can be used to check the rationality of the result.

Claims

1. A method for implementing matrix operations, characterized in that: For the matrix operation, a first digital result is determined according to a first analog addition by means of a first memristor arrangement, wherein a second digital result is determined according to a second analog addition by means of a second memristor arrangement, and wherein the first digital result and the second digital result are digitally added, wherein a first voltage is applied to a first memristor of the first memristor arrangement, wherein a second voltage is applied to a second memristor of the first memristor arrangement at least partially overlapping in time therewith, wherein a first sum current is detected at a first output of the first memristor arrangement, the first sum current representing a current flowing through the first memristor and the second memristor, wherein the first voltage is applied to a third memristor of the second memristor arrangement at least partially overlapping in time therewith, wherein the second voltage or a third voltage is applied to a fourth memristor of the second memristor arrangement at least partially overlapping in time therewith, wherein a second sum current is detected at a second output of the second memristor arrangement, the second sum current representing a current flowing through the third memristor and the fourth memristor, wherein the result of the matrix operation is determined according to the first sum current and the second sum current, The first voltage and the second voltage differ by a factor, and the factor is a power of 2.

2. The method according to claim 1, characterized in that The first digital result is determined as a function of a first simulation result, wherein the second digital result is determined as a function of a second simulation result, wherein the simulation results are determined at least partially overlapping in time.

3. The method according to claim 1, characterized in that The first voltage is defined according to a first element of a first matrix, wherein the second voltage is defined according to a second element of the first matrix, wherein a first resistance value of the first memristor is defined according to a first element of the second matrix, wherein a second resistance value of the second memristor is defined according to a second element of the second matrix, and wherein a result of the matrix operation represents a scalar product of the matrices.

4. The method according to claim 3, characterized in that At least one resistance value of the memristor is programmed according to the elements of the second matrix.

5. The method according to any one of claims 3 or 4, characterized in that The resistance values ​​of at least two memristors are defined or programmed according to the elements of the second matrix.

6. The method according to any one of claims 3 to 4, characterized in that A plurality of memristors are arranged in a matrix arrangement, wherein the second matrix or plurality of second matrices define an arrangement of resistance values ​​of the plurality of memristors, and wherein the memristors in the matrix arrangement have resistance values ​​or are programmed with the resistance values, the resistance values ​​in the resistance value arrangement corresponding to their positions in the matrix arrangement in terms of their indexes.

7. The method according to any one of claims 3 to 4, characterized in that At least two groups of memristors have or are programmed with resistance values ​​that are defined based on elements of the same second matrix.

8. The method according to claim 6, characterized in that At least a portion of the memristors in at least two groups of memristors in the matrix arrangement are used to determine the same sum current.

9. The method according to claim 6, characterized in that At least one memristor from one of the at least two groups of memristors in the matrix arrangement is not considered when determining the summed current of the memristors of another group of the at least two groups of memristors.

10. The method according to any one of claims 3 to 4, characterized in that The first voltage is an analog signal generated by a digital-to-analog converter based on a digital signal defined by a first element of the first matrix, and / or the second voltage is an analog signal generated by a digital-to-analog converter based on a digital signal defined by a second element of the first matrix.

11. The method according to any one of claims 3 to 4, characterized in that The factors are defined according to the resolution of the analog-to-digital converter or according to the bit factorization on which the matrix operation is based.

12. The method according to any one of claims 3 to 4, characterized in that The first sum current includes at least a first current and a second current, wherein the first current flows through the first memristor when the first voltage is applied to the first memristor, and wherein the second current flows through the second memristor when the second voltage is applied to the second memristor.

13. The method according to any one of claims 3 to 4, characterized in that The first voltage is applied simultaneously to the first memristor and the third memristor, or the second voltage is applied simultaneously to at least the second memristor and the fourth memristor, wherein a first sum current of currents flowing through the first memristor and the second memristor is detected, wherein a second sum current of currents flowing through the third memristor and the fourth memristor is detected, and wherein a result of the matrix operation is determined based on the first sum current and the second sum current.

14. The method according to any one of claims 1 to 4, characterized in that A digital signal defining a value of at least one bit is determined by an analog-to-digital converter from the sum current.

15. The method according to any one of claims 1 to 4, characterized in that A plurality of sum currents are determined, wherein a plurality of bits are determined from the plurality of sum currents, wherein at least one bit defined from one of the sum currents is added to at least one bit defined from another of the sum currents.

16. The method according to claim 15, characterized in that At least one bit in a register is arranged shifted relative to the least significant bit of the result of the matrix operation towards the most significant bit of the result of the matrix operation before being added to another bit from another register.

17. The method according to claim 15, characterized in that At least one bit in the register is arranged adjacent to another bit from another register with respect to the least significant bit of the result of the matrix operation before being added to the other bit.

18. The method according to any one of claims 3 to 4, characterized in that A plurality of memristors are arranged in a matrix arrangement, wherein the second matrix or plurality of second matrices define an arrangement of resistance values ​​of the plurality of memristors, and wherein the memristors in the matrix arrangement have resistance values ​​or are programmed with resistance values, the resistance values ​​in the resistance value arrangement corresponding to their positions in the matrix arrangement in terms of their indexes.

19. A device for implementing matrix operations, characterized in that: The device comprises a first memristor arrangement and a second memristor arrangement, wherein the device comprises a first analog-to-digital converter and a second analog-to-digital converter, and wherein the device is configured to determine, for a matrix operation, a first digital result from a first analog addition performed by means of the first memristor arrangement and the first analog-to-digital converter, and to determine a second digital result from a second analog addition performed by means of the second memristor arrangement and the second analog-to-digital converter, wherein a first voltage can be applied to a first memristor of the first memristor arrangement, wherein a second voltage can be applied to a second memristor of the first memristor arrangement at least partially overlapping in time, wherein a first total current can be detected at a first output of the first memristor arrangement, the first total current representing a current flowing through the first memristor and the second memristor, wherein the first voltage can be applied to a third memristor of the second memristor arrangement at least partially overlapping in time, wherein the second voltage can be applied to a fourth memristor of the second memristor arrangement at least partially overlapping in time, wherein a second total current can be detected at a second output of the second memristor arrangement, the second total current representing a current flowing through the third memristor and the fourth memristor, The first voltage and the second voltage differ by a factor, and the factor is a power of 2.

20. The device according to claim 19, characterized in that A plurality of memristors are arranged to form a matrix arrangement.

21. The device according to any one of claims 19 to 20, characterized in that The first and second analog-to-digital converters are designed to detect information about at least one sum current.

22. The device according to any one of claims 19 to 20, characterized in that The apparatus includes a first analog-to-digital converter for generating the first voltage and a second analog-to-digital converter for generating the second voltage.

23. The device according to claim 20, characterized in that The device provides a memristor arrangement in which two memristors are arranged at nodes of rows and columns of the matrix arrangement, the two memristors being variable in opposite directions with respect to their charge-dependent resistance value.

24. A device, characterized in that The device comprises a microprocessor, a switching device and a memory having registers which are designed to control the device according to one of claims 19 to 23 in the method according to one of claims 1 to 18 .

25. A computer program product comprising instructions which, when executed by means of a computer, cause the computer to perform the method according to any one of claims 1 to 18.

26. A machine-readable storage medium having stored thereon the computer program product according to claim 25.

Images