Method and circuit for checking the quality of metallization of a multilayer printed circuit

Abstract

The invention relates to a multilayer printed circuit (1), comprising a test circuit (1a) comprising n through holes (3), the n through holes (3) being connected in series between a first electrical terminal (4a) and a second electrical terminal (4b) so that an applied current at least partially flows through each of the n through holes (3). The test circuit (1a) comprises trace segments (20a to 23a; 20b to 23b) in each layer (10 to 13), each of the n through holes (3) connecting a trace segment of one layer to a trace segment of another layer. The test circuit (1a) comprises: a measuring device (6) for measuring a potential difference at its terminals; a storage device for storing a threshold value; and a comparison device for comparing the potential difference with the threshold value to verify that the printed circuit (1) is valid when the potential difference is below the threshold value.

Description

Technical Field

[0001] The invention relates to a method for checking the quality of the metallization of a multilayer printed circuit, said multilayer comprising an upper layer and a lower layer sandwiching at least one intermediate layer. Background Art

[0002] Previously, the common tests used to check the quality of the metallization of printed circuits included an electrical continuity test, which enabled the detection of possible discontinuity defects of the formed tracks.Such inspection tests therefore enabled the effective detection of surface defects of the metallization layer.

[0003] In contrast, these common tests do not provide any information about the thickness of the deposited metallization layer, although this manufacturing parameter also presents considerable importance.

[0004] To avoid this, document FR-A-2 892 595 discloses a method for checking the thickness of the metallization of a printed circuit, which enables a systematic and rapid check of a produced printed circuit comprising superimposed upper and lower layers.

[0005] The method foresees producing a test circuit comprising n through-holes, called vias, where n is an integer greater than or equal to 2. On the one hand, these vias are provided with an inner peripheral wall suitable for being covered with a metal profile during a metallization step of the printed circuit.

[0006] On the other hand, the through holes are electrically connected in series between two electrical terminals so that a current applied between the electrical terminals flows through each through hole in the height direction thereof.

[0007] The inspection circuit constitutes a reduced-size mirror image of the printed circuit, making it possible to provide information representative of the thickness of the metallization layer formed on the printed circuit.

[0008] A current of a defined intensity is then applied between two electrical terminals of the test circuit and the corresponding potential difference between the electrical terminals is measured.

[0009] The measured value is then compared with a threshold value representative of the potential difference, obtained for a metallization layer with a predetermined minimum thickness deposited on the peripheral wall of each hole, in order to validate the printed circuit when the measured value is below the threshold value.

[0010] This verification is validly related to the thickness of the metallized traces present on the upper and lower layers and the metallized holes electrically connecting them. The document fails to indicate or suggest how to check the thickness of the metallized traces of one or more intermediate layers inserted between the upper and lower layers and the perforation of the metallized holes on each layer and the positioning of the metal outline of the holes relative to the traces of each layer, the perforations must be centered relative to their metal outlines surrounding them.

[0011] Therefore, for a printed circuit having an upper layer and a lower layer and at least one intermediate layer inserted between the upper layer and the lower layer, the problem on which the invention is based is to carry out non-destructive testing of the printed circuit, said non-destructive testing not only concerning the holes and the metallization of the outer layers, but also concerning the nominal thickness of the conductive material forming the tracks of one or more internal intermediate layers, the centering of the perforation of the holes relative to its metallization that surrounds them, and the positioning of the metallized holes relative to the internal tracks of each layer. Summary of the invention

[0012] To this end, the invention relates to a method for checking the quality of the metallization of a multilayer printed circuit, said multilayer comprising an upper layer and a lower layer sandwiching at least one intermediate layer, each layer having tracks made of conductive material and through-going holes, called vias, provided with inner peripheral walls suitable for being covered with a metal profile during a metallization step of the printed circuit, said method comprising:

[0013] • producing an inspection circuit comprising n through-holes, wherein n is an integer greater than or equal to 3, said n through-holes being electrically connected in series between two electrical terminals so that a current applied between said electrical terminals flows at least partially through each of the n through-holes in a height direction thereof,

[0014] • Applying a current of a certain intensity between the two electrical terminals of the circuit under test,

[0015] • measure the corresponding potential difference, and

[0016] • Compare the measured value with a threshold value representing the potential difference to verify that the printed circuit is valid if the measured value is below the threshold value,

[0017] It is worth noting that the inspection circuit is configured to pass through at least one trace segment of each layer of the printed circuit, each of the n through holes connects a trace segment of one layer to a trace segment of another layer, and the threshold value represents the potential difference obtained for the following situations:

[0018] • the n through-holes of the inspection circuit are provided with a metal profile having a predetermined minimum thickness, which is deposited on the peripheral wall of each through-hole between the two layers to which the through-hole connects,

[0019] • The metal outline on each layer is aligned with the trace segments on that layer, and

[0020] • Check that trace segments on each layer of the circuit have minimum metallization thickness.

[0021] The technical effect achieved by the invention is to check the entire production quality of the printed circuit with one overall single measurement.

[0022] The new pattern of the inspection circuit consists in combining the old pattern proposed by the closest prior art exemplified by FR-A-2 892 595, passing through all layers simultaneously, both outer layers as upper and lower layers and inner layer(s) as intermediate layer(s).

[0023] The inspection circuit passes through all layers and each trace segment of each layer is made of a metallic material such as copper, advantageously by allocating the number of connections in proportion to the thickness of the metallic material.

[0024] In addition to detecting excessive metallization defects on the outside of the printed circuit (i.e., the upper and lower layers) and metallization defects in the through-holes (which can also be done in the closest prior art), the present invention also makes it possible to detect insufficient thickness of the metallization of one or more intermediate layers and misalignment of the through-holes relative to the trace segments to which they should be connected.

[0025] Misalignment of the perforations in the vias can result in increased resistance of the inspection circuit because the metal outline or pastille surrounding the perforations no longer has the same metallization geometry to conduct current through the inspection circuit.

[0026] The method according to the invention thus extends the inspection method according to the closest prior art to multilayer printed circuits by adapting it.

[0027] Advantageously, the number of trace segments of the inspection circuit on the same layer of the printed circuit is selected according to the nominal metallization thickness of the traces on said layer. This enables the inspection circuit to be representative for inspecting thickness differences of the metallization on the various layers.

[0028] Advantageously, the layer is in the shape of a rectangular plane and has a width and a length, and the trace segments of the inspection circuit on the same layer are divided into trace segments extending along the width of the layer and trace segments extending along the length.

[0029] The perforations opened in their wafers forming the associated metal outlines enclosing the perforations may be offset, resulting in an offset between the vias and the trace segments on a given layer, which offset may occur mainly in two dimensions of the layer and cause the overall resistance of the pattern to rise. Such offsets in width and / or length can be effectively checked by the method for checking the quality of metallization of printed circuits according to the present invention.

[0030] The present invention also relates to a printed circuit, which includes an upper layer and a lower layer sandwiching at least one intermediate layer, each layer having a trace made of a conductive material and a through hole called a through hole, the through hole being provided with an inner peripheral wall covered with a metal outline, and it is noteworthy that the printed circuit includes an inspection circuit for implementing such an inspection method, the inspection circuit includes n through holes, the n through holes are electrically connected in series between a first and a second electrical terminal, so that a current applied between these electrical terminals flows at least partially through each of the n through holes along its height direction, the inspection circuit includes a trace segment in each layer of the printed circuit, each of the n through holes connects a trace segment of one layer to a trace segment of another layer, and the inspection circuit includes: a measuring device for measuring a potential difference at its terminals; a storage device for storing a threshold value; and a comparison device for comparing the measured potential difference with the threshold value to confirm that the printed circuit is valid when the measured potential difference is lower than the threshold value.

[0031] The inspection circuit passes locally through each layer to inspect the metallization of the through-holes and their connections to the trace segments present on each layer as well as the metal thickness of each trace segment in order to establish a complete qualified diagnostic of the printed circuit.

[0032] Advantageously, the printed circuit comprises at least four superposed layers, the inspection circuit comprises a number n of through-holes at least equal to 30, wherein there are 8 trace segments on the upper layer, 9 trace segments on the lower layer, 6 trace segments on the first intermediate layer and 6 trace segments on the second intermediate layer, the metallization thickness of the trace segments of the upper and lower layers is equal, and the minimum metallization thickness of the trace segments of the first and second intermediate layers is equal and 35% to 65% smaller than the metallization thickness of the trace segments of the upper and lower layers.

[0033] The number of trace segments on one layer forming part of the inspection circuit compared to the number of trace segments on one layer takes into account the ratio of the metallization thickness between the two layers.

[0034] Advantageously, for the upper layer: 4 trace segments extend along the width of the upper layer and 4 trace segments extend along the length; for the first intermediate layer starting from the upper layer: 3 trace segments extend along the width of the first intermediate layer and 3 trace segments extend along the length; for the second intermediate layer starting from the upper layer: 3 trace segments extend along the width of the second intermediate layer and 3 trace segments extend along the length; and for the lower layer: 6 trace segments extend along the width of the lower layer and 3 trace segments extend along the length.

[0035] Advantageously, the first electrical terminal is constituted by two conductive contacts connected to each other by conductive traces, and one of the contacts is connected to a first through-hole among the n through-holes by a conductive trace, and the second electrical terminal is constituted by two conductive contacts connected to each other by conductive traces, and one of the contacts is connected to a last through-hole among the n through-holes by a conductive trace, the first electrical terminal and the second electrical terminal being carried by an upper layer of the printed circuit.

[0036] Advantageously, the n through-holes of the inspection circuit each have a diameter equal to the smallest diameter of the other through-holes of the printed circuit.

[0037] Advantageously, the trace segments of the inspection circuit on each layer have a thickness equal to the thickness of the traces extending on said layer.

[0038] Advantageously, the test circuit is integrated in a functional part of the printed circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Other characteristics, objectives and advantages of the present invention will become apparent from a reading of the following detailed description taken in light of the accompanying drawings, which are given by way of non-limiting examples and in which:

[0040] - Figure 1 is a schematic representation of a view of a multilayer printed circuit provided with an inspection circuit according to one embodiment of the invention, the layers being shown placed next to each other so as to be visible, rather than being superimposed as in the final printed circuit,

[0041] - Figure 2 is a schematic representation of a top view of an inspection circuit for inspecting a multilayer printed circuit according to one embodiment of the invention, so that in this figure the traces present on the various superimposed layers can be seen and these traces are identified relative to the layers carrying them,

[0042] - Figure 3 is a schematic representation of a cross-sectional view of an inspection circuit for inspecting a multilayer printed circuit according to one embodiment of the invention, in which figure it is possible to see metallized through-holes extending in the thickness direction of the printed circuit, and trace segments present on the various layers forming part of the inspection circuit at this cross-section,

[0043] - Figure 4 The possible eccentricity of a metallized hole forming a through-hole relative to its metal contour surrounding it and to a trace segment joined to the metallized hole at one layer of a printed circuit in two dimensions, respectively, in the lateral and longitudinal directions, which eccentricity may render the printed circuit unqualified, is shown and is detected by implementing an inspection method according to the invention for inspecting the quality of metallization of multilayer printed circuits. DETAILED DESCRIPTION

[0044] exist Figure 1 and Figure 2 In the drawings, in each layer of the printed circuit, only one metallized hole or through-hole is marked as 3, and only one trace segment extending along the length and only one trace segment extending along the width are marked as 20a, 20b; 21a, 21b; 22a, 22b; and 23a, 23b, respectively, according to the layer of the printed circuit carrying the trace segment, but the content described for one marked element is described for all unmarked elements of the same type.

[0045] Reference is made to all drawings and primarily to Figure 1 and Figure 2 The invention relates to a method for checking the quality of the metallization of a printed circuit 1 having a plurality of layers 10 to 13 comprising an upper layer 10 and a lower layer 13 sandwiching at least one intermediate layer 11 , 12 .

[0046] exist Figure 1 and Figure 2 In FIG. 1 , a printed circuit 1 is shown, which includes four layers 10 to 13, wherein the upper layer 10 and the lower layer 13 sandwich at least the first intermediate layer 11 and the second intermediate layer 12. This is not restrictive, and the printed circuit 1 may also include 3 layers, and more than four layers.

[0047] Each layer 10 to 13 has a track made of conductive material and a through-hole, called via 3, provided with an inner peripheral wall which is metallized during a metallization step of the printed circuit 1 so as to have the metallic outline of the via.

[0048] The method comprises producing a test circuit 1a comprising n through-holes 3, wherein n is an integer greater than or equal to 3, the n through-holes 3 being electrically connected in series between two electrical terminals 4a, 4b, so that a current applied between the electrical terminals 4a, 4b flows at least partially through each of the n through-holes 3 in the height direction thereof.

[0049] “At least partially” means that some of the through holes 3 are passed through by current from the upper layer 10 or the lower layer 13 to the first intermediate layer 11 or the second intermediate layer 12 (or vice versa), while other through holes 3 are completely passed through by current from the upper layer 10 to the lower layer 13 (or vice versa).

[0050] The method proposes applying a current of a predetermined intensity between the two electrical terminals 4a, 4b of the test circuit 1a. Figure 1 4 , which is shown by a voltage generator connected to the electrical terminals 4 a , 4 b of the test circuit 1 a , one electrical connection of which is referenced 7 .

[0051] Then, the respective potential difference across the electrical terminals 4a, 4b of the test circuit 1a is measured at 6 and a comparison is made between the measured voltage value and a threshold representing the potential difference, so that the printed circuit 1 is verified to be valid when the measured value is below the threshold.

[0052] What may cause the printed circuit 1 to fail is firstly an insufficient thickness of the conductive material, in particular copper, of the tracks on at least one of the layers 10 to 13 of the printed circuit 1, which may be one or more of the upper layer 10, the lower layer 13, the intermediate layers 11 or 12. The inspection method according to the closest prior art does not allow the thickness of the conductive material of one or more intermediate layers 11, 12 to be verified.

[0053] Special reference Figure 4 In conjunction with other figures, the second factor that may cause the printed circuit 1 to fail is poor alignment of the metallized holes in its metal profile or the metallized disc made of conductive material, and the perforation 3b must penetrate the metal profile or disc in the middle area of ​​the metal profile or metallized disc 3a. Poor alignment increases the resistance of the inspection circuit 1a and makes it possible to identify that the printed circuit 1 is unqualified.

[0054] Still specifically referring to Figure 4 Combined with Figure 1 and Figure 2 , what may cause the printed circuit 1 to fail is again insufficient electrical connection between the through hole 3 and the trace segments 20a to 23a; 20b to 23b present on one of the layers 10 to 13, which increases the resistance of the inspection circuit 1a and makes it possible to identify that the printed circuit 1 is failed.

[0055] As we will see below, especially in Figure 1 In the example, one or more trace segments 20a to 23a; 20b to 23b on each of the layers 10 to 13 may extend along the width or length of the layers 10 to 13. An offset of the perforation in one or both of these directions relative to the associated trace segment 20a to 23a; 20b to 23b may increase the resistance of the inspection circuit 1a and enable detection of a failure of the printed circuit 1.

[0056] exist Figure 4 In FIG. 1 , the offset of the through hole 3 along the length and along the width are marked as Δx and Δy, respectively. Figure 4 , the trace segments extending along the length and width are labeled 20a and 20b as they exist on the upper layer 10 of the printed circuit 1, but this is not restrictive and may relate to the trace segments 20a to 23a; 20b to 23b of all layers 10 to 13 of the printed circuit 1.

[0057] Thus, the inspection circuit 1a can use part of the through holes 3 of the printed circuit 1 to test the nonconformity of the printed circuit 1. When at least one of the above defects of one or more through holes 3 of the inspection circuit 1a is detected, it can be determined that the defect or defects also affect one or more through holes 3 of the printed circuit 1.

[0058] Generally speaking, alignment defects of perforations 3a in the wafer or metal outline 3b of via 3 or electrical connection defects with the trace segments will also concern other vias 3 of printed circuit 1, since perforations are performed simultaneously and correspondingly to each other.

[0059] More specifically with reference to Figures 1 to 3 , in order to implement the method according to the invention, the inspection circuit 1a is configured to pass through at least one trace segment 20a to 23a; 20b to 23b of each of the layers 10 to 13 of the printed circuit 1. Each of the n through-holes 3 connects one trace segment 20a to 23a; 20b to 23b of one layer 10 to 13 to one trace segment 20a to 23a; 20b to 23b of another layer 10 to 13.

[0060] The threshold value for determining whether the printed circuit 1 is qualified represents the potential difference obtained for the following situations: the n through holes 3 of the inspection circuit 1a are provided with a metal profile having a predetermined minimum thickness, and the metal profile is deposited on the peripheral wall of each through hole 3 between the two layers 10 to 13 connected to the through hole 3; the metal profile located on each layer 10 to 13 is aligned with the trace segments 20a to 23a; 20b to 23b on the layer; and the trace segments on each of the layers 10 to 13 of the inspection circuit 1a have a minimum metallization thickness.

[0061] Too small a thickness or misalignment of the wafer or metal outline of the through hole 3 or of the trace segments 20a to 23a; 20b to 23b will increase the resistance of the inspection circuit 1a measuring the voltage across it and enable the printed circuit 1 to be detected as defective.

[0062] It is advisable to carry out a preliminary calibration step consisting in transcribing the potential differences measured for a layer 10 to 13 of a given thickness deposited inside the through-hole 3 of the prototype check circuit 1a. Subsequently, once this calibration step has been carried out, the method according to the invention makes it possible to systematically check all printed circuits 1 having a plurality of layers 10 to 13 directly on the production line in a very short time, and thus to detect all parts having metallization defects, i.e. those parts whose metallization layer thickness is less than the required thickness, or whose through-hole 3 is poorly aligned in its wafer perforation, or whose through-hole 3 is poorly aligned with its trace segment 20a to 23a; 20b to 23b.

[0063] The number of trace segments 20a to 23a; 20b to 23b of the inspection circuit 1a on the same layer 10 to 13 of the printed circuit 1 can be selected according to the nominal metallization thickness of the traces on said layers 10 to 13. Without limitation, the upper layer 10 and the lower layer 13 can have a metallization thickness of 60 microns, while the intermediate layers 11, 12 or the first and second intermediate layers 11, 12 can have a metallization thickness of 35 microns.

[0064] The layers 10 to 13 may be in the shape of a rectangular plane and have a width and a length, advantageously on a board, through-holes 3 extending along the thickness of the printed circuit 1 , through-holes 3 through which current flows, this current coming from a feed circuit, one electrical connection of which is marked 7 .

[0065] The trace segments 20a to 23a; 20b to 23b of the inspection circuit 1a on the same layer 10 to 13 can be divided into trace segments 20a to 23a extending along the width of the layer 10 to 13 and trace segments 20b to 23b extending along the length. Figure 1 and Figure 2 Visible in.

[0066] exist Figure 3 In the embodiment, the inspection circuit 1 a passes through the first through hole 3 from the upper layer 10 to the lower layer 13 , and then passes through the second through hole 3 from the lower layer 13 to the first intermediate layer 11 closest to the upper layer 10 among the two intermediate layers 10 to 13 .

[0067] Next, the inspection circuit 1a is passed from the first intermediate layer 11 to the second intermediate layer 12 through the third through hole 3, then from the second intermediate layer 12 to the upper layer 10 through the fourth through hole 3, and finally from the upper layer 10 to the lower layer 13 of the printed circuit 1 through the fifth through hole 3. Thus, all layers 10 to 13 of the printed circuit 1 are tested, but not all through holes 3 are tested, and only the number n of through holes 3 are tested.

[0068] Especially refer to Figures 1 to 3 The invention also relates to a printed circuit 1 comprising an upper layer 10 and a lower layer 13 sandwiching at least one intermediate layer 11, 12, each layer 10 to 13 having traces made of conductive material and through-holes called through-holes 3 provided with inner peripheral walls covered with a metal profile.

[0069] According to the present invention, the printed circuit 1 comprises an inspection circuit 1a, which implements the inspection method as described above, and the inspection circuit 1a comprises n through-holes 3 electrically connected in series between a first electrical terminal 4a and a second electrical terminal 4b, so that a current applied between the electrical terminals 4a, 4b flows at least partially through each of the n through-holes 3 along the height direction thereof, n being at least equal to 3.

[0070] The inspection circuit 1a includes trace segments 20a to 23a; 20b to 23b in each of the layers 10 to 13 of the printed circuit 1, and each of the n through holes 3 connects a trace segment 20a to 23a; 20b to 23b of one layer 10 to 13 to a trace segment 20a to 23a; 20b to 23b of another layer 10 to 13.

[0071] The check circuit 1a comprises measuring means 6 for measuring the potential difference V at its terminals, storage means for storing a threshold value, and comparison means for comparing the measured potential difference with the threshold value to verify that the printed circuit 1 is valid when the measured potential difference is below the threshold value.

[0072] The check circuit 1 a may be implemented on a portion of the functional surface of each printed circuit 1 produced or on a process tape such as that which ensures the mechanical coupling of the printed circuit during its production.

[0073] More specifically with reference to Figure 1 and Figure 2 , the printed circuit 1 may include at least four superposed layers 10 to 13. Figure 2 In FIG. 1 , the trace segments without special marks 20a, 20b are trace segments existing on the upper layer 10 of the printed circuit 1, and the trace segments with points 23a, 23b are trace segments existing on the lower layer 13 of the printed circuit 1. Figure 1 In the diagram, the special mark of each of the layers 10 to 13 is decorated with a small square.

[0074] The grid-shaped trace segments 21 a , 21 b are trace segments present on the first intermediate layer 11 of the printed circuit 1 , and the shaded trace segments 22 a , 22 b are trace segments present on the second intermediate layer 12 of the printed circuit 1 .

[0075] The inspection circuit 1a may include n through holes 3, which is at least equal to 30, 8 trace segments 20a, 20b on the upper layer 10, 9 trace segments 23a, 23b on the lower layer 13, 6 trace segments 21a, 21b on the first intermediate layer 11, and 6 trace segments 22a, 22b on the second intermediate layer 12, and the total number of trace segments is 1 less than the number of through holes 3.

[0076] The metallization thickness of the trace segments 20a, 20b; 23a, 23b of the upper layer 10 and the lower layer 13 can be equal, and the minimum metallization thickness of the trace segments 21a, 21b; 22a, 22b of the first and second intermediate layers 11, 12 can also be equal and 35% to 65% smaller than the metallization thickness of the trace segments of the upper layer 10 and the lower layer 13.

[0077] More specifically with reference to Figure 1, the upper layer 10 may include 4 trace segments 20a extending along the width of the upper layer 10 and 4 trace segments 20b extending along the length. The first intermediate layer 11 as the first intermediate layer starting from the upper layer 10 may include 3 trace segments 21a extending along the width of the first intermediate layer 11 and 3 trace segments 21b extending along the length.

[0078] The second intermediate layer 12, which is the second intermediate layer from the upper layer 10, may include three trace segments 22a extending along the width of the second intermediate layer 12 and three trace segments 22b extending along the length. Finally, the lower layer 13 may include six trace segments 23a extending along the width of the lower layer 13 and three trace segments 23b extending along the length.

[0079] For a printed circuit 1 having four layers 10 to 13, the above description is given in principle and in particular in Figure 2 The pattern shown in FIG. 1 can be extended to more layers, such as 6 or 8 layers, or even more. When the number of layers of the printed circuit 1 changes, the inspection circuit 1a is redefined to pass through all layers equally to achieve test coverage.

[0080] As especially in Figure 1 and Figure 2 As can be seen in FIG. 4 , the first electrical terminal 4a may be constituted by two conducting contacts 4a, 5a connected to each other by a conducting track, and thus one of the contacts is connected to a first of the n through-holes 3 by a conducting track.

[0081] Similarly, the second electrical terminal 4b may consist of two conducting contacts 4b, 5b connected to each other by a conducting trace, and thus one of the contacts 5b is connected to the last of the n through-holes 3 by a conducting trace.

[0082] The first and second electrical terminals 4a, 4b of the feed circuit 7 connected to the outside of the printed circuit 1 can be carried by the upper layer 10 of the printed circuit 1, but this is not restrictive. The first and second electrical terminals 4a, 4b can be carried by the lower layer 13 of the printed circuit 1, which is preferably carried by one or more of the intermediate layers 10 to 13.

[0083] The n through-holes 3 of the inspection circuit 1a may each have a diameter equal to the smallest diameter of the other through-holes 3 of the printed circuit 1. This enables the resistance of the inspection circuit 1a to be aligned to the highest resistance obtained in the printed circuit 1. However, in general, all through-holes 3 of the printed circuit 1 have the same diameter.

[0084] The track segments 20a to 23a; 20b to 23b of the check circuit 1a on each layer 10 to 13 may have a thickness equal to the thickness of the tracks extending on said layers 10 to 13. This is the case when the check circuit 1a is integrated in a functional part of the printed circuit 1.

[0085] The invention can be applied to any printed circuit 1, in particular a printed circuit board 1, having connecting through-holes 3, but can also be applied to substrates other than substrates for printed circuit boards. It is also possible to use SMI technology, i.e. a substrate made of plastic or another insulator, with copper tracks connected to each other by metallized through-holes 3.

Claims

1. A method for checking the quality of the metallization of a multilayer (10 to 13) printed circuit (1), said multilayer (10 to 13) comprising an upper layer (10) and a lower layer (13) sandwiching at least one intermediate layer (11, 12), each layer (10 to 13) having a track made of conductive material and a through hole called a through hole (3), said through hole (3) being provided with an inner peripheral wall suitable for being covered with a metal profile during a metallization step of the printed circuit (1), said method comprising: producing an inspection circuit (1a) comprising n through holes (3), wherein n is an integer greater than or equal to 3, the n through holes (3) being electrically connected in series between two electrical terminals (4a, 4b), so that a current applied between the electrical terminals (4a, 4b) at least partially flows through each of the n through holes (3) in the height direction thereof, applying an electric current of a determined intensity between two electrical terminals (4a, 4b) of the test circuit (1a), · measure the corresponding potential difference, and comparing the measured value with a threshold value representing the potential difference to verify that the printed circuit (1) is valid when the measured value is below the threshold value, The invention is characterized in that the inspection circuit (1a) is configured to pass through at least one trace segment (20a to 23a; 20b to 23b) of each layer (10 to 13) of the printed circuit (1), each of the n through holes (3) connects a trace segment (20a to 23a; 20b to 23b) of one layer (10 to 13) to a trace segment (20a to 23a; 20b to 23b) of another layer, and the threshold value represents the potential difference obtained for the following situations: The n through holes (3) of the inspection circuit (1a) are provided with a metal profile having a predetermined minimum thickness, which is deposited on the peripheral wall of each through hole (3) between the two layers (10 to 13) to which the through hole (3) is connected, The metal outline on each layer (10 to 13) is aligned with the trace segments (20a to 23a; 20b to 23b) on that layer (10 to 13), and · The trace segments on each layer (10 to 13) of the inspection circuit (1a) have a minimum metallization thickness, The printed circuit (1) comprises at least three superimposed layers, including an upper layer, a lower layer and a middle layer.

2. The method according to claim 1, characterized in that The number of trace segments (20a to 23a; 20b to 23b) of the inspection circuit (1a) on the same layer (10 to 13) of the printed circuit (1) is selected according to the nominal metallization thickness of the traces on said layer (10 to 13).

3. The method according to claim 1 or 2, characterized in that: The layers (10 to 13) are in the shape of a rectangular plane and have a width and a length, and the trace segments (20a to 23a; 20b to 23b) of the inspection circuit (1a) on the same layer (10 to 13) are divided into trace segments (20a to 23a) extending along the width of the layer (10 to 13) and trace segments (20b to 23b) extending along the length.

4. A printed circuit (1) comprising an upper layer (10) and a lower layer (13) sandwiching at least one intermediate layer (11, 12), each layer (10 to 13) having a track made of a conductive material and a through hole called a through hole (3) provided with an inner peripheral wall covered with a metal profile, characterized in that A printed circuit (1) comprising an inspection circuit (1a) for implementing the method for inspection according to any one of the preceding claims, the inspection circuit (1a) comprising n through holes (3), the n through holes (3) being electrically connected in series between a first electrical terminal (4a) and a second electrical terminal (4b), so that a current applied between these electrical terminals (4a, 4b) flows at least partially through each of the n through holes (3) in the height direction thereof, the inspection circuit (1a) comprising trace segments (20a to 23a; 20b to 23b) in each layer (10 to 13) of the printed circuit (1), each of the n through holes (3) connecting one trace segment (20a to 23a; 20b to 23b) of one layer (10 to 13) to one trace segment (20a to 23a) of another layer; 20b to 23b), the inspection circuit (1a) comprises: a measuring device (6) for measuring the potential difference at its terminals (4a, 4b); a storage device for storing a threshold value; and a comparison device for comparing the measured potential difference with the threshold value to confirm that the printed circuit (1) is valid when the measured potential difference is lower than the threshold value.

5. The printed circuit (1) according to claim 4, characterized in that It comprises at least four superposed layers (10 to 13), the inspection circuit (1a) comprising a number n of through holes (3) of at least 30, wherein there are 8 trace segments (20a, 20b) on the upper layer (10), 9 trace segments (23a, 23b) on the lower layer (13), 6 trace segments (21a, 21b) on the first intermediate layer (11) and 6 trace segments (22a; 22b) on the second intermediate layer (12). b), the metallization thickness of the trace segments (20a, 20b; 23a, 23b) of the upper layer (10) and the lower layer (13) is equal, and the minimum metallization thickness of the trace segments (21a, 21b; 22a, 22b) of the first and second intermediate layers (11, 12) is equal and is 35% to 65% smaller than the metallization thickness of the trace segments (20a, 20b; 23a, 23b) of the upper layer (10) and the lower layer (13).

6. The printed circuit (1) according to claim 5, characterized in that For the upper layer (10): 4 trace segments (20a) extend along the width of the upper layer (10) and 4 trace segments (20b) extend along the length; for the first intermediate layer (11) starting from the upper layer (10): 3 trace segments (21a) extend along the width of the first intermediate layer (11) and 3 trace segments (21b) extend along the length; for the second intermediate layer (12) starting from the upper layer (10): 3 trace segments (22a) extend along the width of the second intermediate layer (12) and 3 trace segments (22b) extend along the length; and for the lower layer (13): 6 trace segments (23a) extend along the width of the lower layer (13) and 3 trace segments (23b) extend along the length.

7. The printed circuit (1) according to any one of claims 4 to 6, characterized in that The first electrical terminal (4a) is composed of two conductive contacts (4a, 5a) connected to each other by a conductive trace, and one of the contacts (5a) is connected to the first through-hole among the n through-holes (3) by the conductive trace, and the second electrical terminal (4b) is composed of two conductive contacts (4b, 5b) connected to each other by a conductive trace, and one of the contacts (5b) is connected to the last through-hole among the n through-holes (3) by the conductive trace, and the first and second electrical terminals (4a, 4b) are carried by an upper layer (10) of the printed circuit (1).

8. The printed circuit (1) according to any one of claims 4 to 6, characterized in that Each of the n through holes (3) of the inspection circuit (1a) has a diameter equal to the smallest diameter of the other through holes (3) of the printed circuit (1).

9. The printed circuit (1) according to any one of claims 4 to 6, characterized in that The trace segments (20a to 23a; 20b to 23b) of the inspection circuit (1a) on each layer (10 to 13) have a thickness equal to the thickness of the trace extending on the layer (10 to 13).

10. The printed circuit (1) according to any one of claims 4 to 6, characterized in that The test circuit (1a) is integrated in the functional part of the printed circuit (1).

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