Semiconductor structure and method for manufacturing the same

Abstract

The present invention relates to a semiconductor structure and a preparation method thereof; comprising: a support layer, including a pad region; a plurality of grooves formed in the pad region of the support layer; a pad located on the support layer and at least located in the pad region, wherein the pad is partially embedded in the groove. In the semiconductor structure, a support layer having a plurality of grooves in the pad region is formed below the pad. During the wire bonding process, even if the pad is flat and most of the pads will be squeezed out under the action of the bonding pressure, a portion of the bottom of the wire will sink into the groove because there is a support layer with grooves below the pad, so that the contact surface between the wire and the pad is uneven, thereby increasing the adhesion between the wire and the pad and reducing the risk of the wire falling off.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor device manufacturing, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] In the existing process, when the wire bonding process is performed on the pad, in order to increase the adhesion between the wire and the pad, the surface of the pad needs to be roughened before the wire bonding process; then, since the pad is generally made of aluminum with a relatively soft hardness, the pad will be quickly flattened under the action of the bonding force during the wire bonding process, causing the rough surface to fail and failing to achieve the effect of enhancing the adhesion between the wire and the pad. At the same time, since the wire flattens the pad below it, the current can only flow from the areas on both sides of the wire during operation, which will cause a significant reduction in the current during operation; and if the opening in the protective layer is too small or the wire is crooked, causing the wire to approach the protective layer, the pad layer below, which is extruded and discharged outward, will lift or crack the protective layer upwards, or cause the pad to overflow, thereby causing quality problems. Summary of the invention

[0003] Based on this, it is necessary to provide a semiconductor structure and a method for preparing the same in order to solve the above problems in the prior art.

[0004] In order to achieve the above object, on the one hand, the present invention provides a semiconductor structure, comprising:

[0005] The support layer includes a pad area; the support layer in the pad area has a plurality of grooves;

[0006] A welding pad is located on the support layer and at least in the welding pad area, and the welding pad is partially embedded in the groove.

[0007] In the above-mentioned semiconductor structure, a support layer with several grooves is formed in the pad area below the welding pad. During the wire bonding process, even if the welding pad is flat and most of the welding pads will be squeezed out under the action of the bonding pressure, due to the support layer with grooves under the welding pad, part of the bottom of the welding wire will sink into the groove, making the contact surface between the welding wire and the welding pad uneven, thereby increasing the adhesion between the welding wire and the welding pad and reducing the risk of the welding wire falling off.

[0008] In one embodiment, the support layer is a single-layer structure, the support layer includes a dielectric layer or a polymer layer, and the depth of the groove is less than or equal to the thickness of the support layer.

[0009] In one embodiment, the support layer is a laminated structure, and the support layer includes:

[0010] A first material layer, wherein an initial groove is formed in the first material layer, and a depth of the initial groove is less than or equal to a thickness of the first material layer;

[0011] The second material layer is located on the upper surface of the first material layer, the sidewall of the initial groove and the bottom of the initial groove; the thickness of the second material layer is less than the depth of the initial groove.

[0012] In one embodiment, the support layer is a laminated structure, and the support layer includes:

[0013] a first material layer;

[0014] The second material layer is located on the upper surface of the first material layer. The second material layer has a plurality of grooves therein, and the depth of the grooves is less than or equal to the thickness of the second material layer.

[0015] In one embodiment, the first material layer is a dielectric layer and the second material layer is a polymer layer, or the first material layer is a polymer layer and the second material layer is a dielectric layer.

[0016] In one embodiment, the semiconductor structure further comprises:

[0017] a substrate having an integrated circuit formed therein;

[0018] A passivation layer is located on the upper surface of the substrate; the support layer is located on the upper surface of the passivation layer;

[0019] A redistribution layer, located on the support layer and connected to the integrated circuit and the pad;

[0020] A seed layer, located between the support layer and the pad, between the redistribution layer and the support layer, and between the redistribution layer and the integrated circuit;

[0021] A protective layer, located on the upper surface of the support layer and covering the redistribution layer and the pad; an opening is formed in the protective layer, and the opening exposes the pad;

[0022] A welding wire has one end located in the opening and connected to the welding pad.

[0023] In one example, there is a gap between the bottom of the welding wire and the bottom of the groove. The gap between the bottom of the welding wire and the bottom of the groove allows a welding pad to be retained between the welding wire and the bottom of the groove. During operation, the current can flow through the welding pads in the groove in addition to the welding pads on both sides of the welding wire, thereby increasing the current during operation.

[0024] In one example, a notch is provided in the protective layer at the lower part of the opening, so that the width of the lower part of the opening is greater than the width of the upper part of the opening. By forming a notch in the protective layer at the lower part of the opening, a buffer space can be formed at the lower part of the opening, and the notch can accommodate the solder pads squeezed out by the solder wires, thereby preventing the protective layer from being lifted up or cracked, and preventing the solder pads from overflowing, thereby ensuring the quality of the product.

[0025] The present invention also provides a method for preparing a semiconductor structure, comprising the following steps:

[0026] forming a support layer, wherein the support layer includes a pad region; a plurality of grooves are formed in the pad region of the support layer;

[0027] A welding pad is formed at least in the welding pad area of ​​the support layer, and the welding pad is partially embedded in the groove.

[0028] In the preparation method of the above-mentioned semiconductor structure, a support layer with a plurality of grooves is formed in the pad area below the welding pad. During the wire bonding process, even if the welding pad is flat and most of the welding pads will be squeezed out under the action of the bonding pressure, since there is a support layer with grooves below the welding pad, part of the bottom of the welding wire will sink into the groove, making the contact surface between the welding wire and the welding pad uneven, thereby increasing the adhesion between the welding wire and the welding pad and reducing the risk of the welding wire falling off.

[0029] In one embodiment, forming the support layer comprises the following steps:

[0030] forming a dielectric layer;

[0031] The dielectric layer is etched to form the groove in the dielectric layer, and the depth of the groove is less than or equal to the thickness of the dielectric layer.

[0032] In one embodiment, forming the support layer comprises the following steps:

[0033] forming a polymer layer;

[0034] The polymer layer is exposed and developed to form the groove in the polymer layer, wherein the depth of the groove is less than or equal to the thickness of the polymer layer.

[0035] In one embodiment, forming the support layer comprises the following steps:

[0036] forming a first material layer;

[0037] forming a second material layer on the upper surface of the first material layer;

[0038] The groove is formed in the second material layer, and the depth of the groove is less than or equal to the thickness of the second material layer.

[0039] In one embodiment, forming the support layer comprises the following steps:

[0040] forming a first material layer;

[0041] forming an initial groove in the first material layer, wherein the depth of the initial groove is less than or equal to the thickness of the first material layer;

[0042] A second material layer is formed on the upper surface of the first material layer, the sidewalls and the bottom of the initial groove.

[0043] In one embodiment, the first material layer is a dielectric layer and the second material layer is a polymer layer, or the first material layer is a polymer layer and the second material layer is a dielectric layer.

[0044] In one embodiment, before forming the support layer, the following steps are also included:

[0045] providing a substrate having an integrated circuit formed therein;

[0046] A passivation layer is formed on the upper surface of the substrate; the support layer is formed on the upper surface of the passivation layer;

[0047] Before forming the bonding pad in the groove, the method further includes forming interconnection holes in the support layer and the passivation layer, wherein the interconnection holes expose the integrated circuit region;

[0048] While forming the bonding pad in the pad region of the support layer, a redistribution layer is also formed on the support layer, wherein the redistribution layer is connected to the bonding pad and the integrated circuit;

[0049] Before forming the pad and the redistribution layer, the method further includes forming a seed layer on the upper surface of the support layer and in the interconnection hole; the pad and the redistribution layer are formed on the upper surface of the seed layer;

[0050] After forming the bonding pad in the pad area of ​​the support layer, the following steps are also included:

[0051] forming a protective layer on the upper surface of the support layer, wherein the protective layer covers the redistribution layer and the pad;

[0052] forming an opening in the protective layer, wherein the opening exposes the welding pad;

[0053] A welding wire is provided, and one end of the welding wire is connected to the welding pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 A flowchart of a method for preparing a semiconductor structure according to an embodiment of the present invention;

[0055] Figures 2 to 25 It is a schematic diagram of the cross-sectional structure of the structure obtained in each step of the method for preparing a semiconductor structure in one embodiment of the present invention; wherein, Figure 20 to Figure 25 It is also a schematic cross-sectional structural diagram of a different semiconductor structure provided in another embodiment of the present invention.

[0056] Description of reference numerals:

[0057] 10 Support layer

[0058] 101 First Material Layer

[0059] 102 Second material layer

[0060] 103 Grooves

[0061] 104 Initial Groove

[0062] 11 Base

[0063] 12 Passivation layer

[0064] 13 Seed layer

[0065] 14 Solder pad

[0066] 15 Rewiring Layer

[0067] 16 Protective layer

[0068] 161 Opening

[0069] 162 Gap

[0070] 163 Bottom protective layer

[0071] 164 Top protective layer

[0072] 17. Wire Bonding

[0073] 18 Alloy layer

[0074] 19 Patterned mask layer DETAILED DESCRIPTION

[0075] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0076] It should be noted that when an element is considered to be "connected" to another element, it may be directly connected to another element and integrated therewith, or there may be an intermediate element at the same time. The terms "installed", "one end", "the other end" and similar expressions used herein are for illustrative purposes only.

[0077] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0078] In one embodiment, Figure 1 As shown, the present invention provides a method for preparing a semiconductor structure, comprising the following steps:

[0079] S11: forming a support layer, the support layer including a pad area; the pad area of ​​the support layer has a plurality of grooves;

[0080] S12: forming a soldering pad at least in the soldering pad region of the support layer, wherein the soldering pad is partially embedded in the groove.

[0081] In the preparation method of the above-mentioned semiconductor structure, a support layer 10 having a plurality of grooves 103 in the pad area is formed below the solder pad 14, that is, the support layer 10 having the grooves 103 in the pad area is first formed, and then the solder pad 14 is formed in the pad area of ​​the support layer 10. During the wire bonding process, even if the solder pad 14 is flat and most of the solder pad 14 will be squeezed out under the action of the bonding pressure, since there is a support layer 10 having the grooves 103 below the solder pad 14, part of the bottom of the solder wire will sink into the grooves 103, so that the contact surface between the solder wire and the solder pad 14 is uneven, thereby increasing the adhesion between the solder wire and the solder pad 14 and reducing the risk of the solder wire falling off.

[0082] In one example, if Figure 2 As shown, before step S11, the following steps are also included:

[0083] Providing a substrate 11, wherein an integrated circuit structure (not shown) is formed in the substrate 11;

[0084] A passivation layer 12 is formed on the upper surface of the substrate 11 ; and the support layer 10 in step S11 is formed on the upper surface of the passivation layer 12 .

[0085] In one example, the base 11 may include but is not limited to a silicon substrate.

[0086] In one example, the passivation layer 12 covers the upper surface of the substrate 11. The passivation layer 12 may include a single layer structure or a stacked layer structure including multiple material layers. The passivation layer 12 may include but is not limited to at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0087] In an optional example, the support layer 10 is a single-layer structure, and step S11 may include the following steps:

[0088] S111: forming a dielectric layer, which is the support layer 10 at this time. Figure 2 As shown, the dielectric layer is formed on the upper surface of the passivation layer 12; specifically, the dielectric layer can be formed by a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process; the dielectric layer can include but is not limited to a silicon oxide layer, a silicon nitride layer or a silicon oxynitride layer, etc.;

[0089] S112: etching the dielectric layer to form a groove 103 in the dielectric layer. The depth of the groove 103 may be less than or equal to the thickness of the dielectric layer. Specifically, first, a patterned mask layer 19 is formed on the upper surface of the dielectric layer. Figure 2 As shown, the patterned mask layer 19 may include but is not limited to a patterned photoresist layer; then, the dielectric layer is dry-etched or wet-etched based on the patterned mask layer 19 to form a groove 103 in the dielectric layer; finally, the patterned mask layer 19 is removed, as shown in FIG. Figure 3 and Figure 4 shown.

[0090] When the depth of the groove 103 can be smaller than the thickness of the dielectric layer, as Figure 3 As shown, the depth of the groove 103 can be set according to actual needs. For example, the depth of the groove 103 can be 1 / 3, 2 / 3 or 3 / 4 of the thickness of the dielectric layer, etc.; of course, in other examples, the depth of the groove 103 can also be equal to the thickness of the dielectric layer, such as Figure 4 As shown, the groove 103 penetrates the dielectric layer along the thickness direction.

[0091] In another optional example, the support layer 10 is a single-layer structure, and step S11 may include the following steps:

[0092] S111: forming a polymer layer, which is the support layer 10. Specifically, the polymer layer may be formed on the upper surface of the passivation layer 12 by a spin coating process, but not limited to a spin coating process. The polymer layer may include, but not limited to, a polyimide (PI) layer or a polybenzoxazole (PBO) layer.

[0093] S112: exposing and developing the polymer layer to form a groove 103 in the polymer layer. The depth of the groove 103 may be less than or equal to the thickness of the polymer layer. Specifically, the polymer layer may be directly exposed and developed based on a double exposure process or a light shielding / transmitting alternating mask to form the groove 103 in the polymer layer. The structure formed may be as follows: Figure 3 and Figure 4 shown.

[0094] When the depth of the groove 103 can be less than the thickness of the polymer layer, as Figure 3 As shown, the depth of the groove 103 can be set according to actual needs. For example, the depth of the groove 103 can be 1 / 3, 2 / 3 or 3 / 4 of the thickness of the polymer layer, etc.; of course, in other examples, the depth of the groove 103 can also be equal to the thickness of the polymer layer, such as Figure 4 As shown, the groove 103 penetrates the polymer layer along the thickness direction.

[0095] In another example, the support layer 10 is a laminated structure, and step S11 includes the following steps:

[0096] S111: forming a first material layer 101;

[0097] S112: forming a second material layer 102 on the upper surface of the first material layer 101, wherein the second material layer 102 and the first material layer 101 together constitute a support layer 10;

[0098] S113 : forming a groove 103 in the second material layer 102 , wherein the depth of the groove 103 is less than or equal to the thickness of the second material layer 102 .

[0099] In one example, the first material layer 101 may be a polymer layer, and the second material layer 102 may be a dielectric layer; at this time, in step S111, a spin coating process may be used but is not limited to form the first material layer 101 on the upper surface of the passivation layer 12, and the first material layer 101 may include but is not limited to a polyimide layer or a polybenzoxazole layer; in step S112, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process may be used to form the second material layer 102; the second material layer 102 may include but is not limited to a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, etc.; in step S113, a patterned mask layer 19 may be first formed on the upper surface of the second material layer 102, such as Figure 5 As shown, the patterned mask layer 19 may include but is not limited to a patterned photoresist layer; then the second material layer 102 is etched based on the patterned mask layer 19; finally, the patterned mask layer 19 is removed, as shown in FIG. Figure 6 shown.

[0100] In another example, the first material layer 101 may be a medium, and the second material layer 102 may be a polymer layer; in this case, in step S111, the first material layer 101 may be formed by a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process; the first material layer 101 may include but is not limited to a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, etc.; in step S112, the second material layer 102 may be formed by a spin coating process but is not limited to a spin coating process, and the second material layer 102 may include but is not limited to a polyimide layer or a polybenzoxazole layer; in step S113, the second material layer 102 may be directly exposed and developed based on a double exposure process or a light-shielding / light-transmitting alternating mask to form a groove 103 in the second material layer 102.

[0101] It should be noted that, in the above example, while forming the groove 103 , interconnection holes (not shown) are also formed in the support layer 10 and the passivation layer 12 , and the interconnection holes expose the integrated circuit region.

[0102] In yet another example, step S11 may include the following steps:

[0103] S111: forming a first material layer 101;

[0104] S112: exposing and developing the first material layer 101 to form an initial groove 104 in the first material layer 101, wherein the depth of the initial groove 104 is less than or equal to the thickness of the first material layer 101;

[0105] S113: forming a second material layer 102 on the upper surface of the first material layer 101, the sidewall and the bottom of the initial groove 104, wherein the thickness of the second material layer 102 is less than the depth of the initial groove 104, such as Fig. 9 and Fig.10 As shown, the first material layer 101 and the second material layer 102 together constitute the support layer 10.

[0106] In one example, the first material layer 101 may be a polymer layer, and the second material layer 102 may be a dielectric layer; in step S111, the first material layer 101 may be formed on the upper surface of the passivation layer 12 by a spin coating process but not limited thereto, and the first material layer 101 may include but not limited to a polyimide layer or a polybenzoxazole layer; in step S112, the first material layer 101 may be directly exposed and developed based on a double exposure process or a light shielding / transmitting alternating mask to form an initial groove 104 in the first material layer 101; the depth of the initial groove 104 may be less than the thickness of the first material layer 101 (e.g., Figure 7 ), or may be equal to the thickness of the first material layer 101 (as shown Figure 8As shown); in step S113, a second material layer 102 may be formed by a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process; the second material layer 102 may include but is not limited to a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, and the like.

[0107] In another example, the first material layer 101 may be a dielectric layer, and the second material layer 102 may be a polymer layer; in step S111, the first material layer 101 may be formed by a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process; the first material layer 101 may include but is not limited to a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, etc.; in step S112, a patterned mask layer (not shown) may be first formed on the upper surface of the first material layer 101, and the patterned mask layer may include but is not limited to a patterned photoresist layer; then the first material layer 101 is etched based on the patterned mask layer; finally, the patterned mask layer is removed; in step S113, the second material layer 102 may be formed by but is not limited to a spin coating process, and the second material layer 102 may include but is not limited to a polyimide layer or a polybenzoxazole layer.

[0108] It should be noted that in the above example, while forming the initial groove 104, interconnect holes (not shown) are also formed in the support layer 10 and the passivation layer 12, and the interconnect holes expose the integrated circuit area. After forming the second material layer 102, a groove 103 is formed in the support layer 10.

[0109] In one example, the shape of the groove 103 in the above examples may include but is not limited to a rectangular strip, a cross, or a star (a six-pointed star or a five-pointed star, etc.), etc.

[0110] In one example, in step S12, Figures 11 to 13 As shown, the pad 14 may be formed by, but not limited to, electroplating and other processes; the pad 14 may include, but not limited to, an aluminum pad.

[0111] In an optional example, while forming the pad 14 in the pad region of the support layer 10, a redistribution layer 15 is also formed on the support layer 10, and the redistribution layer 15 is connected to the pad 14 and the integrated circuit. Specifically, the redistribution layer 15 can be formed by, but not limited to, an electroplating process, and the redistribution layer 15 can include, but not limited to, an aluminum redistribution layer.

[0112] For an example, see Figures 11 to 13Before forming the solder pad 14 and the redistribution layer 15, the process further includes forming a seed layer 13 on the upper surface of the support layer 10 and in the interconnection hole; the solder pad 14 and the redistribution layer 15 are formed on the upper surface of the seed layer 13. Specifically, the seed layer 13 may be formed by, but not limited to, a sputtering or electroplating process, and the seed layer 13 may include, but not limited to, a titanium layer or a titanium nitride layer, and the like.

[0113] After step S12, the following steps are also included:

[0114] S13: forming a protection layer 16 on the upper surface of the support layer 10, wherein the protection layer 16 covers the pads of the redistribution layer 15 and 14;

[0115] S14: forming an opening 161 in the protective layer 16, wherein the opening 161 exposes the bonding pad 14, such as Figures 14 to 19 As shown;

[0116] S15: Provide a welding wire 17, and connect one end of the welding wire 17 to the welding pad 14, such as Figure 20 to Figure 25 In one example, the protective layer 16 may be a single-layer structure, such as Figures 14 to 16 In other examples, the protective layer 16 may be a laminated structure including a bottom protective layer 163 and a top protective layer 164, such as Figures 17 to 19 Specifically, the protective layer 16 may include but is not limited to a silicon oxide layer, a silicon nitride layer or a silicon oxynitride layer, etc. It should be noted that under the same etching conditions, the bottom protective layer 163 has a higher etching selectivity than the top protective layer 164.

[0117] In an optional embodiment, the protective layer 16 below the opening 161 formed in step S14 has a notch 162, and the notch 162 extends from the bottom of the opening 161 into the protective layer 16. Figures 14 to 19 As shown; by forming a notch 162 in the protective layer 16 below the opening 161, a buffer space can be formed below the opening 161. The notch 162 can accommodate the welding wire 15 that squeezes the outer row of welding pads 14, preventing the protective layer 16 from being lifted up or cracked, and preventing the welding pads 14 from overflowing, thereby ensuring the quality of the product.

[0118] When the protective layer 16 is a single-layer structure, a dry etching process can be used to directly etch the protective layer 16 to form an opening 161 with a notch 162 at the bottom; when the protective layer 16 is a stacked structure including a bottom protective layer 163 and a top protective layer 164, a dry etching process can be used to first form an initial opening in the top protective layer 161, and then a wet etching process can be used to etch the bottom protective layer 163 to form an opening 161 with a notch 162 at the bottom.

[0119] In one example, the bonding wire 17 may include but is not limited to copper wire, aluminum wire, gold wire, or the like.

[0120] In an optional example, when the welding wire 17 is bonded to the welding pad 14, the welding wire 17 and the welding pad 14 will react to form an alloy layer 18 at the junction section of the two. Figure 20 to Figure 25 shown.

[0121] In one example, there is a gap between the bottom of the welding wire 17 and the bottom of the groove 103. The gap between the bottom of the welding wire 17 and the bottom of the groove 103 allows the welding pad 14 to be retained between the welding wire 17 and the bottom of the groove 103. During operation, the current can flow through the welding pad 14 in the groove 103 in addition to the welding pads 14 on both sides of the welding wire 17, thereby increasing the amount of current during operation.

[0122] In another embodiment, please combine Figures 2 to 19 Continue reading Figure 20 to Figure 25 The present invention also provides a semiconductor structure, including: a support layer 10, the support layer 10 includes a pad area (not shown); the pad area of ​​the support layer 10 has a plurality of grooves 103; a pad 14, the pad 14 is located on the support layer 10, and at least in the pad area, and the pad 14 is partially embedded in the groove 103.

[0123] In the above-mentioned semiconductor structure, a support layer 10 having a plurality of grooves 103 in the pad area is formed below the soldering pad 14, that is, a support layer 10 having grooves 103 in the pad area is first formed, and then a soldering pad 14 is formed in the pad area of ​​the support layer 10. During the wire bonding process, even if the soldering pad 14 is flat and most of the soldering pad 14 will be squeezed out under the action of the bonding pressure, since there is a support layer 10 having grooves 103 below the soldering pad 14, part of the bottom of the soldering wire will sink into the grooves 103, so that the contact surface between the soldering wire and the soldering pad 14 is uneven, thereby increasing the adhesion between the soldering wire and the soldering pad 14 and reducing the risk of the soldering wire falling off.

[0124] In an optional example, the support layer 10 may be a single-layer structure, such as Fig.23 As shown, the depth of the groove 103 may be less than or equal to the thickness of the support layer 10; the support layer 10 may include a dielectric layer or a polymer layer.

[0125] In another example, the support layer 10 may be a laminated structure, and the support layer 10 may include: a first material layer 101; a second material layer 102, the second material layer 102 is located on the upper surface of the first material layer 101, and a plurality of grooves 103 are formed in the second material layer 102, such as Fig.24 As shown, the depth of the groove 103 may be less than or equal to the thickness of the second material layer 102 .

[0126] In another example, the support layer 10 is a laminated structure, and the support layer 10 includes: a first material layer 101, an initial groove is formed in the first material layer 101, and the depth of the initial groove can be less than or equal to the thickness of the first material layer 101; a second material layer 102, the second material layer 102 is located on the upper surface of the first material layer 101, the sidewall of the initial groove and the bottom of the initial groove; the thickness of the second material layer 102 is less than the depth of the initial groove, so as to form a groove 103 in the support layer 10, as shown in FIG. Fig.25 shown.

[0127] In one example, the first material layer 101 may be a dielectric layer, and the second material layer 102 may be a polymer layer; in another example, the first material layer 101 may be a polymer layer, and the second material layer 102 may be a dielectric layer.

[0128] In the above examples, the dielectric layer may include but is not limited to a silicon oxide layer, a silicon nitride layer or a silicon oxynitride layer, etc., and the polymer layer may include but is not limited to a polyimide layer or a polybenzoxazole layer.

[0129] In one example, when the depth of the groove 103 is less than the thickness of the supporting layer 10, the depth of the groove 103 can be set according to actual needs. For example, the depth of the groove 103 can be 1 / 3, 2 / 3 or 3 / 4 of the thickness of the supporting layer 10, etc.; of course, in other examples, the depth of the groove 103 can also be equal to the thickness of the supporting layer 10, that is, the groove 103 penetrates the supporting layer 10 along the thickness direction.

[0130] In one example, the shape of the groove 103 in the above examples may include but is not limited to a rectangular strip, a cross, or a star (a six-pointed star or a five-pointed star, etc.), etc.

[0131] In one example, the pad 14 may include, but is not limited to, an aluminum pad.

[0132] In an optional embodiment, the semiconductor structure also includes: a substrate 11, an integrated circuit (not shown) is formed in the substrate 11; a passivation layer 12, the passivation layer 12 is located on the upper surface of the substrate 11; a support layer 10 is located on the upper surface of the passivation layer 12; a redistribution layer 15, the redistribution layer 15 is located on the support layer 10, and is connected to the integrated circuit and the pad 14; a seed layer 13, the seed layer 13 is located between the support layer 10 and the pad 14, between the redistribution layer 15 and the support layer 10, and between the redistribution layer 15 and the integrated circuit; a protective layer 16, the protective layer 16 is located on the upper surface of the support layer 10, and covers the redistribution layer 15 and the pad 14; an opening 161 is formed in the protective layer 16, and the opening 161 exposes the pad 14; a welding wire 17, one end of the welding wire 17 is located in the opening 161 and is connected to the pad 14.

[0133] In one example, the base 11 may include but is not limited to a silicon substrate.

[0134] In one example, the passivation layer 12 covers the upper surface of the substrate 11. The passivation layer 12 may include a single layer structure or a stacked layer structure including multiple material layers. The passivation layer 12 may include but is not limited to at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0135] In one example, the redistribution layer 15 may include, but is not limited to, an aluminum redistribution layer.

[0136] In one example, the seed layer 13 may include but is not limited to a titanium layer or a titanium nitride layer, and the like.

[0137] In one example, the bonding wire 17 may include but is not limited to copper wire, aluminum wire, gold wire, or the like.

[0138] In an optional example, when the welding wire 17 is bonded to the welding pad 14, an alloy layer 18 is formed at the junction section of the welding wire 17 and the welding pad 14. Figure 20 to Figure 25 shown.

[0139] In one example, there is a gap between the bottom of the welding wire 17 and the bottom of the groove 103. The gap between the bottom of the welding wire 17 and the bottom of the groove 103 allows the welding pad 14 to be retained between the welding wire 17 and the bottom of the groove 103. During operation, the current can flow through the welding pad 14 in the groove 103 in addition to the welding pads 14 on both sides of the welding wire 17, thereby increasing the amount of current during operation.

[0140] In one example, the protective layer 16 may be a single-layer structure, such as Figure 20 to Figure 22 As shown, in other examples, the protective layer 16 may be a laminated structure including a bottom protective layer 163 and a top protective layer 164, such as Figure 23 to Figure 25 As shown. Specifically, the protective layer 16 may include but is not limited to a silicon oxide layer, a silicon nitride layer or a silicon oxynitride layer, etc. It should be noted that, under the same etching conditions, the bottom protective layer 163 has a higher etching selectivity than the top protective layer 164. It should be further noted that when the protective layer 16 is a stacked structure including a bottom protective layer 163 and a top protective layer 164, the gap 162 is formed in the bottom protective layer 163.

[0141] In another example, the protective layer 16 below the opening 161 has a notch 162, and the notch 162 extends from the lower portion of the opening 161 into the protective layer 16. Figures 14 to 19As shown; by forming a notch 162 in the protective layer 16 below the opening 161, a buffer space can be formed below the opening 161. The notch 162 can accommodate the welding wire 15 that squeezes the outer row of welding pads 14, preventing the protective layer 16 from being lifted up or cracked, and preventing the welding pads 14 from overflowing, thereby ensuring the quality of the product.

[0142] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0143] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor structure, characterized in that: include: The support layer includes a pad area; the support layer in the pad area has a plurality of grooves; A soldering pad, located on the support layer and at least in the pad region, wherein a portion of the soldering pad is embedded in the groove; The semiconductor structure further includes: a substrate having an integrated circuit structure therein; A passivation layer is located on the upper surface of the substrate; the support layer is located on the upper surface of the passivation layer; A redistribution layer, located on the support layer and connected to the integrated circuit and the pad; a seed layer, located between the support layer and the pad, between the redistribution layer and the support layer, and between the redistribution layer and the integrated circuit structure; A protective layer, located on the upper surface of the support layer and covering the redistribution layer and the pad; an opening is formed in the protective layer, and the opening exposes the pad; a welding wire, one end of which is located in the opening and connected to the welding pad; A notch is provided in the protection layer at the lower portion of the opening, so that the width of the lower portion of the opening is greater than the width of the upper portion of the opening.

2. The semiconductor structure according to claim 1, characterized in that: The support layer is a single-layer structure, and the support layer includes a dielectric layer or a polymer layer. The depth of the groove is less than or equal to the thickness of the support layer.

3. The semiconductor structure according to claim 1, characterized in that: The support layer is a laminated structure, and the support layer includes: A first material layer, wherein an initial groove is formed in the first material layer, and a depth of the initial groove is less than or equal to a thickness of the first material layer; The second material layer is located on the upper surface of the first material layer, the sidewall of the initial groove and the bottom of the initial groove; the thickness of the second material layer is less than the depth of the initial groove.

4. The semiconductor structure according to claim 1, characterized in that: The support layer is a laminated structure, and the support layer includes: a first material layer; The second material layer is located on the upper surface of the first material layer. The second material layer has a plurality of grooves therein, and the depth of the grooves is less than or equal to the thickness of the second material layer.

5. The semiconductor structure according to claim 3 or 4, characterized in that: The first material layer is a dielectric layer and the second material layer is a polymer layer, or the first material layer is a polymer layer and the second material layer is a dielectric layer.

6. The semiconductor structure according to claim 1, characterized in that A gap exists between the bottom of the welding line and the bottom of the groove.

7. A method for preparing a semiconductor structure, characterized in that: The steps include: forming a support layer, wherein the support layer includes a pad region; a plurality of grooves are formed in the pad region of the support layer; forming a solder pad at least in the solder pad region of the support layer, wherein the solder pad is partially embedded in the groove; Before forming the support layer, the following steps are also included: providing a substrate having an integrated circuit formed therein; A passivation layer is formed on the upper surface of the substrate; the support layer is formed on the upper surface of the passivation layer; Before forming the bonding pad in the groove, the method further includes forming interconnection holes in the support layer and the passivation layer, wherein the interconnection holes expose the integrated circuit region; While forming the bonding pad in the pad region of the support layer, a redistribution layer is also formed on the support layer, wherein the redistribution layer is connected to the bonding pad and the integrated circuit; Before forming the pad and the redistribution layer, the method further includes forming a seed layer on the upper surface of the support layer and in the interconnection hole; the pad and the redistribution layer are formed on the upper surface of the seed layer; After forming the bonding pad in the pad area of ​​the support layer, the following steps are also included: forming a protective layer on the upper surface of the support layer, wherein the protective layer covers the redistribution layer and the pad; An opening is formed in the protective layer, and the opening exposes the pad; a notch is provided in the protective layer below the opening, so that the width of the lower portion of the opening is greater than the width of the upper portion of the opening.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that: Forming the support layer comprises the following steps: forming a dielectric layer; The dielectric layer is etched to form the groove in the dielectric layer, and the depth of the groove is less than or equal to the thickness of the dielectric layer.

9. The method for preparing a semiconductor structure according to claim 7, characterized in that: Forming the support layer comprises the following steps: forming a polymer layer; The polymer layer is exposed and developed to form the groove in the polymer layer, wherein the depth of the groove is less than or equal to the thickness of the polymer layer.

10. The method for preparing a semiconductor structure according to claim 7, characterized in that: Forming the support layer comprises the following steps: forming a first material layer; forming a second material layer on the upper surface of the first material layer; The groove is formed in the second material layer, and the depth of the groove is less than or equal to the thickness of the second material layer.

11. The method for preparing a semiconductor structure according to claim 7, characterized in that: Forming the support layer comprises the following steps: forming a first material layer; forming an initial groove in the first material layer, wherein the depth of the initial groove is less than or equal to the thickness of the first material layer; A second material layer is formed on the upper surface of the first material layer, the sidewalls and the bottom of the initial groove.

12. The method for preparing a semiconductor structure according to claim 10 or 11, characterized in that: The first material layer is a dielectric layer and the second material layer is a polymer layer, or the first material layer is a polymer layer and the second material layer is a dielectric layer.

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