Semiconductor device and method of manufacturing the same

Abstract

Provided is a semiconductor device and a method of manufacturing a semiconductor device. The method includes forming a first isolation feature in a peripheral region of a substrate; after forming the first isolation feature, recessing a cell region of the substrate; after recessing the cell region of the substrate, forming a second isolation feature in the cell region of the substrate; forming a plurality of control gates on the cell region of the substrate; and forming a gate stack on the peripheral region of the substrate.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing the same. Background Art

[0002] In the past few decades, the semiconductor integrated circuit industry has experienced exponential growth. During the development of integrated circuits, the functional density (i.e., the number of internal connection devices per wafer area) has increased extensively, while the geometric size (i.e., the smallest component (or line) that can be produced using the process) has decreased. In some integrated circuit designs, one advancement achieved as the technology node shrinks is the replacement of polysilicon gate electrodes with metal gate electrodes, thereby reducing the feature size and improving device performance.

[0003] Ultra-fast flash technology enables designers to create cost-effective high-performance programmable system-on-chip (SOC) solutions by using split-gate flash memory cells. The large-scale expansion of the third generation embedded super-flash memory (ESF3) makes it possible to design flash memories with high memory array density. Summary of the Invention

[0004] According to some embodiments of the present disclosure, a method of manufacturing a semiconductor device includes: forming a first isolation feature in a peripheral region of a substrate; after forming the first isolation feature, recessing a cell region of the substrate; after recessing the cell region of the substrate, forming a second isolation feature in the cell region of the substrate; forming a plurality of control gates on the cell region of the substrate; and forming a gate stack on the peripheral region of the substrate.

[0005] According to some embodiments of the present disclosure, a method of manufacturing a semiconductor device includes: forming a first isolation feature in a peripheral region of a substrate; after forming the first isolation feature, depositing a floating gate layer on the peripheral region and a cell region of the substrate; forming a groove in the floating gate layer and the cell region of the substrate; forming a second isolation feature in the groove; forming a plurality of control gates on the floating gate layer on the cell region of the substrate; and forming a gate stack on the peripheral region of the substrate.

[0006] According to some embodiments of the present disclosure, a semiconductor device includes a substrate, isolation features, memory cells, and semiconductor devices. The substrate has a cell region, a peripheral region, and a transition region between the cell region and the peripheral region. The isolation features are located in the transition region, wherein the substrate includes a protruding portion located between a first portion and a second portion of the isolation feature, the second portion being located between the first portion and the cell region, and an upper surface of the first portion of the isolation feature has a first portion and a second portion lower than the first portion, and the second portion is located between the first portion and the second portion of the isolation feature. The memory cells are located on the cell region of the substrate. The semiconductor devices are located on the peripheral region of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The aspects of the present disclosure will be better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with the standard practice in the industry, the various features of the drawings are not drawn to scale. In fact, the dimensions of the features may be arbitrarily scaled for the sake of clear discussion.

[0008] Figure 1A and 1B is a flowchart of a method for fabricating a semiconductor device according to some embodiments;

[0009] Figures 2A to 21C is a method for fabricating a semiconductor device at different stages according to some embodiments;

[0010] Figures 22A to 22B is a cross-sectional view of a semiconductor device according to some embodiments;

[0011] Figures 23A to 23B is a cross-sectional view of a semiconductor device according to some embodiments;

[0012] Figures 24A to 24B is a cross-sectional view of a semiconductor device according to some embodiments.

[0013]

SYMBOL DESCRIPTION

[0014] 110: Substrate

[0015] 112: Cell region

[0016] 112a: Active region

[0017] 112b: Substrate portion

[0018] 112S: Upper surface

[0019] 112R: Recess

[0020] 112T: Trench

[0021] 114: Peripheral region

[0022] 114a: Active region

[0023] 114S: Upper surface

[0024] 114T: Groove

[0025] 116: Transition region

[0026] 116p: Protrusion

[0027] 116T: Groove

[0028] 116T’: Groove

[0029] 120: Buffer layer

[0030] 120’: Patterned buffer layer

[0031] 130: Hard mask layer

[0032] 130’: Patterned hard mask layer

[0033] 144: Isolation feature

[0034] 144T: Upper surface

[0035] 144B: Lower surface

[0036] 146: Isolation feature

[0037] 146B: Lower surface

[0038] 146T: Upper surface

[0039] 146TA: Upper surface

[0040] 146TB: Upper surface

[0041] 150: Buffer layer

[0042] 160: Hard mask layer

[0043] 170: Buffer layer

[0044] 180: Tunnel thin layer

[0045] 180’: Patterned tunnel thin layer

[0046] 182: Tunnel layer

[0047] 188: Dielectric layer

[0048] 190: Floating gate thin layer

[0049] 190’: Patterned floating gate thin layer

[0050] 192: Floating gate

[0051] 200: Buried layer

[0052] 200’: Patterened buried layer

[0053] 210: Hard mask layer

[0054] 210’: Patterened hard mask layer

[0055] 222: Isolation feature

[0056] 222T: Upper surface

[0057] 222B: Lower surface

[0058] 226: Isolation feature

[0059] 226T: Upper surface

[0060] 226B: Lower surface

[0061] 300: Gate stack

[0062] 300’: Semiconductor stack

[0063] 300”: Semiconductor stack

[0064] 310: Thin dielectric layer

[0065] 312: Dielectric layer

[0066] 314: Dielectric layer

[0067] 320: Control gate thin layer

[0068] 322: Control gate

[0069] 324: Control gate layer

[0070] 330: Hard mask layer

[0071] 332: Hard mask

[0072] 334: Hard mask layer

[0073] 340: Spacer

[0074] 345: Spacer

[0075] 352: Selective gate dielectric layer

[0076] 362: Selective gate

[0077] 364: Erase gate

[0078] 370: Hard mask

[0079] 400: Semiconductor device

[0080] 400’:Dummy semiconductor device

[0081] 400SD: Source / drain region

[0082] 410: Gate stack

[0083] 510: Etch stop layer

[0084] 520: Interlayer dielectric

[0085] 10: Memory cell

[0086] SR: Source region

[0087] DR: Drain region

[0088] SRD: Dielectric layer

[0089] M: Method

[0090] S1 to S20: Steps

[0091] B - B: Line

[0092] C - C: Line Detailed implementation manners

[0093] The following disclosure provides many different embodiments or exemplifications to implement different features of the provided inventive subject matter. The following specific exemplifications of the components and their arrangements are for simplifying the disclosure. These are of course only exemplifications and are not intended to be restrictive. For example, the description of the first feature being formed on or above the second feature includes embodiments where the first feature and the second feature are in direct contact, and also includes embodiments where other features are formed between the first feature and the second feature, such that the first feature and the second feature are not in direct contact. In addition, in various embodiments, the disclosure may repeat reference numerals and / or use words. This repetition is for simplicity and clarity, and does not itself limit the relationship between various embodiments and / or configurations.

[0094] Furthermore, relative spatial terms, such as "beneath", "below", "lower", "above", "upper", etc., are used to facilitate the description of the relationship between elements or features depicted in the drawings and other elements or features. The relative spatial terms include different directions of the element during use or operation in addition to the directions depicted in the drawings. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the relative spatial descriptions used herein can be interpreted accordingly.

[0095] A flash memory can be formed on a bulk silicon substrate and various biasing conditions are used to read and write data values. For example, an EFS3 cell (or so-called "third-generation flash memory" cell) includes a pair of symmetric split-gate memory cells, where each split-gate memory cell includes a pair of source / drain regions and a channel region disposed therebetween. In the EFS3 architecture, one of the source / drain regions of each split-gate memory cell is a shared source / drain region shared with its adjacent cell, and the other source / drain region is the unique source / drain region of the cell. Inside each split-gate memory cell, a floating gate is disposed above the channel region of the cell, and a control gate is disposed above the floating gate. A select gate is disposed on one side of the floating gate and the control gate (e.g., between a single source / drain region of the EFS3 cell and the sidewalls of the floating gate and / or the control gate). At least one cell is configured to store a variable charge level on the floating gate, where the level of the charge corresponds to the data state stored in the cell and is stored in a non-volatile manner such that the stored charge / data persists without power.

[0096] By changing the amount of charge stored on the floating gate, the threshold voltage V of the memory cell device can be correspondingly changed. th . For example, to perform a programming operation on the cell (e.g., write logic "0", program to "0", V th is high), a relatively high bias voltage (e.g., at least one order of magnitude higher) is applied to the control gate, relative to the voltage applied across the channel region and / or the voltage applied to the select gate. This high bias voltage promotes Fowler-Nordheim tunneling of carriers from the channel region to the control gate. When the carriers tunnel to the control gate, the carriers are trapped in the floating gate and change the V of the cell. th . Conversely, to perform an erase operation on the cell (e.g., write logic "1", erase to "1", V th is low), a relatively high bias voltage (e.g., at least one order of magnitude higher) is applied to the erase gate, relative to the voltage applied across the channel region and / or the voltage applied to the control gate. This high bias voltage promotes Fowler-Nordheim tunneling of carriers from the floating gate to the erase gate, thereby removing the carriers from the floating gate and again changing the V of the cell in a predictable manner. th . Subsequently, during a read operation, a voltage is applied to the select gate to turn on a portion of the channel region. Applying a voltage to the select gate attracts carriers to a portion of the channel region adjacent to the select gate. When the select gate voltage is applied, greater than V th but less than V th + ΔVth A voltage is applied to the control gate (where ΔV th V is caused by the captured charge on the floating gate th If the memory cell device is turned on (i.e., allows charge to flow), it is considered to contain a first data state (e.g., a logic "1" is read). If the memory cell device is not turned on, it is considered to contain a second data state (e.g., a logic "0" is read).

[0097] Because of the high voltages involved in performing programming and / or erasing operations, high energy implants are used in some cases to form the source / drain regions of a flash memory cell. As a result, the source / drain regions of a flash memory cell can be implanted deeper than the source / drain regions of a low voltage complementary metal-oxide-semiconductor (CMOS) device. This additional implant depth can help reduce current crowding at the substrate surface near the edges of the source / drain regions.

[0098] Some embodiments of the present disclosure relate to flash memory devices formed on a recessed area of ​​a substrate. Although some embodiments are shown below with respect to split-gate flash memory, it should be understood that the concept is not limited to split-gate flash memory cells, but is also applicable to other types of flash memory cells and other types of semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), fin field effect transistors (FinFETs), etc.

[0099] Figure 1A and 1B is a flow chart of a method M for manufacturing a semiconductor device at different stages according to some embodiments. Figures 2A to Figure 21C A method of manufacturing a semiconductor device at different stages according to some embodiments is shown. It should be understood that additional steps may be implemented before, during or after method M, and in other embodiments of method M, some of the steps described may be replaced or eliminated.

[0100] Figure 2A is a top view of a semiconductor device according to some embodiments, Figure 2B It is along Figure 2A A cross-sectional view taken along line BB. Figure 1A and Figure 2A and 2B, Method M begins at step S1, in which a substrate 110 is provided, and a liner layer 120 and a hard mask layer 130 are formed on the substrate 110. In some embodiments, the substrate 110 may be a semiconductor substrate, such as a bulk silicon substrate, a germanium substrate, a compound semiconductor substrate, or other suitable substrates. The substrate 110 may include: an epitaxial layer on a bulk semiconductor; a silicon germanium layer on bulk silicon; a silicon layer on bulk silicon germanium; or a semiconductor-on-insulator (SOI) structure. The substrate 110 includes a cell region 112, a peripheral region 114, and a transition region 116. The peripheral region 114 is located at at least one edge of the cell region 112. For example, the peripheral region 114 surrounds the cell region 112. The transition region 116 is disposed between the cell region 112 and the peripheral region 114.

[0101] The liner layer 120 may be a thin film including silicon oxide formed using, for example, a thermal oxidation process. The liner layer 120 may serve as a buffer layer between the substrate 110 and the hard mask layer 130. The liner layer 120 may also be used as an etch stop layer for etching the hard mask layer 130 in subsequent processes. In some embodiments, the hard mask layer 130 is formed of a dielectric material such as silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). For example, the thickness of the liner layer 120 may be in the range of about 30 angstroms to about 300 angstroms.

[0102] Refer to Figure 1A and Figure 3 , wherein Figure 3 the cross-sectional position of Figure 2B is the same as the cross-sectional position of Figure 2B . Method M proceeds to step S2, in which the patterned substrate 110 is patterned to form a plurality of trenches in the transition region and the peripheral region. In this embodiment, the liner layer 120 and the hard mask layer 130 (refer to Figure 2B ) are patterned to form a patterned liner layer 120' and a patterned hard mask layer 130' respectively, and the patterned substrate 110 is patterned to form a trench 116T in the transition region 116 and at least one trench 114T in the peripheral region 114.

[0103] For example, in the hard mask layer 130 (see Figure 2B)A photoresist layer is formed thereon and then patterned through a photolithography process to form openings in the photoresist layer, exposing the hard mask layer 130 on the peripheral region 114 and the transition region 116 of the substrate 110 (see Figure 2B ) in certain regions. The exposed portions of the hard mask layer 130 and the underlying cushion layer 120 (refer to Figure 2B ) are etched and removed, and the remaining hard mask layer 130 and the underlying cushion layer 120 (refer to Figure 2B ) are referred to as the patterned hard mask layer 130' and the patterned cushion layer 120'. The patterned hard mask layer 130' covers the unit region 112 and a portion of the peripheral region 114 of the substrate 110, and exposes a portion of the peripheral region 114 and the transition region 116 of the substrate 110. Then, the patterned hard mask layer 130' is used as an etching mask to etch the exposed portion of the peripheral region 114 and the transition region 116 of the substrate 110, for example, by dry etching such as reactive-ion etching (RIE) or wet etching using a liquid substrate etchant. For example, gas etchants such as HBr and Cl 2 can be used to etch the substrate 110, and the hard mask layer 130' can have higher etching resistance to this etchant compared to the substrate 110. Through this etching process, trenches 114T and 116T are formed.

[0104] Refer to Figure 1A and Figure 4A and 4B , where Figure 4A is a top view of a semiconductor device according to some embodiments, Figure 4B is a cross-sectional view taken along line B-B of Figure 4A . Method M proceeds to step S3, where isolation features are formed in the trenches in the transition region and the peripheral region. In this embodiment, isolation features 144 and 146 are respectively formed in trenches 114T and 116T. The isolation features 144 and 146 define the active regions 114a in the peripheral region 114. It should be noted that in some other embodiments, the number of isolation features 144 can be multiple, and multiple isolation features 144 can define multiple active regions 114a in the peripheral region 114. In some embodiments, the isolation features 144 and 146 are made of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), or other low-K dielectric materials. In this embodiment, the opening sizes of the trenches 114T and 116T can cause a loading effect during the etching process, such that the bottom of the trench 116T is lower than the bottom of the trench 114T, so the lower surface 146B of the isolation feature 146 is lower than the lower surface 144B of the isolation feature 144.

[0105] In some embodiments, a dielectric material can be formed on the structure by a suitable process such as a high-density-plasma (HDP) chemical vapor deposition (CVD) process, a sub-atmospheric CVD (SACVD) process, a high aspect-ratio process (HARP), a spin-on-dielectric (SOD) process, etc. Figure 3 The dielectric material can overfill trenches 114T and 116T. In some embodiments, a liner oxide (not shown) can be selectively pre-formed. In some embodiments, the liner oxide can be a thermal oxide. Then, a chemical mechanical polish (CMP) process is performed to remove the excess dielectric material outside trenches 114T and 116T, and the CMP process can make the upper surface of the dielectric material flush with the upper surface of the patterned hard mask layer 130', thereby forming isolation features 144 and 146.

[0106] Referring to Figure 1A and Figure 5 where Figure 5 the cross-sectional position of Figure 4B is the same as the cross-sectional position of

[0107] Referring to Figure 1A and Figure 6A and 6B where Figure 6A is a top view of the semiconductor device, Figure 6B is along Figure 6ACross-sectional view taken along line B-B. Method M proceeds to step S5, in which the patterned buffer layer and hard mask layer are formed to expose the cell regions of substrate 110. In the present embodiment, layers 150 to 170, hard mask layer 130', and buffer layer 120' are patterned by an appropriate etching process to remove portions of buffer layer 170, hard mask layer 160, buffer layer 150, hard mask layer 130', and buffer layer 120' above cell region 112. For example, a photoresist layer is formed on buffer layer 170 (refer to Figure 5 ), and then patterned by an exposure lithography process to form openings in the photoresist layer, such that certain regions of buffer layer 170 (refer to Figure 5 ) above cell region 112 of substrate 110 are exposed. The patterning process includes etching the exposed portions of buffer layer 170 and underlying layers 150 and 160, 130' and 120' (refer to Figure 5 ). After the etching process, cell region 112 of substrate 110 is exposed. The etching process may also remove buffer layer 170 above surrounding region 114 and transition region 116 (refer to Figure 5 ). The remaining hard mask layer 160 covers a portion of surrounding region 114 and transition region 116. In some embodiments, portions of isolation feature 146 not covered by hard mask layer 160 may be etched. For example, the etching process may smooth the corners of isolation feature 146 not covered by hard mask layer 160.

[0108] Refer to Figure 1A and Figure 7 , where Figure 7 the cross-sectional position of Figure 6BThe cross-sectional positions are the same. Method M proceeds to step S6, in which the unit region of the substrate is recessed. In the present embodiment, the unit region 112 of the substrate 110 is recessed. For example, wet oxidation is used to oxidize the surface layer of the exposed region of the substrate 110 that is not covered by the hard mask layer 160. Thereafter, the oxidized surface layer is removed from the substrate 110 using, for example, wet etching, dry etching, or a combination of wet etching and dry etching. The etchant in the wet etching and / or dry etching process can include HF or other suitable etchants. The removal of the oxidized surface layer creates a recess 112R in the unit region 112. For example, the upper surface 112S of the unit region 112 is lower than the upper surface 114S of the surrounding region 114. The depth of the recess 112R is from about 50 angstroms to about 2000 angstroms. In some embodiments, the hard mask layer 160 has a higher etching resistance to the etchant used in the etching process than the oxidized surface layer, thereby protecting the underlying layers in the peripheral region 114 from being etched. In some embodiments, the portion of the isolation feature 146 that is not covered by the hard mask layer 160 can be further etched during this process. For example, the upper surface 146TB of the portion of the isolation feature 146 that is not covered by the hard mask layer 160 can be higher than the upper surface 112S of the unit region 112, but lower than the upper surface 146TA of the portion of the isolation feature 146 that is covered by the hard mask layer 160. In other words, the upper surface 146T of the isolation feature 146 has a stepped shape.

[0109] Refer to Figure 1A and Figure 8 , where Figure 8 the cross-sectional position of is the same as that of Figure 7 Method M proceeds to step S7, in which a tunneling thin layer is formed on the unit region of the substrate. In the present embodiment, a tunneling thin layer 180 is then conformally formed above the substrate 110. In some embodiments, the tunneling thin layer 180 can include, for example, a dielectric material such as silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), a high-k material, other non-conductive materials, or a combination thereof. Thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition, atomic layer deposition (ALD), ozone oxidation, other suitable processes, or a combination thereof can be used to form the tunneling thin layer 180. Thermal oxidation can result in the tunneling thin layer 180 having a uniform thickness on the unit region 112. In some embodiments, the formation of the tunneling thin layer 180 can also form a dielectric layer 188 above the hard mask layer 160. The dielectric layer 188 and the tunneling thin layer 180 have the same material.

[0110] Refer to Figure 1A and Figure 9 wherein Figure 9 has the same cross-sectional position as Figure 8 Method M proceeds to step S8, where a floating gate thin layer, a liner layer, and a hard mask layer are formed on the substrate. In the present embodiment, above the structure in Figure 8 (i.e., above the tunneling thin layer 180, the isolation feature 146, and the dielectric layer 188), a floating gate thin layer 190 is conformally formed. The floating gate thin layer 190 may include polysilicon. For example, it may be formed using a suitable silicon source material and by low-pressure chemical vapor deposition (LPCVD) method, chemical vapor deposition method, and physical vapor deposition sputtering method. The deposited floating gate thin layer may have an ideal thickness for the floating gate. For example, the thickness of the floating gate thin layer 190 ranges from about 50 angstroms to about 150 angstroms. If the thickness of the floating gate thin layer 190 is greater than about 150 angstroms, a thick floating gate will be formed, and the control gate subsequently formed on the floating gate will have a higher upper surface, which will make it difficult to integrate the manufacturing process of the memory device with the high-k metal gate process of the logic device. If the thickness of the floating gate thin layer 190 is less than about 50 angstroms, the formed memory device may have poor storage capacity. If desired, the floating gate thin layer 190 can be ion implanted to the desired conduction type. For example, the floating gate thin layer 190 can be in-situ doped. The floating gate thin layer 190 may include other gate materials, such as metals, metal alloys, single-crystalline silicon, or combinations thereof.

[0111] After forming the floating gate thin layer 190, another liner layer 200 is conformally formed above the floating gate thin layer 190, and another hard mask layer 210 is conformally formed above the liner layer 200. The liner layer 200 can be formed by: dielectric materials, such as an oxide layer. The liner layer 200 can be used as a buffer layer between the floating gate thin layer 190 and the hard mask layer 210. The hard mask layer 210 can be formed of a dielectric material, such as a dielectric material of silicon nitride (SiN) or other suitable materials.

[0112] Refer to Figure 1A and refer to Figures 10A to 10C wherein Figure 10A is a top view of the semiconductor device, Figure 10B is a cross-sectional view taken along line B-B of Figure 10A and Figure 10C is a cross-sectional view taken along line C-C of Figure 10A . Method M proceeds to step S9, in which the substrate is patterned to form a plurality of trenches in the cell region. In the present embodiment, patterning Figure 9The hard mask layer 210, the buffer layer 200, the floating gate thin layer 190, the tunneling thin layer 180, and the substrate 110 are formed, thereby forming a trench 112T in the cell region 112 and a trench 116T' in the transition region 116. In some embodiments, the width of the trench 116T' intercepted along Figure 10A line B - B may be greater than the width of the trench 116T' intercepted along Figure 10A line C - C. In this embodiment, the trench 116T' exposes an upper portion of the sidewall of the isolation feature 146 and a portion of the surface 146TB of the isolation feature 146 that is not covered by the hard mask layer 160. The lower portion of the sidewall of the isolation feature 146 may be covered by the protruding portion 116p of the substrate 110. In some embodiments, the protruding portion 116p has a tapered shape. For example, the protruding portion 116p tapers upward. The tip of the protruding portion 116p is lower than the upper surfaces 146TB and 146TA of the isolation component 146. In some embodiments, the tip of the protruding portion 116p is substantially flush with the upper surface 112S of the cell region 112 of the substrate 110.

[0113] For example, a photoresist layer is formed on the hard mask layer 210 (see Figure 9 ), and then it is patterned by an exposure lithography process, thereby forming an opening in the photoresist layer such that the photoresist layer exposes multiple regions of the hard mask layer 210 (see Figure 9 ). The exposed portion of the hard mask layer 210 is etched (refer to Figure 9 ) to pattern the hard mask layer 210. After the patterning process, the patterned hard mask layer 210' covers multiple portions of the buffer layer 200 (refer to Figure 9 ) and exposes multiple portions of the buffer layer 200 (refer to Figure 9 ).

[0114] Then, using the patterned hard mask layer 210' as an etching mask, the exposed portions of the buffer layer 200, the floating gate thin layer 190, the underlying tunneling thin layer 180, and the substrate 110 are etched through multiple dry etching processes, such as reactive ion etching (RIE). The dry etching process can use various gas etchants. For example, in the dry etching process, gas etchants such as HBr, Cl 2 , CF 4 , and / or CHF 3 can be used. The patterned hard mask layer 210' may have a higher etching selectivity than the buffer layer 200, the floating gate thin layer 190, the tunneling thin layer 180, and the substrate 110 (refer to Figure 9)Higher etching resistance to the etchant, thereby protecting the underlying layer in the cell region 112 from being etched. The dielectric layer 188 can be removed by a dry etching process. The hard mask layer 160 can have higher etching resistance to the etchant than the dielectric layer 188, the floating gate thin layer 190, the tunneling thin layer 180, and the substrate 110 (refer to Figure 9 ) to protect the underlying layer in the peripheral region 114 from being etched. Through the etching process, trenches 112T and 116T' are formed.

[0115] In this embodiment, Figure 9 the hard mask layer 210 is patterned into a patterned hard mask layer 210', Figure 9 the liner layer 200 is patterned into a patterned liner layer 200', Figure 9 the floating gate thin layer 190 is patterned into a patterned floating gate thin layer 190', Figure 9 the tunneling thin layer 180 is patterned into a patterned tunneling thin layer 180', and the substrate 110 is patterned to include a plurality of base portions 112b in the cell region 112. These base portions 112b are separated from each other by the trenches 112T. The tunneling thin layer 180' is disposed on the substrate 110, the floating gate thin layer 190' is disposed on the tunneling thin layer 180', the patterned liner layer 200' is disposed on the floating gate thin layer 190', and the hard mask layer 210' is disposed on the patterned liner layer 200'. Through the etching process, the Figure 9 portions of the hard mask layer 210', the liner layer 200', the floating gate thin layer 190', and the tunneling thin layer 180' on the peripheral region 114 are removed.

[0116] Refer to Figure 1B and Figures 11A to 11C , Figure 11A is a top view of the semiconductor device, Figure 11B is a cross-sectional view taken along line B-B of Figure 11A , Figure 11C is a cross-sectional view taken along line C-C of Figure 11A . The method M proceeds to step S10, where isolation features are formed in the trenches in the cell region. In this embodiment, the isolation features 222 and 226 are formed in the trenches 112T and 116T' respectively. The isolation feature 222 defines a plurality of active regions 112a (e.g., portions of the base portions 112b) in the cell region 112. The isolation feature 226 isolates the active regions 112a in the cell region 112 from the active regions 114a in the surrounding region 114. Depending on the topography of the trench 116T', the width of the isolation feature 226 taken along Figure 11A line B-B can be greater than the width of the isolation feature 226 taken along Figure 11AThe width taken along line C-C. In this embodiment, the substrate 110 includes a protruding portion 116p between the isolation features 146 and 226 in the transition region 116. The protruding portion 116p tapers upward. In some embodiments, the isolation features 222 and 226 are made of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), or other low-k dielectric materials.

[0117] In some embodiments, through suitable processes such as high-density plasma chemical vapor deposition process, sub-atmospheric chemical vapor deposition process, high aspect ratio process, spin-on dielectric material process, etc., a dielectric material can be formed above Figure 10B and Figure 10C the structure. The dielectric material can fill the trenches 112T and 116T' to overfill. In some embodiments, a liner oxide (not shown) can be selectively pre-formed. In some embodiments, the liner oxide can be a thermal oxide. Then, a chemical mechanical polishing (CMP) process is performed to remove the excess dielectric material outside the trenches 112T and 116T', and the CMP process can make the upper surface of the dielectric material flush with the upper surface of the patterned hard mask layer 160, thereby forming the isolation features 222 and 226. In some embodiments, this chemical mechanical polishing removes the dielectric layer 188 (such as an oxide layer) above the hard mask layer 160.

[0118] The isolation feature 222 can contact the base portion 112b of the substrate 110, the patterned tunneling thin layer 180', the patterned floating gate thin layer 190', the patterned spacer layer 200', and the patterned mask layer 210'. In this embodiment, the isolation feature 226 contacts the upper part of the sidewall of the isolation feature 146 and a part of the surface of the isolation feature 146 not covered by the hard mask layer 160.

[0119] In this embodiment, the bottom of the trench 116T' is higher than the bottom of the trench 116T, such that the lower surface 226B of the isolation feature 226 is higher than the lower surface 146B of the isolation feature 146. In some other embodiments, the lower surface 226B of the isolation feature 226 may not be higher than the lower surface 146B of the isolation feature 146. For example, the bottom of the trench 116T' can be lower than the bottom of the trench 116T, such that the lower surface 226B of the isolation feature 226 is lower than the lower surface 146B of the isolation feature 146. Or, in some other embodiments, the bottom of the trench 116T' can be substantially flush with the bottom of the trench 116T, such that the lower surface 226B of the isolation feature 226 is substantially flush with the lower surface 146B of the isolation feature 146.

[0120] Refer to Figure 1Band Figures 12A to 12B , Figures 12A to 12B has the same cross-sectional position as Figures 11B to 11C . Method M proceeds to step S10, in which the isolation features in the cell region are recessed. In the present embodiment, the isolation features 222 and 226 are recessed by a wet etching process. For example, a liquid etchant such as HF is sprayed onto Figures 11A to 11C 's structure, thereby etching the isolation features 222 and 226. The patterned hard mask layer 210' and the patterned hard mask layer 160 have a higher etch resistance to the etchant than the isolation features 222 and 226, thereby protecting the isolation features 144 and 146 under the hard mask layer 160 from being etched and protecting the layers 180' to 200' under the mask layer 210' from being etched. In some other embodiments, the portion of the isolation feature 146 not covered by the hard mask layer 160 can be etched by a wet etching process.

[0121] Referring to Figure 1B and Figures 13A to 13B , Figures 13A to 13B has the same cross-sectional position as Figures 12A to 12B . Method M proceeds to step S12, in which the hard mask layer is removed. In the present embodiment, the patterned hard mask layer 210' and the patterned hard mask layer 160 are removed, thereby exposing the liner layers 200' and 150. This removal method may include an appropriate etch-back process, such as using phosphoric acid as the etchant. The liner layers 200' and 150 may have a higher etch resistance to this etching process than the patterned hard mask layers 210' and 160, so that the liner layers 200' and 150 can protect the underlying layers from being etched during the etching process. In some embodiments, the isolation features 222 and 226 may have a higher etch resistance to the etching process than the patterned hard mask layers 210' and 160, such that the isolation features 222 and 226 remain unchanged after the etching process.

[0122] Referring to Figure 1B and Figures 14A to 14B . Figures 14A to 14B has the same cross-sectional position as Figures 13A to 13B . Method M proceeds to step S13, in which the isolation features are recessed. In the present embodiment, the isolation features 222 and 226 are recessed by a wet etching process. For example, a liquid etchant such as HF is dispensed onto Figure 13A and 13B 's structure, thereby etching the isolation features 222 and 226. By the wet etching process, the liner layers 200' and 150 can be removed (refer to Figures 13A to 13B)。The hard mask layer 130’ and the floating gate thin layer 190’ may have a higher etch resistance to the etchant than the isolation features 222 and 226 and the liner layers 200’ and 150 (refer to Figures 13A to 13B ) higher etch resistance. Therefore, the tunneling thin layer 180’ under the floating gate thin layer 190’ can be protected from etching, and the liner layer 120’ under the hard mask layer 130’ can be protected from etching. In some embodiments, a portion of the isolation feature 226 adjacent to the isolation feature 146 is etched by a wet etching process. After the recessing step, the floating gate thin layer 190’ protrudes above the upper surfaces of the isolation features 222 and 226. The step of recessing the isolation member 222 can increase the coupling ratio between the subsequently formed floating gate and the control gate.

[0123] Refer to Figure 1B and Figure 15A and 15B , Figure 15A and 15B , the cross-sectional positions of Figures 14A to 14B are the same as the cross-sectional positions of Figures 14A to 14B . The method M proceeds to step S14, in which a dielectric thin layer, a control gate thin layer, and a hard mask layer are formed above the substrate. In this embodiment, the dielectric thin layer 310 is conformally formed on the 2 structure of 3 . In some embodiments, the dielectric thin layer 310 and the tunneling thin layer 180’ may have the same or different materials. In other words, for example, the dielectric thin layer 310 may include a dielectric material such as silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), high-k materials, other non-conductive materials, or combinations thereof. The dielectric thin layer 310 can be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), ozone oxidation, other suitable processes, or combinations thereof.

[0124] The control gate thin layer 320 is conformally formed above the dielectric thin layer 310. The control gate thin layer 320 may include polysilicon. For example, it can be formed using a suitable silicon source material and by low-pressure chemical vapor deposition (LPCVD) methods, chemical vapor deposition methods, and physical vapor deposition sputtering methods. If desired, the control gate thin layer 320 can be ion-implanted to the desired conduction type. It should be understood that the control gate thin layer 320 can include other gate materials such as metals, metal alloys, single-crystalline silicon, or combinations thereof.

[0125] The hard mask layer 330 is conformally formed above the control gate thin layer 320. The hard mask layer 330 can include a single layer or multiple layers. In some embodiments, the hard mask layer 330 includes SiN / Si 2Layers of / SiN stack or other suitable materials. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), ozone oxidation, other suitable processes, or combinations thereof can be used to form the hard mask layer 330.

[0126] Refer to Figure 1B and Figures 16A to 16D where Figure 16A is a top view of a semiconductor device, Figure 16B is a cross-sectional view taken along line B-B of Figure 16A and Figure 16C is a cross-sectional view taken along line C-C of Figure 16A and Figure 16D is a cross-sectional view taken along line D-D of Figure 16A Method M proceeds to step S15, in which the dielectric thin layer, the control gate thin layer, and the hard mask layer are patterned to form a gate stack above the cell region of the substrate. In this embodiment, Figure 15A and 15B The hard mask layer 330, the control gate thin layer 320, the dielectric thin layer 310, the floating gate thin layer 190', and the tunneling thin layer 180' of Figure 15A and 15B are patterned to form a plurality of gate stacks 300 on the cell region 112 of the substrate 110 and semiconductor stacks 300' on the peripheral region 114 and the transition region 116. The Figure 15A and 15B hard mask layer 330 of Figure 15A and 15B can be patterned to form a plurality of hard masks 332 and a hard mask layer 334. The Figure 15A and 15B control gate thin layer 320 of Figure 15A and 15B can be patterned to form a plurality of control gates 322 and a control gate layer 324. The

[0127] dielectric thin layer 310 of Figure 15A and 15B can be patterned to form a plurality of dielectric layers 312 and a dielectric layer 314. The Figure 15A and 15B floating gate thin layer 190' of Figure 15A and 15B can be patterned to form a plurality of floating gates 192. In some embodiments, the floating gate 192 can be thinner than the control gate 322. The Figure 15A and 15B tunneling thin layer 180' of

[0127] can be patterned to form a plurality of tunneling layers 182.

[0127] In some embodiments, at least one gate stack 300 includes a tunneling layer 182, a floating gate 192, a dielectric layer 312, a control gate 322, and a hard mask 332. At least one gate stack 300 may further include a pair of spacers 340, which are disposed on the floating gate 192 and on opposite sides of the dielectric layer 312, the control gate 322, and the hard mask 332. For clarity, the spacers 340 are shown inFigure 16B and 16C shown in, but omitted in Figure 16A In some embodiments, the spacer 340 includes an inner silicon oxide layer, an intermediate silicon nitride layer, and an outer silicon oxide layer. The semiconductor stack 300' may include a dielectric layer 314, a control gate layer 324 on the dielectric layer 314, and a hard mask layer 334 above the control gate layer 324.

[0128] Referring to Figure 1B and Figure 17A and 17B , wherein Figure 17A and 17B the cross-sectional positions of are the same as those of Figure 16B and 16C respectively. The method M proceeds to step S16, where spacers are formed on opposite sides of the gate stack. In this embodiment, spacers 345 are formed on opposite sides of the gate stack 300. In some embodiments, the spacer 345 is a high-temperature oxide layer or other suitable dielectric layer. In some embodiments, a thin dielectric layer may be conformally formed on the structure of Figures 16A to 16C , and an etching process (e.g., a dry etching process) is performed to remove the horizontal portion of the thin dielectric layer, thereby forming the spacer 345.

[0129] Referring to Figure 1B and Figure 18A and 18B , Figure 18A and Figure 18B the cross-sectional positions of are the same as those of Figure 17A and 17B respectively. The method M proceeds to step S17, where a source region is formed between two adjacent gate stacks. In this embodiment, the spacer 345 between two adjacent gate stacks 300 is removed, and a source region SR is formed between the two adjacent gate stacks 300. For example, a patterned photoresist layer is formed by a combination of spin coating, exposure, and development processes, thereby exposing the region of the substrate 110 between the adjacent gate stacks 300. Then, the exposed spacer 345 is removed, and ions are implanted into the region to form the source region SR. A common source (CS) dielectric layer SRD is formed above the source region SR. The common source dielectric layer SRD may be a dielectric isolation structure and may be formed by oxidizing the substrate 110, other suitable processes, or a combination thereof. Then, the patterned photoresist layer is removed, and the removal method may be performed, for example, by solvent stripping or plasma ashing.

[0130] Referring to Figure 1B and Figures 19A to 19C , Figure 19A is a top view of the semiconductor device,Figure 19B is a cross-sectional view taken along line B-B of Figure 19A , and Figure 19C is a cross-sectional view taken along line C-C of Figure 19A . Method M proceeds to step S18, where an erase gate and a select gate are formed on opposite sides of the gate stack. In the present embodiment, on a first side of the gate stack 300, a plurality of select gate dielectric layers 352 and a plurality of select gates (or word lines) 362 are formed, and on a second side of the gate stack 300, a plurality of erase gates 364 are formed. For example, a dielectric layer is formed on the substrate 110, e.g., by thermal oxidation, chemical vapor deposition, or atomic layer deposition, a conductive layer is deposited on the dielectric layer, and then the conductive layer is patterned or etched back. Next, a plurality of hard masks 370 are respectively formed on the patterned conductive layer, and another etching process is performed to pattern the patterned conductive layer and the dielectric layer using the hard mask 370 as a mask to form the erase gate 364, the select gate 362, and the select gate dielectric layer 352. In some embodiments, the erase gate 364 and the select gate 362 may be made of polysilicon or other suitable materials. If desired, the erase gate 364 and the select gate 362 may be ion implanted to the desired conduction type. For example, the erase gate 364 and the select gate 362 may be in-situ doped. In some embodiments, the select gate dielectric layer 352 may include silicon oxide, silicon nitride, silicon oxynitride, other non-conductive materials, or combinations thereof.

[0131] Referring to Figure 1B and Figure 20A and 20B , where Figure 20A and 20B the cross-sectional positions of Figure 19B and 19C are the same as the cross-sectional positions of Figure 19B and 19C respectively. Method M proceeds to step S19, in which semiconductor devices are formed in the surrounding and transition regions. In the present embodiment, the semiconductor stack 300' of Figure 19B and Figure 19C is removed to expose the patterned mask layer 130' (see Figure 19A and 19B)The substrate 110 is exposed to expose the peripheral region 114. Then, the isolation features 146 and 144 are recessed until the upper surfaces of the isolation members 146 and 184 are substantially flush with the substrate 110 in the peripheral region 114. At least one semiconductor device 400 is formed above the substrate 110 in the peripheral region 114, and at least one dummy semiconductor device 400' is formed above the isolation feature 146. In some embodiments, the semiconductor device 400 may be a transistor (e.g., a high-κ metal gate (HKMG) transistor and / or a logic transistor), and the present disclosure is not limited thereto. In some embodiments, the dummy semiconductor device 400' and the semiconductor device 400 are made of the same material.

[0132] In some embodiments, one or more ion implantation processes are performed on the substrate 110 to form a drain region DR in the cell region 112 and a source / drain region 400SD in the peripheral region 114. The drain region DR and the source / drain region 400SD may be formed by the same or different ion implantation processes. In some embodiments, the gate stack 300 and the select gate 362 are disposed at a position between the source region SR and the drain region DR, and the drain region DR is disposed adjacent to the select gate 362, respectively.

[0133] Refer to Figure 1B and Figures 21A to 21C , Figure 21A is a top view of the semiconductor device, Figure 21B is a cross-sectional view taken along line B-B of Figure 21A , Figure 21C is a cross-sectional view taken along line C-C of Figure 21A The method M proceeds to step S20, in which an etch stop layer and an interlayer dielectric layer are formed. In the present embodiment, in Figure 20A and 20BAn etch stop layer 510 is conformally formed over the structure, and an interlayer dielectric (ILD) 520 is formed over the etch stop layer 510. Then, a chemical mechanical polishing (CMP) process is performed to make the upper surface of the interlayer dielectric 520 flush with the upper surfaces of the erase gate 364, the control gate 322, the select gate 362 of the memory cell 10, and the upper surface of the gate stack 410 of the semiconductor device 400. In some embodiments, the gate stack 410 may include a gate dielectric, a work function metal layer over the gate dielectric, and a metal over the work function metal layer. In some embodiments, the gate stack 410 may include a metal. Thereby, a plurality of memory cells 10 are formed. At least one memory cell 10 includes two gate stacks 300, one erase gate 364, two select gates 362, one source region SR, and two drain regions DR. Two adjacent memory cells 10 share one drain region DR.

[0134] In Figures 21A to 21C the floating gate 192 of the memory cell 10 is formed without planarization, thereby preventing the dishing and wear problems of the floating gate 192 caused by the planarization process, and then preventing the over-polishing of the floating gate 192 at the center of the array, thereby improving the thickness uniformity of the floating gates in the center and the edge of the array. Therefore, the floating gates 192 of the memory cells 10 in the center and the edge of the cell region 112 have substantially the same thickness. In some embodiments, the tunneling layer 182 is formed by oxidation method and thus has a uniform thickness. In other words, the tunneling layer 182 has substantially the same thickness. With this configuration, the memory cells 10 can have substantially the same electrical properties, thereby improving the yield. The term "substantially" as used herein may be used to modify any quantitative representation, which may allow the quantitative variation without changing the underlying function associated therewith. It should be noted that Figures 21A to 21C the number of the memory cells 10 in

[0135] In Figures 21B to 21CIn [the figure], the isolation features 146 and 226 in the transition region 116 are connected to form an isolation feature. The substrate 110 has a protruding portion 116p between the first part and the second part of the isolation feature (e.g., between the isolation features 146 and 226). In some embodiments, the upper surface 146T of the first part of the isolation feature (e.g., the isolation feature 146) has a first part 146TA and a second part 146TB located between the first part 146TA and the second part of the isolation feature (e.g., the isolation feature 226). The second part 146TB can be lower than the first part 146TA. For example, the second part 146TB can be substantially flush with the upper surface 226T of the second part of the isolation feature (e.g., the isolation feature 226) and the upper surface 222T of the isolation feature 222. In some embodiments, the first part 146TA can be substantially flush with the upper surface 144T of the isolation feature 144.

[0136] In some embodiments, the lower surface 146B of the first part of the isolation feature (e.g., the isolation feature 146) and the lower surface 226B of the second part of the isolation feature (e.g., the isolation feature 226) are at different heights. In some embodiments, the dummy semiconductor device 400' is above the first part 146TA of the upper surface 146T of the first part of the isolation feature (e.g., the isolation feature 146), while the semiconductor stack 300" is above the second part of the isolation feature (e.g., the isolation feature 226).

[0137] Figures 22A to Figure 22B is a cross-sectional view of a semiconductor device according to some embodiments. Figure 22A and 22B The cross-sectional positions of Figure 21B and 21C are the same as the cross-sectional positions of Figures 22A to Figure 22B The difference between the semiconductor device of Figures 21B to 21C and the semiconductor device of Figures 10A to 10C is the topography of the isolation features 146 and 226. In this embodiment, the trench 116T' (as shown in Figures 22A to Figure 22B exposes the entire sidewall of the isolation feature 146, and the isolation feature 226 formed in the trench 116T' contacts the sidewall of the isolation feature 146 without any part of the substrate 110 intervening therebetween. Figures 22A to Figure 22B The other relevant structural details of the semiconductor device of Figures 21A to 21C are similar to those of the semiconductor device of

[0138] Figures 23A to Figure 23B is a cross-sectional view of a semiconductor device according to some embodiments. Figure 23A and 23B The cross-sectional positions of Figure 21B and 21C are the same as the cross-sectional positions of Figures 23A to Figure 23BSemiconductor devices and Figures 21B to 21C The difference between the semiconductor devices is that in the present embodiment, lower surfaces 144B and 146B of isolation features 144 and 146 are higher than lower surfaces 222B and 226B of isolation features 222 and 226 . Figures 23A to Figure 23B Other relevant structural details of the semiconductor device are similar to Figures 21A to 21C The semiconductor device is described above, and therefore the description thereafter will not be repeated.

[0139] Figures 24A to 24B is a cross-sectional view of a semiconductor device according to some embodiments. Figure 24A and 24B The cross-sectional positions are Figure 21B and 21C The cross-sectional positions are the same. Figures 24A to 24B Semiconductor devices and Figures 21B to 21C The difference between the semiconductor devices 100 and 101 is that in the present embodiment, the lower surface 146B of the isolation feature 146 is substantially flush with the lower surfaces 222B and 226B of the isolation features 222 and 226 . Figure 24A and 24B Other relevant structural details of the semiconductor device are similar to Figures 21A to 21C The semiconductor device is described above, and therefore the description thereafter will not be repeated.

[0140] The present disclosure is applicable to the manufacture of embedded flash memory. Based on the above discussion, it can be seen that the present disclosure provides multiple advantages. However, it should be understood that other embodiments may provide additional advantages, and not all advantages must be disclosed here, and not all embodiments require special advantages. One of the advantages is that the floating gate is formed without planarization, thereby preventing the disk-shaped depression and wear problem of the floating gate caused by the planarization process, thereby preventing the floating gate in the center of the array from being over-polished, thereby improving the thickness uniformity of the floating gate in the center and edge of the array and improving productivity. Another advantage is that the patterned hard mask used to protect the peripheral area during the substrate recessing process can also be used to protect the peripheral area in other processes (such as oxidizing the surface layer of the substrate to form a tunneling layer, patterning the floating gate layer, forming a groove in the cell area and / or recessing the isolation feature), thereby saving the number of masks.

[0141] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes: forming a first isolation feature in a peripheral region of a substrate; after forming the first isolation feature, recessing a unit region of the substrate; after recessing the unit region of the substrate, forming a second isolation feature in the unit region of the substrate; forming a plurality of control gates on the unit region of the substrate; and forming a gate stack on the peripheral region of the substrate.

[0142] In some embodiments, the method further includes forming a third isolation feature in a transition region of the substrate when forming the first isolation feature, where the transition region is located between the cell region and the peripheral region.

[0143] In some embodiments, the method further includes forming a fourth isolation feature in the transition region of the substrate when forming the second isolation feature, where the fourth isolation feature is connected to the third isolation feature.

[0144] In some embodiments, recessing the cell region of the substrate causes a portion of the transition region of the substrate to be recessed and exposes a sidewall of the third isolation feature.

[0145] In some embodiments, forming the fourth isolation feature causes the fourth isolation feature to be formed in the recessed portion of the transition region of the substrate.

[0146] In some embodiments, the method further includes forming a mask layer on the peripheral region of the substrate before recessing the cell region of the substrate, where the mask layer covers the first isolation feature and exposes the cell region of the substrate.

[0147] In some embodiments, forming the second isolation feature includes: forming a trench in the cell region of the substrate; filling the trench with a dielectric material; and planarizing the dielectric material until reaching the mask layer covering the first isolation feature.

[0148] In some embodiments, the method further includes recessing the second isolation feature after forming the second isolation feature while the mask layer maintains coverage of the first isolation feature.

[0149] According to some embodiments of the present disclosure, a method of manufacturing a semiconductor device includes: forming a first isolation feature in a peripheral region of a substrate; after forming the first isolation feature, depositing a floating gate layer on the peripheral region and a cell region of the substrate; forming a groove in the floating gate layer and the cell region of the substrate; forming a second isolation feature in the groove; forming a plurality of control gates on the floating gate layer on the cell region of the substrate; and forming a gate stack on the peripheral region of the substrate.

[0150] In some embodiments, the method further includes recessing the cell region of the substrate after forming the first isolation feature.

[0151] In some embodiments, the method further includes forming a first mask layer on the peripheral region of the substrate before depositing the floating gate layer, where the first mask layer covers the first isolation feature and exposes the cell region of the substrate.

[0152] In some embodiments, forming the trench includes forming a second mask layer over the floating gate layer and the cell region of the substrate; and etching the floating gate layer and the cell region of the substrate through the second mask layer.

[0153] In some embodiments, the method further includes recessing the second isolation feature while the first mask layer remains covering the first isolation feature and the second mask layer covers the floating gate layer.

[0154] In some embodiments, the method further includes removing the first mask layer and the second mask layer after forming the second isolation feature; and recessing the second isolation feature after removing the first mask layer and the second mask layer.

[0155] In some embodiments, the method further includes removing a portion of the floating gate layer on the peripheral region of the substrate when forming the groove in the floating gate layer and the cell region of the substrate.

[0156] In some embodiments, the method further includes forming a tunneling layer on the substrate before depositing the floating gate layer, wherein forming the groove causes the groove to be formed in the tunneling layer.

[0157] According to some embodiments of the present disclosure, a semiconductor device includes a substrate, an isolation feature, a memory cell, and a semiconductor device. The substrate has a cell region, a peripheral region, and a transition region between the cell region and the peripheral region. The isolation feature is located in the transition region, wherein the substrate includes a protruding portion located between a first portion and a second portion of the isolation feature, the second portion is located between the first portion and the cell region, and an upper surface of the first portion of the isolation feature has a first portion and a second portion lower than the first portion, and the second portion is located between the first portion and the second portion of the isolation feature. The memory cell is located on the cell region of the substrate. The semiconductor device is located on the peripheral region of the substrate.

[0158] In some embodiments, a lower surface of the first portion of the isolation feature and a lower surface of the second portion of the isolation feature are at different heights.

[0159] In some embodiments, the semiconductor device further includes a dummy semiconductor device located above the first portion of the upper surface of the first portion of the isolation feature.

[0160] In some embodiments, the semiconductor device further includes a semiconductor stack located above the second portion of the isolation feature.

[0161] The foregoing outlines the features of multiple embodiments, and those of ordinary skill in the art can better understand various aspects of this disclosure. Those of ordinary skill in the art should understand that this disclosure can be used as a basis for designing or modifying other processes or structures to achieve the same purposes and / or obtain the same advantages as those mentioned in the embodiments. Those of ordinary skill in the art should also understand that these equivalent structures do not exceed the spirit and scope of this disclosure, and various changes, substitutions, and transformations can be made. Herein, the spirit and scope of this disclosure cover these changes, substitutions, and transformations.

Claims

1. A method of manufacturing a semiconductor device, characterized in that, comprising: etching a first trench in a peripheral region of a substrate; filling the first trench with a first dielectric material to form a first isolation feature in the first trench; after filling the first trench with the first dielectric material, recessing a cell region of the substrate; after recessing the cell region of the substrate, forming a second isolation feature in the cell region of the substrate; forming a plurality of control gates on the cell region of the substrate; and forming a gate stack on the peripheral region of the substrate.

2. The method according to claim 1, characterized in that, further comprising: when etching the first trench, etching a transition trench in a transition region of the substrate, wherein the transition region is located between the cell region and the peripheral region; and filling the transition trench with the first dielectric material to form a third isolation feature in the transition trench.

3. The method according to claim 2, characterized in that, further comprising: when forming the second isolation feature, forming a fourth isolation feature in the transition region of the substrate, wherein the fourth isolation feature is connected to the third isolation feature.

4. The method according to claim 3, characterized in that, wherein recessing the cell region of the substrate causes a part of the transition region of the substrate to be recessed and exposes a sidewall of the third isolation feature.

5. The method according to claim 4, characterized in that, wherein forming the fourth isolation feature causes the fourth isolation feature to be formed in the recessed part of the transition region of the substrate.

6. The method according to claim 1, characterized in that, further comprising: forming a mask layer on the peripheral region of the substrate before recessing the cell region of the substrate, wherein the mask layer covers the first isolation feature and exposes the cell region of the substrate.

7. The method according to claim 6, characterized in that, wherein forming the second isolation feature comprises: etching a second trench in the cell region of the substrate; filling the second trench with a second dielectric material to form a second isolation feature in the second trench; planarizing the second dielectric material until reaching the mask layer covering the first isolation feature.

8. The method according to claim 6, characterized in that, further comprising: after forming the second isolation feature, recessing the second isolation feature while the mask layer maintains covering the first isolation feature.

9. A method of manufacturing a semiconductor device, characterized in that, comprising: forming a first isolation feature in a peripheral region of a substrate; after forming the first isolation feature, depositing a floating gate layer on the peripheral region and a cell region of the substrate, wherein a part of the floating gate layer is located on an upper surface of the first isolation feature; forming a groove in the floating gate layer and the cell region of the substrate; forming a second isolation feature in the groove; forming a plurality of control gates on the floating gate layer on the cell region of the substrate; and forming a gate stack on the peripheral region of the substrate.

10. The method according to claim 9, wherein, further comprising: after forming the first isolation feature, recessing the cell region of the substrate.

11. The method according to claim 9, wherein, further comprising: before depositing the floating gate layer, forming a first mask layer on the peripheral region of the substrate, wherein the first mask layer covers the first isolation feature and exposes the cell region of the substrate.

12. The method according to claim 11, wherein, forming the groove comprises: forming a second mask layer on the floating gate layer and the cell region of the substrate; and etching the floating gate layer and the cell region of the substrate via the second mask layer.

13. The method according to claim 12, wherein, further comprising: when the first mask layer maintains covering the first isolation feature and the second mask layer covers the floating gate layer, recessing the second isolation feature.

14. The method according to claim 12, wherein, further comprising: after forming the second isolation feature, removing the first mask layer and the second mask layer; and after removing the first mask layer and the second mask layer, recessing the second isolation feature.

15. The method according to claim 9, wherein, further comprising: when forming the groove in the floating gate layer and the cell region of the substrate, removing the portion of the floating gate layer.

16. The method according to claim 9, wherein, further comprising: before depositing the floating gate layer, forming a tunneling layer on the substrate, wherein forming the groove causes the groove to be formed in the tunneling layer.

17. A semiconductor device, wherein, comprising: a substrate having a cell region, a peripheral region, and a transition region between the cell region and the peripheral region; an isolation feature located in the transition region, wherein the substrate includes a protruding portion located between a first portion and a second portion of the isolation feature, the second portion being located between the first portion and the cell region, and an upper surface of the first portion of the isolation feature has a first local portion, a second local portion lower than the first local portion, and a connecting local portion, and the second local portion is located between the first local portion and the second portion of the isolation feature, the connecting local portion extends downward from an edge of the first local portion to a bottom of the connecting local portion, the whole of the connecting local portion is laterally separated from the protruding portion, and the second local portion extends laterally from the bottom of the connecting local portion to a position directly above the protruding portion; a memory cell located on the cell region of the substrate; and a semiconductor device located on the peripheral region of the substrate.

18. The semiconductor device according to claim 17, wherein, a lower surface of the first portion of the isolation feature and a lower surface of the second portion of the isolation feature are at different heights.

19. The semiconductor device according to claim 17, wherein, It further includes a dummy semiconductor device located above the first portion of the upper surface of the first part of the isolation feature.

20. The semiconductor device according to claim 17, wherein, it further includes a semiconductor stack located above the second part of the isolation feature.

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