Semiconductor Structure and Method for Forming the Same

Abstract

An embodiment of the present invention provides a semiconductor structure and a method for forming the same. The semiconductor structure includes a first all-around gate field effect transistor located on a substrate and a first fin field effect transistor adjacent to the first all-around gate field effect transistor. The first all-around gate field effect transistor includes a plurality of first nanostructures and a first gate stack surrounding the first nanostructures. The first fin field effect transistor includes a first fin structure and a second gate stack located on the first fin structure. The semiconductor structure further includes a gate cutting component inserted between the first gate stack of the first all-around gate field effect transistor and the second gate stack of the first fin field effect transistor.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor structure, and more particularly to a semiconductor structure having isolation components and a method of forming the same. Background Art

[0002] The electronics industry has an ever-increasing demand for smaller, faster electronic devices that can simultaneously support more and more complex and sophisticated functions. Therefore, manufacturing low-cost, high-performance, and low-power integrated circuits (ICs) is an ongoing trend in the semiconductor industry. To date, these goals have been largely achieved by shrinking the size of semiconductor integrated circuits (e.g., the minimum feature size), thereby increasing production efficiency and reducing associated costs. However, this miniaturization has also made semiconductor manufacturing processes more complex. Therefore, achieving continuous development of semiconductor integrated circuits and devices requires similar development in semiconductor manufacturing processes and technologies.

[0003] Recently, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing OFF-state current, and reducing short-channel effect (SCE). One type of multi-gate device that has been introduced is the gate-all-around (GAA) transistor. The name gate-all-around device comes from the fact that its gate structure can extend around the channel region, thus opening the channel from two or four sides. Gate-all-around devices are compatible with traditional complementary metal oxide semiconductor (CMOS) processes, and this structure allows them to be significantly scaled down while maintaining gate control and mitigating short-channel effects. In traditional processes, gate-all-around devices provide channels in silicon nanowires. However, the manufacturing integration of gate-all-around components around nanowires can be challenging. For example, although current methods are satisfactory in many respects, continuous improvement is still needed. Summary of the Invention

[0004] Embodiments of the present invention aim to provide a semiconductor structure and a method of forming the same to solve at least one of the above problems.

[0005] Embodiments of the present invention provide a semiconductor structure. The semiconductor structure includes a first all-around gate field-effect transistor located on a substrate and a first fin field-effect transistor adjacent to the first all-around gate field-effect transistor. The first all-around gate field-effect transistor includes a plurality of first nanostructures and a first gate stack surrounding the first nanostructures. The first fin field-effect transistor includes a first fin structure and a second gate stack located on the first fin structure. The semiconductor structure further includes a gate cutting component inserted between the first gate stack of the first all-around gate field-effect transistor and the second gate stack of the first fin field-effect transistor.

[0006] Embodiments of the present invention provide a semiconductor structure. The semiconductor structure includes a first all-around gate field-effect transistor, a second all-around gate field-effect transistor, and a first fin field-effect transistor located on a substrate. The first all-around gate field-effect transistor includes a plurality of first nanostructures and a first gate stack surrounding the first nanostructures. The second all-around gate field-effect transistor includes a plurality of second nanostructures and a second gate stack surrounding the second nanostructures. The first fin field-effect transistor includes a first fin structure and a third gate stack located on the first fin structure. The semiconductor structure further includes an isolation component inserted between the first nanostructures of the first all-around gate field-effect transistor and the second nanostructures of the second all-around gate field-effect transistor. The semiconductor structure further includes a first gate cutting component of the isolation component inserted between the first gate stack of the first all-around gate field-effect transistor and the third gate stack of the first fin field-effect transistor.

[0007] Embodiments of the present invention provide a method for forming a semiconductor structure. The method includes sequentially forming a first semiconductor layer and a second semiconductor layer on a substrate, etching the second semiconductor layer to form a depression in a first region of the substrate, alternately stacking a plurality of third semiconductor layers and a plurality of fourth semiconductor layers on the first semiconductor layer from the depression, patterning the third semiconductor layer, the fourth semiconductor layer, and the first semiconductor layer to form a first fin structure in the first region of the substrate, and patterning the second semiconductor layer and the first semiconductor layer to form a second fin structure in a second region of the substrate, removing the fourth semiconductor layer and the first semiconductor layer from the first fin structure to form a plurality of nanostructures from the third semiconductor layer of the first fin structure, and removing the first semiconductor layer from the second fin structure to form a floating fin element from the second semiconductor layer of the second fin structure, forming a first gate stack across the nanostructures and the floating fin element, and after forming the first gate stack, forming a first gate cutting component through the first gate stack.

[0008] The beneficial effects of the present invention are that the semiconductor structure may include a first all-around gate field-effect transistor and a first fin field-effect transistor adjacent to the first all-around gate field-effect transistor. The first all-around gate field-effect transistor may include a first nanostructure and a first gate stack surrounding the first nanostructure. The first fin field-effect transistor may include a first floating fin element and a second gate stack located above the first floating fin element. The semiconductor structure may further include a gate cutting component that may be inserted between the first gate stack of the first all-around gate field-effect transistor and the second gate stack of the first fin field-effect transistor. Therefore, with the semiconductor structure according to the embodiments of the present invention, for an integrated circuit including different types of devices, lower process difficulty and greater design flexibility can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The content of the embodiments of the present invention can be better understood through the following detailed description in conjunction with the accompanying drawings. It should be emphasized that, according to industrial standard practices, many components (features) are only for illustrative purposes and are not drawn to scale. In fact, for the sake of clear discussion, the sizes of various components may be arbitrarily increased or decreased.

[0010] Figure 1 is a perspective schematic diagram showing a semiconductor structure according to some embodiments of the present invention.

[0011] Figure 2A 、 Figure 2B 、 Figure 2C 、 Figure 2D-2 、 Figures 2E-2 to 2E-5 、 Figures 2F-2 to 2F-5 、 Figures 2G-2 to 2G-5 、 Figures 2H-2 to 2H-6 、 Figures 2I-2 to 2I-6 、 Figures 2J-2 to 2J-4 and Figures 2K-2 to 2K-4 are cross-sectional schematic diagrams showing the semiconductor structure at various intermediate stages of formation according to some embodiments of the present invention.

[0012] Figure 2D-1 、 Figure 2E-1 、 Figure 2F-1 、 Figure 2G-1 、 Figure 2H-1 、 Figure 2I-1 、 Figure 2J-1 and Figure 2K-1 are top-view schematic diagrams showing the semiconductor structure at various intermediate stages of formation according to some embodiments of the present invention.

[0013] Figure 3 is a flowchart showing a method of forming a semiconductor structure according to some embodiments of the present invention.

[0014] Figures 4A - 4D is a cross-sectional schematic diagram showing the formation of a cutting trench according to some embodiments of the present invention.

[0015] Figures 5A - 5D FIG. 4 is a cross-sectional schematic diagram showing the formation of a gate cutting opening according to some embodiments of the present invention.

[0016] Figure 6-1 , Figure 7-1 , Figure 8-1 , Figure 9-1 , Figure 10-1 , Figure 11-1 , Figure 12-1 , Figure 13-1 , Figure 14-1 , Figure 15-1 , Figure 16-1 , Figure 17-1 , Figure 18-1 , Figure 19-1 , Figure 20-1 , Figure 21-1 as well as Figure 22-1 FIG. 4 is a schematic top view showing various modifications of a semiconductor structure according to some embodiments of the present invention.

[0017] Figure 6-2 and Figure 6-3 , Figures 7-2 to 7-4 , Figure 8-2 , Figure 9-2 , Figure 10-2 , Figure 11-2 , Figure 12-2 , Figure 13-2 , Figure 14-2 , Figure 14-3 , Figure 15-2 , Figure 16-2 , Figure 17-2 , Figure 18-2 , Figure 19-2 , Figure 20-2 , Figure 21-2 as well as Figure 22-2 2 is a schematic cross-sectional view showing various modifications of a semiconductor structure according to some embodiments of the present invention.

[0018] The reference numerals are as follows:

[0019] 12: Semiconductor structure

[0020] 14:Semiconductor structure

[0021] 16: Semiconductor structure

[0022] 18:Semiconductor structure

[0023] 20:Semiconductor structure

[0024] 22:Semiconductor structure

[0025] 24:Semiconductor structure

[0026] 26:Semiconductor structure

[0027] 28: Semiconductor structure

[0028] 30: Semiconductor structure

[0029] 32: Semiconductor structure

[0030] 34: Semiconductor structure

[0031] 36: Semiconductor structure

[0032] 38: Semiconductor structure

[0033] 40: Semiconductor structure

[0034] 42: Semiconductor structure

[0035] 44: Semiconductor structure

[0036] 46: Semiconductor structure

[0037] 102: Substrate

[0038] 103: Lower fin element

[0039] 103’: Lower fin element

[0040] 104: First semiconductor layer

[0041] 104’: First semiconductor layer

[0042] 106: Second semiconductor layer

[0043] 106’: Second semiconductor layer

[0044] 108: Depression

[0045] 110: Third semiconductor layer

[0046] 110’: Third semiconductor layer

[0047] 112: Fourth semiconductor layer

[0048] 112’: Fourth semiconductor layer

[0049] 118: First fin structure

[0050] 120: Second fin structure

[0051] 122: Trench

[0052] 124: Isolation structure

[0053] 126:Dummy gate structure

[0054] 126 1 : Gate structure

[0055] 126 2 : Gate structure

[0056] 126 3 : Gate structure

[0057] 126 4 : Gate structure

[0058] 128: dummy gate dielectric layer

[0059] 130: dummy gate electrode layer

[0060] 132: gate spacer

[0061] 134: source / drain component

[0062] 136: source / drain component

[0063] 138: interlayer dielectric

[0064] 140: patterned mask layer

[0065] 144: cutting trench

[0066] 144A: first bottom surface

[0067] 144B: second bottom surface

[0068] 146: isolation component

[0069] 148: dielectric liner

[0070] 150: dielectric fill layer

[0071] 152 1 : gate trench

[0072] 152 2 : gate trench

[0073] 152 3 : gate trench

[0074] 152 4 : gate trench

[0075] 152: gate trench

[0076] 154: gap

[0077] 156: gap

[0078] 158: inner spacer

[0079] 160: final gate stack

[0080] 160 1 : final gate stack

[0081] 160 2 : Final gate stack

[0082] 160 3 : Final gate stack

[0083] 160 4 : Final gate stack

[0084] 162: Interface layer

[0085] 164: High-k gate dielectric layer

[0086] 166: Metal gate electrode layer

[0087] 168: Patterned mask layer

[0088] 170: Opening

[0089] 172: Gate cut opening

[0090] 174: Gate cut component

[0091] 174A: Gate cut component

[0092] 174B: Gate cut component

[0093] 200: First region

[0094] 300: Second region

[0095] 402: Hard mask layer

[0096] 404: Bottom layer

[0097] 406: Intermediate layer

[0098] 408: Top layer

[0099] 410: Opening

[0100] 412: Opening

[0101] 414: Cutting trench

[0102] 502: Metal protection layer

[0103] 504: Hard mask layer

[0104] 506: Bottom layer

[0105] 508: Intermediate layer

[0106] 510: Top layer

[0107] 514: Opening

[0108] 514’: Opening

[0109] 514s: Opening

[0110] 516: Dielectric layer

[0111] 518: Gate cut opening

[0112] 1000: Method

[0113] 1002: Step

[0114] 1004: Step

[0115] 1006: Step

[0116] 1008: Step

[0117] 1010: Step

[0118] 1012: Step

[0119] 1014: Step

[0120] 1016: Step

[0121] 1018: Step

[0122] 1020: Step

[0123] 1022: Step

[0124] 1024: Step

[0125] 1026: Step

[0126] 1028: Step

[0127] 1030: Step

[0128] CH: Channel region

[0129] SD: Source / drain region

[0130] T1: All-around gate field-effect transistor

[0131] T2: Fin field-effect transistor Detailed implementation manner

[0132] The following content provides multiple different embodiments or examples for implementing different components of the embodiments of the present invention. Specific embodiments or examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, when it is mentioned in the description that the first component is formed on (or above) the second component, it may include embodiments where the first and second components are in direct contact, or it may include embodiments where additional components are formed between the first and second components such that the first and second components are not in direct contact. Additionally, the embodiments of the present invention may repeat element symbols and / or letters in many examples. These repetitions are for the purposes of simplicity and clarity, and they do not themselves represent a specific relationship between the various embodiments and / or configurations being discussed.

[0133] Some variations of the embodiments are described herein. In the various schematic diagrams and illustrated embodiments, like element symbols are used to represent like elements. It should be noted that additional steps may be provided before, during, and after the method, and for some other method embodiments, some steps may be replaced or omitted.

[0134] Furthermore, when describing a quantity or range using terms such as "about," "approximate," or similar terms, the purpose of these terms is to cover quantities within a reasonable range, such as within + / - 10% of the quantity mentioned, or other values understood by those skilled in the art. For example, the term "about 5 nanometers (nm)" covers a size range from 4.5 nanometers to 5.5 nanometers.

[0135] The following described gate-all-around (GAA) transistor structure can be patterned by any suitable method. For example, one or more photolithography processes can be used to pattern the gate-all-around transistor structure, and the photolithography process includes double patterning or multi-patterning processes. Generally, the double patterning or multi-patterning process combines photolithography with self-aligned processes, which can create patterns with smaller pitch compared to the patterns obtained by direct single photolithography processes. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed beside the patterned sacrificial layer using a self-aligned process. Then the sacrificial layer is removed, and the remaining spacers are used to pattern the gate-all-around structure.

[0136] Fin field effect transistors (FinFETs) are widely used in integrated circuits (ICs) that include different types of devices, such as logic devices, memory devices (e.g., static random access memory (SRAM)), etc. Compared to FinFETs, gate-all-around field effect transistors can exhibit improved gate control over the channel region, such as lower drain-induced barrier lowering (DIBL). Embodiments of the present invention relate to structures and formation methods, in which a hybrid structure including gate-all-around field effect transistors and FinFETs on the same semiconductor substrate (or chip) is provided. In addition, the hybrid structure provided by embodiments of the present invention further includes isolation components and gate cutting components, such that these transistors are electrically isolated from each other. Therefore, through the semiconductor structure of embodiments of the present invention, for integrated circuits including different types of devices, lower process difficulty and greater design flexibility can be achieved.

[0137] Figure 1 FIG. 4 is a perspective schematic diagram showing a semiconductor structure according to some embodiments of the present invention. According to some embodiments, a semiconductor structure 12 is provided, as Figure 1 shown. According to some embodiments, the semiconductor structure 12 includes a substrate 102 and a first fin structure 118 and a second fin structure 120 on the substrate 102. For example, the first fin structure 118 can be used to form a gate-all-around field effect transistor (GAA FET) device, and the second fin structure 120 can be used to form a fin field effect transistor (FinFET) device.

[0138] To better understand the semiconductor structure, Figure 1 an X-Y-Z reference coordinate system is shown, which can be used in subsequent figures. The X-axis and the Y-axis are substantially in the horizontal direction, and the horizontal direction is parallel to the main surface of the substrate 102. The Y-axis spans the X-axis, for example, the Y-axis is substantially perpendicular to the X-axis. The Z-axis is substantially in the vertical direction, which is perpendicular to the main surface of the substrate 102 (or the X-Y plane).

[0139] According to some embodiments, the first fin structure 118 includes a lower fin element 103 formed by a portion of the substrate 102 and an upper fin element formed by an epitaxial stack, the epitaxial stack including semiconductor layers 104, 110, and 112. According to some embodiments, the second fin structure 120 includes a lower fin element 103 formed by a portion of the substrate 102 and an upper fin element formed by an epitaxial stack, the epitaxial stack including semiconductor layers 104 and 106.

[0140] According to some embodiments, the first fin structure 118 and the second fin structure 120 extend in the X direction. That is, according to some embodiments, the first fin structure 118 and the second fin structure 120 each have a major axis direction parallel to the X direction. The X direction may also be referred to as the channel extension direction. According to some embodiments, the first fin structure 118 and the second fin structure 120 each include a channel region CH and source / drain regions SD, and the channel region CH is defined between the source / drain regions SD. Figure 1 For illustrative purposes, one channel region CH and two source / drain regions SD are shown, but not limited thereto. The number of the channel region CH and the source / drain regions SD may depend on semiconductor device design requirements and / or performance considerations. A gate structure (not shown) will be formed with a major axis direction parallel to the Y direction and extending across the channel region CH of the first fin structure 118 and the second fin structure 120. The Y direction may also be referred to as the gate extension direction.

[0141] Figures 2A to 2K-4 FIG. is a schematic diagram showing a semiconductor structure at various intermediate stages according to some embodiments of the present invention.

[0142] Figure 2A FIG. is a semiconductor structure 12 after forming a first epitaxial stack according to some embodiments of the present invention.

[0143] According to some embodiments, the semiconductor structure 12 includes a substrate 102, as Figure 2A shown. According to some embodiments, the semiconductor structure 12 includes a first region 200 and a second region 300. A fully-depleted gate field-effect transistor will be formed in the first region 200, and a fin field-effect transistor will be formed in the second region 300. In some embodiments, the first region 200 is adjacent to the second region 300.

[0144] In some embodiments, the substrate 102 is a silicon substrate. In some embodiments, the substrate 102 includes an elemental semiconductor (e.g., germanium); a compound semiconductor (e.g., gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb)); an alloy semiconductor (e.g., SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP); or a combination of the foregoing. Additionally, the substrate 102 optionally includes an epitaxial (epi) layer, which can be strained to enhance performance, can include a silicon-on-insulator (SOI) substrate, and / or have other suitable performance characteristics.

[0145] According to some embodiments, a first semiconductor layer 104 is formed on the substrate 102, and a second semiconductor layer 106 is formed on the first semiconductor layer 104, as Figure 2AAs shown. In some embodiments, the first semiconductor layer 104 has a thickness ranging from about 1.5 nanometers (nm) to about 20 nanometers. In some embodiments, the second semiconductor layer 106 has a thickness ranging from about 5 nanometers to about 300 nanometers.

[0146] According to some embodiments, the first semiconductor layer 104 has a lattice constant different from that of the second semiconductor layer 106. In some embodiments, the first semiconductor layer 104 and the second semiconductor layer 106 have different oxidation rates and / or etching rates. In some embodiments, the first semiconductor layer 104 is formed of silicon germanium (SiGe), where the percentage of germanium (Ge) in the silicon germanium ranges from about 20 atomic / % to about 50 atomic / %, and the second semiconductor layer 106 is formed of silicon. In some embodiments, the first semiconductor layer 104 and the second semiconductor layer 106 are formed using an epitaxial growth process or other techniques, such as molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE), or other suitable techniques. In some embodiments, the first semiconductor layer 104 and the second semiconductor layer 106 are collectively referred to as the first epitaxial stack.

[0147] Figure 2B According to some embodiments, a semiconductor structure 12 is shown after the formation of the recess 108.

[0148] According to some embodiments, an etching process is performed on the semiconductor structure 12 to etch the first epitaxial stack from a first region 200 of the substrate 102. According to some embodiments, a portion of the second semiconductor layer 106 in the first region 200 is removed to form the recess 108, as Figure 2B shown. In some embodiments, before the etching process, a patterned mask layer (not shown) is formed over the second semiconductor layer 106. The patterned mask layer can be a patterned photoresist layer and / or a patterned hard mask layer, and the patterned mask layer is formed to cover a second region 300 of the substrate 102 while exposing the first region 200 of the substrate 102. The etching process can be a dry etching and / or a wet etching, and in the etching process, the first semiconductor layer 104 is used as an etch stop layer. In some embodiments, the etching process is performed until a portion of the first semiconductor layer 104 in the first region 200 is exposed from the recess 108.

[0149] Figure 2C According to some embodiments, a semiconductor structure 12 is shown after the formation of the second epitaxial stack.

[0150] According to some embodiments, a third semiconductor layer 110 and a fourth semiconductor layer 112 are alternately formed from the recess 108 over the first semiconductor layer 104, as Figure 2C shown. In some embodiments, the thickness of each third semiconductor layer 110 ranges from about 1.5 nanometers to about 20 nanometers. The thickness of each fourth semiconductor layer 112 ranges from about 1.5 nanometers to about 20 nanometers. In some embodiments, the thicknesses of the third semiconductor layer 110 and the fourth semiconductor layer 112 are greater than the thickness of the first semiconductor layer 104.

[0151] According to some embodiments, the third semiconductor layer 110 has a lattice constant different from that of the fourth semiconductor layer 112 and the first semiconductor layer 104. In some embodiments, the third semiconductor layer 110 has an oxidation rate and / or an etching rate different from those of the fourth semiconductor layer 112 and the first semiconductor layer 104. In some embodiments, the third semiconductor layer 110 is formed of silicon, and the fourth semiconductor layer 112 is formed of silicon germanium (SiGe), where the percentage of germanium (Ge) in the silicon germanium ranges from about 20 atomic / % to about 50 atomic / %. In some embodiments, the composition of the third semiconductor layer 110 is substantially the same as that of the second semiconductor layer 106, and the composition of the fourth semiconductor layer 112 is substantially the same as that of the first semiconductor layer 104.

[0152] In some embodiments, the third semiconductor layer 110 and the fourth semiconductor layer 112 are formed using an epitaxial growth process (e.g., molecular beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE)) or other techniques. In some embodiments, the portions of the third semiconductor layer 110, the fourth semiconductor layer 112, and the first semiconductor layer 104 in the first region 200 are collectively referred to as the second epitaxial stack. In some embodiments, the first epitaxial stack is located in the second region 300 of the substrate 102, and the second epitaxial stack is located in the first region 200 of the substrate 102.

[0153] A planarization process, such as chemical mechanical polish (CMP), can be performed on the semiconductor structure 12 to remove the portions of the third semiconductor layer 110 and the fourth semiconductor layer 112 formed above the upper surface of the second semiconductor layer 106. The planarization process can also remove the patterned mask layer above the second semiconductor layer 106 to expose the second semiconductor layer 106. According to some embodiments, after the planarization process, the upper surface of the highest third semiconductor layer 110 is substantially coplanar with the upper surface of the second semiconductor layer 106.

[0154] Figure 2D-1 is a semiconductor structure 12 showing after the formation of the first fin structure 118 and the second fin structure 120, according to some embodiments. Figure 2D-2 is alongFigure 2D-1 Schematic cross-sectional view taken along line Y1-Y1 in

[0155] According to some embodiments, the second epitaxial stack in the first region 200, the first epitaxial stack in the second region 300, and the underlying substrate 200 are patterned to form a first fin structure 118 in the first region 200 and a second fin structure 120 in the second region 300, as shown in FIGS. 2D-1 and Figure 2D-2 As shown. According to some embodiments, the first fin structure 118 and the second fin structure 120 are active regions of the semiconductor structure 12, and the active regions will be formed as channel regions and source / drain regions of transistors (e.g., fully wrapped gate field effect transistors and fin field effect transistors). The first fin structure 118 and the second fin structure 120 extend in the X direction and are arranged substantially parallel to each other in the Y direction. That is, according to some embodiments, the first fin structure 118 and the second fin structure 120 have a major axis direction parallel to the X direction.

[0156] In some embodiments, the patterning process includes forming a patterned mask layer (not shown) over the semiconductor structure 12 and etching the portions of the semiconductor structure 12 not covered by the patterned mask layer to form trenches 122 and the first fin structure 118 and the second fin structure 120. The patterned mask layer can be a patterned photoresist layer and / or a patterned hard mask layer. The etching process can be an anisotropic etching process, such as dry etching,

[0157] In some embodiments, after the etching process, the substrate 102 has portions protruding between the trenches 122 to form lower fin elements 103 of the first fin structure 118 and the second fin structure 120. In some embodiments, the remaining portions of the second epitaxial stack (including the first semiconductor layer 104, the third semiconductor layer 110, and the fourth semiconductor layer 112 in the first region 200) form upper fin elements of the first fin structure 118 over the lower fin elements 103. In some embodiments, the remaining portions of the first epitaxial stack (including the first semiconductor layer 104 and the second semiconductor layer 106 in the second region 300) form upper fin elements of the second fin structure 120 over the lower fin elements 103.

[0158] Figure 2E-1 FIGS. are of the semiconductor structure 12 after formation of the isolation structure 124, the plurality of gate structures 126, the source / drain components 134 and 136, and the interlayer dielectric (ILD) layer 138, according to some embodiments. Figure 2E-2 , Figure 2E-3 , Figure 2E-4 and Figure 2E-5 are along Figure 2E-1Schematic cross-sectional views extracted from lines Y1-Y1, X1-X1, X2-X2, and X3-X3. For illustration, Figure 2E-1 The top view schematic only shows the first fin structure 118, the second fin structure 120, the dummy gate structure 126, and the interlayer dielectric layer 138. Other components can be seen in Figures 2E-2 to 2E-5 The cross-sectional schematic view.

[0159] According to some embodiments, an isolation structure 124 is formed over the substrate 102 and surrounds the lower fin element 103 of the first fin structure 118 and the lower fin element 103 of the second fin structure 120, as shown in Figure 2E-2 and Figure 2E-3 shown. According to some embodiments, the isolation structure 124 is configured to electrically isolate the active regions (e.g., the first fin structure 118 and the second fin structure 120), and can also be referred to as a shallow trench isolation (STI) component.

[0160] In some embodiments, the isolation structure 124 is formed of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), other suitable insulating materials, multi-layers of the foregoing, and / or combinations of the foregoing. In some embodiments, forming the isolation structure 124 includes depositing one or more layers of insulating material for the isolation structure 124 over the semiconductor structure 12 to fill the trench 122 ( Figure 2D-2 ), and planarizing the insulating material to remove the portion of the insulating material formed above the upper surfaces of the first fin structure 118 and the second fin structure 120. In some embodiments, the deposition process includes chemical vapor deposition (CVD), such as low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDP-CVD), high aspect ratio process (HARP), flowable CVD (FCVD), atomic layer deposition (ALD), other suitable methods, and / or combinations of the foregoing. The planarization process can be chemical mechanical polishing (CMP).

[0161] Thereafter, an etching process is used to etch the insulating material to form the isolation structure 124, and expose partial sidewalls of the first fin structure 118 and the second fin structure 120. The etching depth can be controlled, for example, by controlling the etching time, to obtain exposed portions of the first fin structure 118 and the second fin structure 120 having a desired height. In some embodiments, the first semiconductor layer 104 of the first fin structure 118 and the first semiconductor layer 104 of the second fin structure 120 are exposed from the isolation structure 124.

[0162] According to some embodiments, a plurality of dummy gate structures 126 are formed on the semiconductor structure 12, as Figures 2E-1 to 2E-5 shown. In some embodiments, the dummy gate structures 126 include the dummy gate structures 126 1 、126 2 、126 3 and 126 4 . In some embodiments, the dummy gate structures 126 extend in the Y direction and are arranged substantially parallel to each other in the X direction. That is, according to some embodiments, the dummy gate structures 126 have a major axis direction parallel to the Y direction. According to some embodiments, the dummy gate structures 126 extend across and surround the channel regions of the first fin structure 118 and the second fin structure 120.

[0163] According to some embodiments, each of the dummy gate structures 126 includes a dummy gate dielectric layer 128 and a dummy gate electrode layer 130 formed on the dummy gate dielectric layer 128, as Figures 2E-2 to 2E-5 shown. In some embodiments, the dummy gate dielectric layer 128 is formed of one or more dielectric materials, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), HfO 2 , HfZrO, HfSiO, HfTiO, HfAlO, and / or combinations of the foregoing. In some embodiments, the dielectric material is formed using atomic layer deposition (ALD), chemical vapor deposition (CVD), thermal oxidation, physical vapor deposition, other suitable methods, and / or combinations of the foregoing. In some embodiments, the dummy gate electrode layer 130 is formed of a conductive material, such as polysilicon (poly-Si), polysilicon germanium (poly-SiGe), or combinations of the foregoing. In some embodiments, the conductive material is formed using chemical vapor deposition (CVD), other suitable techniques, and / or combinations of the foregoing.

[0164] In some embodiments, forming the dummy gate structure 126 includes conformally depositing a dielectric material for the dummy gate dielectric layer 128 on the semiconductor structure 12, depositing a conductive material for the dummy gate electrode layer 130 on the dielectric material, planarizing the conductive material, and patterning the conductive material and the dielectric material into the dummy gate structure 126. The patterning process may include forming an etch mask (not shown) on the conductive material to cover the channel regions of the first fin structure 118 and the second fin structure 120. The etch removes the conductive material and the dielectric material not covered by the etch mask to expose the source / drain regions of the first fin structure 118 and the second fin structure 120.

[0165] According to some embodiments, forming the gate spacer layer 132 along and covering the sidewalls of the dummy gate structure 126, as Figures 2E-3 to 2E-5 shown. According to some embodiments, the gate spacer layer 132 is configured to offset a subsequently formed source / drain component and to isolate the source / drain component from the gate structure.

[0166] In some embodiments, the gate spacer layer 132 is formed of a dielectric material such as silicon oxide (SiO 2 ), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and / or combinations thereof. In some embodiments, forming the gate spacer layer 132 includes conformally depositing a dielectric material for the gate spacer layer 132 on the semiconductor substrate 12, followed by an anisotropic etch process such as dry etching. The etch process removes the horizontal portions of the dielectric material for the gate spacer layer 132 while leaving the vertical portions of the dielectric material on the sidewalls of the dummy gate structure 126 as the gate spacer layer 132.

[0167] According to some embodiments, forming the source / drain component 134 on the first fin structure 118 and forming the source / drain component 136 on the second fin structure 120, as Figures 2E-4 to 2E-5 shown. According to some embodiments, the source / drain components 134 and 136 are formed on both sides of the dummy gate structure 126.

[0168] According to some embodiments, forming source / drain components 134 and 136 includes etching the first fin structure 118 and the second fin structure 120 to form source / drain recesses (not shown) in the source / drain regions. For performance considerations, the etching depth depends on the desired height of the source / drain components 134 and 136. According to some embodiments, thereafter, using an epitaxial growth process, one or more semiconductor materials for the source / drain components 134 and 136 are grown over the first fin structure 118 and the second fin structure 120. The epitaxial growth process can be molecular beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), vapor phase epitaxy (VPE), other suitable techniques, or a combination of the foregoing.

[0169] In some embodiments, the source / drain components 134 and 136 are formed of any material suitable for n-type semiconductor devices and p-type semiconductor devices, such as, for example, Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, SiCP, or a combination of the foregoing. In some embodiments, during the epitaxial growth process, the source / drain components 134 and 136 are doped in-situ. For example, the source / drain components 134 and 136 can be epitaxially grown silicon germanium (SiGe) doped with boron (B). For example, the source / drain components 134 and 136 can be epitaxially grown silicon (Si) doped with carbon (C) to form a silicon:carbon (Si:C) source / drain component, epitaxially grown silicon doped with phosphorus (P) to form a silicon:phosphorus (Si:P) source / drain component, or epitaxially grown silicon doped with both carbon and phosphorus to form a silicon carbon phosphorus (SiCP) source / drain component. In some embodiments, the growth of the source / drain component 134 and the growth of the source / drain component 136 can be performed in different steps.

[0170] According to some embodiments, an interlayer dielectric layer 138 is formed over the semiconductor structure 12, as Figure 2E-1 and Figures 2E-3 to 2E-5 shown. According to some embodiments, the interlayer dielectric layer 138 fills the space between the dummy gate structures 126 to cover the source / drain components 134 and 136.

[0171] In some embodiments, the interlayer dielectric layer 138 is formed of a dielectric material, such as un-doped silicate glass (USG) or doped silicon oxide, such as borophosphosilicate glass (BPSG), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials. In some embodiments, the dielectric material for the interlayer dielectric layer 138 is formed using chemical vapor deposition (e.g., high density plasma chemical vapor deposition (HDP-CVD), plasma enhanced chemical vapor deposition (PECVD), or high aspect ratio trench filling process (HARP)), other suitable methods, or a combination thereof. According to some embodiments, thereafter, the portion of the dielectric material for the interlayer dielectric layer 138 that is above the upper surface of the gate structure 126 is removed using, for example, chemical mechanical polishing (CMP) until the upper surface of the dummy gate structure 126 is exposed. In some embodiments, an upper surface of the interlayer dielectric layer 138 is substantially coplanar with an upper surface of the dummy gate electrode layer 130 .

[0172] Figure 2F-1 The semiconductor structure 12 is shown after forming the saw trenches 144 , according to some embodiments. Figure 2F-2 , Figure 2F-3 , Figure 2F-4 and Figure 2F-5 It is along Figure 2F-1 Schematic diagram of the cross-sections extracted by line Y1-Y1, line X1-X1, line Y2-Y2 and line X2-X2.

[0173] According to some embodiments, through the dummy gate structure 126 3 The first fin structure 118 forms a cutting groove 144, such as Figures 2F-1 to 2F-3 and Figure 2F-5 The cut trench 144 may also be referred to as a cut polysilicon on oxide definition edge (CPODE) pattern. According to some embodiments, the cut trench 144 corresponds to the dummy gate structure 126. 3 The intersection point with the first fin structure 118 is formed by placing the dummy gate structure 126 3Cut into two sections (which may also be referred to as sub-gate structures), and the first fin structure 118 is cut into two sections (which may also be referred to as sub-active regions). According to some embodiments, the cutting trench 144 extends in the Y direction. That is, according to some embodiments, the cutting trench 144 has a major axis direction parallel to the Y direction.

[0174] In some embodiments, forming the cutting trench 144 includes forming a patterned mask layer 140 on the semiconductor structure 12. In some embodiments, the patterned mask layer 140 has an opening 142 corresponding to the cutting trench 144. Thereafter, an etching process is performed to remove the dummy gate structure 126 3 and the portions of the first fin structure 118 not covered by the patterned mask layer 140 to form the cutting trench 144. The etching process will be described in detail later. Figures 4A - 4D The etching process will be described in detail later.

[0175] In some embodiments, the etching process removes the dummy gate structure 126 3 and the first fin structure 118 such that the gate spacers 132 are exposed from the cutting trench 144, as Figure 2F-3 shown. After removing the dummy gate structure 126 3 and the first fin structure 118, the cutting trench 144 extends into the isolation structure 124 and the substrate 102. Due to the difference in etching selectivity between the isolation structure 124 and the substrate 102, the cutting trench 144 has a first bottom surface 144A exposing the isolation structure 124 (as Figure 2F-2 and Figure 2F-3 shown) and a second bottom surface 144B exposing the substrate 102 (as Figure 2F-2 and Figure 2F-5 shown), and the second bottom surface 144B is located at a position deeper than the first bottom surface 144A.

[0176] According to some embodiments, during the etching process, the portions of the first fin structure 118 adjacent to the cutting trench 144 are covered by the gate spacer layer 132 and thus remain unetched, as Figure 2F-5 shown. The respective remaining portions of the third semiconductor layer 110, the fourth semiconductor layer 112, the first semiconductor layer 104, and the lower fin element 103 of the first fin structure 118 are respectively labeled as the third semiconductor layer 110', the fourth semiconductor layer 112', the first semiconductor layer 104', and the lower fin element 103', and they together form a semiconductor stack adjacent to the cutting trench 144, as Figure 2F-5 shown.

[0177] Figure 2G-1 is according to some embodiments, showing the semiconductor structure 12 after forming the isolation member 146. Figure 2G-2 、 Figure 2G-3 、 Figure 2G-4 andFigure 2G-5 is extracted along the Figure 2G-1 lines Y1 - Y1, X1 - X1, Y2 - Y2, and X2 - X2 in

[0178] According to some embodiments, an isolation component 146 is formed in the cut trench 144, as shown in Figures 2G-1 to 2G-4 and Figure 2G-5 . According to some embodiments, the isolation component 146 includes a dielectric liner 148 and a dielectric fill layer 150 located on the dielectric liner 148. According to some embodiments, the isolation component 146 separates and electrically isolates adjacent segments of the dummy gate structure 126 3 and separates and electrically isolates adjacent segments of the first fin structure 118.

[0179] In some embodiments, the dielectric liner 148 is formed of a dielectric material, such as silicon oxide, and the dielectric fill layer 150 is formed of a dielectric material, such as silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, silicon oxycarbide, or a combination of the foregoing. The dielectric liner 148 acts as a liner because the dielectric liner 148 adheres better to the first fin structure 118 than the dielectric fill layer 150, and the dielectric liner 148 separates the dielectric fill layer 180 from the first fin structure 118 to prevent undesired surface charges and stresses caused by contact between the dielectric fill layer 150 and the first fin structure 118. In some embodiments, the dielectric liner 148 and the dielectric fill layer 150 are deposited using chemical vapor deposition (e.g., high - density plasma chemical vapor deposition (HDP - CVD), plasma - enhanced chemical vapor deposition (PECVD), or high aspect ratio trench fill process (HARP)), other suitable techniques, and / or a combination of the foregoing. Thereafter, a planarization process, such as chemical mechanical polishing (CMP), can be performed on the semiconductor structure 12 to remove the portions of the dielectric liner 148 and the dielectric fill layer 150 above the upper surface of the interlayer dielectric layer 138. The planarization process also removes the patterned mask layer 140 ( Figure 2F-2 ). In some embodiments, the upper surface of the isolation component 146 is substantially coplanar with the upper surface of the interlayer dielectric layer 138.

[0180] Figure 2H-1 shows the semiconductor structure 12 after a channel releasing process, according to some embodiments. Figure 2H-2 , Figure 2H-3 , Figure 2H-4 , Figure 2H-5 and Figure 2H-6 are extracted along the Figure 2H-1 lines Y1 - Y1, X1 - X1, Y2 - Y2, X2 - X2, and X3 - X3 in

[0181] According to some embodiments, a channel release process is performed on the semiconductor structure 12. According to some embodiments, first, an etching process is used to remove the dummy gate structure 126 to form a plurality of gate trenches 152, as Figures 2H-1 to 2H-5 shown. According to some embodiments, the gate trenches 152 include the gate trenches 152 1 、152 2 、152 3 and 152 4 . According to some embodiments, the gate trenches 152 expose the channel regions of the first fin structure 118 and the second fin structure 120. In some embodiments, the gate trenches 152 expose the inner sidewalls of the gate spacers 132 facing the channel regions, as Figure 2H-3 、 Figure 2H-5 and Figure 2H-6 shown. In some embodiments, the gate trenches 152 expose the sidewalls of the isolation member 146, as Figure 2H-1 and Figure 2H-2 shown.

[0182] In some embodiments, the etching process includes one or more etching processes. For example, when the dummy gate electrode layer 130 is formed of polysilicon, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the dummy gate electrode layer 130. For example, a plasma dry etching, dry chemical etching, and / or wet etching can then be used to remove the dummy gate dielectric layer 128.

[0183] According to some embodiments, the channel release process also includes using etching to remove the first semiconductor layer 104 and the fourth semiconductor layer 112. According to some embodiments, the first semiconductor layer 104 and the fourth semiconductor layer 112 of the first fin structure 118 are removed to form a gap 154, as Figure 2H-4 and Figure 2H-5 shown. According to some embodiments, the first semiconductor layer 104 of the second fin structure 120 is removed to form a gap 156.

[0184] According to some embodiments, a gap 154 is formed between adjacent third semiconductor layers 110 and between the lowest third semiconductor layer 110 and the lower fin element 103. After the etching process, four main surfaces of the third semiconductor layer 110 are exposed. According to some embodiments, the exposed third semiconductor layer 110 forms a nanostructure, which can act as a channel region of the resulting semiconductor device (e.g., a gate-all-around field effect transistor). As used herein, the term "nanostructure" refers to a semiconductor layer having a cylindrical shape, a bar shape, and / or a sheet shape. According to some embodiments, the nanostructure (e.g., a nanowire structure or a nanosheet) extends between the source / drain components 134.

[0185] According to some embodiments, a gap 156 is formed between the second semiconductor layer 106 and the lower fin element 103. After the gap 156 is formed, the second semiconductor layer 106 of the second fin structure 120 can also be referred to as a floating fin element, which floats above the lower fin element 103. According to some embodiments, the floating fin element 106 of the second fin structure 120 can act as a channel region of the resulting semiconductor device (e.g., a fin field effect transistor).

[0186] In some embodiments, the upper surface of the highest nanostructure 110 is substantially flush with the upper surface of the floating fin element 106. In some embodiments, the bottom surface of the lowest nanostructure 110 is substantially flush with the bottom surface of the floating fin element 106.

[0187] In some embodiments, the etching process includes a selective wet etching process, such as an ammonia hydroxide-hydrogen peroxide-water mixture (APM). In some embodiments, the wet etching process uses an etchant, such as ammonium hydroxide (NH 4 OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), and / or potassium hydroxide (KOH) solution.

[0188] According to some embodiments, after the channel release process, an inner spacer layer 158 is formed in the gap 154 and in the gap 156, as Figure 2H-5 and Figure 2H-6According to some embodiments, the inner spacer layer 158 is formed on the surfaces of the source / drain features 134 and 136 exposed by the gaps 154 and 156. According to some embodiments, the inner spacer layer 158 is aligned below the gate spacer layer 132. According to some embodiments, the inner spacer layer 158 is formed between the source / drain features 134 and 136 and the final gate stack formed subsequently, and is configured to reduce the parasitic capacitance (i.e., Cgs and Cgd) between the final gate stack and the source / drain features.

[0189] In some embodiments, the inner spacer layer 158 is formed of a dielectric material, such as silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN), silicon carbide nitride (SiCN), and / or a combination thereof. In some embodiments, the inner spacer layer 158 is formed using a deposition process followed by an etching process. In some embodiments, the deposition process includes chemical vapor deposition (e.g., plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD)), atomic layer deposition (ALD), other suitable techniques, and / or a combination thereof. In some embodiments, the etching process includes plasma dry etching, dry chemical etching, and / or wet etching.

[0190] Figure 2I-1 The semiconductor structure 12 is shown after forming a plurality of final gate stacks 160 , according to some embodiments. Figure 2I-2 , Figure 2I-3 , Figure 2I-4 , Figure 2I-5 and Figure 2I-6 It is along Figure 2I-1 Schematic diagram of the cross-section extracted by line Y1-Y1, line X1-X1, line Y2-Y2, line X2-X2 and line X3-X3.

[0191] According to some embodiments, a plurality of final gate stacks 160 are formed on the semiconductor structure 12, such as Figures 2I-1 to 2I-6 The final gate stack 160 includes the final gate stack 160 1 , 160 2 , 160 3 and 160 4 According to some embodiments, a final gate stack 160 is formed to fill the gate trench 152 and the gaps 154 and 156 . According to some embodiments, the final gate stack 160 extends across the nanostructure 110 of the first fin structure 118 and the floating fin element 106 of the second fin structure 120 .

[0192] According to some embodiments, the final gate stack 160 1 , 160 2 , 160 3 and 1604 each includes an interfacial layer 162, a high-k gate dielectric layer 164, and a metal gate electrode layer 166, as Figures 2I-2 to 2I-6 shown. According to some embodiments, the interfacial layer 162 is formed on the exposed surfaces of the nanostructure 110, the floating fin element 106, and the lower fin element 103, as Figures 2I-2 to 2I-6 shown. According to some embodiments, the interfacial layer 162 surrounds the nanostructure 110 and the floating fin element 106. In some embodiments, the interfacial layer 162 is formed of chemically formed silicon oxide. In some embodiments, one or more cleaning processes, such as including ozone (O 3 ), ammonium hydroxide-hydrogen peroxide-water mixture and / or hydrochloric acid-hydrogen peroxide-water mixture, are used to form the interfacial layer 162. Thus, according to some embodiments, a portion of the semiconductor material of the nanostructure 110, the floating fin element 106, and the lower fin element 103 is oxidized to form the interfacial layer 162.

[0193] According to some embodiments, the high-k gate dielectric layer 164 conformally forms along the interfacial layer 162 to surround the nanostructure 110 and the floating fin element 106, as shown in FIGS. 2I-2 to 2I-6. According to some embodiments, the high-k gate dielectric layer 164 also conformally forms along the inner sidewall of the inner spacer 158 facing the channel region and along the inner sidewall of the gate spacer 124 facing the channel region, as Figure 2I-5 and Figure 2I-6 shown. According to some embodiments, because the first semiconductor layer 104 is thinner than the fourth semiconductor layer 112, the remaining portions of the lowest gap 154 and the gap 156 ( Figures 2H-4 to 2H-6 ) are substantially filled with the high-k gate dielectric layer 164, while the other gaps 154 are partially filled with the high-k gate dielectric layer 164, as Figures 2I-4 to 2I-6 shown. According to some embodiments, the high-k gate dielectric layer 164 also conformally forms along the sidewalls of the isolation member 146, as Figure 2I-1 and Figure 2I-2 shown According to some embodiments, the high-k gate dielectric layer 164 also conformally forms along the upper surface of the isolation structure 124, as Figure 2I-2 and Figure 2I-4 shown.

[0194] In some embodiments, the high-k gate dielectric layer 164 is formed of a dielectric material having a high dielectric constant (k value), such as greater than 3.9. In some embodiments, the high-k dielectric layer includes hafnium oxide (HfO 2 ), TiO 2 , HfZrO, Ta 2 O3 , HfSiO 4 , ZrO 2 , ZrSiO 2 , LaO, AlO, ZrO, TiO, Ta 2 O 5 , Y 2 O 3 , SrTiO 3 (STO), BaTiO 3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO 3 (BST), Al 2 O 3 , Si 3 N 4 , silicon oxynitride (SiON), the foregoing combinations, or other suitable materials. In some embodiments, an atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), and / or other suitable techniques are used to form the high-k gate dielectric layer 164.

[0195] According to some embodiments, the metal gate electrode layer 166 is formed over the high-k gate dielectric layer 164 and fills the remaining portions of the gate trenches 152 and the gaps 154, as Figures 2I-1 to 2I-6 shown. According to some embodiments, the metal gate electrode layer 166 surrounds the nanostructures 110 and the floating fin elements 106. In some embodiments, the metal gate electrode layer 166 is formed of more than one conductive material, such as metals, metal alloys, conductive metal oxides, and / or metal nitrides, other suitable conductive materials, and / or the foregoing combinations. The metal gate electrode layer 166 can be a multi-layer structure having various combinations of the following layers: a diffusion barrier layer, a work function layer having a selected work function for n-channel and p-channel transistors (to enhance device performance, such as the threshold voltage), a capping layer (to prevent oxidation of the work function layer), an adhesion layer (to adhere the work function layer to the next layer), and a metal fill layer (to reduce the resistance value of the gate stack) and / or other suitable layers.

[0196] In some embodiments, the metal gate electrode layer 166 may be made of Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable conductive materials, or multiple layers thereof. The metal gate electrode layer 166 may be formed using atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), electron beam evaporation, or other suitable processes. In addition, for N-type field effect transistors and P-type field effect transistors using different gate electrode materials and / or different work function materials, the metal gate electrode layer 166 may be formed separately.

[0197] According to some embodiments, a planarization process, such as chemical mechanical polishing (CMP), is performed on the semiconductor structure 12 to remove the high-k gate dielectric layer 164 and the metal gate electrode layer 166 formed on the upper surface of the interlayer dielectric layer 138. According to some embodiments, after the planarization process, the upper surface of the metal gate electrode layer 166, the upper surface of the isolation feature 146, and the upper surface of the interlayer dielectric layer 138 are substantially coplanar.

[0198] According to some embodiments, the interface layer 162, the high-k gate dielectric layer 164, and the metal gate electrode layer 166 are combined to form the final gate stack 160. 1 , 160 2 , 160 3 and 160 4 The final gate stack 160 may engage the channel region of the transistor (i.e., the nanostructure 110 of the first fin structure 118 and the floating fin element 106 of the second fin structure 120) so that current may flow between the source / drain features 134 and between the source / drain features 136 during operation. In some embodiments, the final gate stack 160 1 , 160 2 , 160 3 and 160 4 In other words, according to some embodiments, the final gate stack 160 1 , 160 2 , 160 3 and 160 4 The long axis direction of the gate stack 160 is parallel to the Y direction. The final gate stack 160 is arranged in the X direction. In addition, according to some embodiments, the final gate stack 160 3 The isolation element 146 is separated into two sections (or sub-gate stacks), such as Figure 2I-1 and Figure 2I-2 shown.

[0199] The portion of the final gate stack 160 inserted into the source / drain component 134 is combined with the source / drain component 134 to form a gate-all-around field-effect transistor (GAA FET) T1, as Figure 2I-1 and Figure 2I-5 shown. That is, according to some embodiments, the gate-all-around field-effect transistor T1 is formed at the intersection of the first fin structure 118 and the final gate stack 160, except at the intersection of the first fin structure 118 and the final gate stack 160 3 where the isolation component 146 is located. According to some embodiments, the isolation component 146 is located between two gate-all-around field-effect transistors T1 and electrically isolates them, as Figure 2I-1 and Figure 2I-5 shown. In addition, according to some embodiments, a semiconductor stack including a fourth semiconductor layer 112’, a third semiconductor layer 110’, a first semiconductor layer 104’, and a lower fin element 103’ is located between the source / drain component 134 of the gate-all-around field-effect transistor T1 and the isolation component 146, as Figure 2I-5 shown.

[0200] The portion of the final gate stack 160 inserted into the source / drain component 136 is combined with the source / drain component 136 to form a fin field-effect transistor (FinFET) T2, as Figure 2I-1 and Figure 2I-6 shown. That is, according to some embodiments, the fin field-effect transistor T2 is formed at the intersection of the second fin structure 120 and the final gate stack 160.

[0201] Figure 2J-1 shows a semiconductor structure 12 after forming the gate cut opening 172 according to some embodiments. Figure 2I-2 , Figure 2I-3 and Figure 2I-4 are cross-sectional schematic views taken along the lines Y1-Y1, X1-X1, and Y2-Y2 in Figure 2J-1 .

[0202] According to some embodiments, a cutting process is performed on the final gate stack 160 to form a gate cut opening 172, as Figure 2J-1 , Figure 2J-2 and Figure 2J-4 shown. According to some embodiments, the gate cut opening 172 cuts each final gate stack 160 into multiple segments. According to some embodiments, the gate cut opening 172 is formed through the final gate structure 160 and exposes the isolation structure 124, as Figure 2J-2 and Figure 2J-4 shown. In some embodiments, the widths of these cut openings 172 in the Y direction are substantially the same as each other.

[0203] According to some embodiments, a cutting process includes forming a patterned mask layer 168 over a semiconductor structure 12, as Figures 2J-1 to 2J-4 shown. In some embodiments, the patterned mask layer 168 has an opening 170 corresponding to a gate cut opening 172, but is offset from fin structures 118 and 120, as Figure 2J-1 shown. According to some embodiments, an etching process is then performed to remove portions of the metal gate electrode layer 168 and the high-k gate dielectric layer 166 until the isolation structure 124 is exposed. The etching process will be discussed in detail Figures 5A - 5D hereinafter.

[0204] In addition, according to some embodiments, the opening 170 of the patterned mask layer 168 partially overlaps the isolation member 146 such that two gate cut openings 172 adjacent to the isolation member 146 form a through portion of the isolation member 146 to remove portions of the dielectric liner 148 and the dielectric fill layer 150, as Figure 2J-2 shown.

[0205] Figure 2K-1 FIGS. are semiconductor structures 12 after forming gate cut members 174, according to some embodiments. Figure 2K-2 , Figure 2K-3 and Figure 2K-4 are cross-sectional schematic views taken along lines Y1-Y1, X1-X1, and Y2-Y2 in Figure 2K-1 .

[0206] According to some embodiments, a gate cut member 174 is formed in the gate cut opening 172, as Figures 2K-1 to 2K-4 shown. According to some embodiments, the gate cut member 174 separates and electrically isolates adjacent segments of the final gate stack 160 such that the all-around gate field-effect transistor T1 and the adjacent fin field-effect transistor T2, which originally shared the same final gate stack 160, are electrically isolated from each other. According to some embodiments, the gate cut member 174 adjacent to the isolation member 146 contacts both the dielectric liner 148 and the dielectric fill layer 150. According to some embodiments, the dielectric liner 148 extends below the gate cut member 174, as Figure 2K-2 shown.

[0207] In some embodiments, the gate cut component 174 is formed of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or a combination of the foregoing. In some embodiments, a chemical vapor deposition process (e.g., high density plasma chemical vapor deposition (HDP-CVD), plasma enhanced chemical vapor deposition (PECVD), or high aspect ratio trench fill process (HARP)), other suitable techniques, and / or a combination of the foregoing is used to deposit the dielectric material for the gate cut component 174. Thereafter, a planarization process, such as chemical mechanical polishing (CMP), may be performed on the semiconductor structure 12 to remove the dielectric material above the upper surface of the interlayer dielectric layer 138. The planarization process also removes the patterned mask layer 168. In some embodiments, the upper surface of the gate cut component 174, the upper surface of the isolation component 146, the upper surface of the interlayer dielectric layer 138, and the upper surface of the metal gate electrode layer 166 are substantially coplanar.

[0208] Aspects of embodiments of the present invention relate to a formation method and structure in which a hybrid structure including a fully wrapped gate field effect transistor T1 and a fin field effect transistor T2 is provided on the same semiconductor substrate. According to some embodiments, the hybrid structure further includes an isolation component 146 inserted between two adjacent fully wrapped gate field effect transistors T1 and a gate cut component 174 inserted between the fully wrapped gate field effect transistor T1 and the fin field effect transistor T2.

[0209] In the case where the gate cut component is formed before the replacement of the final gate stack with a dummy gate structure, the fill window for filling the high-k gate dielectric layer and the metal gate electrode layer between the active region and the gate cut component may be too small to form a reliable final gate stack, resulting in a low yield. In the case where the isolation component is formed after the formation of the metal gate stack, due to the differences in etching selectivity among various materials (such as metals, dielectrics, and semiconductors), it is difficult to etch through the final gate stack and simultaneously etch the active region to form a cut trench for the isolation component.

[0210] Embodiments of the present invention provide a method for forming a semiconductor structure, in which the isolation component is formed before the replacement process of the final gate stack, and the gate cut component is formed after the formation of the final gate stack. Thus, the method of embodiments of the present invention can reduce the difficulty of the etching process for forming the cut trench and expand the fill tolerance of the metal gate structure, thereby improving device performance and product yield. Therefore, the hybrid structure provided by embodiments of the present invention can achieve lower process difficulty and greater design flexibility for integrated circuits including different types of devices (e.g., logic devices, memory devices, etc.).

[0211] Figure 3FIG. 1000 is a flow chart showing a method of forming a semiconductor structure according to some embodiments of the present invention. According to some embodiments, method 1000 is used to form the aforementioned Figures 2A to 2K-4 semiconductor structure 12.

[0212] According to some embodiments, at step 1002, a substrate 102 is provided, as Figure 2A shown. According to some embodiments, at step 1004, a first epitaxial stack including a first semiconductor layer 104 and a second semiconductor layer 106 is formed on the substrate 102, as Figure 2A shown. According to some embodiments, at step 1006, the first epitaxial stack is etched to form a recess 108, as Figure 2B shown. According to some embodiments, at step 1008, a second epitaxial stack including a third semiconductor layer 110 and a fourth semiconductor layer 112 is formed from the recess 108, as Figure 2C shown.

[0213] According to some embodiments, at step 1010, a first fin structure 118 and a second fin structure 120 are formed, as Figure 2D-1 and Figure 2D-2 shown. According to some embodiments, at step 1012, an isolation structure 124 is formed around the lower fin elements 103 of the first fin structure 118 and the second fin structure 120, as Figures 2E-1 to 2E-5 shown. According to some embodiments, at step 1014, a dummy gate structure 126 is formed across the first fin structure 118 and the second fin structure 120, and a gate spacer layer 132 is formed along the dummy gate structure 126, as Figures 2E-1 to 2E-5 shown. According to some embodiments, at step 1016, source / drain components 134 and 136 are formed on the first fin structure 118 and the second fin structure 120, and an interlayer dielectric layer 138 is formed on the source / drain components 134 and 136, as Figures 2E-1 to 2E-5 shown.

[0214] According to some embodiments, at step 1018, a cut trench 144 is formed through the first fin structure 118, as Figures 2F-1 to 2F-5 shown. According to some embodiments, at step 1020, an isolation component 146 is formed in the cut trench 144, as Figures 2G-1 to 2G-5 shown.

[0215] According to some embodiments, at step 1022, the dummy gate structure 126 is removed and a channel release process is performed to form a nanostructure 110 of the first fin structure 118 and a floating fin element 106 of the second fin structure 120, as Figures 2H-1 to 2H-5 shown. According to some embodiments, at step 1024, an inner spacer layer 158 is formed, as Figures 2H-1 to 2H-6As shown. According to some embodiments, at step 1026, a final gate stack 160 is formed across the nanostructure 110 and the floating fin element 106, as Figures 2I-1 to 2I-5 shown.

[0216] According to some embodiments, at step 1028, a gate cut opening 170 is formed through the final gate stack 160, as Figures 2J-1 to 2J-4 shown. According to some embodiments, at step 1030, a gate cut member 174 is formed in the gate cut opening 170, as Figures 2K-1 to 2K-4 shown.

[0217] Figures 4A - 4D FIG. is a cross-sectional schematic view showing the formation of a cut trench 414 according to some embodiments of the present invention. Figure 4D The cut trench 414 shown can be similar to Figures 2F-1 to 2F-5 the cut trench 144 shown.

[0218] According to some embodiments, forming the cut trench 414 includes forming a hard mask layer 402 over the dummy gate electrode layer 130 and an interlayer dielectric (not shown), and forming a three-layer mask structure over the hard mask layer 402, as Figure 4A shown. In some embodiments, the hard mask layer 402 is formed of silicon nitride, silicon oxide, silicon oxynitride, and / or a combination of the foregoing. According to some embodiments, the three-layer mask structure includes a bottom layer 404, an intermediate layer 406 over the bottom layer 404, and a top layer 408 over the intermediate layer 406. In some embodiments, the top layer 408 is formed of photoresist and is patterned using a photolithography process to have an opening 410. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, drying (e.g., hard baking), other suitable processes, or a combination of the foregoing. In some embodiments, the intermediate layer 406 is formed of an inorganic material, and the bottom layer 404 is formed of a silicon-doped bottom anti-reflection coating (BARC).

[0219] According to some embodiments, an etching process is performed to remove the portions of the intermediate layer 406, the bottom layer 404, and the hard mask layer 406 below the opening 410 to form an opening 412, as Figure 4B shown; removing the three-layer mask structure, as Figure 4C shown; and removing the portions of the dummy gate electrode layer 130 and the dummy gate dielectric layer 128 not covered by the patterned mask layer 402 to form a cut opening 414, as Figure 4D shown.

[0220] An etching process can be performed in a plasma etching chamber, such as the Kiyo etcher provided by Lam Research (located in Fremont, California). The plasma etching chamber can be operated in a pulsed plasma mode that includes a pulse-on period and a pulse-off period. The ratio during the pulse-on period can be defined as the duty cycle. According to some embodiments, the steps of the etching process include: (1) a de-scum step of cleaning the photoresist material remaining in the opening 410 after the lithography process on the top layer 408 to fully expose the intermediate layer 406; (2) a middle-layer open step of etching the intermediate layer 406; (3) a bottom-layer open step of etching the bottom layer 404; (4) a hard-mask open step of etching the hard mask layer 402; (5) a strip step of removing the top layer 408, the intermediate layer 406, and the bottom layer 404 to expose the hard mask layer 402; (6) an oxide break-through step of removing the native oxide formed on the dummy gate electrode layer 130; (7) a main etching step of etching the dummy gate electrode layer 130, the dummy gate dielectric layer 128, and the first fin structure 118 (including the third semiconductor layer 110, the fourth semiconductor layer 112, and the lower fin element 103); (8) an over etching step of controlling the cut trench 414 to stop at a desired depth; (9) an ashing step of removing residues, polymers, and / or by-products from the semiconductor structure.

[0221] According to some embodiments, during the de-scum step, the etching chamber provides a bias voltage in the range of about 60 volts (V) to about 360 V, a duty cycle in the range of about 95% to about 100%, and an RF source power in the range of about 100 watts to about 600 watts. The de-scum step uses CF with a flow rate in the range of about 50 standard cubic centimeters per minute (sccm) to about 300 sccm 4 and Ar with a flow rate in the range of about 50 sccm to 300 sccm as etching precursors and lasts for about 4 seconds to about 24 seconds at a pressure of about 1.5 millitorr (mTorr) to about 9 mTorr.

[0222] According to some embodiments, during the intermediate layer opening step, the etching chamber provides a bias voltage in the range of about 200V to about 1200V, a duty cycle in the range of about 95% to about 100%, and a radio frequency source power in the range of about 400 watts to about 2400 watts. The intermediate layer opening step uses CH with a flow rate in the range of about 12.5 sccm to about 75 sccm 2 F 2 , CF with a flow rate in the range of about 37.5 sccm to about 225 sccm 4 and O with a flow rate in the range of about 1.5 sccm to about 9 sccm 2 as the etching precursors, and lasts for about 15 seconds to about 90 seconds at a pressure of about 5 mTorr to about 30 mTorr.

[0223] According to some embodiments, during the bottom layer opening step, the etching chamber provides a bias voltage in the range of about 100V to about 600V, a duty cycle in the range of about 95% to about 100%, and a radio frequency source power in the range of about 500 watts to about 3000 watts. The bottom layer opening step uses SO with a flow rate in the range of about 50 sccm to about 30 sccm 2 , O with a flow rate in the range of about 12.5 sccm to about 75 sccm 2 and He with a flow rate in the range of about 100 sccm to about 600 sccm as the etching precursors, and lasts for about 22.5 seconds to about 135 seconds at a pressure of about 3.5 mTorr to about 21 mTorr.

[0224] According to some embodiments, during the hard mask opening step, the etching chamber provides a bias voltage in the range of about 200V to about 1200V, a duty cycle in the range of about 95% to about 100%, and a radio frequency source power in the range of about 400 watts to about 2400 watts. The hard mask opening step uses CHF with a flow rate in the range of about 50 sccm to about 30 sccm 3 , O with a flow rate in the range of about 2.5 sccm to about 15 sccm 2 and He with a flow rate in the range of about 100 sccm to about 600 sccm as the etching precursors, and lasts for about 10 seconds to about 60 seconds at a pressure of about 2.5 mTorr to about 15 mTorr.

[0225] According to some embodiments, during the stripping step, the etching chamber provides a bias voltage in the range of about 15V to about 90V, a duty cycle in the range of about 95% to about 100%, and a radio frequency source power in the range of about 500 watts to about 3000 watts. The stripping step uses O with a flow rate in the range of about 10 sccm to about 60 sccm 2 as the etching precursor, and lasts for about 15 seconds to about 90 seconds at a pressure of about 5 mTorr to about 30 mTorr.

[0226] According to some embodiments, during the oxide breakthrough step, the etch chamber provides a bias voltage in the range of about 30V to about 180V, a duty cycle in the range of about 95% to about 100%, and a radio frequency source power in the range of about 150 watts to about 900 watts. The oxide breakthrough step uses CF with a flow rate in the range of about 10 sccm to about 60 sccm 4 , Ar with a flow rate in the range of about 20 sccm to about 120 sccm as an etch precursor, and is carried out at a pressure of about 2.5 mTorr to about 15 mTorr for about 7.5 seconds to about 45 seconds.

[0227] According to some embodiments, during the main etch step, the etch chamber provides a bias voltage in the range of about 350V to about 2100V, a duty cycle in the range of about 95% to about 100%, and a radio frequency source power in the range of about 700 watts to about 4200 watts. The main etch step uses HBr with a flow rate in the range of about 150 sccm to about 900 sccm, O with a flow rate in the range of about 5 sccm to 30 sccm 2 , He with a flow rate in the range of about 400 sccm to about 2400 sccm as an etch precursor, and is carried out at a pressure of about 40 mTorr to about 240 mTorr for about 30 seconds to about 180 seconds.

[0228] According to some embodiments, during the over-etch step, the etch chamber provides a bias voltage in the range of about 700V to about 4200V, a duty cycle in the range of about 5% to about 8%, and a radio frequency source power in the range of about 200 watts to about 1200 watts. The over-etch step uses SiCH with a flow rate in the range of about 2.5 sccm to about 15 sccm 4 , N with a flow rate in the range of about 25 sccm to about 150 sccm 2 , Cl with a flow rate in the range of about 150 sccm to about 900 sccm 2 and as an etch precursor, and is carried out at a pressure of about 40 mTorr to about 240 mTorr for about 30 seconds to about 180 seconds. The duty cycle of the over-etch step is much lower than that of the main etch step, and the etching can be precisely controlled to extend the cut trench 414 to a desired depth, such as into the substrate 102.

[0229] According to some embodiments, during the ashing step, the etch chamber provides a bias voltage in the range of about 15V to about 90V, a duty cycle in the range of about 95% to about 100%, and a radio frequency source power in the range of about 500 watts to about 3000 watts. The ashing step uses O with a flow rate in the range of about 10 sccm to about 60 sccm 2 , and is carried out at a pressure of about 5 mTorr to about 30 mTorr for about 15 seconds to about 90 seconds.

[0230] In some embodiments, steps of an etching process are performed in-situ in the same etching chamber to prevent a semiconductor structure from being exposed to an oxygen-containing environment. After the etching process, a sulfuric acid hydrogen peroxide mixture (SPM, H 2 SO 4 +H 2 O 2 ) and / or dilute hydrochloric acid (dHF) are used to clean the semiconductor structure.

[0231] Figures 5A - 5D FIG. is a cross-sectional schematic diagram showing the formation of a gate cut opening 518 according to some embodiments of the present invention. Figure 5D The shown gate cut opening 518 may be similar to Figures 2J-1 to 2J-4 the shown gate cut opening 172.

[0232] According to some embodiments, forming the gate cut opening 518 includes forming a metal protection layer 502 over a metal gate electrode layer 166, an isolation component 146, and an interlayer dielectric layer (not shown), forming a hard mask layer 504 over the metal protection layer 502, and forming a three-layer mask structure over the hard mask layer 504, as Figure 5A shown. In some embodiments, the metal protection layer 502 protects the metal gate electrode material from oxidation and may be formed of TiN. In some embodiments, the hard mask layer 504 is formed of silicon nitride, silicon oxide, silicon oxynitride, and / or a combination of the foregoing. According to some embodiments, the three-layer mask structure includes a bottom layer 506, an intermediate layer 508 over the bottom layer 506, and a top layer 510 over the intermediate layer 508. In some embodiments, the top layer 510 is formed of photoresist and is patterned using a photolithography process to have an opening 512; the intermediate layer 508 is formed of an inorganic material, and the bottom layer 506 is formed of a silicon-doped bottom anti-reflection coating (BARC).

[0233] According to some embodiments, a first etching process is performed to remove portions of the intermediate layer 508, the bottom layer 506, and the hard mask layer 504 below the opening 512 to form an opening 514, as Figure 5B shown.

[0234] The first etching process may be performed in a plasma etching chamber, such as a Kiyo etcher. The steps of the first etching process include: (1) a de-scum step of cleaning the photoresist material remaining in the opening 512 after the photolithography process on the top layer 510 to completely expose the intermediate layer 508; (2) an intermediate layer opening step of etching the intermediate layer 508; (3) a bottom layer opening step of etching the bottom layer 506; and (4) a hard mask opening step of etching the hard mask layer 504 to expose the metal protection layer 502.

[0235] According to some embodiments, during the slag removal step, the etching chamber provides a bias voltage in the range of about 60V to about 360V, a duty cycle in the range of about 95% to about 100%, and a radio frequency source power in the range of about 100 watts to about 600 watts. The slag removal step uses CF with a flow rate in the range of about 50 sccm to about 300 sccm 4 and Ar with a flow rate in the range of about 50 sccm to about 300 sccm as the etching precursor, and lasts for about 4 seconds to about 24 seconds at a pressure of about 1.5 mTorr to about 9 mTorr.

[0236] According to some embodiments, during the intermediate layer opening step, the etching chamber provides a bias voltage in the range of about 200V to about 1200V, a duty cycle in the range of about 95% to about 100%, and a radio frequency source power in the range of about 400 watts to about 2400 watts. The intermediate layer opening step uses CH with a flow rate in the range of about 12.5 sccm to about 75 sccm 2 F 2 and CF with a flow rate in the range of about 37.5 sccm to about 225 sccm 4 and O with a flow rate in the range of about 1.5 sccm to 9 sccm 2 as the etching precursor, and lasts for about 15 seconds to about 90 seconds at a pressure of about 5 mTorr to about 30 mTorr.

[0237] According to some embodiments, during the bottom layer opening step, the etching chamber provides a bias voltage in the range of about 100V to about 600V, a duty cycle in the range of about 95% to about 100%, and a radio frequency source power in the range of about 500 watts to about 3000 watts. The bottom layer opening step uses SO with a flow rate in the range of about 50 sccm to about 30 sccm 2 and O with a flow rate in the range of about 12.5 sccm to 75 sccm 2 and He with a flow rate in the range of about 100 sccm to about 600 sccm as the etching precursor, and lasts for about 22.5 seconds to about 135 seconds at a pressure of about 3.5 mTorr to about 21 mTorr.

[0238] According to some embodiments, during the hard mask opening step, the etching chamber provides a bias voltage in the range of about 200V to about 1200V, a duty cycle in the range of about 95% to about 100%, and a radio frequency source power in the range of about 400 watts to about 2400 watts. The hard mask opening step uses CHF with a flow rate in the range of about 50 sccm to 300 sccm 3 and O with a flow rate in the range of about 2.5 sccm to about 15 sccm 2and He with a flow rate ranging from about 100 sccm to about 600 sccm as an etching precursor, and for about 25 seconds to about 150 seconds at a pressure ranging from about 2.5 mTorr to about 15 mTorr.

[0239] In some embodiments, the first etching process further includes a stripping step after the hard mask opening step to remove the three-layer mask structure. In some embodiments, the steps of the first etching process are performed in situ in the same etching chamber. After the first etching process, a sulfuric acid hydrogen peroxide mixture and / or dilute hydrochloric acid (dHF) can be used to clean the semiconductor structure.

[0240] Since both vertical etching and lateral etching occur simultaneously during the first etching process, the opening 514 may expand to have a critical dimension larger than the target critical dimension (CD). In some embodiments, a dielectric layer 516 is conformally formed over the semiconductor structure to partially fill the opening 514 to restore the expanded critical dimension of the opening 514, as Figure 5C shown. The opening 514 after partially filling the dielectric layer 516 is labeled as opening 514'. In some embodiments, the dielectric layer 516 is formed of the same material as the hard mask layer 504, such as SiN.

[0241] According to some embodiments, a second etching process is performed to remove portions of the dielectric layer 516, the metal gate electrode layer 166, and the high-k gate dielectric layer 164 below the opening 514' to form a gate cut opening 518, as Figure 5D shown. In some embodiments, the second etching process may also remove portions of the isolation component 146 below the opening 514'.

[0242] The second etching process can be performed in a plasma etching chamber, such as a Kiyo etcher. The steps of the second etching process include: (1) a hard mask opening step to etch the dielectric layer 516; (2) a protective layer opening step to etch the protective layer 502; (3)-(6) first, second, third, and fourth main etching steps to etch the gate electrode layer 166 and the high-k gate dielectric layer 164 and control the gate cut opening 518 to stop at a desired depth. The first, second, third, and fourth main etching steps are used to remove different materials of the final gate stack (e.g., metal, metal nitride, high-k dielectric, etc.), and the first, second, third, and fourth main etching steps can be repeated several times.

[0243] According to some embodiments, during the hard mask opening step, the etching chamber provides a bias voltage ranging from about 200 V to about 1200 V, a duty cycle ranging from about 95% to about 100%, and a radio frequency source power ranging from about 400 watts to about 2400 watts. The hard mask opening step uses CHF with a flow rate ranging from about 50 sccm to 300 sccm3 O with a flow rate ranging from about 2.5 sccm to about 15 sccm 2 and He with a flow rate ranging from about 100 sccm to about 600 sccm as the etching precursor, and for about 7.5 seconds to about 45 seconds at a pressure of about 2.5 mTorr to about 15 mTorr.

[0244] According to some embodiments, during the protective layer opening step, the etching chamber provides a bias voltage ranging from about 100 V to about 600 V, a duty cycle ranging from about 95% to about 100%, and a radio frequency source power ranging from about 400 W to about 2400 W. The protective layer opening step uses Cl with a flow rate ranging from about 50 sccm to 300 sccm 2 and BCl with a flow rate ranging from about 10 sccm to about 60 sccm 3 and Ar with a flow rate ranging from about 10 sccm to about 10000 sccm as the etching precursor, and for about 7.5 seconds to about 45 seconds at a pressure of about 1.5 mTorr to about 9 mTorr.

[0245] According to some embodiments, during the first main etching step, the etching chamber provides a bias voltage ranging from about 150 V to about 900 V, a duty cycle ranging from about 45% to about 55%, and a radio frequency source power ranging from about 600 W to about 3600 W. The first main etching step uses Cl with a flow rate ranging from about 50 sccm to 300 sccm 2 and BCl with a flow rate ranging from about 10 sccm to about 60 sccm 3 and Ar with a flow rate ranging from about 10 sccm to about 10000 sccm as the etching precursor, and for about 5 seconds to about 30 seconds at a pressure of about 15 mTorr to about 90 mTorr.

[0246] According to some embodiments, during the second main etching step, the etching chamber provides a bias voltage ranging from about 300 V to about 1800 V, a duty cycle ranging from about 45% to about 55%, and a radio frequency source power ranging from about 600 W to about 3600 W. The second main etching step uses Cl with a flow rate ranging from about 50 sccm to 300 sccm 2 and BCl with a flow rate ranging from about 10 sccm to about 60 sccm 3 and Ar with a flow rate ranging from about 10 sccm to about 10000 sccm as the etching precursor, and for about 7.5 seconds to about 45 seconds at a pressure of about 30 mTorr to about 180 mTorr.

[0247] According to some embodiments, during the third main etching step, the etching chamber provides a bias voltage in the range of about 150V to about 900V, a duty cycle in the range of about 45% to about 55%, and a radio frequency source power in the range of about 600 watts to about 3600 watts. The third main etching step uses Cl with a flow rate in the range of about 50 sccm to 300 sccm 2 , BCl with a flow rate in the range of about 10 sccm to about 60 sccm 3 , and Ar with a flow rate in the range of about 10 sccm to about 10000 sccm as etching precursors, and lasts for about 5 seconds to about 30 seconds at a pressure of about 15 mTorr to about 90 mTorr.

[0248] According to some embodiments, during the fourth main etching step, the etching chamber provides a bias voltage in the range of about 300V to about 1800V, a duty cycle in the range of about 5% to about 20%, and a radio frequency source power in the range of about 600 watts to about 3600 watts. The third main etching step uses Cl with a flow rate in the range of about 50 sccm to 300 sccm 2 , BCl with a flow rate in the range of about 10 sccm to about 60 sccm 3 , and Ar with a flow rate in the range of about 10 sccm to about 10000 sccm as etching precursors, and lasts for about 7.5 seconds to about 45 seconds at a pressure of about 30 mTorr to about 180 mTorr. The duty cycle of the fourth main etching step is much lower than that of the first, second, and third main etching steps, and the etching can be precisely controlled to extend the gate cut opening 518 to the desired depth.

[0249] According to some embodiments, the second etching process may also include an ashing step after the fourth main etching step of the last cycle to remove residues, polymers, and / or by-products from the semiconductor structure. In some embodiments, the steps of the second etching process are performed in-situ in the same etching chamber. After the second etching process, the semiconductor structure can be cleaned using dilute hydrochloric acid (dHF) and / or an ammonia-hydrogen peroxide-water mixture (Standard Clean 1).

[0250] Figure 6-1 FIG. 6-1 is a top schematic view of a semiconductor structure 14 according to some embodiments of the present invention, and the semiconductor structure 14 is a modification of the semiconductor structure 12 Figure 2K-1 . FIGS. 6-2 and 6-3 are cross-sectional schematic views taken along lines Y1-Y1 and X3-X3 in Figure 6-1 according to some embodiments of the present invention. According to some embodiments, the semiconductor structure 14 is similar to the semiconductor structure 12, except that an isolation member 146 is formed through the second fin structure 120.

[0251] According to some embodiments, after performing step 1016, a cutting trench (not shown) is formed through the dummy gate structure 126 3 and the second fin structure 120, and an isolation component 146 is formed in the cutting trench. According to some embodiments, the cutting trench (or the isolation component 146) corresponds to the intersection of the dummy gate structure 126 3 and the second fin structure 120, thereby cutting the dummy gate structure (not shown) into two segments and cutting the second fin structure 120 into two segments. The cutting trench can be formed using the steps Figures 4A to 4D shown above. According to some embodiments, after performing steps 1022 - 1030, the isolation component 146 is located between two fin field-effect transistors T2 and electrically isolates them, as Figure 6-1 shown.

[0252] In addition, according to some embodiments, during the etching process for forming the cutting trench, the portion of the second fin structure 120 adjacent to the isolation component 146 is covered by the gate spacer 132 and remains unetched. According to some embodiments, the unetched portions of the second semiconductor layer 106, the first semiconductor layer 104, and the lower fin element 103 of the second fin structure 120 are respectively labeled as the second semiconductor layer 106’, the first semiconductor layer 104’, and the lower fin element 103’, as Figure 6-3 shown. According to some embodiments, the semiconductor stack including the second semiconductor layer 106’, the first semiconductor layer 104’, and the lower fin element 103’ is located between the source / drain component 136 of the fin field-effect transistor T2 and the isolation component 146, as Figure 6-3 shown.

[0253] Figure 7-1 is a top view schematic diagram showing a semiconductor structure 16 according to some embodiments of the present invention, and the semiconductor structure 16 is Figure 2K-1 a modification of the semiconductor structure 12. Figures 7-2 to 7-4 is a cross-sectional schematic diagram extracted along the lines Y1 - Y1, X2 - X2, and X3 - X3 in Figure 6-1 according to some embodiments of the present invention. According to some embodiments, the semiconductor structure 16 is similar to the semiconductor structure 12, except that an isolation component 146 is formed through both the first fin structure 118 and the second fin structure 120.

[0254] According to some embodiments, after performing step 1016, a cutting trench (not shown) is formed through the dummy gate structure 126 3and a first fin structure 118 and a second fin structure 120, and forming an isolation component 146 in the cutting trench. According to some embodiments, the cutting trench (or the isolation component 146) cuts a dummy gate structure (not shown) into two sections, cuts the first fin structure 118 into two sections, and cuts the second fin structure 120 into two sections. The cutting trench can be formed using the steps Figures 4A to 4D shown above. According to some embodiments, after performing steps 1022 - 1030, the isolation component 146 is located between two all-around gate field-effect transistors T1 and between two fin field-effect transistors T2, as Figure 7-1 , Figure 7-3 and Figure 7-4 shown.

[0255] Figure 8-1 , Figure 9-1 and Figure 10-1 are top view schematic diagrams showing semiconductor structures 18, 20, and 22 according to some embodiments of the present invention. The semiconductor structures 18, 20, and 22 are respectively Figure 2K-1 , Figure 6-1 and Figure 7-1 modifications of the semiconductor structures 12, 14, and 16. Figure 8-2 , Figure 9-2 and Figure 10-2 are cross-sectional schematic diagrams showing, according to some embodiments of the present invention, along Figure 8-1 , Figure 9-1 and Figure 10-1 the line Y1 - Y1 in. According to some embodiments, the semiconductor structures 18, 20, and 22 are respectively similar to the semiconductor structures 12, 14, and 16, except that no gate cutting openings are formed adjacent to the isolation component 146. Thus, according to some embodiments, the high-k gate dielectric layer 164 of the final gate stack 160 3 is formed along and in contact with the dielectric liner 148 of the isolation component 146.

[0256] Figure 11-1 , Figure 12-1 and Figure 13-1 are top view schematic diagrams showing semiconductor structures 24, 26, and 28 according to some embodiments of the present invention. The semiconductor structures 24, 26, and 28 are respectively Figure 8-1 , Figure 9-1 and Figure 10-1 modifications of the semiconductor structures 18, 20, and 22. Figure 11-2 , Figure 12-2 and Figure 13-2 are cross-sectional schematic diagrams showing, according to some embodiments of the present invention, along Figure 11-1 , Figure 12-1 and Figure 13-1Schematic cross-sectional view extracted along line Y1-Y1 in. According to some embodiments, semiconductor structures 24, 26, and 28 are respectively similar to semiconductor structures 18, 20, and 22, except for the final gate stack 160 3 The high-k gate dielectric layer 164 of forms along and contacts the dielectric liner 148 and the dielectric fill layer 150 of the isolation member 146. According to some embodiments, this is because during step 1022, the portion of the dielectric liner 148 that contacts the dummy gate structure 126 3 is also removed, thereby exposing the dielectric fill layer 150 from the isolation trench 152 3 .

[0257] Figure 14-1 , Figure 15-1 and Figure 16-1 are top-down schematic views showing semiconductor structures 30, 32, and 34 according to some embodiments of the present invention. Semiconductor structures 30, 32, and 34 are respectively Figure 2K-1 , Figure 6-1 and Figure 7-1 modifications of semiconductor structures 12, 14, and 16. Figure 14-2 , Figure 15-2 and Figure 16-2 are according to some embodiments of the present invention, showing cross-sectional schematic views extracted along line Y1-Y1 in Figure 14-1 , Figure 15-1 and Figure 16-1 . According to some embodiments, semiconductor structures 30, 32, and 34 are respectively similar to semiconductor structures 12, 14, and 16, except that the length of the gate cutting member 174A adjacent to the isolation member 146 along the Y direction is shorter than that of the gate cutting member 174 not adjacent to the isolation member 146. According to some embodiments, this is because during step 1028, the portion of the dielectric liner 148 that contacts the final gate stack 160 3 remains unetched. In addition, Figure 14-1 shows the final gate stack 160 that is not cut by the gate cutting member 174 4 . Figure 14-3 is according to some embodiments of the present invention, showing a cross-sectional schematic view extracted along line Y2-Y2 in Figure 14-1 . In some embodiments, the final gate stack 160 4 continuously extends and surrounds the nanostructures 110 of the first fin structure 118 and the second fin structure 120, as shown in Figure 14-1 and Figure 14-3 . That is, the all-around gate field-effect transistor T1 and the fin field-effect transistor T2 share a continuous final gate stack 160 4 .

[0258] Figure 17-1 , Figure 18-1 andFigure 19-1 FIG. 0 is a top view schematic diagram showing semiconductor structures 36, 38, and 40, which are modifications of semiconductor structures 30, 32, and 34 of Figure 14-1 , Figure 15-1 and Figure 16-1 respectively. FIGS. 17-1, 18-1, and 19-1 are cross-sectional schematic diagrams taken along line Y1-Y1 in Figure 17-2 , Figure 18-2 and Figure 19-2 according to some embodiments of the present invention. According to some embodiments, semiconductor structures 36, 38, and 40 are respectively similar to semiconductor structures 30, 32, and 34, except that the gate cutting member 174A contacts both the dielectric layer 148 and the dielectric filling layer 150 of the isolation member 146. According to some embodiments, this is because during step 1028, the portion of the dielectric layer 148 that contacts the final gate stack 160 3 is removed, while the dielectric filling layer 150 remains unetched.

[0259] Figure 20-1 , Figure 21-1 and Figure 22-1 are top view schematic diagrams showing semiconductor structures 42, 44, and 46, which are modifications of semiconductor structures 12, 14, and 16 of Figure 2K-1 , Figure 6-1 and Figure 7-1 respectively. Figure 20-2 , Figure 21-2 and Figure 22-2 are cross-sectional schematic diagrams taken along line Y1-Y1 in FIGS. 20-1, 21-1, and 22-1 according to some embodiments of the present invention. According to some embodiments, semiconductor structures 42, 44, and 46 are respectively similar to semiconductor structures 12, 14, and 16, except that the length of the gate cutting member 174B adjacent to the isolation member 146 along the Y direction is shorter than that of the gate cutting member 174 not adjacent to the isolation member 146. According to some embodiments, this is because during step 1028, the dielectric layer 148 and the dielectric filling layer 150 are subject to more lateral etching.

[0260] As described above, the semiconductor structure includes a hybrid structure, which includes a first and a second gate-all-around field-effect transistor T1 and a fin field-effect transistor T2 located on the same substrate 102. The first gate-all-around field-effect transistor T1 includes a first nanostructure 110 and a first gate stack 160 surrounding the first nanostructure 110. The second gate-all-around field-effect transistor T1 includes a second nanostructure 110 and a second gate stack 160 surrounding the second nanostructure 110. An isolation component 146 is inserted between the first nanostructure 110 of the first gate-all-around field-effect transistor T1 and the second nanostructure 110 of the second gate-all-around field-effect transistor T1. The fin field-effect transistor T2 includes a floating fin element 106 and a third gate stack 160 on the floating fin element 106. A first gate cutting component 174 is inserted between the isolation component 146 and the third gate stack 160 of the first fin field-effect transistor T2. Therefore, for an integrated circuit including different types of devices, the hybrid structure can achieve lower process difficulty and greater design flexibility.

[0261] In addition, the method for forming the semiconductor structure includes forming the isolation component 146 before replacing the dummy gate structure 126 with the final gate stack 160, and forming the gate cutting component 174 after forming the final gate stack 160. Thus, the method of the embodiment of the present invention can reduce the difficulty of the etching process for forming the cutting trench and expand the filling tolerance of the metal gate structure, thereby improving device performance and product yield.

[0262] Embodiments of a semiconductor structure are provided herein. The semiconductor structure may include a first gate-all-around field-effect transistor and a first fin field-effect transistor adjacent to the first gate-all-around field-effect transistor. The first gate-all-around field-effect transistor may include a first nanostructure and a first gate stack surrounding the first nanostructure. The first fin field-effect transistor may include a first floating fin element and a second gate stack on the first floating fin element. The semiconductor structure may further include a gate cutting component, and the gate cutting component may be inserted between the first gate stack of the first gate-all-around field-effect transistor and the second gate stack of the first fin field-effect transistor. Therefore, through the semiconductor structure of the embodiment of the present invention, for an integrated circuit including different types of devices, lower process difficulty and greater design flexibility can be achieved.

[0263] In some embodiments, a semiconductor structure is provided. The semiconductor structure may include a first gate-all-around field-effect transistor (GAA FET) located on a substrate and a first fin field-effect transistor (FinFET) adjacent to the first gate-all-around field-effect transistor. The first gate-all-around field-effect transistor includes a plurality of first nanostructures and a first gate stack surrounding the first nanostructures. The first fin field-effect transistor includes a first fin structure and a second gate stack located on the first fin structure. The semiconductor structure further includes a gate cut component inserted between the first gate stack of the first gate-all-around field-effect transistor and the second gate stack of the first fin field-effect transistor. In some embodiments, the first fin field-effect transistor includes a lower fin element located under a first floating fin element. The first floating fin element and the lower fin element are separated by a portion of a gate dielectric layer of the second gate stack. In some embodiments, the first fin field-effect transistor includes an inner spacer layer interposed between the first floating fin element and the lower fin element and beside the above-mentioned portion of the gate dielectric layer. In some embodiments, the upper surface of the tallest nanostructure among the first nanostructures is substantially flush with the upper surface of the first fin structure. In some embodiments, the bottom surface of the lowest nanostructure among the first nanostructures is substantially flush with the bottom surface of the first floating fin element. In some embodiments, the semiconductor structure further includes a second fin field-effect transistor adjacent to the first fin field-effect transistor. The second fin field-effect transistor includes a second fin structure. The semiconductor structure further includes an isolation component inserted between the first fin structure of the first fin field-effect transistor and the second fin structure of the second fin field-effect transistor. In some embodiments, the semiconductor structure further includes a semiconductor stack along a lower portion of a sidewall of the isolation component and a spacer layer along an upper portion of the sidewall of the isolation component. In some embodiments, the semiconductor structure further includes a second gate-all-around field-effect transistor located on the substrate. The second gate-all-around field-effect transistor includes a plurality of second nanostructures. The isolation component is inserted between the first nanostructures of the first gate-all-around field-effect transistor and the second nanostructures of the second gate-all-around field-effect transistor.

[0264] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a first gate-all-around field-effect transistor, a second gate-all-around field-effect transistor, and a first fin field-effect transistor located over a substrate. The first gate-all-around field-effect transistor includes a plurality of first nanostructures and a first gate stack surrounding the first nanostructures. The second gate-all-around field-effect transistor includes a plurality of second nanostructures and a second gate stack surrounding the second nanostructures. The first fin field-effect transistor includes a first fin structure and a third gate stack located over the first fin structure. The semiconductor structure further includes an isolation component inserted between the first nanostructures of the first gate-all-around field-effect transistor and the second nanostructures of the second gate-all-around field-effect transistor. The semiconductor structure further includes a first gate cut component inserted between the first gate stack of the first gate-all-around field-effect transistor and the third gate stack of the first fin field-effect transistor. In some embodiments, the first gate stack of the first gate-all-around field-effect transistor includes a first gate dielectric layer and a first gate electrode layer located over the first gate dielectric layer. The first gate dielectric layer and the first gate electrode layer directly contact the first gate cut component. In some embodiments, the semiconductor structure further includes a second fin field-effect transistor located over the substrate. The second fin field-effect transistor includes a second fin structure and a fourth gate stack located over the second fin structure. The fourth gate stack includes a fourth gate dielectric layer and a fourth gate electrode layer located over the fourth gate dielectric layer. The fourth gate dielectric layer directly contacts the isolation component, and the fourth gate electrode layer is separated from the isolation component by the fourth gate dielectric layer. In some embodiments, the isolation component includes a dielectric fill layer and a dielectric liner surrounding the dielectric fill layer and contacting the fourth gate dielectric layer. In some embodiments, the dielectric fill layer contacts the fourth gate dielectric layer.

[0265] In some embodiments, a method of forming a semiconductor structure is provided. The method includes forming a first semiconductor layer and a second semiconductor layer over a substrate in sequence, etching the second semiconductor layer to form a recess in a first region of the substrate, alternately stacking a plurality of third semiconductor layers and a plurality of fourth semiconductor layers over the first semiconductor layer from the recess, patterning the third semiconductor layer, the fourth semiconductor layer, and the first semiconductor layer to form a first fin structure in the first region of the substrate, and patterning the second semiconductor layer and the first semiconductor layer to form a second fin structure in a second region of the substrate, removing the fourth semiconductor layer and the first semiconductor layer from the first fin structure to form a plurality of nanostructures from the third semiconductor layer of the first fin structure, and removing the first semiconductor layer from the second fin structure to form a floating fin element from the second semiconductor layer of the second fin structure, forming a first gate stack across the nanostructures and the floating fin element, and after forming the first gate stack, forming a first gate cut component through the first gate stack. In some embodiments, the method further includes forming an isolation component through the first fin structure before forming the nanostructures and the floating fin element. In some embodiments, the method further includes forming a dummy gate structure across the first fin structure and the second fin structure, forming a gate spacer layer along sidewalls of the dummy gate structure, etching the dummy gate structure and the first fin structure to form a cut trench, filling the cut trench with a dielectric material to form the isolation component, and after forming the isolation component, removing the dummy gate structure. In some embodiments, the step of etching the dummy gate structure and the first fin structure includes a main etching step with a first duty cycle and an over-etching step with a second duty cycle, the second duty cycle being lower than the first duty cycle. After the over-etching step, a bottom surface of the cut trench is lower than an upper surface of the substrate. In some embodiments, the method further includes forming a second gate stack across the floating fin element and adjacent to the isolation component, and forming a second gate cut component through a portion of the isolation component and a portion of the second gate stack. In some embodiments, the first semiconductor layer and the fourth semiconductor layer are formed of silicon germanium, and the second semiconductor layer and the third semiconductor layer are formed of silicon.

[0266] The foregoing outlines components of several embodiments so that those of ordinary skill in the art may better understand the aspects of the embodiments of the present invention. Those of ordinary skill in the art should understand that they can readily use the embodiments of the present invention as a basis to design or modify other processes and structures for achieving the same purposes and / or advantages as those introduced herein. Those of ordinary skill in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention shall be defined as that determined by the appended claims.

Claims

1. A semiconductor structure, comprising: A first all-around gate field-effect transistor located on a substrate, wherein the first all-around gate field-effect transistor comprises: a plurality of first nanostructures and a first gate stack surrounding the plurality of first nanostructures; A first fin field-effect transistor adjacent to the first all-around gate field-effect transistor, wherein the first fin field-effect transistor comprises: a first fin structure and a second gate stack located on the first fin structure, wherein the first fin structure comprises: a first floating fin element, and the second gate stack of the first fin field-effect transistor comprises: a gate dielectric layer covering an upper surface, sidewalls, and a bottom surface of the first floating fin element; and A gate cutting component inserted between the first gate stack of the first all-around gate field-effect transistor and the second gate stack of the first fin field-effect transistor.

2. The semiconductor structure according to claim 1, wherein the first fin field-effect transistor comprises: A lower fin element located under the first floating fin element, wherein the first floating fin element and the lower fin element are separated by a part of the gate dielectric layer of the second gate stack.

3. The semiconductor structure according to claim 2, wherein the first fin field-effect transistor comprises: An inner spacer layer between the first floating fin element and the lower fin element and beside the part of the gate dielectric layer.

4. The semiconductor structure according to claim 1, wherein an upper surface of the tallest nanostructure among the plurality of first nanostructures is flush with an upper surface of the first fin structure.

5. The semiconductor structure according to claim 1, wherein a bottom surface of the lowest nanostructure among the plurality of first nanostructures is flush with a bottom surface of a first floating fin element.

6. The semiconductor structure according to claim 1, further comprising: A second fin field-effect transistor adjacent to the first fin field-effect transistor, wherein the second fin field-effect transistor comprises: a second fin structure; and An isolation component inserted between the first fin structure of the first fin field-effect transistor and the second fin structure of the second fin field-effect transistor.

7. The semiconductor structure according to claim 6, further comprising: A semiconductor stack along a lower part of a sidewall of the isolation component; and A spacer layer along an upper part of the sidewall of the isolation component.

8. The semiconductor structure according to claim 6, further comprising: A second all-around gate field-effect transistor located on the substrate, wherein the second all-around gate field-effect transistor comprises: a plurality of second nanostructures, wherein the isolation component is inserted between the plurality of first nanostructures of the first all-around gate field-effect transistor and the plurality of second nanostructures of the second all-around gate field-effect transistor.

9. A semiconductor structure, comprising: A first all-around gate field-effect transistor located on a substrate, wherein the first all-around gate field-effect transistor comprises: a plurality of first nanostructures and a first gate stack surrounding the plurality of first nanostructures; A second all-around gate field-effect transistor is located on the substrate, where the second all-around gate field-effect transistor includes: a plurality of second nanostructures and a second gate stack surrounding the plurality of second nanostructures; An isolation component is inserted between the plurality of first nanostructures of the first all-around gate field-effect transistor and the plurality of second nanostructures of the second all-around gate field-effect transistor, where the bottom surface of the isolation component is lower than the upper surface of the substrate; A first fin field-effect transistor is located on the substrate, where the first fin field-effect transistor includes: a first fin structure and a third gate stack located on the first fin structure; and A first gate cutting component is inserted between the first gate stack of the first all-around gate field-effect transistor and the third gate stack of the first fin field-effect transistor.

10. The semiconductor structure according to claim 9, where the first gate stack of the first all-around gate field-effect transistor includes: A first gate dielectric layer; and A first gate electrode layer located on the first gate dielectric layer, where the first gate dielectric layer and the first gate electrode layer are in direct contact with the first gate cutting component.

11. The semiconductor structure according to claim 9, further includes: A second fin field-effect transistor is located on the substrate, where the second fin field-effect transistor includes: a second fin structure and a fourth gate stack located on the second fin structure, where the fourth gate stack includes: A fourth gate dielectric layer, where the fourth gate dielectric layer is in direct contact with the isolation component; and A fourth gate electrode layer located on the fourth gate dielectric layer, where the fourth gate electrode layer and the isolation component are separated by the fourth gate dielectric layer.

12. The semiconductor structure according to claim 11, where the isolation component includes: A dielectric filling layer; and A dielectric liner surrounding the dielectric filling layer and contacting the fourth gate dielectric layer.

13. The semiconductor structure according to claim 12, where the dielectric filling layer is in contact with the fourth gate dielectric layer.

14. A method for forming a semiconductor structure, including: Sequentially forming a first semiconductor layer and a second semiconductor layer on a substrate; Etching the second semiconductor layer to form a depression in a first region of the substrate; Alternately stacking a plurality of third semiconductor layers and a plurality of fourth semiconductor layers on the first semiconductor layer from the depression; Patterning the plurality of third semiconductor layers, the plurality of fourth semiconductor layers, and the first semiconductor layer to form a first fin structure in the first region of the substrate, and patterning the second semiconductor layer and the first semiconductor layer to form a second fin structure in a second region of the substrate; Removing the plurality of fourth semiconductor layers and the first semiconductor layer from the first fin structure to form a plurality of nanostructures from the plurality of third semiconductor layers of the first fin structure, and removing the first semiconductor layer from the second fin structure to form a floating fin element from the second semiconductor layer of the second fin structure, where an isolation component is formed through the first fin structure before forming the plurality of nanostructures and the floating fin element; Form a first gate stack across the plurality of nanoscale structures and the floating fin element; And After forming the first gate stack, form a first gate cut component through the first gate stack.

15. The method of forming a semiconductor structure according to claim 14, further comprising: Form a dummy gate structure across the first fin structure and the second fin structure; Form a gate spacer layer along the sidewalls of the dummy gate structure; Etch the dummy gate structure and the first fin structure to form a cut trench; Fill the cut trench with a dielectric material to form the isolation component; And After forming the isolation component, remove the dummy gate structure.

16. The method of forming a semiconductor structure according to claim 15, wherein the step of etching the dummy gate structure and the first fin structure comprises: A main etching step with a first duty cycle; And An over-etching step with a second duty cycle, wherein the second duty cycle is lower than the first duty cycle, and after the over-etching step, the bottom surface of the cut trench is lower than the upper surface of the substrate.

17. The method of forming a semiconductor structure according to claim 14, further comprising: Form a second gate stack across the floating fin element and adjacent to the isolation component, and Form a second gate cut component through a portion of the isolation component and a portion of the second gate stack.

18. The method of forming a semiconductor structure according to claim 14, wherein the first semiconductor layer and the plurality of fourth semiconductor layers are formed of silicon germanium, and the second semiconductor layer and the plurality of third semiconductor layers are formed of silicon.

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