Integrated chip and method for forming transistor device

Abstract

In some embodiments, the present disclosure relates to an integrated chip comprising a gate dielectric layer, a gate electrode, a field plate dielectric layer, and a field plate. The gate dielectric layer is disposed on a substrate and between a source region and a drain region. The gate electrode is disposed on the gate dielectric layer. The field plate dielectric layer is disposed on the substrate and between the gate dielectric layer and the drain region. The field plate is disposed on the field plate dielectric layer and spaced apart from the gate dielectric layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to an integrated chip and a method of forming a transistor device. Background Art

[0002] Power metal-oxide-semiconductor field-effect transistors (MOSFETs) are MOSFETs designed to handle high power levels (e.g., high voltage and / or high current). Power MOSFETs are used in display drivers, power converters, motor controllers, and vehicle power units. One type of power MOSFET is the laterally diffused metal-oxide semiconductor (LDMOS) transistor. LDMOS transistors offer high gain, high power output, and high efficiency at high frequencies, making them commonly used with microwave and radio frequency (RF) power amplifiers. Summary of the Invention

[0003] An embodiment of the present invention provides an integrated chip, comprising: a gate dielectric layer, arranged on a substrate and between a source region and a drain region; a gate electrode, arranged on the gate dielectric layer; a field plate dielectric layer, arranged on the substrate and between the gate dielectric layer and the drain region; and a field plate, arranged on the field plate dielectric layer, wherein the field plate dielectric layer is separated from the gate dielectric layer.

[0004] An embodiment of the present invention provides an integrated chip, comprising: a gate electrode, disposed on a substrate between a first source / drain region and a second source / drain region; a field plate dielectric layer, disposed on the substrate and between the gate electrode and the second source / drain region; a field plate, disposed on a central portion of the field plate dielectric layer; and a spacer structure, disposed on an outer portion of the field plate dielectric layer and surrounding an outer side wall of the field plate.

[0005] An embodiment of the present invention provides a method for forming a transistor device, comprising: forming a source region separated from a drain region on or within a substrate; forming a continuous field plate dielectric layer above the substrate; forming a continuous field plate layer above the continuous field plate dielectric layer; performing a first removal process to remove an outer portion of the continuous field plate layer to form a field plate, and removing an outer portion of the continuous field plate dielectric layer; forming a spacer structure on the outer side wall of the field plate and above the substrate; forming a continuous gate dielectric layer above the substrate and the field plate; forming a continuous gate electrode layer above the continuous gate dielectric layer; and performing a second removal process to remove an outer portion of the continuous gate electrode layer and an outer portion of the continuous gate dielectric layer, thereby forming a gate electrode above the gate dielectric layer separated from the field plate and the continuous field plate dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 Cross-sectional views illustrating some embodiments of a laterally diffused metal oxide semiconductor (LDMOS) transistor having a field plate disposed over a field plate dielectric layer and laterally surrounded by spacer structures.

[0008] Figure 2 illustrate Figure 1 Cross-sectional views of some alternative embodiments of LDMOS transistors are shown in which the field plate has a topmost surface that is lower than a topmost surface of the gate electrode.

[0009] Figure 3 Cross-sectional views illustrating still other embodiments of LDMOS transistors including a field plate dielectric layer that is thicker than and spaced apart from the gate dielectric layer.

[0010] Figure 4 Cross-sectional views illustrating some embodiments of a III / V power device having a field plate disposed over a field plate dielectric layer and laterally surrounded by spacer structures.

[0011] Figures 5 to 21 Cross-sectional views illustrating some embodiments of a method of forming a high power device by first forming a field plate and then forming a gate electrode laterally alongside the field plate to reduce the spacing between the field plate and the gate electrode.

[0012] Figure 22 Description and Figures 5 to 21Flowcharts of some embodiments of methods of forming high power devices corresponding to the methods described in FIG.

[0013] [Explanation of Symbols]

[0014] 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2100: Cross-sectional view

[0015] 102: substrate

[0016] 104: Low-doped drift region

[0017] 106a: first source / drain region

[0018] 106b: second source / drain region

[0019] 107: Channel area

[0020] 108: Field board

[0021] 108t, 110t: top surface

[0022] 110: Gate electrode

[0023] 112: Field plate dielectric layer

[0024] 112c, 902c: center part

[0025] 112p, 902p: outer part

[0026] 114: Spacer structure

[0027] 116: Gate dielectric layer

[0028] 118: Dielectric spacer layer

[0029] 120: Internal connection structure

[0030] 122: Internal connection hole

[0031] 124: Internal connection wiring

[0032] 126: Interconnect Dielectric Structure

[0033] 202: Silicide layer

[0034] 402: Channel layer

[0035] 404: Valid Layer

[0036] 406: Isolation Structure

[0037] 408: Passivation layer

[0038] 410a: First source / drain contact

[0039] 410b: Second source / drain contact

[0040] 602: First masking structure

[0041] 604: Ion Implantation Process

[0042] 702: Continuous field plate dielectric layer

[0043] 704: Continuous field plate layer

[0044] 802: Second masking structure

[0045] 1002: Continuous spacer layer

[0046] 1302: Continuous gate dielectric layer

[0047] 1402: Continuous gate layer

[0048] 1404: Third masking structure

[0049] 1702: Conformal dielectric layer

[0050] 2200: Method

[0051] 2202, 2204, 2206, 2208, 2210, 2212, 2214, 2216: Action

[0052] d1: first distance

[0053] d2: second distance

[0054] d3: third distance

[0055] d4: fourth distance

[0056] d5: fifth distance

[0057] d6: sixth distance

[0058] d7: seventh distance DETAILED DESCRIPTION

[0059] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are set forth below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include embodiments in which the first feature and the second feature are formed to be in direct contact, and may also include embodiments in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0060] Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," and "upper," may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0061] Laterally diffused metal oxide semiconductor (LDMOS) transistors are high-voltage devices commonly used in amplifiers, such as microwave power amplifiers, audio power amplifiers, and radio frequency (RF) amplifiers. For example, in some RF amplifiers, LDMOS transistors are coupled and integrated into the RF amplifier to assist with envelope tracking, in which the power supplied to the RF amplifier is continuously manipulated to improve the efficiency of the RF amplifier. In some examples, LDMOS transistors have a field plate, which is a conductive element disposed above the drift region to enhance device performance by manipulating the electric field generated by the gate electrode (e.g., reducing the peak electric field). By manipulating the electric field generated by the gate electrode, LDMOS transistors can achieve a higher breakdown voltage.

[0062] In some embodiments, a field plate is disposed between the drain region and the gate electrode in an LDMOS transistor. To reduce capacitance between the gate electrode and the drain region, the field plate is spaced apart from the gate electrode and electrically coupled to the source region. By reducing capacitance between the gate electrode and the drain region, the on-state resistance of the LDMOS transistor can be reduced, thereby reducing power loss during on- and off-state switching.

[0063] In some embodiments, to form an LDMOS transistor including a field plate and a gate electrode, a gate dielectric layer and a field plate dielectric layer are formed over a substrate. The field plate dielectric layer may have a thickness greater than the gate dielectric layer. The field plate and gate electrode may then be formed simultaneously by depositing an electrode layer over the gate dielectric layer and the field plate dielectric layer, and removing portions of the electrode layer to form a field plate disposed over the field plate dielectric layer and spaced apart from a gate electrode disposed over the gate dielectric layer. However, in these embodiments, the width of the gate dielectric layer and the width of the field plate dielectric layer may be large to provide a larger processing window, which is required to ensure that the field plate is formed directly over the field plate dielectric layer and the gate electrode is formed directly over the gate dielectric layer.

[0064] Various embodiments of the present disclosure relate to reducing the spacing between a field plate and a gate electrode in a high-power device (e.g., an LDMOS transistor) by forming a field plate first and then forming the gate electrode. In some embodiments, a continuous field plate dielectric layer can be formed above a substrate, and then a field plate layer is formed above the field plate dielectric layer. The continuous field plate dielectric layer can be patterned together with the field plate layer using a spacer structure to form a field plate above the field plate dielectric layer. In these embodiments, the width of the field plate dielectric layer is reduced because a land-on process window for landing the field plate on the field plate dielectric layer is no longer required. As a result, the total area of ​​a high-power device (e.g., an LDMOS device) on the substrate can be reduced by approximately 15% to 20%, thereby increasing device density without sacrificing the reliability of the high-power device (e.g., the LDMOS device).

[0065] Figure 1 A cross-sectional view 100 illustrates some embodiments of an LDMOS transistor including a field plate dielectric layer completely spaced apart from a gate dielectric layer.

[0066] Figure 1The cross-sectional view 100 of FIG. 1 includes a first source / drain region 106 a and a second source / drain region 106 b disposed within a substrate 102. In some other embodiments, the first source / drain region 106 a and the second source / drain region 106 b may be disposed above the substrate 102. In some embodiments, the first source / drain region 106 a and the second source / drain region 106 b may have a first doping type (e.g., n-type) with a first dopant concentration. In some embodiments, the second source / drain region 106 b is also disposed within a low-doped drift region 104 of the substrate 102. In these embodiments, the low-doped drift region 104 may be a portion of the substrate 102 of the first doping type (e.g., n-type) with a second dopant concentration that is less than the first dopant concentration. In some embodiments, the first source / drain region 106 a is spaced apart from the low-doped drift region 104, and the channel region 107 separates the first source / drain region 106 a from the low-doped drift region 104. In some embodiments, the first source / drain region 106 a may correspond to a source region, and the second source / drain region 106 b may correspond to a drain region. In some embodiments, the substrate 102 is undoped or doped with a second doping type (e.g., p-type) that is different from the first doping type (e.g., n-type).

[0067] Furthermore, a field plate 108 and a gate electrode 110 are disposed on the substrate 102. The field plate 108 and the gate electrode 110 are laterally spaced apart. In some embodiments, the field plate 108 directly overlies the low-doped drift region 104, and the gate electrode 110 directly overlies the channel region 107. In some embodiments, the field plate 108 is directly disposed on the field plate dielectric layer 112, and the gate electrode 110 is directly disposed on the gate dielectric layer 116. In some embodiments, the gate dielectric layer 116 is spaced apart from the field plate dielectric layer 112 and therefore does not contact the field plate dielectric layer 112. In some embodiments, the field plate dielectric layer 112 includes a central portion 112c and an outer portion 112p surrounding the central portion 112c. In some embodiments, the central portion 112c of the field plate dielectric layer 112 is thicker than the outer portion 112p of the field plate dielectric layer 112. Furthermore, in some embodiments, field plate 108 directly overlies central portion 112c of field plate dielectric layer 112 and does not directly overlie outer portions 112p of field plate dielectric layer 112. In some embodiments, spacer structure 114 laterally surrounds field plate 108 and directly overlies outer portions 112p of field plate dielectric layer 112. In these embodiments, spacer structure 114 may have a bottommost surface that is lower than the bottommost surface of field plate 108. In some embodiments, spacer structure 114 serves to protect field plate 108 during formation of field plate 108 on field plate dielectric layer 112 and also serves to protect field plate 108 when gate electrode 110 is formed after field plate 108 is formed. In some embodiments, gate dielectric layer 116 is thinner than both central portion 112c and outer portions 112p of field plate dielectric layer 112. Field plate 108 distributes the electric field between second source / drain region 106b and channel region 107. In these embodiments, since the field plate dielectric layer 112 has a higher breakdown voltage than the gate dielectric layer 116 , the field plate dielectric layer 112 may be thicker than the gate dielectric layer 116 .

[0068] In some embodiments, the topmost surface 108t of the field plate 108 is substantially coplanar with the topmost surface 110t of the gate electrode 110. In some embodiments, a dielectric spacer layer 118 may surround the gate electrode 110 and the field plate 108. In some embodiments, the spacer structure 114 may be disposed directly between the dielectric spacer layer 118 and the field plate 108. In some embodiments, the dielectric spacer layer 118 may protect the outer sidewalls of the field plate 108 and the outer sidewalls of the gate electrode 110 and provide electrical isolation between the field plate 108 and the gate electrode 110.

[0069] In some embodiments, an interconnect structure 120 is formed over the substrate 102, the field plate 108, and the gate electrode 110. In these embodiments, the interconnect structure 120 includes an interconnect via 122 and an interconnect wire 124 embedded in an interconnect dielectric structure 126. In some embodiments, to reduce capacitance between the gate electrode 110 and the second source / drain region 106b, the field plate 108 is electrically coupled to the first source / drain region 106a via the interconnect via 122 and the interconnect wire 124.

[0070] In some embodiments, the field plate 108 is formed before the gate electrode 110, and the field plate 108 and the field plate dielectric layer 112 are patterned simultaneously. Furthermore, in some embodiments, the gate electrode 110 and the gate dielectric layer 116 are formed simultaneously. In these embodiments, the spacing between the field plate 108 and the gate electrode 110 is more controllable, and thus the distance between the field plate 108 and the gate electrode 110 can be reduced to increase the device density of the LDMOS transistor without sacrificing electrical performance.

[0071] Figure 2 A cross-sectional view 200 illustrating some alternative embodiments of LDMOS transistors.

[0072] In some embodiments, the silicide layer 202 may be formed directly on the first source / drain region 106 a, the second source / drain region 106 b, the field plate 108, and / or the gate electrode 110. In some embodiments, the silicide layer 202 may include, for example, cobalt silicide, titanium silicide, nickel silicide, or some other suitable metal silicide material. In these embodiments, the silicide layer 202 may facilitate coupling the interconnect via 122 to the first source / drain region 106 a, the second source / drain region 106 b, the field plate 108, and / or the gate electrode 110.

[0073] Furthermore, in some embodiments, the topmost surface 110t of the gate electrode 110 can be disposed above the topmost surface 108t of the field plate 108. In these embodiments, planarization steps of the gate electrode 110 and / or the field plate 108 can be omitted during fabrication to reduce fabrication costs and improve time efficiency. However, when the topmost surface 110t of the gate electrode 110 and the topmost surface 108t of the field plate 108 are not substantially coplanar, simultaneously forming the interconnect via 122 on the field plate 108 and the gate electrode 110 can be challenging. In some embodiments, the thickness of the gate electrode 110 and the thickness of the field plate 108 can each be, for example, in a range between approximately 100 angstroms and approximately 2000 angstroms. In some embodiments, the gate dielectric layer 116 and the field plate dielectric layer 112 can each have a thickness in a range between approximately 10 angstroms and approximately 1000 angstroms, for example.

[0074] In some embodiments, the outer portion 112p of the field plate dielectric layer 112 has a width equal to the first distance d1. In some embodiments, for example, the first distance d1 may be in a range between approximately 5 nanometers and approximately 15 nanometers. In some embodiments, the field plate dielectric layer 112 is spaced apart from the interconnect via 122 disposed above the second source / drain region 106b by a second distance d2, for example, in a range between approximately 35 nanometers and approximately 40 nanometers. In some embodiments, the field plate 108 is spaced apart from the interconnect via 122 disposed above the second source / drain region 106b by a third distance d3, for example, in a range between approximately 45 nanometers and approximately 50 nanometers. In some embodiments, the field plate dielectric layer 112 is spaced apart from the gate dielectric layer 116 by a fourth distance d4, for example, in a range between approximately 50 nanometers and approximately 60 nanometers. In some embodiments, field plate 108 is spaced apart from gate electrode 110 by a fifth distance d5, which is, for example, in a range between approximately 60 nanometers and approximately 70 nanometers. In some embodiments, because field plate 108 and field plate dielectric layer 112 are formed simultaneously and before gate electrode 110 and gate dielectric layer 116, the width of field plate dielectric layer 112 can be reduced, thereby reducing the area of ​​the LDMOS transistor by approximately 15% to 20%.

[0075] Figure 3 A cross-sectional view 300 illustrates still other embodiments of an LDMOS transistor including a field plate disposed over a field plate dielectric layer and surrounded by a spacer structure.

[0076] In some embodiments, the field plate dielectric layer 112 has a substantially uniform thickness across its width. Thus, in some embodiments, the field plate dielectric layer 112 may not have an outer portion ( Figure 2 In these embodiments, the bottom surface of the spacer structure 114 and the bottom surface of the field plate dielectric layer 112 may directly contact the substrate 102 .

[0077] In some embodiments, the gate dielectric layer 116 and the field plate dielectric layer 112 comprise the same material, while in other embodiments, the gate dielectric layer 116 and the field plate dielectric layer 112 may comprise different materials. Similarly, in some embodiments, the spacer structure 114 comprises the same material as the field plate dielectric layer 112, while in other embodiments, the spacer structure 114 comprises a different material than the field plate dielectric layer 112. In still other embodiments, the spacer structure 114 may include multiple material layers. In some embodiments, the gate dielectric layer 116, the field plate dielectric layer 112, and the spacer structure 114 may comprise, for example, one or more of the following materials: oxide (e.g., silicon dioxide), silicon oxynitride, silicon nitride, etc.

[0078] Furthermore, since the gate electrode 110 and the field plate 108 are formed separately, in some embodiments, the gate electrode 110 and the field plate 108 may comprise different materials. In other embodiments, the gate electrode 110 comprises the same material as the field plate 108. In some embodiments, the field plate 108 and the gate electrode 110 may comprise one or more of the following materials: a semiconductor material (e.g., polysilicon, amorphous silicon), a metal (e.g., titanium nitride, titanium, tantalum nitride, tantalum, aluminum, tungsten), or some other suitable conductive material.

[0079] In some embodiments, the dielectric spacer layer 118 and / or the interconnect dielectric structure 126 may include, for example, nitrides (e.g., silicon nitride, silicon oxynitride), carbides (e.g., silicon carbide), oxides (e.g., silicon oxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), low-k oxides (e.g., carbon-doped oxides, SiCOH), etc. Furthermore, in some embodiments, the interconnect vias 122 and the interconnect wires 124 may include conductive materials such as, for example, titanium, tantalum, aluminum, tungsten, copper, or some other suitable conductive materials.

[0080] Figure 4 A cross-sectional view 400 illustrates some embodiments of a GaN or III / V power device having a field plate disposed over a field plate dielectric layer and laterally surrounded by spacer structures.

[0081] In some embodiments, the field plate 108 and the gate electrode 110 are formed on the active layer 404 of the III / V semiconductor device. In these embodiments, the channel layer 402 may be disposed on the substrate 102 and between the substrate 102 and the active layer 404. In some embodiments, the channel layer 402 comprises a binary III / V semiconductor (e.g., a first III-nitride material such as gallium nitride or gallium arsenide), and the active layer 404 comprises a ternary III / V semiconductor (e.g., a second III-nitride material such as aluminum gallium nitride or aluminum gallium arsenide). In some embodiments, a first source / drain contact 410a is disposed on the active layer 404, and a second source / drain contact 410b is disposed on the active layer 404. In some embodiments, the first source / drain contact 410a and the second source / drain contact 410b comprise a conductive material such as titanium, tantalum, aluminum, or the like. In some embodiments, the first source / drain contact 410a, the second source / drain contact 410b, the gate electrode 110, and the field plate 108 are laterally surrounded by the passivation layer 408. In addition, in some embodiments, the isolation structure 406 may surround the outer sidewalls of the active layer 404 and the upper portion of the channel layer 402.

[0082] In some embodiments of the III / V power device, the field plate 108 is disposed on a field plate dielectric layer 112 and surrounded by a spacer structure 114, and the gate electrode 110 is disposed on a gate dielectric layer 116 and spaced apart from the field plate 108. It should be understood that the field plate 108 disposed on the field plate dielectric layer 112 and surrounded by the spacer structure 114 formed before the gate electrode 110 may also be used in devices other than III / V power devices or LDMOS transistors, and such other embodiments are also within the scope of the present disclosure.

[0083] During operation of the III / V power device, a heterojunction serving as the channel region 107 is formed at the interface between the active layer 404 and the channel layer 402. Current flows through the channel region 107, and the field plate 108 can be controlled to manipulate the electric field in the channel region 107 to reduce the breakdown voltage of the III / V power device. Because the field plate 108 is formed before the gate electrode 110 and because the field plate 108 is formed simultaneously with the field plate dielectric layer 112, the field plate 108 can be positioned closer to the gate electrode 110 and the second source / drain contact 410 b, thereby increasing device density without sacrificing overall III / V power device performance.

[0084] Figures 5 to 21 Cross-sectional views 500 through 2100 illustrate some embodiments of a method of forming a high power device (eg, an LDMOS transistor) over a substrate, wherein a field plate is formed prior to forming a gate electrode to reduce the size of the high power device. Figures 5 to 21 It is about the method, but it should be understood that Figures 5 to 21 The structure disclosed in the method is not limited to the method, but can exist independently as a structure independent of the method.

[0085] like Figure 5 As shown in cross-sectional view 500 of FIG, a substrate 102 is provided. In various embodiments, the substrate 102 may include any type of semiconductor body (e.g., a silicon / complementary metal oxide semiconductor (CMOS) block, silicon germanium (SiGe), silicon on insulator (SOI), etc.), such as a semiconductor wafer or one or more dies located on a wafer, and any other type of semiconductor and / or epitaxial layer formed on and / or associated with the semiconductor.

[0086] like Figure 6 As shown in the cross-sectional view 600 of , in some embodiments, a first masking structure 602 is formed over the substrate 102, and an ion implantation process 604 is performed to dope the substrate 102 and form a low-doped drift region 104 within the substrate 102. In some embodiments, the first masking structure 602 can be formed using a photolithography process and a removal (e.g., etching) process. In some embodiments, the first masking structure 602 includes a photoresist or a hard mask material. In some embodiments, the low-doped drift region 104 can have a first doping type (e.g., n-type). In addition, in some embodiments, the substrate 102 can be undoped, or have a second doping type (e.g., p-type) that is different from the first doping type (e.g., n-type). In other embodiments, such as (for example) when the device to be formed is Figure 4 In the III / V power device described in , the formation of the low-doped drift region 104 can be omitted.

[0087] like Figure 7As shown in cross-sectional view 700 of FIG, in some embodiments, a continuous field plate dielectric layer 702 is formed over substrate 102. Furthermore, in some embodiments, a continuous field plate layer 704 is formed over the continuous field plate dielectric layer 702. In some embodiments, the continuous field plate dielectric layer 702 can be formed by a thermal oxidation process, an in-situ steam generation (ISSG) oxide process, or some other deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.). In some embodiments, the continuous field plate dielectric layer 702 can include, for example, an oxide (e.g., silicon dioxide), silicon oxynitride, silicon nitride, etc. In some embodiments, the continuous field plate dielectric layer 702 can have a thickness ranging from, for example, approximately 10 angstroms to approximately 1000 angstroms.

[0088] In some embodiments, the continuous field plate layer 704 may include, for example, a semiconductor material (e.g., polysilicon, amorphous silicon), a metal (e.g., titanium nitride, titanium, tantalum nitride, tantalum, aluminum, tungsten), or some other suitable conductive material. Furthermore, in some embodiments, the continuous field plate layer 704 may be formed by a deposition process (e.g., PVD, CVD, ALD, sputtering, etc.). In some embodiments, the continuous field plate layer 704 may have a thickness ranging from, for example, approximately 100 angstroms to approximately 2000 angstroms.

[0089] like Figure 8 As shown in the cross-sectional view 800 of FIG. , in some embodiments, a second masking structure 802 is formed over the continuous field plate layer 704. In some embodiments, the second masking structure 802 directly overlies the low-doped drift region 104. In some embodiments, the second masking structure 802 can be formed using a photolithography process and a removal (e.g., etching) process and include a photoresist or hard mask material. In some embodiments, the second masking structure 802 can have a width equal to the sixth distance d6, which is, for example, in a range between approximately 10 nanometers and approximately 1 micron.

[0090] like Figure 9 As shown in the cross-sectional view 900 of FIG. 8 , in some embodiments, a removal process is performed to remove the continuous field plate layer ( Figure 7704) to form the field plate 108 over the substrate 102. In some embodiments, after the removal process for forming the field plate 108, the continuous field plate dielectric layer 702 includes an outer portion 902p that is thinner than the central portion 902c, wherein the central portion 902c of the continuous field plate dielectric layer 702 is directly and completely located below the second masking structure 802. In these embodiments, the removal process also removes the upper portion of the continuous field plate dielectric layer 702 not covered by the second masking structure 802, but does not completely remove the continuous field plate dielectric layer 702 not covered by the second masking structure 802. Therefore, after the removal process for forming the field plate 108, the outer portion 902p of the continuous field plate dielectric layer 702 completely covers the substrate 102. For example, the outer portion 902p of the continuous field plate dielectric layer 702 can protect the substrate 102 from subsequent processing steps (e.g., dry etching / plasma etching).

[0091] In some other embodiments, the removal process used to form the field plate 108 may completely remove portions of the continuous field plate dielectric layer 702 not covered by the second masking structure 802. In such other embodiments, the substrate 102 may be damaged by subsequent processing steps such as, for example, dry etching / plasma etching.

[0092] In some embodiments, the removal process may be or include a dry etching process. In some embodiments, the removal process may include a process for removing the continuous field plate layer ( Figure 8 704) and a second dry etchant is used to remove portions of the continuous field plate dielectric layer 702. In some embodiments, the second dry etchant is different from the first dry etchant, while in other embodiments, the same dry etchant is used for the removal process. In some embodiments, the first dry etchant can be or include, for example, CF4, CHF3, C4F8, etc., and the second dry etchant can be or include, for example, chlorine, argon, HBr4, etc.

[0093] like Figure 10 As shown in the cross-sectional view 1000 of FIG. 1 , in some embodiments, a continuous spacer layer 1002 is formed on the substrate 102. In some embodiments, before forming the continuous spacer layer 1002, the second masking structure ( Figure 9 In other embodiments, the second masking structure ( Figure 9 802) may remain on the field plate 108 and may be formed on the second masking structure ( Figure 9 A continuous spacer layer 1002 is formed over the field plate dielectric layer 702 (shown as 802 ). However, in some embodiments, the continuous spacer layer 1002 may be formed over the continuous field plate dielectric layer 702 and over the field plate 108 .

[0094] In some embodiments, the continuous spacer layer 1002 can be formed by a thermal oxidation process and / or a deposition process (e.g., PVD, CVD, ALD, sputtering, etc.). In some embodiments, the continuous spacer layer 1002 can include, for example, an oxide (e.g., silicon dioxide), silicon oxynitride, silicon nitride, etc. In some embodiments, the continuous spacer layer 1002 can include multiple layers of the aforementioned materials. In some embodiments, the continuous spacer layer 1002 can have a thickness ranging from, for example, approximately 5 nanometers to approximately 15 nanometers.

[0095] like Figure 11 As shown in the cross-sectional view 1100 of FIG. 1 , in some embodiments, a removal process is performed to remove the continuous spacer layer ( Figure 10 1002) to form a spacer structure 114 that surrounds the field plate 108. In some embodiments, the spacer structure 114 is configured on the outer portion 902p of the continuous field plate dielectric layer 702 and is configured at the same height from the substrate 102 as the field plate 108. In some embodiments, the spacer structure 114 has substantially curved outer sidewalls, while in other embodiments, the spacer structure 114 may have flat / straight sidewalls, jagged / rough sidewalls, or a combination thereof. In some embodiments, the spacer structure 114 does not cover the topmost surface 108t of the field plate 108. In some embodiments, the removal process may be a dry etching process performed in a substantially vertical direction. In these embodiments, a masking structure may not be required to form the spacer structure 114. In some embodiments, Figure 11 The removal process may include a dry etchant such as, for example, CF 4 , CHF 3 , C 4 F 8 , etc. In some embodiments, the outer portion 902 p of the continuous field plate dielectric layer 702 protects the substrate 102 from being damaged by the removal process used to form the spacer structure 114 .

[0096] In some embodiments, the spacer structure 114 comprises the same material as the continuous field plate dielectric layer 702. In these embodiments, the continuous spacer layer ( Figure 10 The thickness of the substrate 1002 is controlled by a predetermined etching time. Figure 11 For example, in some embodiments, the predetermined etching time may be used to remove the Figure 11 Removal process to remove the continuous spacer layer ( Figure 10 1002), but without removing the continuous field plate dielectric layer 702. In some other embodiments, Figure 11 The removal process can remove some of the continuous field plate dielectric layer 702 so that the thickness of the continuous field plate dielectric layer 702 is reduced; however, Figure 11After the removal process, the continuous field plate dielectric layer 702 still completely covers the substrate 102 to protect the substrate 102 from being Figure 11 The removal process is damaged.

[0097] In some other embodiments, the Figure 11 The removal process is sufficient to completely remove the continuous spacer layer ( Figure 10 In other embodiments of this type, Figure 11 After the removal process, the continuous spacer layer ( Figure 10 The thin layer 1002 shown in FIG. 1002 may still remain on the continuous field plate dielectric layer 702. In such other embodiments, the thin layer 1002 may remain on the continuous field plate dielectric layer 702. Figure 12 The removal process removes the continuous spacer layer ( Figure 10 1002) of a thin layer (not shown).

[0098] like Figure 12 As shown in the cross-sectional view 1200 of FIG. 1 , in some embodiments, a removal process is performed to remove the continuous field plate dielectric layer ( Figure 11 The outer portion ( 702 ) not covered by the spacer structure 114 Figure 11 902p), thereby forming a field plate dielectric layer 112 disposed below the field plate 108 and the spacer structure 114. In some other embodiments, Figure 12 The removal process can also remove the field plate dielectric layer directly disposed on the continuous Figure 11 The outer portion ( Figure 11 902p) on a continuous spacer layer ( Figure 10 Furthermore, in some embodiments, if the field plate dielectric layer 112 and the spacer structure 114 comprise the same material, then Figure 12 The removal process can reduce the size of the spacer structure 114. However, in these embodiments, Figure 12 After the removal process, the spacer structure 114 may still exist to define the Figure 12 The field plate dielectric layer 112 is formed by a removal process.

[0099] In some embodiments, the field plate dielectric layer 112 includes an outer portion 112p disposed directly below the spacer structure 114 and a central portion 112c surrounded by the outer portion 112p and disposed directly below the field plate 108. In some embodiments, the central portion 112c of the field plate dielectric layer 112 is thicker than the outer portions 112p of the field plate dielectric layer 112. In some embodiments, the outer portions 112p of the field plate dielectric layer 112 have a width equal to a first distance d1. In some embodiments, the first distance d1 may be, for example, in a range between approximately 5 nanometers and approximately 15 nanometers.

[0100] In some embodiments, the removal process for forming the field plate dielectric layer 112 may be or include wet etching. In some embodiments, the wet etching may remove the continuous field plate dielectric layer ( Figure 11 In some embodiments, the removal process for forming the field plate dielectric layer 112 does not require a masking structure. In some other embodiments, Figure 12 The removal process may include a dry etchant such as, for example, CF4, CHF3, C4F8, etc. In addition, in some other embodiments, Figure 11 The removal process and Figure 12 The removal processes of the two may include the same dry etchant and may be performed simultaneously in a single step. In other embodiments, different etchants may be used to perform the removal processes of the two. Figure 11 The removal process and Figure 12 removal process.

[0101] Since the field plate dielectric layer 112 is formed based on the field plate 108 and the spacer structure 114, the field plate dielectric layer 112 can be considered to be formed together with the field plate 108 in a self-aligned process. In this way, the field plate dielectric layer 112 and the field plate 108 can have a smaller width, thereby reducing the device density of the overall LDMOS transistor.

[0102] like Figure 13 As shown in the cross-sectional view 1300 of FIG, in some embodiments, a continuous gate dielectric layer 1302 can be formed over the substrate 102. In some embodiments, the continuous gate dielectric layer 1302 can be formed by a thermal oxidation process and / or a deposition process (e.g., PVD, CVD, ALD, sputtering, etc.). In some embodiments, the continuous gate dielectric layer 1302 can include, for example, an oxide (e.g., silicon dioxide), silicon oxynitride, silicon nitride, etc. In some embodiments, the continuous gate dielectric layer 1302 can have a thickness ranging from, for example, approximately 10 angstroms to approximately 1000 angstroms. In some embodiments, the thickness of the continuous gate dielectric layer 1302 can be less than the thickness of the outer portion 112p and the central portion 112c of the field plate dielectric layer 112.

[0103] like Figure 14As shown in cross-sectional view 1400 of FIG, in some embodiments, a continuous gate layer 1402 is formed over the continuous gate dielectric layer 1302. In some embodiments, the continuous gate layer 1402 comprises the same material as the field plate 108, while in other embodiments, the continuous gate layer 1402 comprises a different material than the field plate 108. In some embodiments, the continuous gate layer 1402 may comprise, for example, a semiconductor material (e.g., polysilicon, amorphous silicon), a metal (e.g., titanium nitride, titanium, tantalum nitride, tantalum, aluminum, tungsten), or some other suitable conductive material. Furthermore, in some embodiments, the continuous gate layer 1402 may be formed by a deposition process (e.g., PVD, CVD, ALD, sputtering, etc.). In some embodiments, the continuous gate layer 1402 may have a thickness ranging from, for example, approximately 100 angstroms to approximately 2000 angstroms.

[0104] Furthermore, in some embodiments, a third masking structure 1404 is formed over the continuous gate layer 1402. In some embodiments, the third masking structure 1404 may be formed using a photolithography process and a removal (e.g., etching) process and may include a photoresist or hard mask material. In some embodiments, the third masking structure 1404 may have a width equal to a seventh distance d7, which may be, for example, in a range between approximately 10 nanometers and approximately 1 micron. In some embodiments, the third masking structure 1404 may partially overlie or not overlie the low-doped drift region 104.

[0105] like Figure 15 As shown in the cross-sectional view 1500 of FIG. 1 , in some embodiments, a removal process is performed to remove the mask according to the third masking structure ( Figure 14 1404) removes the continuous gate dielectric layer ( Figure 14 1302) and the outer portion of the continuous gate layer ( Figure 14 1402) to form a gate electrode 110 on the gate dielectric layer 116. In some embodiments, the removal process may be or include a dry etching process. In some embodiments, Figure 15 The removal process may include removing the continuous gate layer ( Figure 14 1402) and a first dry etchant for removing portions of the continuous gate dielectric layer ( Figure 14 In some embodiments, the first dry etchant may be or include, for example, CF4, CHF3, C4F8, etc., and the second dry etchant may be or include, for example, chlorine, argon, HBr4, etc. In some embodiments, the first dry etchant may be or include, for example, chlorine, argon, HBr4, etc. Figure 15 The third masking structure is removed during the removal process ( Figure 14 In some embodiments, a wet etchant or a dry etchant may be used to form the third masking structure ( Figure 14 1404) is removed.

[0106] In some embodiments, the gate electrode 110 may have a topmost surface 110t located above, below, or at approximately the same height above the substrate 102 as the topmost surface 108t of the field plate 108. Furthermore, in some embodiments, the gate dielectric layer 116 is completely separated from the field plate dielectric layer 112. In some embodiments, the gate dielectric layer 116 is disposed at a fourth distance d4 from the field plate dielectric layer 112, and the gate electrode 110 is disposed at a fifth distance d5 from the field plate 108. In some embodiments, the fourth distance d4 is, for example, in a range between approximately 50 nanometers and approximately 60 nanometers, and the fifth distance d5 is, for example, in a range between approximately 60 nanometers and approximately 70 nanometers. In some embodiments, since the field plate 108 and the field plate dielectric layer 112 are formed before forming the gate electrode 110 and the gate dielectric layer 116 , the fourth distance d4 and / or the fifth distance d5 are reduced, which may increase the device density of the overall LDMOS device on the substrate 102 by approximately 15% to 20%.

[0107] In some embodiments, the removal process may be or include a dry etching process. In some embodiments, the removal process may include a process for removing the continuous field plate layer ( Figure 8 704) and a second dry etchant is used to remove portions of the continuous field plate dielectric layer 702. In some embodiments, the second dry etchant is different from the first dry etchant, while in other embodiments, the same dry etchant is used for the removal process. In some embodiments, the first dry etchant can be or include, for example, CF4, CHF3, C4F8, etc., and the second dry etchant can be or include, for example, chlorine, argon, HBr4, etc.

[0108] In some embodiments, since the field plate 108 may be subjected to a higher voltage bias than the gate electrode 110 , the field plate dielectric layer 112 is thicker than the gate dielectric layer 116 to increase the breakdown voltage of the field plate 108 .

[0109] like Figure 16As shown in the cross-sectional view 1600 of FIG, in some embodiments, a planarization process (e.g., chemical mechanical planarization (CMP)) may be performed to make the topmost surface 110t of the gate electrode 110 substantially coplanar with the topmost surface 108t of the field plate 108. The planarization process may remove an upper portion of the gate electrode 110, an upper portion of the field plate 108, and / or an upper portion of the spacer structure 114. In some embodiments, because the gate dielectric layer 116 is thinner than the field plate dielectric layer 112, the gate electrode 110 is thicker than the field plate 108 even though the topmost surface 110t of the gate electrode is substantially coplanar with the topmost surface 108t of the field plate 108. When the topmost surface 110t of the gate electrode 110 is substantially coplanar with the topmost surface 108t of the field plate 108, an interconnect via (e.g., Figure 21 However, in some embodiments, the Figure 16 planarization process.

[0110] like Figure 17 As shown in cross-sectional view 1700 of FIG, in some embodiments, a conformal dielectric layer 1702 may be formed over the gate electrode 110 and the field plate 108. In some embodiments, the conformal dielectric layer 1702 may be formed by a thermal oxidation process and / or a deposition process (e.g., PVD, CVD, ALD, sputtering, etc.). In some embodiments, the conformal dielectric layer 1702 may include, for example, a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a low-k oxide (e.g., carbon-doped oxide, SiCOH), etc. In addition, in some embodiments, the conformal dielectric layer 1702 may include multiple layers of the aforementioned materials.

[0111] like Figure 18 As shown in cross-sectional view 1800 of FIG. 1 , in some embodiments, a removal process is performed to remove the conformal dielectric layer ( Figure 17 1702) to form a dielectric spacer layer 118 that laterally surrounds the gate electrode 110 and the spacer structure 114. In some embodiments, the dielectric spacer layer 118 provides structural protection for the gate electrode 110 and the field plate 108 and provides electrical isolation between the gate electrode 110 and the field plate 108. In some embodiments, Figure 18 After the removal process, the dielectric spacer layer 118 may have substantially curved outer sidewalls and upper surfaces, while in other embodiments, for example, the outer sidewalls and upper surfaces of the dielectric spacer layer 118 may be flat / sloped, jagged / rough, or a combination thereof.

[0112] In some embodiments, Figure 18 The removal process can be a dry etching process performed in a substantially vertical direction. In these embodiments, no masking structure is required to form the dielectric spacer layer 118. In some embodiments, Figure 18 The removal process may include a dry etchant such as, for example, CF4, CHF3, C4F8, etc.

[0113] like Figure 19 As shown in cross-sectional view 1900 of FIG, in some embodiments, an ion implantation process is performed to dope regions of substrate 102 to form first and second source / drain regions 106a, 106b in substrate 102. In some other embodiments, first and second source / drain regions 106a, 106b may be formed above substrate 102. In some embodiments, first and second source / drain regions 106a, 106b may have a first doping type (e.g., n-type) and may have a doping concentration greater than that of the low-doped drift region 104. In some embodiments, a masking structure (not shown) may be used during the ion implantation process to form first and second source / drain regions 106a, 106b in desired regions on substrate 102. In some embodiments, a gate electrode 110 and a field plate 108 are disposed between first and second source / drain regions 106a, 106b. In some embodiments, the first source / drain region 106a is a source region because the first source / drain region 106a is configured closer to the gate electrode 110 than to the field plate 108; and the second source / drain region 106b is a drain region because the second source / drain region 106b is configured closer to the field plate 108 than to the gate electrode 110.

[0114] like Figure 20As shown in the cross-sectional view 2000 of FIG, in some embodiments, a silicide layer 202 is formed over the first source / drain region 106a, the second source / drain region 106b, the field plate 108, and / or the gate electrode 110. In some embodiments, the silicide layer 202 can be formed by depositing a transition metal layer covering the first source / drain region 106a, the second source / drain region 106b, the field plate 108, and / or the gate electrode 110, and then heating the transition metal layer to react with the semiconductor material of the first source / drain region 106a, the second source / drain region 106b, the field plate 108, and / or the gate electrode 110. Therefore, in some embodiments, the silicide layer 202 can include nickel silicide, titanium silicide, cobalt silicide, platinum silicide, tungsten silicide, or some other metal semiconductor material. In some other embodiments, if the gate electrode 110 and / or the field plate 108 include metal instead of semiconductor material, no silicide layer is formed on the gate electrode 110 and / or the field plate 108 .

[0115] like Figure 21 As shown in cross-sectional view 2100 of FIG, in some embodiments, an interconnect structure 120 is formed over the substrate 102. In some embodiments, the interconnect structure 120 includes a network of interconnect vias 122 and interconnect wiring 124 coupled to the first source / drain region 106a, the second source / drain region 106b, the gate electrode 110, and / or the field plate 108. In some embodiments, the interconnect vias 122 and the interconnect wiring 124 are embedded within an interconnect dielectric structure 126. In some embodiments, the interconnect structure 120 is formed by various steps of a deposition process (e.g., PVD, CVD, ALD, sputtering, etc.), a removal process (e.g., wet etching, dry etching, CMP), and / or a patterning process (e.g., photolithography / etching). For example, in some embodiments, the interconnect structure 120 is formed by a single damascene process and / or a dual damascene process. In some embodiments, the interconnect dielectric structure 126 includes, for example, nitrides (e.g., silicon nitride, silicon oxynitride), carbides (e.g., silicon carbide), oxides (e.g., silicon oxide), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k oxides (e.g., carbon-doped oxides, SiCOH), etc. Furthermore, in some embodiments, the interconnect vias 122 and the interconnect wires 124 may include conductive materials such as, for example, titanium, tantalum, aluminum, tungsten, copper, or some other suitable conductive materials.

[0116] In some embodiments, the field plate 108 can be coupled to the first source / drain region 106a to reduce the capacitance between the gate electrode 110 and the second source / drain region 106b. In addition, in some embodiments, the field plate 108 is completely separated from the gate electrode 110 to reduce the capacitance between the gate electrode 110 and the second source / drain region 106b.

[0117] To reduce the capacitance between the gate electrode and the drain region, the field plate is spaced apart from the gate electrode and can be electrically coupled to the source region. By reducing the capacitance between the gate electrode and the drain region, the resistance of the LDMOS transistor when it is turned on is reduced, and thus the power loss of the LDMOS during on- and off-switching is reduced. However, by forming the field plate 108 on the field plate dielectric layer 112 before forming the gate electrode 110 on the gate dielectric layer 116, the overall device density of the LDMOS transistor can be increased while maintaining the reliability of the LDMOS transistor.

[0118] Figure 22 Description Figures 5 to 21 The cross-sectional views 500 to 2100 correspond to flow diagrams of some embodiments of the method 2200 .

[0119] Although method 2200 is described below and is set forth as a series of actions or events, it should be understood that the illustrated order of such actions or events should not be interpreted as having a limiting meaning. For example, some actions can occur in different orders and / or occur simultaneously with other actions or events other than the actions or events illustrated and / or described herein. In addition, it may not be necessary for all illustrated actions to implement one or more aspects or embodiments illustrated herein. In addition, one or more of the actions illustrated herein can be implemented in one or more separate actions and / or stages.

[0120] At act 2202, a lowly doped drift region is formed within a substrate. Figure 5 Cross-sectional view 500 is illustrated corresponding to some embodiments of act 2202 .

[0121] At act 2204 , a continuous field plate layer is formed over the continuous field plate dielectric layer on the substrate. Figure 6 Cross-sectional view 600 is illustrated corresponding to some embodiments of act 2204 .

[0122] At act 2206 , a first removal process is performed to remove outer portions of the continuous field plate layer to form a field plate over the continuous field plate dielectric layer and over the lowly doped drift region. Figure 8 Cross-sectional view 800 is illustrated corresponding to some embodiments of act 2206 .

[0123] At act 2208 , spacer structures are formed on the outer sidewalls of the field plate and over the substrate. Figure 10 Cross-sectional view 1000 is illustrated corresponding to some embodiments of act 2208 .

[0124] At act 2210, a continuous gate dielectric layer is formed over the substrate and the field plate. Figure 12 Cross-sectional view 1200 is illustrated corresponding to some embodiments of act 2210 .

[0125] At act 2212 , a gate electrode layer is formed over the continuous gate dielectric layer. Figure 13 Cross-sectional view 1300 is illustrated corresponding to some embodiments of act 2212 .

[0126] At act 2214 , a second removal process is performed to remove an outer portion of the gate electrode layer and an outer portion of the continuous gate dielectric layer to form a gate electrode over the gate dielectric layer. Figure 14 Cross-sectional view 1400 is illustrated corresponding to some embodiments of act 2214 .

[0127] At act 2216 , a first source / drain region and a second source / drain region are formed in the substrate, wherein a field plate and a gate electrode are located between the first source / drain region and the second source / drain region. Figure 18 Cross-sectional view 1800 is illustrated corresponding to some embodiments of act 2216 .

[0128] Therefore, the present disclosure is directed to forming a high power device having a field plate disposed over a field plate dielectric layer before a gate electrode over a gate dielectric layer to reduce the spacing between the field plate and the gate electrode, thereby increasing the device density of the overall high power device.

[0129] Therefore, in some embodiments, the present disclosure relates to an integrated chip, comprising: a gate dielectric layer configured on a substrate and between a source region and a drain region; a gate electrode configured on the gate dielectric layer; a field plate dielectric layer configured on the substrate and between the gate dielectric layer and the drain region; and a field plate configured on the field plate dielectric layer, wherein the field plate dielectric layer is separated from the gate dielectric layer.

[0130] In some other embodiments, the integrated chip further includes: a spacer structure surrounding the outer sidewall of the field plate and directly disposed on the field plate dielectric layer.

[0131] In some other embodiments, in the integrated chip, the spacer structure is directly configured on the outer portion of the field plate dielectric layer, wherein the field plate is directly configured on the central portion of the field plate dielectric layer, and wherein the central portion of the field plate dielectric layer is thicker than the outer portion of the field plate dielectric layer.

[0132] In some other embodiments, in the integrated chip, the field plate has a topmost surface configured at a first height above the topmost surface of the substrate, wherein the gate electrode has a topmost surface configured at a second height above the topmost surface of the substrate, and wherein the first height is approximately equal to the second height.

[0133] In some other embodiments, in the integrated chip, the field plate is electrically coupled to the source region.

[0134] In some other embodiments, in the integrated chip, the field plate comprises a material different from that of the gate electrode.

[0135] In some other embodiments, in the integrated chip, the field plate directly overlies the low-doped drift region of the substrate, and the low-doped drift region has a lower doping concentration than the drain region.

[0136] In other embodiments, the present disclosure relates to an integrated chip, comprising: a gate electrode disposed on a substrate between a first source / drain region and a second source / drain region; a field plate dielectric layer disposed on the substrate and between the gate electrode and the second source / drain region; a field plate disposed on a central portion of the field plate dielectric layer; and a spacer structure disposed on an outer portion of the field plate dielectric layer and surrounding an outer side wall of the field plate.

[0137] In some other embodiments, in the integrated chip, the central portion of the field plate dielectric layer is thicker than the outer portion of the field plate dielectric layer.

[0138] In some other embodiments, in the integrated chip, the substrate comprises gallium nitride.

[0139] In some other embodiments, in the integrated chip, the spacer structure has a topmost surface at the same height above a topmost surface of the substrate as the field plate.

[0140] In some other embodiments, the integrated chip further includes: a gate dielectric layer directly disposed between the gate electrode and the substrate, wherein the gate dielectric layer has a width equal to that of the gate electrode.

[0141] In some other embodiments, in the integrated chip, the gate dielectric layer has a first thickness, the outer portion of the field plate dielectric layer has a second thickness greater than the first thickness, and the central portion of the field plate dielectric layer has a third thickness greater than the second thickness.

[0142] In some other embodiments, in the integrated chip, the gate electrode is thicker than the field plate.

[0143] In some other embodiments, in the integrated chip, an upper surface of the field plate and an upper surface of the gate electrode are substantially coplanar.

[0144] In some other embodiments, the present disclosure relates to a method for forming a high-voltage transistor device, the method comprising: forming a source region separated from a drain region on or in a substrate; forming a continuous field plate dielectric layer above the substrate; forming a continuous field plate layer above the continuous field plate dielectric layer; performing a first removal process to remove an outer portion of the continuous field plate layer to form a field plate, and removing an outer portion of the continuous field plate dielectric layer; forming a spacer structure on the outer side wall of the field plate and above the substrate; forming a continuous gate dielectric layer above the substrate and the field plate; forming a continuous gate electrode layer above the continuous gate dielectric layer; and performing a second removal process to remove an outer portion of the continuous gate electrode layer and an outer portion of the continuous gate dielectric layer, thereby forming a gate electrode above the gate dielectric layer separated from the field plate and the field plate dielectric layer.

[0145] In some other embodiments, the method further includes: performing a third removal process after forming the spacer structure to further remove the outer portion of the continuous field plate dielectric layer that is not covered by the spacer structure or the field plate, thereby forming a field plate dielectric layer under the spacer structure and the field plate.

[0146] In some other embodiments, the method further includes: performing a planarization process to remove an upper portion of the field plate and / or an upper portion of the gate electrode, wherein after the planarization process, the topmost surface of the field plate is substantially coplanar with the topmost surface of the gate electrode.

[0147] In some other embodiments, the method further includes: forming an internal connection structure above the field plate and the gate electrode, the internal connection structure including an internal connection wiring and an internal connection through hole located in the internal connection dielectric layer, wherein the internal connection structure electrically couples the field plate to the source region.

[0148] In some other embodiments, in the method, the first removal process and the second removal process include dry etching.

[0149] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated chip comprising: a gate dielectric layer disposed on the substrate and between the source region and the drain region; a gate electrode, disposed on the gate dielectric layer; a field plate dielectric layer, disposed on the substrate and between the gate dielectric layer and the drain region; a field plate, disposed on the field plate dielectric layer; a spacer structure surrounding an outer sidewall of the field plate and directly disposed on the field plate dielectric layer and spaced apart from the gate electrode; as well as a dielectric spacer layer surrounding the gate electrode, the field plate and the spacer structure and contacting the gate electrode and the spacer structure; wherein the spacer structure separates the dielectric spacer layer from the field plate, The field plate dielectric layer is spaced apart from the gate dielectric layer, and the field plate has a topmost surface configured at a first height above a topmost surface of the substrate, the gate electrode has a topmost surface configured at a second height above the topmost surface of the substrate, and wherein the first height is equal to the second height, The field plate has a lowermost surface configured at a third height above the topmost surface of the substrate, the gate electrode has a lowermost surface configured at a fourth height above the topmost surface of the substrate, and wherein the third height is higher than the fourth height.

2. The integrated chip according to claim 1 , wherein the spacer structure is directly configured on an outer portion of the field plate dielectric layer, wherein the field plate is directly configured on a central portion of the field plate dielectric layer, and wherein the central portion of the field plate dielectric layer is thicker than the outer portion of the field plate dielectric layer, and the width of the outer portion of the field plate dielectric layer is equal to the width of the spacer structure. The integrated chip according to claim 1 , wherein the field plate is electrically coupled to the source region. The integrated chip according to claim 1 , wherein the field plate comprises a different material from that of the gate electrode. 5 . The integrated chip according to claim 1 , wherein the field plate directly overlies a low-doped drift region of the substrate, and wherein the low-doped drift region has a lower doping concentration than the drain region.

6. An integrated chip comprising: a gate electrode disposed on the substrate between the first source / drain region and the second source / drain region; a field plate dielectric layer, disposed on the substrate and between the gate electrode and the second source / drain region; a field plate disposed on a central portion of the field plate dielectric layer; as well as a spacer structure disposed on an outer portion of the field plate dielectric layer, surrounding an outer sidewall of the field plate and spaced apart from the gate electrode, wherein a lower portion of the spacer structure contacts an upper surface of the outer portion of the field plate dielectric layer, the lower portion of the spacer structure contacts a side surface of the central portion of the field plate dielectric layer, the upper surface of the outer portion of the field plate dielectric layer is directly connected to the side surface of the central portion of the field plate dielectric layer, and an upper portion of the spacer structure contacts the outer sidewall of the field plate. 7 . The integrated chip of claim 6 , wherein the central portion of the field plate dielectric layer is thicker than the outer portions of the field plate dielectric layer. The integrated chip according to claim 6 , wherein the substrate comprises gallium nitride. 9 . The integrated chip of claim 6 , wherein the spacer structure has a topmost surface at the same height above a topmost surface of the substrate as the field plate.

10. The integrated chip according to claim 6, further comprising: A gate dielectric layer is directly disposed between the gate electrode and the substrate, wherein the gate dielectric layer has a width equal to that of the gate electrode.

11. The integrated chip of claim 10, wherein the gate dielectric layer has a first thickness, wherein the outer portion of the field plate dielectric layer has a second thickness greater than the first thickness, and wherein the central portion of the field plate dielectric layer has a third thickness greater than the second thickness. 12 . The integrated chip according to claim 6 , wherein the gate electrode is thicker than the field plate. 13 . The integrated chip according to claim 12 , wherein an upper surface of the field plate is coplanar with an upper surface of the gate electrode.

14. A method of forming a transistor device, comprising: forming a source region separated from the drain region on or in the substrate; forming a continuous field plate dielectric layer on the substrate; forming a continuous field plate layer on the continuous field plate dielectric layer; performing a first removal process to remove an outer portion of the continuous field plate layer to form a field plate and to remove an outer portion of the continuous field plate dielectric layer; forming a spacer structure on an outer sidewall of the field plate and on the substrate; forming a continuous gate dielectric layer on the substrate and the field plate, such that an outer portion of the continuous gate dielectric layer covers and contacts the field plate dielectric layer, the field plate, and the spacer structure; forming a continuous gate electrode layer on the continuous gate dielectric layer; as well as A second removal process is performed to remove an outer portion of the continuous gate electrode layer and the covering of the continuous gate dielectric layer and contact the field plate dielectric layer, the field plate, and the outer portion of the spacer structure, thereby forming a gate electrode on the gate dielectric layer separated from the field plate and the continuous field plate dielectric layer.

15. The method according to claim 14, further comprising: After forming the spacer structure, a third removal process is performed to further remove an outer portion of the continuous field plate dielectric layer not covered by the spacer structure or the field plate, thereby forming a field plate dielectric layer under the spacer structure and the field plate.

16. The method according to claim 14, further comprising: A planarization process is performed to remove an upper portion of the field plate and / or an upper portion of the gate electrode, wherein after the planarization process, a topmost surface of the field plate is substantially coplanar with a topmost surface of the gate electrode.

17. The method according to claim 14, further comprising: An interconnect structure is formed above the field plate and the gate electrode, wherein the interconnect structure includes an interconnect wiring and an interconnect via located in an interconnect dielectric layer, wherein the interconnect structure electrically couples the field plate to the source region. The method according to claim 14 , wherein the first removal process and the second removal process comprise dry etching.

Images