Substrates and electronic packages with embedded electronic components

Abstract

The present disclosure provides a substrate and an electronic package embedded with electronic components, wherein the substrate embedded with electronic components includes: a first wiring layer; a first electronic component, which is arranged on the first wiring layer; a first insulating material, which covers at least a portion of each of the first wiring layer and the first electronic component; a second wiring layer, which is arranged on the first insulating material; a second electronic component, which is arranged on the second wiring layer and is connected to the first electronic component in an electrically parallel manner; a second insulating material, which is arranged on the first insulating material and covers at least a portion of each of the second wiring layer and the second electronic component; and a first via, which passes through the first insulating material and connects the first electronic component and the second wiring layer.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0167953 filed on December 16, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a substrate with embedded electronic components and an electronic package. Background Art

[0003] Recently, electronic devices are required to be not only thinner and smaller, but also have high performance and high functionality. Therefore, the number of electronic components to be mounted on a printed circuit board is increasing, while the number of electronic components that can be mounted on the surface of the printed circuit board is limited. For example, as the size and thickness of electronic devices decrease, the size of the printed circuit board is also required to decrease. Therefore, a technology for a substrate with electronic components embedded in a printed circuit board has been developed in which electronic components (such as passive components and active components) are embedded in the printed circuit board. Summary of the invention

[0004] This Summary is provided to introduce selected concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0005] An aspect of the present disclosure is to provide an electronic component-embedded substrate having a shortened electrical connection path.

[0006] An aspect of the present disclosure is to provide an electronic component-embedded substrate having improved power integrity (PI) characteristics due to an increase in capacitance and / or a decrease in equivalent series inductance (ESL) of the electronic component.

[0007] An aspect of the present disclosure is to provide a substrate embedded with electronic components with reduced warpage.

[0008] According to one aspect of the present disclosure, a substrate embedded with electronic components includes: a first wiring layer; a first electronic component disposed on the first wiring layer; a first insulating material covering at least a portion of each of the first wiring layer and the first electronic component; a second wiring layer disposed on the first insulating material; a second electronic component disposed on the second wiring layer and connected to the first electronic component in an electrically parallel manner; a second insulating material disposed on the first insulating material and covering at least a portion of each of the second wiring layer and the second electronic component; and a first via penetrating the first insulating material and connecting the first electronic component and the second wiring layer.

[0009] According to another aspect of the present disclosure, an electronic package includes: the above-mentioned substrate embedded with electronic components; a semiconductor package, mounted on the substrate embedded with electronic components through at least one first electrically connected metal piece; and a main board, the substrate embedded with electronic components is mounted on the main board through at least one second electrically connected metal piece.

[0010] According to another aspect of the present disclosure, a substrate embedded with electronic components includes: a first insulating material, surrounding one or more first electronic components; and a second insulating material, disposed on the first insulating material, and surrounding one or more second electronic components. The one or more first electronic components are connected to each other through a first wiring layer arranged on one side of the first insulating material. The one or more second electronic components are connected to each other through a second wiring layer arranged on the other side of the first insulating material. The one or more first electronic components are connected to the second wiring layer through vias. The one or more first electronic components are arranged to at least partially overlap with the one or more second electronic components in the stacking direction of the first insulating material and the second insulating material, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 schematically illustrates an example of a block diagram of an electronic device system according to an exemplary embodiment;

[0013] Figure 2 is a schematic perspective view of an electronic device according to an exemplary embodiment;

[0014] Figure 3 is a schematic cross-sectional view of a substrate with embedded electronic components according to an exemplary embodiment;

[0015] FIG. 4A to FIG. 8 schematically illustrates a process of manufacturing a substrate embedded with electronic components according to an exemplary embodiment;

[0016] Fig. 9 is a schematic cross-sectional view showing an example of an electronic package in which a semiconductor package is mounted on an electronic component-embedded substrate according to an exemplary embodiment; and

[0017] Fig.10 is a schematic circuit diagram illustrating circuits between electronic components included in an electronic component-embedded substrate according to an exemplary embodiment. DETAILED DESCRIPTION

[0018] The following detailed description is provided to help the reader gain a comprehensive understanding of the methods, devices and / or systems described herein. However, various changes, modifications and equivalents of the methods, devices and / or systems described herein will be apparent to those of ordinary skill in the art. The order of operations described herein is merely exemplary and is not limited to the order set forth herein, but changes may be made that will be apparent to those of ordinary skill in the art, except for operations that must be performed in a particular order. In addition, descriptions of functions and configurations that will be well known to those of ordinary skill in the art may be omitted for clarity and brevity.

[0019] The features described herein may be implemented in different forms and should not be construed as limited to the examples described herein. Rather, the examples described herein have been provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art.

[0020] Here, it is noted that the use of the term "may" with respect to an example or embodiment (e.g., with respect to what an example or embodiment may include or implement) means that there is at least one example or embodiment that includes or implements such features, while all examples and embodiments are not limited thereto.

[0021] Throughout the specification, when an element such as a layer, a region, or a substrate is described as being “on”, “connected to”, or “coupled to” another element, the element may be directly “on”, “connected to”, or “coupled to” another element, or one or more other elements may be present between them. In contrast, when an element is described as being “directly on”, “directly connected to”, or “directly coupled to” another element, other elements may not be present between them.

[0022] As used herein, the term "and / or" includes any one of the associated listed items and any combination of any two or more items.

[0023] Although terms such as "first", "second", and "third" may be used herein to describe various members, components, regions, layers, or portions, these members, components, regions, layers, or portions are not limited by these terms. Rather, these terms are only used to distinguish one member, component, region, layer, or portion from another member, component, region, layer, or portion. Therefore, without departing from the teachings of the examples described herein, the first member, first component, first region, first layer, or first portion referred to may also be referred to as the second member, second component, second region, second layer, or second portion.

[0024] For ease of description, spatially relative terms such as "above", "above", "below", and "below" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. Such spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientations depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element described as being "above" or "above" relative to another element will then be "below" or "below" relative to the other element. Therefore, the term "above" includes both "above" and "below" orientations depending on the spatial orientation of the device. The device may also be positioned in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative terms used herein will be interpreted accordingly.

[0025] The terms used herein are only used to describe various examples and are not used to limit the present disclosure. Unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. The terms "comprise", "include" and "have" list the existence of the stated features, quantities, operations, components, elements and / or their combinations, but do not exclude the existence or addition of one or more other features, quantities, operations, components, elements and / or their combinations.

[0026] Variations in the shapes shown in the drawings may occur due to manufacturing techniques and / or tolerances. Therefore, the examples described herein are not limited to the specific shapes shown in the drawings but include variations in shapes that occur during manufacturing.

[0027] The features of the examples described herein can be combined in various ways that will be apparent after understanding the disclosure of the present application. In addition, although the examples described herein have various configurations, other configurations that will be apparent after understanding the disclosure of the present application are feasible.

[0028] The drawings may not be drawn to scale, and the relative size, proportions, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience.

[0029] Subsequently, examples are described in more detail with reference to the accompanying drawings.

[0030] Electronic Devices

[0031] Figure 1 is a schematic block diagram illustrating an example of an electronic device system.

[0032] Reference Figure 1 , the electronic device 1000 may house a mainboard 1010 therein. The mainboard 1010 may include chip-related components 1020, network-related components 1030, other components 1040, etc., which are physically or electrically connected thereto. These components may be connected to other electronic components to be described below through various signal lines 1090.

[0033] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, etc.; application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processors (e.g., graphics processing units (GPU)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto, but may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may have the form of a package including the above-mentioned chips or electronic components.

[0034] The network-related components 1030 may include components that operate according to protocols such as: Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Only (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Wireless Local Area Network (LAN), Bluetooth, 3G protocol, 4G protocol and 5G protocol, as well as any other wireless protocols and wired protocols specified after the above protocols. However, the network-related component 1030 is not limited thereto, but may also include components operating according to various other wireless standards or protocols or wired standards or protocols. In addition, the network-related component 1030 may be combined with the above-mentioned chip-related component 1020 together with each other.

[0035] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramics (LTCC), electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto and may also include passive components for various other purposes, etc. In addition, the other components 1040 may also be combined with the chip-related components 1020 and / or the network-related components 1030.

[0036] Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that may or may not be physically connected or electrically connected to the mainboard 1010. These other components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, etc., but are not limited thereto. For example, these other components may also include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (e.g., a hard disk drive), a compact disk (CD) drive, a digital versatile disk (DVD) drive, etc. In addition, other electronic components for various purposes may be used according to the type of the electronic device 1000, etc.

[0037] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto, but may be any other electronic device that processes data.

[0038] Figure 2 is a schematic perspective view of an electronic device according to an example.

[0039] Reference Figure 2 , the electronic component may be, for example, a smart phone 1100. A mainboard 1110 may be housed in the smart phone 1100, and various electronic components 1120 may be physically or electrically connected to the mainboard 1110. In addition, other electronic components (such as a camera module 1130 and / or a speaker 1140) that may or may not be physically or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. Some of the electronic components 1120 may be chip-related components (e.g., semiconductor packages 1121), but are not limited thereto. The semiconductor package 1121 may be a surface mount type in which a device such as a semiconductor chip or a passive component is mounted on a package substrate in the form of a substrate having multiple layers in which electronic components are embedded, but is not limited thereto. On the other hand, the electronic device is not necessarily limited to the smart phone 1100, and may be another electronic device as described above.

[0040] Substrate with embedded electronic components

[0041] Figure 3 is a schematic cross-sectional view of a substrate with embedded electronic components according to an example.

[0042] Reference Figure 3, the electronic component-embedded substrate according to the example includes: a base substrate 110; an electronic component 120, embedded in the base substrate 110 through a connection conductor 121; a first accumulation structure 130, disposed on one side of the base substrate 110; a second accumulation structure 140, disposed on the other side of the base substrate 110; a first passivation layer 150, disposed on the first accumulation structure 130; and a second passivation layer 160, disposed on the second accumulation structure 140. If necessary, the electronic component-embedded substrate may further include an electrical connection metal member (not shown), which is disposed in an opening of each of the first passivation layer 150 and the second passivation layer 160.

[0043] In this specification, the meaning of "disposed on any component" is not limited to a direction, but refers to being disposed on the upper side or upper surface of any component. In some cases, the meaning of "disposed on any component" may be the case of being disposed on the lower side or lower surface of any component.

[0044] The base substrate 110 includes a region in which the electronic component 120 is embedded. The base substrate may include an insulating material 111, a wiring layer 112, a via 113, and a through via 114. Specifically, the base substrate includes: a first wiring layer 112A; a first insulating material 111A, covering the first wiring layer 112A; a second wiring layer 112B, arranged on the first insulating material 111A; a first via 113A, penetrating the first insulating material 111A, and connecting the second wiring layer 112B and the first electronic component 120A; a first through-hole 114A, penetrating the first insulating material 111A, and connecting the first wiring layer 112A and the second wiring layer 112B; a second insulating material 111B, arranged on the first insulating material 111A, and covering the second wiring layer 112B; a third wiring layer 112C, arranged on the second insulating material 111B; a second via 113B, penetrating the second insulating material 111B, and connecting the third wiring layer 112C and the second electronic component 120B; and a second through-hole 114B, penetrating the second insulating material 111B, and connecting the second wiring layer 112B and the third wiring layer 112C.

[0045] The first electronic component 120A is mounted on the first wiring layer 112A through the first connecting conductor 121A and is covered by the first insulating material 111A. In addition, as described above, the first electronic component 120A can be connected to the second wiring layer 112B through the first via 113A that penetrates the first insulating material 111A. On the other surface of the first insulating material 111A that is opposite to the surface of the first insulating material 111A on which the second insulating material 111B is disposed, the first insulating material 111A and the first wiring layer 112A may be coplanar. Therefore, the first wiring layer 112A may be exposed on the first insulating material 111A.

[0046] The second electronic component 120B is mounted on the second wiring layer 112B through the second connection conductor 121B and is covered by the second insulating material 111B. In addition, as described above, the second electronic component 120B can be connected to the third wiring layer 112C through the second via 113B that penetrates the second insulating material 111B. On the surface of the second insulating material 111B on which the first insulating material 111A is disposed, the second insulating material 111B and the second wiring layer 112B may be coplanar. Therefore, the second wiring layer 112B may be exposed on the second insulating material 111B.

[0047] The first electronic component 120A may be mounted on the first wiring layer 112A by surface mounting technology (SMT) through the first connection conductor 121A. Similarly, the second electronic component 120B may be mounted on the second wiring layer 112B by surface mounting technology (SMT) through the second connection conductor 121B.

[0048] The first electronic component 120A and the second electronic component 120B may be connected to each other through the first via 113A and the second wiring layer 112B. In this case, as described below, the first electronic component 120A and the second electronic component 120B may be connected in parallel. The first via 113A and the second wiring layer 112B are provided at a height between the first electronic component 120A and the second electronic component 120B so that the first electronic component 120A and the second electronic component 120B may be directly connected without passing through another wiring layer.

[0049] The first electronic component 120A and the second electronic component 120B are arranged along the thickness direction. At this time, the first electronic component 120A and the second electronic component 120B may be arranged in such a manner that the first electronic component 120A and the second electronic component 120B may overlap each other in the thickness direction. For example, the projections of the first electronic component 120A and the second electronic component 120B on a plane perpendicular to the thickness direction may overlap each other. In addition, the thickness direction may be the stacking direction of the first insulating material 111A and the second insulating material 111B.

[0050] As shown in the drawings, each of the first electronic component 120A and the second electronic component 120B can be a plurality of electronic components. In this case, the plurality of first electronic components 120A can be spaced apart from each other by a predetermined distance. In addition, the space between the plurality of first electronic components 120A can be filled with the first insulating material 111A, so that the plurality of first electronic components 120A can be spaced apart from each other by the first insulating material 111A. In addition, the plurality of second electronic components 120B can also be arranged in the same or similar manner as the plurality of first electronic components 120A described above. In addition, the plurality of first electronic components 120A can be arranged to at least partially overlap with the plurality of second electronic components 120B in the stacking direction of the first insulating material 111A and the second insulating material 111B, respectively.

[0051] The first electronic component 120A and the second electronic component 120B can be connected to a semiconductor package (not shown) mounted on a substrate embedded with electronic components through the wiring layers 132A and 132B included in the first accumulation structure 130. Therefore, the electrical connection path between the first electronic component 120A and / or the second electronic component 120B and the semiconductor package (not shown) can be shortened. In addition, the loss of electrical signals, etc. can be significantly reduced.

[0052] On the other hand, generally, the electronic components embedded in the substrate are embedded to be biased toward the side where the semiconductor package (not shown) is mounted so as to face the semiconductor package (not shown), thereby shortening the signal path with the semiconductor package (not shown) mounted on the substrate embedded with the electronic components. In this case, the substrate may have an asymmetric structure due to having an area where the electronic components are mounted and an area where the electronic components are not mounted, so warping and the like may occur. In the case of the substrate embedded with electronic components according to the example of the present disclosure, the first electronic component 120A and the second electronic component 120B are not embedded to be biased toward the side where the semiconductor package (not shown) is mounted, but are embedded in the base substrate 110 approximately symmetrically in the thickness direction. Therefore, the warping of the substrate can be reduced.

[0053] On the other hand, as described below, the first electronic component 120A and the second electronic component 120B may be passive components each having an electrode, for example, the first electronic component 120A may include a body 120Ab and an electrode 120Ap, and the second electronic component 120B may include a body 120Bb and an electrode 120Bp. In this case, the electrode 120Ap of the first electronic component 120A and the electrode 120Bp of the second electronic component 120B may be connected to each other through the first via 113A and the second wiring layer 112B of the base substrate 110. In addition, the electrode 120Ap of the first electronic component 120A and the electrode 120Bp of the second electronic component 120B may be connected in parallel. Therefore, the capacitance of the electronic component may be increased and / or the ESL (equivalent series inductance) may be reduced, and the power integrity (PI) characteristic may be improved.

[0054] Fig.10 A circuit diagram of a first electronic component 120A and a second electronic component 120B is schematically shown. Here, the capacitance value of the first electronic component 120A and the capacitance value of the second electronic component 120B are represented by C1 and C2, respectively. As shown in the drawings, since the first electronic component 120A and the second electronic component 120B are electrically connected in parallel to each other, the total capacitance value can be increased to C1+C2. At this time, as shown in the drawings, each of the first electronic component 120A and the second electronic component 120B is shown as a plurality of electronic components.

[0055] The first build-up structure 130 may include an insulating layer 131, a wiring layer 132, and a via 133. Specifically, the first build-up structure 130 includes: a first insulating layer 131A; a first wiring layer 132A disposed on the first insulating layer 131A; a first via 133A penetrating the first insulating layer 131A and connecting the first wiring layer 132A and the third wiring layer 112C of the base substrate 110 to each other; a second insulating layer 131B disposed on the first insulating layer 131A; a second wiring layer 132B disposed on the second insulating layer 131B; and a second via 133B penetrating the second insulating layer 131B and connecting the second wiring layer 132B and the first wiring layer 132A.

[0056] The second build-up structure 140 may include an insulating layer 141, a wiring layer 142, and a via 143. Specifically, the second build-up structure 140 includes: a first insulating layer 141A; a first wiring layer 142A disposed on the first insulating layer 141A; a first via 143A penetrating the first insulating layer 141A and connecting the first wiring layer 142A and the first wiring layer 112A of the base substrate 110 to each other; a second insulating layer 141B disposed on the first insulating layer 141A; a second wiring layer 142B disposed on the second insulating layer 141B; and a second via 143B penetrating the second insulating layer 141B and connecting the second wiring layer 142B and the first wiring layer 142A.

[0057] Hereinafter, each configuration of the electronic component-embedded substrate according to examples will be described in more detail.

[0058] As described above, the base substrate 110 includes: a first wiring layer 112A; a first insulating material 111A, covering the first wiring layer 112A; a second wiring layer 112B, arranged on the first insulating material 111A; a first via 113A, penetrating the first insulating material 111A, and connecting the second wiring layer 112B and the first electronic component 120A; a first through-hole 114A, penetrating the first insulating material 111A, and connecting the first wiring layer 112A and the second wiring layer 112B; a second insulating material 111B, arranged on the first insulating material 111A, and covering the second wiring layer 112B; a third wiring layer 112C, arranged on the second insulating material 111B; a second via 113B, penetrating the second insulating material 111B, and connecting the third wiring layer 112C and the second electronic component 120B; and a second through-hole 114B, penetrating the second insulating material 111B, and connecting the second wiring layer 112B and the third wiring layer 112C.

[0059] However, the structure of the base substrate 110 is not limited thereto, and those skilled in the art may change the base substrate 110 as needed. For example, the number of insulating material layers, wiring layers, and / or vias included in the base substrate 110 may be more or less than that shown in the drawings.

[0060] The forming material of each of the first insulating material 111A and the second insulating material 111B is not particularly limited, and any material can be used as long as the material has insulating properties. For example, a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), or a resin in which the thermosetting resin or the thermoplastic resin further contains a reinforcing material (such as an inorganic filler and / or glass cloth (glass fiber, glass fabric)) (for example, prepreg (PPG), ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT), etc.) can be used. If necessary, a photosensitive dielectric (PID) resin can be used.

[0061] The forming materials of the first insulating material 111A and the second insulating material 111B may be the same as or different from each other. In addition, the thickness of the first insulating material 111A and the thickness of the second insulating material 111B may be the same as or different from each other.

[0062] The boundary between the first insulating material 111A and the second insulating material 111B may be made indistinguishable depending on the materials, processes, etc. of the first insulating material 111A and the second insulating material 111B. For example, the first insulating material 111A and the second insulating material 111B are integrated with each other during the lamination process, or the boundary surface is unclear, so it may be difficult to visually inspect the boundary surface between the first insulating material 111A and the second insulating material 111B of the finished electronic component-embedded substrate structure.

[0063] Examples of materials for forming the first wiring layer 112A, the second wiring layer 112B, and the third wiring layer 112C include conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of the first wiring layer 112A, the second wiring layer 112B, and the third wiring layer 112C may perform various functions according to the design. For example, wiring patterns such as ground (GND) patterns, power (PWR) patterns, signal (S) patterns, etc. may be included. In this case, the signal (S) pattern includes various signal patterns (e.g., data signal patterns) in addition to the ground (GND) pattern and the power (PWR) pattern. In addition, via pads, etc. are included.

[0064] Examples of materials for forming the first via hole 113A and the second via hole 113B include conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of the first via hole 113A and the second via hole 113B may be completely filled with a conductive material, or a conductive material may be formed along the wall of the via hole to form the first via hole 113A and the second via hole 113B. In the case where the via hole is formed by forming a conductive material along the wall of the via hole, the inside of the via hole may be filled with an insulating material. In addition, all shapes known in the art (such as a conical shape and a cylindrical shape) may be used as the shape of each of the first via hole 113A and the second via hole 113B.

[0065] The first via 113A may have a structure integrated with the second wiring layer 112B connected to the first via 113 A. The second via 113B may have a structure integrated with the third wiring layer 112C connected to the second via 113B.

[0066] Examples of materials for forming the first through-hole 114A and the second through-hole 114B include conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of the first through-hole 114A and the second through-hole 114B may be formed by completely filling the via hole with a conductive material, or may be formed by forming the conductive material along the wall of the via hole. When the conductive material is formed along the wall of the via hole, when forming the first through-hole 114A or the second through-hole 114B, as shown in the drawings, the inside of the via hole may be filled with an insulating material. In addition, all shapes known in the art, such as a conical shape and a cylindrical shape, may be applied as the shape of each of the first through-hole 114A and the second through-hole 114B.

[0067] The first through via 114A may have a structure integrated with the second wiring layer 112B connected to the first through via 114 A. The second through via 114B may have a structure integrated with the third wiring layer 112C connected to the second through via 114B.

[0068] Each of the first electronic component 120A and the second electronic component 120B may be a chip capacitor having an electrode. For example, the first electronic component 120A and the second electronic component 120B may be a multilayer ceramic capacitor (MLCC), but are not limited thereto. In addition, as described above, the electrode 120Ap of the first electronic component 120A and the electrode 120Bp of the second electronic component 120B may be electrically connected in parallel. For example, each of the first electronic component 120A and the second electronic component 120B may include a first electrode and a second electrode, and the first electrode of the first electronic component 120A and the first electrode of the second electronic component 120B may be connected to each other, and the second electrode of the first electronic component 120A and the second electrode of the second electronic component 120B may be connected to each other.

[0069] However, the embodiment is not limited thereto, and each of the first electronic component 120A and the second electronic component 120B may be a passive component such as an inductor, and may be an active component such as an integrated circuit (IC) or a semiconductor chip.

[0070] Each of the first connection conductor 121A and the second connection conductor 121B may include solder or conductive paste. However, the present invention is not limited thereto, and any material may be used as a material for forming each of the first connection conductor 121A and the second connection conductor 121B.

[0071] As described above, the first accumulation structure 130 includes: a first insulating layer 131A; a first wiring layer 132A, which is arranged on the first insulating layer 131A; a first via 133A, which penetrates the first insulating layer 131A and connects the first wiring layer 132A and the third wiring layer 112C of the base substrate 110 to each other; a second insulating layer 131B, which is arranged on the first insulating layer 131A; a second wiring layer 132B, which is arranged on the second insulating layer 131B; and a second via 133B, which penetrates the second insulating layer 131B and connects the second wiring layer 132B and the first wiring layer 132A.

[0072] However, the structure of the first accumulation structure 130 is not limited thereto and may be changed as desired by those skilled in the art. For example, the number of insulating layers, wiring layers and / or vias included in the first accumulation structure 130 may be more or less than that shown in the drawings.

[0073] The forming material of each of the first insulating layer 131A and the second insulating layer 131B is not particularly limited, and any material can be used as long as the material has insulating properties. For example, a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), or a resin in which the thermosetting resin or the thermoplastic resin further contains a reinforcing material (such as an inorganic filler and / or glass cloth (glass fiber, glass fabric)) (for example, prepreg (PPG), ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT), etc.) can be used. If necessary, a photosensitive dielectric (PID) resin can be used.

[0074] Depending on the material and process of each of the first insulating layer 131A and the second insulating layer 131B, the boundary between the first insulating layer 131A and the second insulating layer 131B may be made indistinguishable. For example, because the first insulating layer 131A and the second insulating layer 131B are integrated with each other or the interface therebetween is not clear, it may be difficult to visually determine the boundary surface between the first insulating layer 131A and the second insulating layer 131B of the finished electronic component-embedded substrate structure.

[0075] In addition, depending on the materials and processes of the first insulating layer 131A and the second insulating material 111B, the boundary between the first insulating layer 131A and the second insulating material 111B may be made indistinguishable. For example, because the first insulating layer 131A and the second insulating material 111B are integrated with each other or the interface is not clear, it may be difficult to visually check the boundary surface between the first insulating layer 131A and the second insulating material 111B of the substrate structure in which the electronic components are embedded.

[0076] The thickness of the first insulating layer 131A and the thickness of the second insulating layer 131B may be respectively smaller than the thickness of each of the first insulating material 111A and the second insulating material 111B of the base substrate 110 in which the electronic component 120 is embedded.

[0077] Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or alloys thereof may be used as materials for forming each of the first wiring layer 132A and the second wiring layer 132B. Each of the first wiring layer 132A and the second wiring layer 132B may perform various functions according to the design. For example, the first wiring layer 132A and the second wiring layer 132B may include wiring patterns such as a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. In this case, the signal (S) pattern includes various signal patterns (e.g., data signal patterns) in addition to the ground (GND) pattern and the power (PWR) pattern. In addition, the first wiring layer 132A and the second wiring layer 132B include via pads, etc.

[0078] The material used to form the first via hole 133A and the second via hole 133B includes a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Each of the first via hole 133A and the second via hole 133B may be completely filled with a conductive material, or a conductive material may be formed along the wall of the via hole to form the first via hole 133A and the second via hole 133B. When the via hole is formed by forming a conductive material along the wall of the via hole, the inside of the via hole may be filled with an insulating material. In addition, all shapes known in the art (such as a conical shape and a cylindrical shape) may be applied to the shape of each of the first via hole 133A and the second via hole 133B.

[0079] The first via 133A may have a structure integrated with the first wiring layer 132A connected to the first via 133 A. The second via 133B may have a structure integrated with the second wiring layer 132B connected to the second via 133B.

[0080] As described above, the second accumulation structure 140 includes: a first insulating layer 141A; a first wiring layer 142A, which is arranged on the first insulating layer 141A; a first via 143A, which penetrates the first insulating layer 141A and connects the first wiring layer 142A and the first wiring layer 112A of the base substrate 110 to each other; a second insulating layer 141B, which is arranged on the first insulating layer 141A; a second wiring layer 142B, which is arranged on the second insulating layer 141B; and a second via 143B, which penetrates the second insulating layer 141B and connects the second wiring layer 142B and the first wiring layer 142A.

[0081] However, the structure of the second accumulation structure 140 is not limited thereto and may be changed as desired by those skilled in the art. For example, the number of insulating layers, wiring layers and / or vias included in the second accumulation structure 140 may be more or less than that shown in the drawings.

[0082] The material used to form each of the first insulating layer 141A and the second insulating layer 141B is not particularly limited, and any material can be used as long as the material has insulating properties. For example, a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as a polyimide), or a resin in which the thermosetting resin or the thermoplastic resin further contains a reinforcing material (such as an inorganic filler and / or glass cloth (glass fiber, glass fabric)) (for example, prepreg (PPG), ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT), etc.) can be used. If necessary, a photosensitive dielectric (PID) resin can be used.

[0083] Depending on the materials and processes of the first insulating layer 141A and the second insulating layer 141B, the boundary between the first insulating layer 141A and the second insulating layer 141B may be made indistinguishable. For example, because the first insulating layer 141A and the second insulating layer 141B are integrated with each other or the interface between the first insulating layer 141A and the second insulating layer 141B is unclear during the lamination process, it may be difficult to visually identify the interface between the first insulating layer 141A and the second insulating layer 141B in the finished electronic component-embedded substrate structure.

[0084] In addition, depending on the materials and processes of the first insulating layer 141A and the first insulating material 111A, the boundary between the first insulating layer 141A and the first insulating material 111A may also be made indistinguishable. For example, during the lamination process, the first insulating layer 141A and the first insulating material 111A may be integrated with each other or the interface therebetween may become unclear, and thus it may be difficult to visually determine the interface between the first insulating layer 141A and the first insulating material 111A in the finished electronic component-embedded substrate structure.

[0085] The thickness of the first insulating layer 141A and the thickness of the second insulating layer 141B may be respectively smaller than the thickness of each of the first insulating material 111A and the second insulating material 111B of the base substrate 110 in which the electronic component 120 is embedded.

[0086] Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or alloys thereof may be used as materials for forming each of the first wiring layer 142A and the second wiring layer 142B. Each of the first wiring layer 142A and the second wiring layer 142B may perform various functions according to the design. For example, the first wiring layer 142A and the second wiring layer 142B may include wiring patterns such as a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. In this case, the signal (S) pattern includes various signal patterns (e.g., data signal patterns) other than the ground (GND) pattern and the power (PWR) pattern. In addition, the first wiring layer 142A and the second wiring layer 142B include via pads, etc.

[0087] The material used to form the first via hole 143A and the second via hole 143B includes a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Each of the first via hole 143A and the second via hole 143B may be completely filled with a conductive material, or the first via hole 143A and the second via hole 143B may be formed by forming a conductive material along the wall of the via hole. In the case where the via hole is formed by forming a conductive material along the wall of the via hole, the interior of the via hole may be filled with an insulating material. In addition, any shape known in the art may be used as the shape of each of the first via hole 143A and the second via hole 143B.

[0088] The first via 143A may have a structure integrated with the first wiring layer 142A connected to the first via 143 A. The second via 143B may have a structure integrated with the second wiring layer 142B connected to the second via 143B.

[0089] The first passivation layer 150 and the second passivation layer 160 may protect the internal structure of the substrate embedded with electronic components according to the example from external physical and chemical damage, etc. The first passivation layer 150 and the second passivation layer 160 may include a thermosetting resin and an inorganic filler. For example, each of the first passivation layer 150 and the second passivation layer 160 may be an ABF layer, but is not limited thereto. For example, each of the first passivation layer 150 and the second passivation layer 160 may be a known photosensitive insulating layer (e.g., an SR (solder resist) layer). The first passivation layer 150 and the second passivation layer 160 may include the same type of material and may have substantially the same thickness as each other, but is not limited thereto. For example, the first passivation layer 150 and the second passivation layer 160 may have different thicknesses.

[0090] The first passivation layer 150 may have one or more openings (not shown) that expose at least a portion of the second wiring layer 132B of the first accumulation structure 130. In addition, the second passivation layer 160 may have one or more openings (not shown) that expose at least a portion of the second wiring layer 142B of the second accumulation structure 140. In this case, a surface treatment layer may be formed on the exposed portion of each of the second wiring layers 132B and 142B. The surface treatment layer may be formed by, for example, gold plating, tin plating, silver plating, nickel plating, etc. If necessary, the openings of each of the first passivation layer 150 and the second passivation layer 160 may include a plurality of via holes.

[0091] FIG. 4A to FIG. 8 A process of manufacturing a substrate embedded with electronic components according to an example is schematically illustrated.

[0092] Reference Figure 4A and Figure 4B , a plating layer 112AC is formed on a carrier film 210 (such as a detachable carrier film (DCF)), and patterning is performed to form a first wiring layer 112A on the seed layer 112AS. Next, referring to Figure 4C and Figure 4D , the first electronic component 120A is disposed on the first wiring layer 112A through a first connecting conductor 121A such as solder or the like, and the first electronic component 120A is sealed with a first insulating material 111A.

[0093] The first wiring layer 112A may be formed by a known method, such as sputtering, subtractive, additive, semi-additive process (SAP), modified semi-additive process (MSAP), etc.

[0094] The first insulating material 111A may be formed by a known method. For example, the first insulating material 111A may be formed by laminating a precursor for forming the first insulating material 111A using a known lamination method and then curing it, or by coating a precursor material by a known coating method and then curing it.

[0095] The first connection conductor 121A can be formed by a known method. For example, the first connection conductor 121A can be formed by applying solder or the like by a screen printing method, a dispenser method, or the like.

[0096] Reference FIG. 5A to FIG. 5C , forming the first via hole 113A, the first through via hole 114A and the second wiring layer 112B. In addition, the second electronic component 120B is disposed on the second wiring layer 112B through the second connection conductor 121B (such as solder), and the second electronic component 120B is sealed with the second insulating material 111B. These formation methods are as described above.

[0097] Reference FIG. 6A to FIG. 6C , the second via hole 113B, the second through via hole 114B, and the third wiring layer 112C are formed. Furthermore, the carrier film 210 is peeled off and the seed layer 112AS is removed by a method such as etching.

[0098] Reference Fig. 7A and Figure 7B , the first insulating layer 131A, the first via 133A, and the first wiring layer 132A of the first accumulation structure 130 and the first insulating layer 141A, the first via 143A, and the first wiring layer 142A of the second accumulation structure 140 are formed respectively. In addition, the second insulating layer 131B, the second via 133B, and the second wiring layer 132B of the first accumulation structure 130 and the second insulating layer 141B, the second via 143B, and the second wiring layer 142B of the second accumulation structure 140 are formed respectively. These formation methods are also as described above.

[0099] Reference Figure 8 , forming a first passivation layer 150 and a second passivation layer 160 .

[0100] Each of the first passivation layer 150 and the second passivation layer 160 may also be formed by a known method. For example, a method of stacking a precursor of each of the first passivation layer 150 and the second passivation layer 160 and then curing or a method of coating a material for forming a passivation layer and then curing may be used.

[0101] Fig. 9 is a schematic cross-sectional view of an example of an electronic package in which a semiconductor package is mounted on an electronic component-embedded substrate according to an example.

[0102] Referring to the accompanying drawings, in the case of using the above-mentioned substrate embedded with electronic components according to the present disclosure, the semiconductor package 300 is mounted on the substrate embedded with electronic components through an electrical connection metal part 310, wherein the embedded electronic component 120 can be electrically connected to the semiconductor chip (not shown) included in the semiconductor package 300 through a relatively short electrical path.

[0103] In addition, the semiconductor package 300 may have a form in which a semiconductor chip (not shown) is mounted on a separate interposer and packaged, but is not limited thereto.

[0104] The semiconductor chip (not shown) may be an application specific integrated circuit (ASIC) and / or a high bandwidth memory (HBM), but is not limited thereto.

[0105] The electrical connection metal member 310 may be made of a low melting point metal such as an alloy containing tin (Sn) or tin (Sn). More specifically, the electrical connection metal member 310 may be formed of solder or the like, but this is only an example and the material is not particularly limited thereto.

[0106] Furthermore, if necessary, the electrical connection metal member 310 may be fixed using an underfill resin.

[0107] On the other hand, the substrate embedded with electronic components may be mounted on a substrate 400 such as a main board through a separate electrical connection metal member 410 .

[0108] As set forth above, according to the embodiments, an electronic component-embedded substrate having a shortened electrical connection path may be provided.

[0109] A substrate embedded with electronic components having improved power integrity (PI) characteristics due to an increase in capacitance and / or a decrease in equivalent series inductance (ESL) of the electronic components may be provided.

[0110] A substrate with electronic components embedded therein with reduced warpage can be provided.

[0111] Although the present disclosure includes specific examples, it will be apparent to those of ordinary skill in the art that various changes in form and detail may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein will be considered to be descriptive only and not for limiting purposes. The description of the features or aspects in each example will be considered to be applicable to similar features or aspects in other examples. If the described techniques are performed in a different order, and / or if the components in the described systems, architectures, devices, or circuits are combined in different ways and / or the components in the described systems, architectures, devices, or circuits are replaced or supplemented with other components or their equivalents, suitable results may be obtained. Therefore, the scope of the present disclosure is not limited by specific embodiments, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents will be interpreted as included in the present disclosure.

Claims

1. A substrate embedded with electronic components, comprising: A first wiring layer; A first electronic component is disposed on the first wiring layer; a first insulating material covering at least a portion of each of the first wiring layer and the first electronic component; A second wiring layer, disposed on the first insulating material; a second electronic component disposed on the second wiring layer; a second insulating material disposed on the first insulating material and covering at least a portion of each of the second wiring layer and the second electronic component; as well as a first via hole penetrating the first insulating material and connecting the first electronic component and the second wiring layer, The first electronic component and the second electronic component are electrically connected to each other in parallel through the first via and the second wiring layer disposed therebetween.

2. The electronic component embedded substrate according to claim 1, wherein: The first electronic component is mounted on the first wiring layer through a first connecting conductor, and The second electronic component is mounted on the second wiring layer through a second connecting conductor.

3. The electronic component embedded substrate according to claim 2, wherein: The first connection conductor and the second connection conductor each include solder.

4. The electronic component embedded substrate according to claim 1, wherein: The second wiring layer is arranged between the first electronic component and the second electronic component in a stacking direction of the first insulating material and the second insulating material. 5 . The electronic component embedded substrate according to claim 1 , further comprising a through via penetrating the first insulating material and connecting the first wiring layer and the second wiring layer.

6. The electronic component embedded substrate according to claim 1, wherein: Each of the first electronic component and the second electronic component includes a capacitor having electrodes.

7. The electronic component embedded substrate according to claim 6, wherein: Each of the first electronic component and the second electronic component includes a first electrode and a second electrode, The first electrode of the first electronic component is connected to the first electrode of the second electronic component, and The second electrode of the first electronic component is connected to the second electrode of the second electronic component.

8. The electronic component embedded substrate according to claim 1, wherein: The first electronic component and the second electronic component are respectively provided as a plurality of first electronic components and a plurality of second electronic components, wherein the plurality of first electronic components are arranged to be spaced apart from each other by a predetermined distance, and The plurality of second electronic components are arranged to be spaced apart from each other by a predetermined distance.

9. The electronic component embedded substrate according to claim 1, wherein: The second electronic component is arranged to overlap with the first electronic component in a stacking direction of the first insulating material and the second insulating material. 10 . The electronic component embedded substrate according to claim 1 , further comprising a third wiring layer provided on the second insulating material and connected to the second electronic component. 11 . The electronic component embedded substrate according to claim 10 , further comprising a second via hole penetrating through the second insulating material and connecting the second electronic component and the third wiring layer. 12 . The electronic component embedded substrate according to claim 10 , further comprising a through via penetrating the second insulating material and connecting the second wiring layer and the third wiring layer.

13. The substrate embedded with electronic components according to claim 10, further comprising: a first build-up structure disposed on the second insulating material and comprising a first insulating layer and a fourth wiring layer; as well as a second build-up structure disposed on the first insulating material and comprising a second insulating layer and a fifth wiring layer, wherein the fourth wiring layer is connected to the third wiring layer, and The fifth wiring layer is connected to the first wiring layer.

14. The electronic component embedded substrate according to claim 13, wherein: The fourth wiring layer is disposed on the first insulating layer and is connected to the third wiring layer through a third via hole, and The fifth wiring layer is disposed on the second insulating layer, and is connected to the first wiring layer through a fourth via hole. 15 . The electronic component-embedded substrate according to claim 13 , further comprising a first passivation layer and a second passivation layer, wherein the first passivation layer and the second passivation layer are disposed on the first accumulation structure and the second accumulation structure, respectively.

16. The electronic component embedded substrate according to claim 13, wherein: The thickness of the first insulating layer and the thickness of the second insulating layer are respectively smaller than the thickness of each of the first insulating material and the second insulating material.

17. The electronic component embedded substrate according to claim 1, wherein: The first insulating material and the first wiring layer are coplanar with each other on a surface of the first insulating material opposite to an interface surface between the first insulating material and the second insulating material.

18. An electronic package, comprising: A substrate with embedded electronic components according to any one of claims 1 to 17; A semiconductor package is mounted on the substrate embedded with the electronic component through at least one first electrical connection metal member; as well as A main board, wherein the substrate embedded with electronic components is mounted on the main board via at least one second electrical connection metal member.

19. A substrate embedded with electronic components, comprising: a first insulating material surrounding one or more first electronic components; as well as a second insulating material disposed on the first insulating material and surrounding one or more second electronic components, wherein the one or more first electronic components are connected to a first wiring layer arranged on one side of the first insulating material, The one or more second electronic components are connected to a second wiring layer arranged on the other side of the first insulating material, and the one or more first electronic components are connected to the second wiring layer through vias, The one or more first electronic components and the one or more second electronic components are electrically connected to each other in parallel through the via and the second wiring layer disposed therebetween. 20 . The electronic component embedded substrate according to claim 19 , further comprising a through via penetrating the first insulating material and connecting the first wiring layer and the second wiring layer.

21. The electronic component embedded substrate according to claim 19, wherein: The one or more first electronic components are arranged to at least partially overlap the one or more second electronic components in a stacking direction of the first insulating material and the second insulating material, respectively.

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