System and method for handling floating point hardware exceptions

Abstract

Embodiments of the present disclosure relate to systems and methods for handling floating point hardware exceptions. One method includes receiving input data at an FP arithmetic operation unit, the FP arithmetic operation unit configured to perform an FP arithmetic operation on the input data. The method also includes determining whether the received input data generates an FP hardware exception in response to the FP arithmetic operation on the input data, wherein the determination occurs prior to performing the FP arithmetic operation. The method further includes converting a value of the received input data to a modified value in response to determining that the received input data generates the FP hardware exception, wherein the conversion eliminates the generation of the FP hardware exception in response to the FP arithmetic operation on the input data.

Description

TECHNICAL FIELD

[0001] This application is a non-provisional U.S. application claiming the benefit of and priority to provisional U.S. application number 62 / 950,626, filed December 19, 2019, the entire contents of which are incorporated herein by reference. BACKGROUND

[0002] Machine learning (ML) systems are typically compute intensive and often perform a large number of floating point (FP) operations. FP arithmetic operators used for FP operations typically conform to the IEEE-754 standard. When one of the inputs to a FP arithmetic operator and / or the output from a FP arithmetic operator is positive infinity, negative infinity, signaling not-a-number (SNAN), etc., a FP hardware exception is generated. Typically, a large number of resources are needed to handle the large number of FP hardware exceptions generated by the large number of FP operations in ML systems. In addition, additional resources are also needed to handle the case where the input to a FP arithmetic operator or the output from a FP arithmetic operator is a denormal number or the input is a quiet not-a-number (QNAN), SNAN, infinity, etc. A denormal number refers to a non-zero number in floating point arithmetic whose magnitude is smaller than the smallest normal number.

[0003] Currently, each FP arithmetic operator typically needs additional data paths to handle the values of the input or output with denormal numbers, QNAN, SNAN, infinity, etc. These additional data paths result in larger footprint, higher power consumption, and increased complexity of the ML system.

[0004] The foregoing examples of the related art and limitations related thereto are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon reading this description and studying the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0005] When read in conjunction with the accompanying Figure One Aspects of the disclosure can be best understood with reference to the following detailed description when considered in connection with the accompanying drawings. It should be noted that various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion. Embodiments will be described with reference to a variety of specific details that can be implemented by one of ordinary skill in the art. Those of ordinary skill in the art will appreciate that the various embodiments can be practiced without such specific details, which are given for purposes of explanation only. In other instances, well-known structures and devices are shown in block diagram form.

[0006] Figure 1 An illustrative example of an architecture configured to efficiently handle FP hardware exceptions is depicted in accordance with an aspect of the present embodiment.

[0007] Figure 2 An illustrative example of a programmable architecture configured to efficiently handle FP hardware exceptions is shown in accordance with an aspect of the present embodiment.

[0008] Figure 3An illustrative example showing an architecture configured to efficiently handle FP hardware exceptions and their tracking according to an aspect of the present embodiments is shown.

[0009] Figure 4 An illustrative example showing a method for efficiently handling FP hardware exceptions according to an aspect of the present embodiments is shown.

[0010] Figure 5 An illustrative example showing another method for efficiently handling FP hardware exceptions according to an aspect of the present embodiments is shown.

[0011] Figure 6 An illustrative example showing a block diagram depicting an example of a computer system suitable for efficiently handling FP hardware exceptions according to an aspect of the present embodiments is shown. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Additionally, the present disclosure can repeat reference numerals and / or letters in each figure to indicate different embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0013] Before various embodiments are described in more detail, it is understood that the embodiments are not limited insofar as elements in such embodiments can vary. It is also to be understood that the particular embodiments described and / or shown herein have elements that can be readily separated from the particular embodiment and combined with any of several other embodiments without losing any of the intended advantages of the embodiments described herein. It is also to be understood that the terminology used herein is for the purpose of describing certain concepts and should not be limiting. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments belong.

[0014] According to some embodiments, input data to FP arithmetic operators of the ML system is modified to avoid generating one or more FP hardware exceptions. As a non-limiting example, when the input data is positive infinity or negative infinity, respectively, the value of the input data (i.e., the operand) to the FP arithmetic operator is replaced with the maximum supported number or the minimum supported number of the system, respectively. Further, when the input data to the FP arithmetic operator is SNAN, the input data can be replaced with zero. In this way, the modified input data will not generate FP hardware exceptions due to its original value (e.g., positive infinity, negative infinity, SNAN, etc.). Further, the input data can be manipulated to handle other cases, such as denormal numbers, QNAN inputs, etc., that can not result in FP hardware exceptions, but can require additional data paths for each FP arithmetic operator to handle these cases. In some non-limiting examples, input data that is either a denormal number or a QNAN input can be replaced with zero. Thus, the need for additional data paths for each FP arithmetic operator to handle FP hardware exceptions or to handle denormal numbers or QNAN inputs is eliminated.

[0015] In some embodiments, the output of the FP arithmetic operators (e.g., addition, subtraction, add-subtract, multiplication, negation, max, min, max-subtract, min-subtract, division, FPx to FPy (where x > y), FPx to FPy (where x < y), FP to integer (Int), etc.) are similarly monitored and replaced to avoid additional data paths for each FP arithmetic operator. As a non-limiting example, even if the input data to the FP arithmetic operator can not result in FP hardware exceptions or special case handling, the output can still require special handling. As an illustrative example, two input operands can each be within the supported range of values, but when added together can be greater than the maximum supported number, resulting in infinity and requiring special handling or generating FP hardware exceptions. Thus, if the FP operator results in positive infinity, the output of the FP operator can be replaced with the maximum supported number. Likewise, if the FP operator results in negative infinity, the output of the FP operator can be replaced with the minimum supported number.

[0016] It can be appreciated that in some non-limiting examples, the number of FP hardware exceptions generated is reduced. In some non-limiting examples, if the output of the FP operator is a denormal number, it can be replaced with zero. It should be appreciated that the discussion regarding the operation of addition is for illustrative purposes only and should not be construed as limiting the scope of the embodiments. For example, similar processes can occur for other operations, such as subtraction, add-subtract, multiplication, negation, max, min, max-subtract, min-subtract, division, FPx to FPy (where x > y), FPx to FPy (where x < y), FP to Int, etc.

[0017] Accordingly, the need for additional data paths for each FP arithmetic operator to handle FP hardware exceptions or to handle exceptional, infinite, SNAN, or QNAN inputs is eliminated. Accordingly, hardware footprint, power consumption, and complexity are reduced.

[0018] Figure 1 An illustrative example of an architecture configured to efficiently handle FP hardware exceptions according to an aspect of the present embodiments is depicted. In some embodiments, a memory 110 is coupled to a logic engine 120, which is coupled to a converter engine 130, which is further coupled to an arithmetic logic unit (ALU) 140. The ALU 140 is an FP arithmetic operator / operation unit configured to perform one or more FP arithmetic operations for ML operations, e.g., addition, subtraction, add-subtraction, multiplication, negation, max, min, max-subtraction, min-subtraction, division, FPx to FPy (where x > y), FPx to FPy (where x < y), FP to Int, etc. According to some embodiments, the memory 110 stores data, e.g., numerical data, non-numerical numbers, etc. In some embodiments, one or more operands for the FP arithmetic operations are stored in the memory 110. It should be appreciated that the operand(s) for the FP arithmetic operations can be fetched as input data 112 and sent thereto. The logic engine 120 receives the input data 112. The logic engine 120 is configured to parse the input data 112 to determine whether the received input data 112 will result in the generation of an FP hardware exception once operated on by the ALU 140. For a non-limiting example, the logic engine 120 is configured to determine whether the input data 112 is a positive infinity, a negative infinity, a SNAN, etc. In other words, the logic engine 120 is configured to determine whether an FP hardware exception will be generated prior to the FP arithmetic operator operating on the input data (i.e., a priori determination). Moreover, the logic engine 120 can be configured to determine whether the input data 112 requires special handling, e.g., QNAN, non-normal number, etc., once operated on by the ALU 140. It should be appreciated that, according to one non-limiting example, the logic engine 120 can be implemented in software. However, it should be appreciated that, in some embodiments, the logic engine 120 can be implemented in hardware. As such, the discussion of embodiments with respect to software implementation is for illustrative purposes only and should not be construed as limiting the scope of the embodiments.

[0019] In some embodiments, the logic engine 120 can transmit the results of its determination 122 to the translator engine 130. For non-limiting examples, the logic engine 120 can transmit whether the input data 112 will generate an FP hardware exception, or whether the input data 112 will require special handling once the input data 112 is operated on by the FP arithmetic operators. It should be appreciated that, in some non-limiting embodiments, the determination 122 can further include the input data 112. However, it should be appreciated that the determination 122 including the input data 112 is for illustrative purposes, and the translator engine 130 can receive the input data 112 independently (e.g., from the memory 110). In response to the determination of the logic engine 120, the translator engine 130 can change the value or content of the input data 112. In some non-limiting examples, when the input data 112 is positive infinity or negative infinity, respectively, the input data 112 is changed to the maximum or minimum supported number of the system. Further, when the input data 112 is SNAN, the input data can be replaced with zero. As such, the input data 112 modified by the translator engine 130 will not generate an FP hardware exception resulting from its original value (e.g., positive infinity, negative infinity, SNAN, etc.). Further, the input data 112 can be manipulated to handle other cases, such as non-regular numbers, QNAN inputs, etc., that can not generate an FP hardware exception, but can still require additional data paths for each FP arithmetic operator to handle these cases. In some non-limiting examples, if the input data 112 is a non-regular number or is a QNAN, the translator engine 130 replaces the input data 112 with zero. It should be appreciated that, if the input data 112 is neither a QNAN nor a SNAN, positive infinity, negative infinity, or a non-regular number, the translator engine 130 can leave the input data 112 unchanged.

[0020] In some embodiments, the converter engine 130 outputs data 132 to the ALU 140. It should be appreciated that the data 132 can be the same as the input data 112 (if the data 112 was not changed), or can be a changed version of the input data 112 changed by the converter engine 130. In some embodiments, the ALU 140 is configured to perform FP arithmetic operations on the received data 132. It should be appreciated that because the input data 112 was changed to avoid the generation of FP hardware exceptions or the need for special handling, FP hardware exceptions are not generated due to input data 112 being positive infinity, negative infinity, and SNAN, and special handling is not needed for input data 112 being positive infinity, negative infinity, and SNAN. However, even though the input to the ALU 140 can be valid numbers, the output can still generate exceptions or need special handling. For a non-limiting example, two valid numbers when added to each other can generate a non-normal number, or result in positive or negative infinity when added to each other. Thus, the output of the ALU 140 is monitored for the presence of a non-normal number or positive or negative infinity. The output 142 of the ALU 140 is input to the logic engine 120, which is configured to determine whether the output 142 is a non-normal number or positive or negative infinity. If the logic engine 120 determines that the output 142 is neither a non-normal number nor positive or negative infinity, then the logic engine 120 outputs the contents 124 without changing its value. In other words, the contents 124 have the same value as the output 142 from the ALU 140. On the other hand, if the logic engine 120 determines that the contents 142 are a non-normal number or positive or negative infinity, then the contents 142 are transmitted to the converter engine 130 as contents 126 for modification of the contents. For example, if the contents 126 are a non-normal number, then the converter engine 130 changes the value to zero and outputs the changed value as output 134. Conversely, if the contents 126 are positive or negative infinity, then the converter engine 130 changes the value to the maximum or minimum supported number of the system and outputs it as contents 134. It should be appreciated that this process is repeated for each input data (i.e., operand) to an FP arithmetic operator and its output. It should also be appreciated that the contents 126 are passed from the logic engine 120 to the converter engine 130 for illustrative purposes, and embodiments should not be construed as limiting in scope. For example, in some embodiments, the converter engine 130 can receive the contents 126 directly from the logic engine 120. In one non-limiting example, the converter engine 130 can receive the data directly from the ALU 140.

[0021] For example, if the logic engine 120 determines that the content 142 is a non- normal number or a positive or negative infinity, the ALU 140 can be signaled to send the content 142 from the ALU 140 to the converter engine 130 for modification of the content. It should be appreciated that this process is repeated for each input data (i.e., operand) to the FP arithmetic operator and its output. It should be appreciated that, in some non-limiting embodiments, the logic engine 120 and the converter engine 130 can be integrated within the same processing block. It should also be appreciated that the communication between the integrated processing block and the ALU 140 can be a bidirectional communication. Further, it should be appreciated that, in some non-limiting embodiments, the logic engine 120, the converter engine 130, and the ALU 140 can be integrated within the same processing block, thereby eliminating the need for data communication between different engine blocks.

[0022] It should be appreciated that, as a result of changing the input data and the output data to avoid the generation of FP hardware exceptions or the need for special handling, the amount of resources required, power consumption, and complexity are reduced.

[0023] Figure 2 An illustrative example of a programmable architecture configured to efficiently handle FP hardware exceptions in FP arithmetic operations is shown in accordance with an aspect of the present embodiment. Figure 2 Similar to Figure 1 Basically. However, it should be appreciated that, in this embodiment, the rule engine 210 can be used to program the logic engine 120 and / or the converter engine 130. In other words, the cases in which the input data to the FP arithmetic operator or its output data is changed can be user programmable. The rule engine 210 enables additional FP hardware exceptions or special handling to be changed or added for other cases.

[0024] Figure 3 An illustrative example of an architecture configured to efficiently handle FP hardware exceptions and their tracking is shown in accordance with an aspect of the present embodiment. Figure 3 Similar to Figure 2 Basically. However, in this embodiment, the memory 310 can be used to track when the input data to the FP arithmetic operator or its output is changed. For example, when the input data 112 or the output 142 of the ALU 140 is a non-normal number, a positive or negative infinity, the out-of-range flag 128 can be generated and stored in the memory 310. In some examples, when the input data 112 is a QNAN or a SNAN, an uninitialized flag 128 can be generated and stored in the memory 310. When the dividend of a division operation is non-zero and the divisor is zero, the generated flag can be a zero-division flag.

[0025] For illustrative purposes, the various input data described above for FP arithmetic operators (e.g., addition, subtraction, or add-subtract, and their changes to the input and their output) should not be construed as limiting the scope of the embodiments, as follows.

[0026]

[0027]

[0028] For illustrative purposes, the various input data described above for FP arithmetic operators (e.g., negation) should not be construed as limiting the scope of the embodiments, as follows.

[0029] Input Altered input FP arithmetic output Generated flags ± Non-regular number ±0 ±0 Out of bounds ± Infinity Max / Min Max / Min Out of bounds ± qnan ±0 ±0 Uninitialized ± snan ±0 ±0 Uninitialized ± Regular number ± Regular number ± Regular number

[0030] For illustrative purposes, the various input data described above for FP arithmetic operators (e.g., multiplication) should not be construed as limiting the scope of the embodiments, as follows.

[0031]

[0032]

[0033] It should be understood that a multiplication operation can have 32-bit input / output, but the operation can be performed as a 16-bit floating point. In other words, 32-bit floating point data is converted to 16-bit floating point, and its value can be limited to a maximum value, a minimum value, or zero. As described above, this conversion can result in an out-of-bound exception handled according to embodiments.

[0034] For illustrative purposes, the various input data described above for FP arithmetic operators (e.g., maximum, minimum, maximum subtract, minimum subtract, as described above) should not be construed as limiting the scope of the embodiments, as follows.

[0035]

[0036]

[0037] For illustrative purposes, the various input data described above for FP arithmetic operators (e.g., division operation) should not be construed as limiting the scope of the embodiments, as follows.

[0038]

[0039]

[0040] It can be appreciated that a division operation can have a 32-bit input / output similar to multiplication, as described above. In other words, the operation can be performed as a 16-bit float. In other words, the 32-bit float data is converted to a 16-bit float, and its value can be limited to a maximum value, a minimum value, or zero. As described above, the conversion can cause an out-of-bounds exception or a divide-by-zero exception to be handled according to embodiments.

[0041] For illustrative purposes, the various input data described above for FP arithmetic operators (e.g., FPx to FPy (where x > y)) should not be construed as limiting the scope of embodiments, as follows.

[0042]

[0043] For illustrative purposes, the various input data described above for FP arithmetic operators (e.g., FPx to FPy (where x < y)) should not be construed as limiting the scope of embodiments, as follows.

[0044]

[0045]

[0046] For illustrative purposes, the various input data described above for FP arithmetic operators (e.g., FPx to Int) should not be construed as limiting the scope of embodiments, as follows.

[0047]

[0048] It can be appreciated that a float to integer operation can have a 16-bit input, so it can not require a 32-bit to 16-bit conversion. In other words, the operation can be performed as a 16-bit float, and it can be converted to an integer, e.g., int9 (as described in the title "System and Method for INT9 Quantization," U.S. Patent No. 8, 1 12, 128, which is incorporated by reference herein in its entirety). <tbd>Patent Application No. 62 / 649, 1 10, filed March 30, 2018, entitled "METHODS AND SYSTEMS FOR <tbd>The value can be clipped to the maximum or minimum value of an integer, and as mentioned above, it can trigger an out-of-bound exception handled according to embodiments.

[0049] Figure 4 An example of a method for efficiently handling FP hardware exceptions according to an aspect of the present embodiments is shown. At step 410, input data is received, e.g., an FP number, a QNAN, a SNAN, an irregular number, etc., as described above with respect to Figures 1-3 step 410. At step 420, it is determined whether the received input data will generate an FP hardware exception in response to an FP arithmetic operation on the input data. It is understood that this determination occurs prior to the FP arithmetic operation being performed. For example, it is determined whether the input data is positive infinity, negative infinity, a SNAN, etc., as described above with respect to Figures 1-3 step 420. In addition, it is determined whether the input data requires special handling, e.g., whether the input data is an irregular number, whether the input data is a QNAN, etc., as described above with respect to Figures 1-3 step 420. In response to determining that the input data will generate an FP hardware exception if operated on by an FP arithmetic operator, the input data is altered at step 430. As a non-limiting example, if the input data is positive infinity, the value of the input data is altered to the maximum supported number, if the input data is negative infinity, the value of the input data is altered to the minimum supported number, if the input data is a SNAN, the input data is altered to a zero value, and so on, as described above with respect to Figures 1-3 step 430. Thus, the alteration of the value of the input data eliminates the generation of the FP hardware exception once the input data is operated on by the FP arithmetic operator. In some embodiments, the value of the input data is also altered if the original input data value requires special handling. As a non-limiting example, if the input data is an irregular number, the value of the input data is altered to zero, if the input data is a QNAN, the value of the input data is altered to zero, and so on. At step 440, the input data (i.e., the altered value or the original value) is operated on by the FP arithmetic operator, as shown in Figures 1-3 step 440. The FP arithmetic operation can be an addition operation, a subtraction operation, an addition-subtraction operation, a multiplication operation, a negation operation, a maximum operation, a minimum operation, a maximum minus operation, a minimum minus operation, a division operation, an FPx to FPy (where x>y) operation, an FPx to FPy (where x<y) operation, an FP to Int operation, etc.

[0050] At step 450, it is determined whether the output result of the FP arithmetic operation will generate an FP hardware exception prior to the FP hardware exception being generated. For example, if the output result of the FP arithmetic operator is positive infinity, negative infinity, etc., it is determined that the output result will generate an FP hardware exception, as shown in Figure 1 - described in FIG. 3. At step 460, in response to determining that the output result will generate an FP hardware exception, the value of the output result is changed, e.g., positive infinity is changed to the maximum supported number of the system, negative infinity is changed to the minimum supported number of the system, etc. It should also be appreciated that in some embodiments, if the output result is a denormal number, the value of the output result is changed to zero.

[0051] It should be appreciated that at step 470, a flag is optionally generated when the input data is determined to generate an FP hardware exception (before generating the FP hardware exception), or when the input data requires special handling (e.g., QNAN, denormal number, etc.), or when the output result of the FP arithmetic operator will generate an FP hardware exception (before generating the FP hardware exception), or if the output result requires special handling (i.e., the output result is a denormal number), etc. The generated flag can be an overflow flag if the value is positive infinity, negative infinity, denormal number, etc. The generated flag can be an uninitialized flag when the data is a QNAN or SNAN. The generated flag can be a zero divide flag when the dividend of a division operation is non-zero and the divisor is zero.

[0052] Figure 5 An example of another method for efficiently handling FP hardware exceptions in FP arithmetic operations according to an aspect of the present embodiment is shown. At step 510, first and second input data are received for an FP arithmetic operation, e.g., addition, subtraction, add-subtraction, multiplication, negation, maximum, minimum, maximum subtraction, minimum subtraction, division, FPx to FPy (where x>y), FPx to FPy (where x Figures 1-3 At step 520, if the first / second input data is a denormal number, QNAN, SNAN, etc., the first / second input data is set to zero, as described in Figures 1-3 At step 530, if the first / second input data is positive infinity, the first / second input data is set to the maximum supported value, and if the first / second input data is negative infinity, it is set to the minimum supported value. It should be appreciated that if any of the input data is a SNAN, QNAN, denormal, positive infinity, or negative infinity, an FP hardware exception will be generated if operated on by the FP arithmetic operator. At step 540, the first input data and the second input data (i.e., the changed value or the original value) are operated on by the FP arithmetic operator, as described in Figures 1-3 At step 550, it is determined whether the output result of the FP arithmetic operation will generate an FP hardware exception before generating the FP hardware exception. For a non-limiting example, if the output result of the FP arithmetic operator is positive infinity, negative infinity, etc., it is determined that the output result will generate an FP hardware exception, as described in Figures 1-3 In step 560, in response to determining that the output result will generate an FP hardware exception, the value of the output result is changed, e.g., positive infinity is changed to the maximum supported number of the system, negative infinity is changed to the minimum supported number of the system, etc. It should also be appreciated that in some embodiments, if the output result is a denormal number, the value of the output result is changed to zero.

[0053] It should be appreciated that in step 570, a flag is optionally generated when the first or second input data is determined to generate an FP hardware exception (before generating the FP hardware exception), or when the first or second input data requires special handling (i.e., QNAN, denormal number, etc.), or when the output result of the FP arithmetic operator will generate an FP hardware exception (before generating the FP hardware exception), or when the output result requires special handling (i.e., the output result is a denormal number), etc. The generated flag can be an overflow flag if the value is positive infinity, negative infinity, denormal number, etc. The generated flag can be an uninitialized flag when the data is a QNAN or SNAN. The generated flag can be a zero divide flag when the dividend of a division operation is non-zero and the divisor is zero.

[0054] Reference is now made to Figure 6 , a block diagram is shown that depicts an example of a computer system suitable for efficient handling of FP hardware exceptions, in accordance with some embodiments. In some examples, the computer system 1100 can be used to implement a computer program, application, method, process, or other software to perform the techniques described above and implement the structures described herein. The computer system 1100 includes a bus 1102 or other communication mechanism for communicating information, which interconnects subsystems and devices, such as a processor 1104, system memory ("memory") 1106, storage devices 1108 (e.g., ROM), disk drives 1110 (e.g., magnetic or optical), communication interfaces 1112 (e.g., modems or Ethernet cards), display devices 1114 (e.g., CRT or LCD), input devices 1116 (e.g., keyboard and pointing devices), and a pointer-cursor control 1118 (e.g., a mouse or trackball). In one embodiment, the pointer-cursor control 1118 invokes one or more commands that at least partially modify rules, e.g., stored in the memory 1106, to define an electronic message preview process.

[0055] According to some examples, computer system 1100 performs particular operations by the processor 1104 executing one or more sequences of instructions contained in system memory 1106. Such instructions can be read into system memory 1106 from another computer-readable medium, such as storage device 1108 or a magnetic disk drive 1110. In some examples, hard-wired circuitry can be used in place of or in combination with software instructions. In the illustrated example, system memory 1106 includes an operating system ("O / S") 1132, an application 1136 (e.g., a host-based, server-based, web service-based distributed (i.e., enterprise) application programming interface ("API"), program, process, or other) including executable instruction modules for implementing logic engine 1138 that determines whether input data would generate an FP hardware exception if operated on by an FP arithmetic operator, or whether the input data requires special handling (i.e., non-normal number, QNAN, etc.), as described in Figures 1-5 Application 1136 also includes a converter engine 1141 that changes a value of input data or output results of an FP arithmetic operator if the logic engine 1138 determines that changing the value would generate an FP hardware exception, or if changing the value would require special handling, as described in Figures 1-5

[0056] In at least one embodiment, the term "computer readable medium" refers to any media that participates in providing instructions to processor 1104 for execution. Such a medium can take many forms, including but not limited to, nonvolatile media, volatile media, and transmission media. Nonvolatile media includes, for example, optical or magnetic disks, such as a magnetic disk drive 1110. Volatile media includes dynamic memory, such as system memory 1106. Transmission media includes coaxial cables, copper wire, and fiber optics, including the wires that comprise bus 1102. Transmission media can also take the form of acoustic or light waves, such as those generated during radio wave and infrared data communications.

[0057] Common forms of computer readable media include, for example, floppy disk, flexible disk, hard disk, magnetic tape, any other magnetic medium, CD-ROM, any other optical medium, punch cards, paper tape, any other physical medium with patterns of holes, RAM, PROM, EPROM, a FLASH- EPROM, any other memory chip or cartridge, a carrier wave, electromagnetic wave, or any other medium from which a computer can read.

[0058] ​In some examples, execution of the sequences of instructions can be performed by a single computer system 1100. According to some examples, two or more computer systems 1100 coupled by communication link 1120 (e.g., LAN, PSTN, or wireless network) can perform the sequences of instructions in coordination with one another. Computer system 1100 can transmit and receive messages, data, and instructions, including programs (i.e., application code) through communication link 1120 and communication interface 1112. Received program code can be executed by processor 1104 as it is received, and / or stored in disk drive 1110, or other non-volatile memory for later execution. In one embodiment, system 1100 is implemented as a handheld device. But in other embodiments, system 1100 can be implemented as a personal computer (i.e., desktop) or any other computing device. In at least one embodiment, any of the above delivery systems can be implemented as a single system 1100, or can be implemented in a distributed architecture including multiple systems 1100.

[0059] In other examples, the systems described above can be implemented from a personal computer, computing device, mobile device, mobile phone, facsimile device, personal digital assistant ("PDA"), or other electronic device.

[0060] In at least some embodiments, the structure and / or functionality of any of the above interfaces and panels can be implemented in software, hardware, firmware, circuitry, or a combination thereof. Note that the structures and constituent elements shown throughout and their functionality can be aggregated with one or more other structures or elements.

[0061] Alternatively, elements and their functionality can be subdivided into constituent sub-elements (if any). As software, the above-described techniques can be implemented using various types of programming or formatting languages, frameworks, syntax, applications, protocols, objects, or techniques, including C, object-oriented C, C++, C#, Flex.TM., Fireworks RTM, Java TM, Javascript TM, AJAX, COBOL, Fortran, ADA, XML, HTML, DHTML, XHTML, HTTP, XMPP, and the like. These can vary and are not limited to the examples or descriptions provided.

[0062] The foregoing description of various embodiments of the claimed subject matter has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the claimed subject matter to the precise form disclosed. Many modifications and variations will be apparent to those skilled in the art. Embodiments were chosen and described in order to best describe the principles of the application and its practical application to thereby enable others skilled in the art to best use the claimed subject matter, various embodiments, and various modifications that are suited to the particular use contemplated.< / tbd> < / tbd>

Claims

1. A computer-implemented method comprising: receiving input data at a floating point arithmetic operation unit, wherein the floating point operation unit is configured to perform a floating point arithmetic operation on the input data; determining whether the received input data generates a floating point hardware exception in response to the floating point arithmetic operation on the input data, wherein the determination occurs prior to performing the floating point arithmetic operation; and in response to determining that the received input data generates the floating point hardware exception, converting a value of the received input data to a modified value, wherein the conversion eliminates generation of the floating point hardware exception in response to the floating point arithmetic operation on the input data, wherein if the input data is positive infinity, the modified value of the input data is a maximum supported value, and wherein if the input data is negative infinity, the modified value of the input data is a minimum supported value.

2. The method of claim 1, further comprising: performing the floating point arithmetic operation on the input data with the modified value to generate an output result.

3. The method of claim 2, wherein the floating point arithmetic operation is selected from one of: an addition operation, a subtraction operation, or an add-subtract operation.

4. The method of claim 2, further comprising: determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception.

5. The method of claim 4, further comprising: setting a value of the output result to zero if the value of the output result is a non-normal number.

6. The method of claim 4, further comprising: setting a value of the output result to a maximum supported number if the value of the output result is positive infinity; and setting a value of the output result to a minimum supported number if the value of the output result is negative infinity.

7. The method of claim 1, further comprising: setting a value of the input data to zero if the input data is a non-normal number.

8. The method of claim 7, further comprising: generating an out-of-range flag associated with the non-normal number.

9. The method of claim 1, further comprising: generating an out-of-range flag associated with the input data.

10. The method of claim 1, further comprising: generating an out-of-range flag associated with the input data.

11. The method of claim 1, further comprising: setting a value of the input data to zero if the input data is qnan.

12. The method of claim 11, further comprising: generating an uninitialized flag associated with the input data.

13. The method of claim 1, wherein the input data is snan, and wherein the modified value is zero.

14. The method of claim 13, further generating an uninitialized flag associated with the input data.

15. A computer-implemented method comprising: receiving first input data at a floating point arithmetic operation unit for a floating point arithmetic operation; receiving second input data at the floating point arithmetic operation unit for the floating point operation; generating an out-of-range flag associated with the input data if the input data is positive infinity or negative infinity; in response to the floating point arithmetic operation on the first input data and the second input data, eliminating a floating point hardware exception by performing one or more of: setting the first input data to zero if the first input data is a non-normal number, qnan, or snan; setting the first input data to a maximum supported value if the first input data is positive infinity; setting the first input data to a minimum supported value if the first input data is negative infinity; if the second input data is a qnan or snan, setting the second input data to zero; if the second input data is positive infinity, setting the second input data to a maximum supported value; and if the second input data is negative infinity, setting the second input data to a minimum supported value.

16. The method of claim 15, further comprising: performing the floating point arithmetic operation on the first input data and the second input data or their modified values to generate an output result.

17. The method of claim 16, wherein the floating point arithmetic operation is selected from one of an addition operation, a subtraction operation, or an add-subtract operation.

18. The method of claim 16, further comprising: if the output result has a value that is a qnan, setting the value of the output result to zero.

19. The method of claim 16, further comprising: if the output result has a value that is positive infinity, setting the value of the output result to a maximum supported number; and if the output result has a value that is negative infinity, setting the value of the output result to a minimum supported number.

20. The method of claim 15, further comprising: generating an overflow flag associated with the qnan.

21. The method of claim 15, further comprising: generating an uninitialized flag associated with qnan input data.

22. The method of claim 15, further comprising: generating an uninitialized flag associated with snan input data.

23. A computer system comprising: a logic engine configured to receive input data for an arithmetic operation to be operated on by a floating point arithmetic operation unit, wherein the logic engine is configured to determine whether the received input data generates a floating point hardware exception in response to the floating point arithmetic operation on the input data, wherein the determination occurs prior to performing the floating point arithmetic operation; and a converter engine configured to convert a value of the received input data to a modified value in response to a determination that the received input data generates the floating point hardware exception, wherein the conversion eliminates the generation of the floating point hardware exception in response to the floating point arithmetic operation on the input data, wherein the modified value of the input data is a maximum supported value if the input data is positive infinity, and wherein the modified value of the input data is a minimum supported value if the input data is negative infinity.

24. The computer system of claim 23, further comprising an arithmetic floating point operator configured to perform the floating point arithmetic operation on the input data having the modified value to generate an output result.

25. The computer system of claim 24, wherein the floating point arithmetic operation is selected from one of an addition operation, a subtraction operation, or an add-subtract operation.

26. The computer system of claim 24, wherein the logic engine is further configured to determine whether the output result of the floating point arithmetic operation generates a floating point hardware exception.

27. The computer system of claim 26, wherein the converter engine is further configured to set the value of the output result to zero if the output result has a value that is a qnan.

28. The computer system of claim 26, wherein the converter engine is further configured to set the value of the output result to a maximum supported number if the value of the output result is positive infinity; and wherein the converter engine is further configured to set the value of the output result to a minimum supported number if the value of the output result is negative infinity.

29. The computer system of claim 23, wherein the converter engine is further configured to set the value of the input data to zero if the input data is a denormal number.

30. The computer system of claim 29, wherein the logic engine is further configured to generate an out-of-range flag associated with the denormal number.

31. The computer system of claim 23, wherein the converter engine is further configured to generate an out-of-range flag associated with the input data.

32. The computer system of claim 23, wherein the logic engine is further configured to generate an out-of-range flag associated with the input data.

33. The computer system of claim 23, wherein the converter engine is further configured to set the value of the input data to zero if the input data is a qnan.

34. The computer system of claim 33, wherein the logic engine is further configured to generate an uninitialized flag associated with the input data.

35. The computer system of claim 23, wherein the input data is a snan, and wherein the modified value is zero.

36. The computer system of claim 35, wherein the logic engine is configured to generate an uninitialized flag associated with the input data.

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