A substrate having electronic components embedded therein

Abstract

The present invention provides a substrate having an electronic component embedded therein, the substrate having an electronic component embedded therein comprising: a core structure including a first insulator and a core wiring layer, and having a cavity penetrating a portion of the first insulator; an electronic component disposed in the cavity; an insulating material covering at least a portion of each of the core structure and the electronic component and disposed in at least a portion of the cavity; a wiring layer disposed on the insulating material; and an accumulation structure disposed on the insulating material and including a second insulator and an accumulation wiring layer. The material of the first insulator has a coefficient of thermal expansion (CTE) smaller than that of the second insulator, and the insulating material has a CTE smaller than that of the material of the second insulator.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0170934 filed on December 19, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety for all purposes by reference. Technical Field

[0002] The present disclosure relates to a substrate having electronic components embedded therein. Background Art

[0003] With the advent of the fifth generation (5G) era, the number of components mounted on the main board of a smartphone has increased. While maintaining compatibility with 4G communication, LTE communication, it may also be necessary to ensure space in which components such as antennas, baseband modems, etc. for 5G communication are mounted. Therefore, it has been considered to reduce the size of components by modularizing the components in the form of a system-in-package (SiP). Summary of the invention

[0004] This summary is provided to introduce selected concepts in a simplified form and further describe the concepts in the following detailed description. This summary is neither intended to identify key features or essential features of the claimed subject matter nor to be used as an aid in determining the scope of the claimed subject matter.

[0005] An aspect of the present disclosure is to provide a substrate having electronic components embedded therein, which can control warpage even if having an asymmetric structure.

[0006] Another aspect of the present disclosure is to provide a substrate having electronic components embedded therein, which may be modularized and miniaturized in the form of a system-in-package (SiP).

[0007] According to an aspect of the present disclosure, in a substrate having an asymmetric structure and having electronic components embedded therein, a coefficient of thermal expansion (CTE) is balanced by causing a difference between an insulating material for embedding the electronic components and an insulating material for accumulation.

[0008] According to one aspect of the present disclosure, a modular structure is achieved by providing a surface mount component on a substrate having electronic components embedded therein.

[0009] For example, a substrate having an electronic component embedded therein includes: a core structure including a first insulator and a plurality of core wiring layers respectively arranged on or in the first insulator, and having a cavity penetrating a portion of the first insulator in a direction from a first surface of the first insulator toward a second surface opposite to the first surface; an electronic component arranged in the cavity; an insulating material covering at least a portion of each of the core structure and the electronic component and arranged in at least a portion of the cavity; a wiring layer arranged on the insulating material; and an accumulation structure arranged on the insulating material and including a second insulator and one or more accumulation wiring layers, the second insulator covering at least a portion of the wiring layer, the one or more accumulation wiring layers respectively arranged on or in the second insulator. The material of the first insulator has a coefficient of thermal expansion (CTE) smaller than that of the material of the second insulator, and the insulating material has a CTE smaller than that of the material of the second insulator.

[0010] For example, a substrate includes: a core structure including a first insulator and a core wiring layer respectively arranged on the first insulator or arranged in the first insulator, and having a cavity that penetrates a portion of the first insulator; an electronic component arranged in the cavity; an insulating material covering at least a portion of each of the core structure and the electronic component and arranged in at least a portion of the cavity; a wiring layer directly arranged on the insulating material; a via layer connecting the wiring layer to one of the connection pads of the core wiring layer and the electronic component in the insulating material; and an accumulation structure arranged on the insulating material and including a second insulator and one or more accumulation wiring layers, the second insulator covering at least a portion of the wiring layer, the one or more accumulation wiring layers respectively arranged on the second insulator or arranged in the second insulator. The insulating material has a coefficient of thermal expansion (CTE) smaller than that of the material of the second insulator. The cavity has a barrier layer as the bottom surface of the cavity. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0012] Figure 1 is a schematic block diagram illustrating an example of an electronic device system.

[0013] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0014] Figure 3is a schematic cross-sectional view showing an example of a substrate having electronic components embedded therein.

[0015] Figure 4 It is along Figure 3 FIG. 1 is a cross-sectional plan view of a substrate having electronic components embedded therein, taken along line II′.

[0016] Figures 5 to 11 It shows the manufacturing Figure 3 A process diagram of an example of a substrate having electronic components embedded therein is shown in FIG. DETAILED DESCRIPTION

[0017] Hereinafter, embodiments of the present disclosure will be described as follows with reference to the accompanying drawings.

[0018] Figure 1 is a schematic block diagram illustrating an example of an electronic device system.

[0019] Reference Figure 1 , the electronic device 1000 may house a mainboard 1010 therein. The mainboard 1010 may include chip-related components 1020, network-related components 1030, other components 1040, etc., which are physically or electrically connected thereto. These components may be connected to other components to be described below through various signal lines 1090.

[0020] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, etc.; application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processors (e.g., graphics processing units (GPU)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto, but may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips or electronic components.

[0021] The network-related components 1030 may include components designated to operate according to protocols such as Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution Data-Only (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Enhanced Data GSM Environment (EDGE), Global System for Mobile Communications (GSM), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, 3G protocols, 4G protocols, and 5G protocols, as well as any other wireless protocols and wired protocols designated after the above protocols. However, the network-related component 1030 is not limited thereto, but may also include components designated to operate according to various other wireless standards or protocols or wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020 together with each other.

[0022] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramics (LTCC), electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto, but may also include passive components for various other purposes, etc. In addition, the other components 1040 may be combined with each other together with the chip-related components 1020 or the network-related components 1030.

[0023] The electronic device 1000 may include other components that may or may not be physically or electrically connected to the mainboard 1010, depending on the type of the electronic device 1000. These other components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), a compass (not shown), an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a mass storage unit (e.g., a hard disk drive) (not shown), a compact disk (CD) drive (not shown), a digital versatile disk (DVD) drive (not shown), etc. However, these other components are not limited thereto, but may also include other components for various purposes according to the type of the electronic device 1000, etc.

[0024] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto, but may be any other electronic device that processes data.

[0025] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0026] Reference Figure 2 , the electronic device may be, for example, a smart phone 1100. The smart phone 1100 may house a mainboard 1110 therein, and various electronic components 1120 may be electrically and / or physically connected to the mainboard 1110. In addition, other components (such as a camera module 1130 and / or a speaker 1140) that may or may not be physically or electrically connected to the mainboard 1110 may be housed in the mainboard 1110. Some of the electronic components 1120 may be chip-related components, such as a semiconductor package 1121, but are not limited thereto. The electronic device is not necessarily limited to the smart phone 1100, but may be other electronic devices as described above.

[0027] Figure 3 is a schematic cross-sectional view showing an example of a substrate having electronic components embedded therein.

[0028] Figure 4 It is along Figure 3 A cross-sectional plan view of a substrate having electronic components embedded therein is shown, taken along line II' in FIG.

[0029] Reference Figure 3 and Figure 4, a substrate 100 having an electronic component embedded therein includes a core structure 110, an electronic component 120, an insulating material 130, a wiring layer 132, a via layer 133, an accumulation structure 160, a first passivation layer 170, and a second passivation layer 180. The core structure 110 includes: first insulators 111a, 111b, and 111c; a plurality of core wiring layers 112a, 112b, 112c, and 112d, which are respectively disposed on or in the first insulators 111a, 111b, and 111c; and a plurality of core via layers 113a, 113b, and 113c, which are respectively disposed in the first insulators 111a, 111b, and 111c. The core structure 110 has a cavity 110H that penetrates a portion of the first insulators 111a, 111b, and 111c in a direction from the upper surface of the first insulators 111a, 111b, and 111c toward the lower surface. The electronic component 120 is disposed in the cavity 110H, for example, in a face-up form. The accumulation structure 160 may include second insulators 140 and 150, one or more accumulation wiring layers 142 and 152 disposed on or in the second insulators 140 and 150, respectively, and one or more via layers 143 and 153 disposed in the second insulators 140 and 150. On the other hand, the thermal expansion coefficient (CTE) of the material of the first insulators 111a, 111b, and 111c is smaller than the thermal expansion coefficient (CTE) of the material of the second insulators 140 and 150. In addition, the material of the insulating material 130 has a CTE smaller than the thermal expansion coefficient (CTE) of the material of the second insulators 140 and 150. The coefficient of thermal expansion (CTE) (average value measured at a glass transition temperature (Tg) or lower based on XY) may have a unit of ppm / °C and may be measured by a thermomechanical analyzer (TMA).

[0030] Recently, there has been a need for technology for embedding active components and / or passive components in a substrate. In a structure of a substrate with components embedded therein, it is easier to control warping in a symmetrical structure than in an asymmetrical structure. However, an asymmetrical structure requires sufficient thickness of the electronic components while removing unnecessary layers. In this case, it is difficult to control warping in strip units and units of the substrate. For example, arc-shaped warping may occur in electronic components arranged face-up. In the recent trend (the area occupied by electronic components is increasing compared to the overall size of the package), the warping effect of the electronic components is reflected on the substrate, and therefore, further problems in warping control occur.

[0031] In the substrate 100 having an electronic component embedded therein, the material of the first insulator 111a, 111b, and 111c of the core structure 110 (the lower structure of the substrate 100) has a coefficient of thermal expansion (CTE) smaller than that of the material of the second insulators 140 and 150 of the accumulation structure 160 (the upper structure of the substrate 100). In this case, the CTE of the upper portion of the substrate 100 may be greater than that of the lower portion thereof. In addition, when the electronic component 120 includes an active component (e.g., a silicon chip), the material of the silicon chip has a relatively lower CTE than that of the organic material of the second insulators 140 and 150, and thus, the upper portion of the substrate 100 may have a CTE greater than that of the lower portion thereof. However, in the substrate 100 having an electronic component embedded therein, the insulating material 130 (the upper structure of the substrate 100) may have a lower CTE than that of the material of the second insulators 140 and 150. Therefore, the balance between the CTE of the upper portion of the substrate 100 and the CTE of the lower portion of the substrate 100 may be improved to solve the problem in terms of warpage deviation, and warpage control in the strip-shaped cells and cells of the substrate 100 may be more effective.

[0032] Hereinafter, elements included in the substrate 100 having electronic components embedded therein will be described in more detail.

[0033] The core structure 110 includes: a first core insulation layer 111a; a first core wiring layer 112a, which is arranged on the lower side of the first core insulation layer 111a; a second core wiring layer 112b, which is arranged on the upper side of the first core insulation layer 111a; the second core insulation layer 111b, which is arranged on the lower side of the first core insulation layer 111a and covers at least a portion of the first core wiring layer 112a; a third core wiring layer 112c, which is arranged on the lower side of the second core insulation layer 111b; the third core insulation layer 111c, which is arranged on the upper side of the first core insulation layer 111a and covers at least a portion of the second core wiring layer 112b; and a fourth core wiring layer 112d, which is arranged on the upper side of the third core insulation layer 111c. The core structure 110 also includes: a first core via layer 113a, which penetrates the first core insulation layer 111a and connects the first core wiring layer 112a and the second core wiring layer 112b to each other; a second core via layer 113b, which penetrates the second core insulation layer 111b and connects the first core wiring layer 112a and the third core wiring layer 112c to each other; and a third core via layer 113c, which penetrates the third core insulation layer 111c and connects the second core wiring layer 112b and the fourth core wiring layer 112d to each other.

[0034] The core structure 110 can also improve the rigidity of the substrate 100 having the electronic components embedded therein according to the specific material, and can be used to ensure the thickness uniformity of the insulating material 130. In addition, since the core structure 110 includes the first core wiring layer 112a, the second core wiring layer 112b, the third core wiring layer 112c and the fourth core wiring layer 112d and the first core via layer 113a, the second core via layer 113b and the third core via layer 113c, various circuits can be designed and upper and lower electrical connection paths can be provided. In addition, since the core structure 110 includes the third core wiring layer 112c, and the third core wiring layer 112c is arranged at a height lower than the lower surface of the electronic component 120, the backside wiring layer can be easily arranged. The core structure 110 may include more layers than those shown in the drawings. Since the number of core wiring layers 112a, 112b, 112c, and 112d of the core structure 110 may be greater than the number of build-up wiring layers 142 and 152 of the build-up structure 160, the center of the substrate 100 may be set on the core structure 110. For example, based on the thickness direction, the center line C of the substrate 100 having the electronic components embedded therein may be set at a height between the upper and lower surfaces of the first insulators 111a, 111b, and 111c. Even in such an asymmetric structure, warpage can be controlled by the above-mentioned CTE adjustment.

[0035] The core structure 110 has a cavity 110H. A barrier layer 115 may be disposed on the bottom surface of the cavity 110H. The cavity 110H may have a blind hole form that penetrates the first core insulation layer 111a and the third core insulation layer 111c but does not penetrate the second core insulation layer 111b. The cavity 110H may have a tapered profile in which the width of the cross section decreases in a direction from the upper side toward the lower side, but the profile of the cavity 110H is not limited thereto.

[0036] The material of the first core insulation layer 111a may be an insulating material. The insulating material may be an insulating material of a copper clad laminate (CCL). The material of each of the second core insulation layer 111b and the third core insulation layer 111c may also be an insulating material. In this case, the insulating material may be an insulating material of resin-coated copper (RCC), but is not limited thereto. In addition, the material of each of the first core insulation layer 111a, the second core insulation layer 111b, and the third core insulation layer 111c may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, an insulating material in which a thermosetting resin or a thermoplastic resin is impregnated with an inorganic filler and / or glass fiber in a core material (such as a prepreg, etc.). When a material having high rigidity (such as a prepreg including glass fiber) is included, warping can be effectively controlled. The second core insulation layer 111b and the third core insulation layer 111c may include the same type of material. The first core insulation layer 111 a may have a thickness greater than that of each of the second core insulation layer 111 b and the third core insulation layer 111 c .

[0037] Each of the first core wiring layer 112a, the second core wiring layer 112b, the third core wiring layer 112c, and the fourth core wiring layer 112d may include a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Each of the first core wiring layer 112a, the second core wiring layer 112b, the third core wiring layer 112c, and the fourth core wiring layer 112d may perform various functions according to the design. For example, each of the first core wiring layer 112a, the second core wiring layer 112b, the third core wiring layer 112c, and the fourth core wiring layer 112d may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. The signal (S) pattern may include various signal patterns other than the ground (GND) pattern, the power (PWR) pattern, and the like, such as a data signal pattern, and the like. Each of the above patterns may have a linear shape, a planar shape, or a pad shape. The first core wiring layer 112a, the second core wiring layer 112b, the third core wiring layer 112c and the fourth core wiring layer 112d may be formed by processes such as additive process (AP), semi-additive (SAP) process, improved SAP (MSAP) process, sealing hole (TT) process, etc. As a result, each of the first core wiring layer 112a, the second core wiring layer 112b, the third core wiring layer 112c and the fourth core wiring layer 112d may include a seed layer, an electroless plating layer and an electrolytic plating layer formed based on the seed layer. Each of the first core wiring layer 112a, the second core wiring layer 112b, the third core wiring layer 112c and the fourth core wiring layer 112d may include a copper foil as the lowermost layer. The first core wiring layer 112a and the second core wiring layer 112b may be formed based on CCL and may have a copper foil layer as the lowermost layer.

[0038] The first core via layer 113a, the second core via layer 113b and the third core via layer 113c respectively penetrate the first core insulation layer 111a, the second core insulation layer 111b and the third core insulation layer 111c, and vertically connect the first core wiring layer 112a, the second core wiring layer 112b, the third core wiring layer 112c and the fourth core wiring layer 112d. The first core via layer 113a, the second core via layer 113b and the third core via layer 113c may also include metal materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or their alloys. Based on the design, each of the first core via layer 113a, the second core via layer 113b and the third core via layer 113c may have a via for a signal, a via for grounding, a via for power, etc. The connection vias of the first core via layer 113a, the second core via layer 113b, and the third core via layer 113c may be completely filled with a metal material, or the metal material may be formed along the wall surface of the via hole. The first core via layer 113a may have an hourglass shape or a cylindrical shape. The second core via layer 113b and the third core via layer 113c may have a profile that tapers in opposite directions to each other, and the first core via layer 113a is between them. The first core via layer 113a, the second core via layer 113b, and the third core via layer 113c may also be formed by a plating process such as AP, SAP, MSAP, TT, etc. As a result, each of the first core via layer 113a, the second core via layer 113b, and the third core via layer 113c may include a seed layer, an electroless plating layer, and an electrolytic plating layer formed based on the seed layer. The first core via layer 113a may be formed based on CCL and may have a copper foil layer as the bottom layer. The connection vias of the first core via layer 113a may be integrated with the pad patterns of the first core wiring layer 112a and the second core wiring layer 112b without boundaries. The connection vias of the second core via layer 113b and the third core via layer 113c may be integrated with the pad patterns of the third core wiring layer 112c and the fourth core wiring layer 112d, respectively, without boundaries with the pad patterns of the third core wiring layer 112c and the fourth core wiring layer 112d.

[0039] The barrier layer 115 may be disposed on the lower surface of the first core insulating layer 111a and may be covered by the second core insulating layer 111b. The barrier layer 115 may be formed by the same plating process as the first core wiring layer 112a, for example, AP, SAP, MSAP, TT, etc. As a result, the barrier layer 115 may include a seed layer as an electroless plating layer and an electroplating layer formed based on the seed layer. The barrier layer 115 may also include a copper foil layer as the lowermost layer. The barrier layer 115 may be formed simultaneously with the first core wiring layer 112a according to the same plating process as the first core wiring layer 112a, and therefore, the barrier layer 115 may be disposed at the same height as the first core wiring layer 112a and may include the same metal material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof. The barrier layer 115 may have a central region exposed from the first core insulating layer 111a through the cavity 110H and an edge region surrounding the central region and covered by the first core insulating layer 111a. A portion of the central region may be removed during the formation of the cavity 110H, and the central region may have a thickness smaller than that of the edge region. For example, the central region and the edge region may have a height difference h.

[0040] The electronic component 120 is disposed in the cavity 110H. The lower surface of the electronic component 120 may be attached to the barrier layer 115 by a known adhesive 125 (e.g., a chip attachment film (DAF)). The electronic component 120 may be constructed as an IC in which hundreds to millions or more devices are integrated into a single chip. For example, the electronic component 120 may be implemented by a processor chip such as a central processing unit (CPU), a graphics processor (GPU), a field programmable gate array (FPGA), an application processor (AP), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, etc., but its example embodiments are not limited thereto. The electronic component 120 may also be implemented by a memory such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM or flash memory), or a logic such as an application specific IC (ASIC). The electronic component 120 may also be constructed as a chip-type passive component.

[0041] The electronic component 120 may be formed based on an effective wafer. The base material of the body of the electronic component 120 may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. Various circuits may be provided in the body. The connection pad 120P may be provided on the effective surface of the body. The electronic component 120 may have an ineffective surface opposite to the effective surface, and the ineffective surface is provided to be attached to the barrier layer 115. The connection pad 120P may be configured to electrically connect the electronic component 120 to other elements, and conductive materials such as copper (Cu), aluminum (Al), etc. may be used as the material of the connection pad 120P of the electronic component 120. A passivation layer may be provided on the effective surface of the body to cover at least a portion of the connection pad 120P and expose at least a portion of the connection pad 120P. The passivation layer may be configured as an oxide layer or a nitride layer, or may be configured as a double layer including an oxide layer and a nitride layer. An insulating layer, etc. may be further provided at a desired position. The electronic component 120 may also be configured as a bare chip, but examples thereof are not limited thereto. The electronic component 120 may also be configured as a packaged chip.

[0042] The insulating material 130 may cover at least a portion of each of the core structure 110 and the electronic component 120, and may fill at least a portion of the cavity 110H. The insulating material 130 embeds the electronic component 120 therein. The material of the insulating material 130 is not necessarily limited. For example, an insulating material may be used as the material of the insulating material 130. In this case, similar to the second core insulating layer 111b and the third core insulating layer 111c, the insulating material of the RCC may be used as the material of the insulating material 130. However, the material of the insulating material 130 is not limited thereto. In addition, the material of the insulating material 130 may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, an insulating material (such as a prepreg, etc.) in which a thermosetting resin or a thermoplastic resin is mixed with an inorganic filler or impregnated with an inorganic filler and / or glass fiber in a core material. When a material having high rigidity (such as a prepreg including glass fiber) is included, warping can be effectively controlled. The insulating material 130 may include the same type of material as the second and third core insulating layers 111 b and 111 c .

[0043] The wiring layer 132 may be disposed on the insulating material 130. The wiring layer 132 may include a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof. The wiring layer 132 may also perform various functions based on the design. For example, the wiring layer 132 may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. The signal (S) pattern may include various signal patterns other than the ground (GND) pattern, the power (PWR) pattern, etc., such as a data signal pattern. Each of the patterns may have a linear shape, a planar shape or a pad shape. The wiring layer 132 may be formed by processes such as AP, SAP, MSAP, TT, etc., and may include a seed layer, an electroless plating layer, and an electrolytic plating layer formed based on the seed layer.

[0044] The via layer 133 penetrates the insulating material 130 and connects the wiring layer 132 to the connection pad 120P of the electronic component 120. The via layer 133 also connects the wiring layer 132 to the fourth core wiring layer 112d. Based on the design, the via layer 133 may also include vias for signals, vias for grounding, vias for power, etc. The via layer 133 may be completely filled with a metal material, or the metal material may be formed along the wall of the via hole. The wall surface of the via layer 133 may have a tapered profile. For example, when viewed in a cross section, the upper side may have a width greater than the width of the lower side. The via layer 133 may also be formed by a plating process such as AP, SAP, MSAP, TT, etc., and may include a seed layer, an electroless plating layer, and an electrolytic plating layer formed based on the seed layer. The via layer 133 may be integrated with at least a portion of the wiring layer 132 without boundaries.

[0045] The build-up structure 160 includes: a first build-up insulating layer 140 disposed on the insulating material 130 and covering at least a portion of the wiring layer 132; a first build-up wiring layer 142 disposed on the first build-up insulating layer 140; a second build-up insulating layer 150 disposed on the first build-up insulating layer 140 and covering at least a portion of the first build-up wiring layer 142; and a second build-up wiring layer 152 disposed on the second build-up insulating layer 150. The build-up structure 160 also includes: a first build-up via layer 143 penetrating the first build-up insulating layer 140 and connecting the wiring layer 132 and the first build-up wiring layer 142 to each other; and a second build-up via layer 153 penetrating the second build-up insulating layer 150 and connecting the first build-up wiring layer 142 and the second build-up wiring layer 152 to each other.

[0046] The accumulation structure 160 allows more wiring to be designed in the upward direction. The accumulation structure 160 includes a first accumulation wiring layer 142 and a second accumulation wiring layer 152 and a first accumulation via layer 143 and a second accumulation via layer 153, thereby allowing various circuits to be designed and providing a vertical electrical connection path. The accumulation structure 160 may include more layers than the layers shown in the drawings. However, the number of layers of the accumulation structure 160 is not limited thereto, and the accumulation structure 160 may include fewer layers than the layers shown in the drawings.

[0047] The first built-up insulating layer 140 and the second built-up insulating layer 150 may be sequentially laminated on the insulating material 130. The materials of the first built-up insulating layer 140 and the second built-up insulating layer 150 do not have to be limited. For example, an insulating material may be used as the material of the first built-up insulating layer 140 and the second built-up insulating layer 150. The insulating material is a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a resin in which a thermosetting resin or a thermoplastic resin is mixed with an inorganic filler (for example, ABF (Ajinomoto Build-up Film, Ajinomoto accumulation film) etc.). The first built-up insulating layer 140 and the second built-up insulating layer 150 may include an insulating resin and an inorganic filler, but may not include glass fiber. The first built-up insulating layer 140 and the second built-up insulating layer 150 may include the same type of material. The first built-up insulating layer 140 and the second built-up insulating layer 150 may be cured and then integrated with each other so that the boundary between them may not be easily obvious.

[0048] The first accumulation wiring layer 142 and the second accumulation wiring layer 152 may include a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof. The first accumulation wiring layer 142 and the second accumulation wiring layer 152 may perform various functions based on the design. For example, the first accumulation wiring layer 142 and the second accumulation wiring layer 152 may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. The signal (S) pattern may include various signal patterns other than the ground (GND) pattern, the power (PWR) pattern, etc., such as a data signal pattern. Each of the patterns may have a linear shape, a planar shape, or a pad shape. The first accumulation wiring layer 142 and the second accumulation wiring layer 152 may be formed by processes such as AP, SAP, MSAP, TT, etc. The first accumulation wiring layer 142 and the second accumulation wiring layer 152 may include a seed layer, an electroless plating layer, and an electrolytic plating layer formed based on the seed layer. First build-up wiring layer 142 and second build-up wiring layer 152 may further include a copper foil layer as a lowermost layer.

[0049] The first accumulation via layer 143 and the second accumulation via layer 153 penetrate the first accumulation insulating layer 140 and the second accumulation insulating layer 150, respectively. The first accumulation via layer 143 and the second accumulation via layer 153 vertically connect the wiring layer 132 and the first accumulation wiring layer 142 and the second accumulation wiring layer 152. The first accumulation via layer 143 and the second accumulation via layer 153 may also include a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof. Based on the design, each of the first accumulation via layer 143 and the second accumulation via layer 153 may also have a via for a signal, a via for grounding, a via for power, etc. The first accumulation via layer 143 and the second accumulation via layer 153 may be completely filled with a metal material, or the metal material may be formed along the wall surface of the via hole. The first accumulation via layer 143 and the second accumulation via layer 153 may have a profile that tapers in the same direction. For example, when viewed in cross section, the upper side may have a width greater than the width of the lower side. The first accumulation via layer 143 and the second accumulation via layer 153 may also be formed by plating processes such as AP, SAP, MSAP, TT, etc., and may include a seed layer, an electroless plating layer, and an electrolytic plating layer formed based on the seed layer. The connecting vias of the first accumulation via layer 143 and the second accumulation via layer 153 may be integrated with the pad patterns of the first accumulation wiring layer 142 and the second accumulation wiring layer 152, respectively, without boundaries.

[0050] The first passivation layer 170 can protect the third core wiring layer 112c from external physical damage and chemical damage. The first passivation layer 170 may be disposed on the lower surface of the second core insulating layer 111b, and may cover at least a portion of the third core wiring layer 112c, and may have a plurality of first openings, each of which exposes at least a portion of the third core wiring layer 112c. The material of the first passivation layer 170 does not have to be limited. For example, an insulating material may be used as the material of the first passivation layer 170. The insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, an insulating material in which a thermosetting resin or a thermoplastic resin is mixed with an inorganic filler or a thermosetting resin or a thermoplastic resin is impregnated with an inorganic filler and / or glass fiber in a core material (such as ABF (Ajinomoto Build-up Film)), but is not limited thereto. Optionally, a solder resist (SR) may be used as the material of the first passivation layer 170.

[0051] The second passivation layer 180 can protect the second built-up wiring layer 152 from external physical damage and chemical damage. The second passivation layer 180 can be disposed on the upper surface of the second built-up insulating layer 150 to cover at least a portion of the second built-up wiring layer 152, and can have a plurality of second openings, each second opening exposing at least a portion of the second built-up wiring layer 152. The material of the second passivation layer 180 does not have to be limited. For example, an insulating material can be used as the material of the second passivation layer 180. The above-mentioned ABF or SR can be used as an insulating material. As needed, the second passivation layer 180 may include a material of a different type from the first passivation layer 170. For example, the second passivation layer 180 may have a smaller coefficient of thermal expansion (CTE). Therefore, the CTE deviation of the upper and lower portions of the substrate can be further improved.

[0052] The first electrically connected metal parts 190 are respectively arranged on the first openings of the first passivation layer 170. The first electrically connected metal parts 190 are respectively connected to the exposed third core wiring layer 112c. The first electrically connected metal parts 190 physically and / or electrically connect the substrate 100 with the electronic components embedded therein to an external entity. For example, the substrate 100 with the electronic components embedded therein can be mounted on the motherboard of the electronic device (ball grid array (BGA) etc.) by the first electrically connected metal parts 190. For example, the first electrically connected metal parts 190 can be formed using tin (Sn) or an alloy including tin (Sn) (such as solder). However, this is only exemplary, and the material of the first electrically connected metal parts 190 is not limited thereto. The first electrically connected metal parts 190 can be a land, a solder ball, a pin, etc. The first electrically connected metal parts 190 may include multiple layers or a single layer. When the first electrically connected metal parts 190 include multiple layers, the first electrically connected metal parts 190 may include a copper column or a solder. When the first electrical connection metal member 190 includes a single layer, the first electrical connection metal member 190 may include tin-silver solder or copper. However, this is also only exemplary, and the example of the first electrical connection metal member 190 is not limited thereto. The number of first electrical connection metal members 190, the gaps between the first electrical connection metal members 190, and the arrangement of the first electrical connection metal members 190 are not necessarily limited thereto, and may vary based on the design. As needed, an under bump metal member (UBM) may be provided on each of the plurality of first openings, and the first electrical connection metal members 190 may be connected to the under bump metal members, respectively.

[0053] The surface mount component 210 may be further disposed on the second passivation layer 180. The surface mount component 210 may be surface mounted on the second passivation layer 180 through the second electrical connection metal piece 220, respectively. The surface mount component 210 may be an active component and / or a passive component. An example of an active component may be the IC described above with respect to the electronic component 120. An example of a passive component may be a chip capacitor such as a multilayer ceramic capacitor (MLCC), a chip inductor such as a power inductor (PI), and the like. The second electrical connection metal piece 220 may each include tin (Sn) or an alloy including tin (Sn), for example, solder, and the like. As required, a molding material may be further disposed on the second passivation layer 180 to cover the surface mount component 210. The molding material may be a known epoxy molding compound (EMC), but is not limited thereto. When the surface mount component 210 is further disposed, the substrate 100 having the electronic component embedded therein may be used as a SiP.

[0054] The substrate 100 having an electronic component embedded therein according to an example may have a plurality of cavities 110H. The above-mentioned barrier layer 115 may be applied to each of the cavities 110H. The same or different electronic components may be disposed in each of the cavities 110H.

[0055] Figures 5 to 11 It shows the manufacturing Figure 3 A process diagram of an example of a substrate having electronic components embedded therein is shown in FIG.

[0056] Reference Figure 5 , a CCL used as the first core insulating layer 111a is prepared. The CCL may have a structure in which a copper foil m1 is laminated on the upper and lower surfaces of an insulating material. A via hole 113ah is formed in the CCL using a mechanical drill or the like. The first core wiring layer 112a and the second core wiring layer 112b and the first core via layer 113a are formed by a plating process. In addition, a barrier layer 115 is formed. Here, although not shown, optionally, the copper foil m1 may be used as a base layer for forming the first core wiring layer 112a and the second core wiring layer 112b, but is not limited thereto.

[0057] Reference Figure 6, the second core insulation layer 111b and the third core insulation layer 111c are formed by laminating a prepreg on the upper and lower sides of the first core insulation layer 111a using RCC or the like. The RCC may have a structure in which the copper foil m2 is laminated on the insulating material. In addition, via holes 113bh and 113ch are formed by laser processing or the like. The third core wiring layer 112c and the fourth core wiring layer 112d and the second core via layer 113b and the third core via layer 113c are formed by a plating process. The release carrier film 310 is attached to the lower side of the core structure 110 manufactured by a series of processes, and the first passivation layer 170 such as ABF is interposed between them. Here, although not shown, optionally, the copper foil m2 may be used as a base layer for forming the third core wiring layer 112c and the fourth core wiring layer 112d, but is not limited thereto.

[0058] Reference Figure 7 , a patterned dry film 320 is attached to the upper side of the core structure 110 , and a cavity 110H having a depth to the barrier layer 115 is formed by a process of removing the core insulating layer through metal etching or sandblasting. The dry film 320 is removed.

[0059] Reference Figure 8 , the electronic component 120 is attached to the barrier layer 115 in the cavity 110H in a face-up form using an adhesive 125. The prepreg is laminated using RCC or the like to form an insulating material 130. The RCC may have a structure in which a copper foil m3 is laminated on an insulating material.

[0060] Reference Fig. 9 , via holes 133h are formed by laser processing, etc. Then, wiring layers 132 and via layers 133 are formed by a plating process.

[0061] Reference Fig.10 , a first built-up insulating layer 140 is formed by laminating ABF on an insulating material 130. After processing a via hole, a first built-up wiring layer 142 and a first built-up via layer 143 are formed by a plating process. A second built-up insulating layer 150, a second built-up wiring layer 152, and a second built-up via layer 153 are formed in a similar manner. The built-up structure 160 is formed by a series of processes.

[0062] Reference Fig.11 , a second passivation layer 180 is formed on the upper side of the accumulation structure 160 by laminating ABF or coating and curing SR. The release carrier film 310 is removed. As required, the first opening and the second opening described above may be formed in the first passivation layer 170 and the second passivation layer 180. In addition, as required, a first electrical connection metal member 190 and a second electrical connection metal member 220 may be formed to mount the surface mount component 210.

[0063] The above-mentioned substrate 100 having electronic components embedded therein may be manufactured through a series of processes. Other contents are the same as above, and detailed description thereof will be omitted.

[0064] As described above, it is possible to provide a substrate having electronic components embedded therein which can control warpage even if having an asymmetric structure.

[0065] In addition, a substrate having electronic components embedded therein which can be modularized and miniaturized in the form of a system-in-package (SiP) can be provided.

[0066] In the example embodiments, the terms "side region", "side surface", etc. may be used to refer to a surface formed by intercepting in the right / left direction, the terms "lower side", "lower part", "lower surface", etc. may be used to refer to a direction facing downward with reference to a cross section in the figure for ease of description, and the terms "upper side", "upper part", "upper surface", etc. may be used to refer to a direction opposite to the above directions. The concept of an element being disposed on a side region, an upper side, an upper region, or a lower region may include a configuration in which the element is in direct contact with an element configured as a reference in various directions and a configuration in which the element is not in direct contact with the reference element. For ease of description, the terms may be defined as above, and the scope of rights of the example embodiments is not particularly limited to the above terms.

[0067] In example embodiments, the term "connection" may refer not only to "direct connection" but also to "indirect connection" by means of an adhesive layer or the like. In addition, the term "electrical connection" may include both a case where an element is "physically connected" and a case where an element is "not physically connected". In addition, the terms "first", "second", etc. may be used to distinguish one element from another, and may not limit the order and / or importance or other related to the elements. In some cases, without departing from the scope of rights of example embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0068] In the example embodiments, the term "example embodiment" may not refer to one and the same example embodiment, but may be provided to describe and emphasize different unique features of each example embodiment. The example embodiments set forth above may be implemented without excluding the possibility of combining with features of other example embodiments. For example, even if a feature described in one example embodiment is not described in another example embodiment, the description may be understood to be related to the other example embodiment unless otherwise noted.

[0069] The terms used in the example embodiments are only used to describe the example embodiments and are not intended to limit the present disclosure. Unless otherwise specified, singular terms include plural forms.

[0070] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A substrate having an electronic component embedded therein, comprising: A core structure including a first insulator and a plurality of core wiring layers respectively disposed on or in the first insulator, and having a cavity penetrating a portion of the first insulator in a direction from a first surface of the first insulator toward a second surface opposite to the first surface; an electronic component, disposed in the cavity; an insulating material covering at least a portion of each of the core structure and the electronic component and disposed in at least a portion of the cavity; A wiring layer, disposed on the insulating material; a build-up structure disposed on the insulating material and comprising a second insulator and one or more build-up wiring layers, the second insulator covering at least a portion of the wiring layer, the one or more build-up wiring layers being disposed on the second insulator or in the second insulator, respectively, and a first passivation layer disposed on a side of the core structure opposite to the side on which the insulating material is disposed, and a second passivation layer disposed on a side of the build-up structure opposite to the insulating material, wherein the material of the first insulator has a thermal expansion coefficient that is smaller than the thermal expansion coefficient of the material of the second insulator, wherein the insulating material has a thermal expansion coefficient that is smaller than the thermal expansion coefficient of the material of the second insulator, and Wherein, the thermal expansion coefficient of the second passivation layer is smaller than the thermal expansion coefficient of the first passivation layer.

2. The substrate having an electronic component embedded therein according to claim 1, wherein: A center line of the substrate having the electronic component embedded therein is disposed at a height between the first surface and the second surface of the first insulator based on a thickness direction of the substrate.

3. The substrate having electronic components embedded therein according to claim 1, wherein: Each of the first insulator and the insulating material includes an insulating resin, an inorganic filler, and glass fiber, and The second insulator includes an insulating resin and an inorganic filler, but does not include glass fiber.

4. The substrate having electronic components embedded therein according to claim 1, wherein: Each of the first insulator and the insulating material includes a prepreg, and The second insulator includes an Ajinomoto deposited film.

5. The substrate having electronic components embedded therein according to claim 1, wherein: The cavity has a barrier layer as a bottom surface of the cavity, and The barrier layer is disposed at the same height as one of the plurality of core wiring layers.

6. The substrate having electronic components embedded therein according to claim 5, wherein: The electronic component has an active surface and an inactive surface opposite to the active surface, the active surface having connection pads disposed thereon, and the inactive surface is disposed to be attached to the barrier layer.

7. The substrate having electronic components embedded therein according to claim 5, wherein: The barrier layer has a first region and a second region, the first region is exposed from the first insulator through the cavity, the second region surrounds the first region and is covered by the first insulator, and The first region has a thickness smaller than a thickness of the second region.

8. The substrate having electronic components embedded therein according to claim 1, wherein: The core structure includes: a first core insulation layer; a first core wiring layer, which is arranged on one side of the first core insulation layer; a barrier layer, which is arranged on the one side of the first core insulation layer; a second core wiring layer, which is arranged on the other side of the first core insulation layer; a second core insulation layer, which is arranged on the one side of the first core insulation layer and covers at least a portion of each of the first core wiring layer and the barrier layer; a third core wiring layer, which is arranged on the second core insulation layer; a third core insulation layer, which is arranged on the other side of the first core insulation layer and covers at least a portion of the second core wiring layer; and a fourth core wiring layer, which is arranged on the third core insulation layer, The first insulator includes the first to third core insulation layers, and The plurality of core wiring layers include the first to fourth core wiring layers.

9. The substrate having electronic components embedded therein according to claim 8, wherein: Each of the first to third core insulation layers includes a prepreg, and The first core insulation layer has a thickness greater than a thickness of each of the second core insulation layer and the third core insulation layer.

10. The substrate having electronic components embedded therein according to claim 8, wherein: The core structure further includes: a first core via layer, penetrating the first core insulation layer and connecting the first core wiring layer and the second core wiring layer to each other; a second core via layer, penetrating the second core insulation layer and connecting the first core wiring layer and the third core wiring layer; and a third core via layer, penetrating the third core insulation layer and connecting the second core wiring layer and the fourth core wiring layer to each other, and The second core via layer and the third core via layer respectively have profiles tapered in opposite directions.

11. The substrate having electronic components embedded therein according to claim 8, further comprising: A via layer penetrates the insulating material and connects the wiring layer to each of the electronic component and the fourth core wiring layer.

12. The substrate having electronic components embedded therein according to claim 8, wherein: The built-up structure includes: a first built-up insulating layer disposed on the insulating material and covering a portion of the wiring layer; a first built-up wiring layer disposed on the first built-up insulating layer; a second built-up insulating layer disposed on the first built-up insulating layer and covering at least a portion of the first built-up wiring layer; and a second built-up wiring layer disposed on the second built-up insulating layer. The second insulator includes the first build-up insulating layer and the second build-up insulating layer, and The one or more build-up wiring layers include the first build-up wiring layer and the second build-up wiring layer.

13. The substrate having electronic components embedded therein according to claim 12, wherein: Each of the first build-up insulating layer and the second build-up insulating layer includes an Ajinomoto deposited film.

14. The substrate having electronic components embedded therein according to claim 12, wherein: The build-up structure further includes: a first build-up via layer penetrating the first build-up insulating layer and connecting the wiring layer and the first build-up wiring layer to each other; and a second build-up via layer penetrating the second build-up insulating layer and connecting the first build-up wiring layer and the second build-up wiring layer to each other, and Each of the first build-up via layer and the second build-up via layer has a tapered profile in which a width of a cross section decreases in a direction from the first build-up via layer or the second build-up via layer toward the core structure.

15. The substrate having electronic components embedded therein according to claim 1, wherein: The first passivation layer has a plurality of first openings, each of the first openings exposing at least a portion of one of the plurality of core wiring layers; as well as A plurality of first electrical connection metal members are respectively disposed on the plurality of first openings and respectively connected to at least a portion of the exposed core wiring layer.

16. The substrate having electronic components embedded therein according to claim 15, wherein: The second passivation layer has a plurality of second openings, each of the second openings exposing at least a portion of the one or more build-up wiring layers; a plurality of second electrical connection metal members, respectively disposed on the plurality of second openings and respectively connected to at least a portion of the exposed build-up wiring layer; as well as One or more surface mount components are mounted on the second passivation layer through the plurality of second electrical connection metal members.

17. A substrate, comprising: A core structure including a first insulator and a core wiring layer respectively disposed on or in the first insulator and having a cavity penetrating a portion of the first insulator; an electronic component, disposed in the cavity; an insulating material covering at least a portion of each of the core structure and the electronic component and disposed in at least a portion of the cavity; A wiring layer is directly disposed on the insulating material; a via layer connecting the wiring layer to one of the core wiring layer and a connection pad of the electronic component in the insulating material; a build-up structure disposed on the insulating material and comprising a second insulator and one or more build-up wiring layers, the second insulator covering at least a portion of the wiring layer, the one or more build-up wiring layers being disposed on the second insulator or in the second insulator, respectively, a first passivation layer disposed on a side of the core structure opposite to the side on which the insulating material is disposed, and a second passivation layer disposed on a side of the build-up structure opposite to the insulating material, wherein the insulating material has a coefficient of thermal expansion that is smaller than a coefficient of thermal expansion of a material of the second insulator, wherein the cavity has a barrier layer as a bottom surface of the cavity, and The thermal expansion coefficient of the second passivation layer is smaller than the thermal expansion coefficient of the first passivation layer.

18. The substrate according to claim 17, wherein Based on the thickness direction of the substrate, a center line of the substrate is disposed at a height between the first surface and the second surface of the first insulator.

19. The substrate according to claim 17, wherein Each of the first insulator and the insulating material includes an insulating resin, an inorganic filler, and glass fiber, and The second insulator includes an insulating resin and an inorganic filler, but does not include glass fiber.

20. The substrate according to claim 17, wherein The core structure comprises: a first core insulation layer, the cavity at least passing through the first core insulation layer; and A second core insulation layer, an edge of the barrier layer being embedded in the second core insulation layer.

Images