Semiconductor device and method of manufacturing the same

Abstract

Semiconductor device and method of manufacturing a semiconductor device. In one example, a semiconductor structure or device includes: a substrate including a conductive structure having a top side and a first shielding terminal on the top side of the conductive structure; an electronic component on the top side of the conductive structure; a package on the top side of the conductive structure and contacting one side of the electronic component; a shield on the top side and side of the package; and a shield interconnect coupling the shield to the first shielding terminal of the conductive structure. Other examples and related methods are also disclosed herein.

Description

Technical Field

[0001] The present disclosure generally relates to electronic devices, and more particularly, to semiconductor devices and methods for manufacturing semiconductor devices. Background Art

[0002] Existing semiconductor packages and methods for forming semiconductor packages are deficient, for example, resulting in excessive cost, reduced reliability, relatively low performance, or too large package size. For those skilled in the art, additional limitations and disadvantages of such methods will become apparent by comparing conventional and traditional methods with the present disclosure and referring to the accompanying drawings. Summary of the Invention

[0003] Various aspects of the present disclosure provide a semiconductor structure, comprising: a substrate including a conductive structure having a top side and a first shielding terminal on the top side of the conductive structure; an electronic component on the top side of the conductive structure; a package on the top side of the conductive structure and contacting one side of the electronic component; a shield on the top side and the side of the package; and a shield interconnect coupling the shield to the first shielding terminal of the conductive structure. In the semiconductor structure, the shield includes a first shielding layer and a second shielding layer on the first shielding layer. The semiconductor structure further includes a dielectric structure coupled to the conductive structure. In the semiconductor structure, the dielectric structure includes a part of the package as a continuous material. In the semiconductor structure, the dielectric structure is separated from the package. In the semiconductor structure, the shield contacts a groove in the package at the side of the package. In the semiconductor structure, the first shielding layer includes a ridge and a ridge protrusion at the side of the package, and the second shielding layer is on the ridge protrusion at the side of the package. In the semiconductor structure, the conductive structure includes a support bar, and the first shielding terminal is on the support bar. In the semiconductor structure, the conductive structure includes a support bar having a dividing bar, and the first shielding terminal is on the dividing bar. In the semiconductor structure, the shield interconnect includes a wire. In the semiconductor structure, the conductive structure includes a paddle adjacent to the electronic component, the first shielding terminal is on the paddle and the shield interconnect couples the shield to the paddle. In the semiconductor structure, the conductive structure includes a paddle adjacent to the electronic component; the first shielding terminal is on one of the support bar or the lead of the conductive structure; a second shielding terminal is on the paddle; and the shield interconnect is coupled to the first shielding terminal, the second shielding terminal and the shield.

[0004] Aspects of the present disclosure provide a method that includes: providing a substrate including a dielectric structure and a conductive structure having a top side and a shielding terminal on the top side of the conductive structure; providing an electronic component on the top side of the conductive structure; providing a package on the top side of the conductive structure and contacting one side of the electronic component; providing a through hole in the package from the top side of the package to the shielding terminal; and providing a shield on the top side and a side surface of the package, wherein the shield includes a shielding interconnect in the through hole connecting the shield to the shielding terminal of the conductive structure. The method further includes providing the through hole in the package to expose the shielding terminal before providing the shield on the top side and the side surface of the package. The method further includes providing a seed layer on the package before providing the shield on the top side and the side surface of the package. In the method, providing the shield includes providing a first shield layer on the top side and the side surface of the package and providing a second shield layer on the first shield layer. The method further includes providing a groove in the package at the side of the package, wherein the package is exposed below the shield at the side of the package.

[0005] Aspects of the present disclosure provide a semiconductor structure that includes: a substrate including a dielectric structure and a conductive structure having a top side, a paddle, and a shielding terminal on the top side of the conductive structure; a first electronic component and a second electronic component on the paddle on the top side of the conductive structure; a package on the top side of the conductive structure and contacting one side of the first electronic component and one side of the second electronic component; a shield on the top side and a side surface of the package; a shielding wall between the first electronic component and the second electronic component and contacting the shield; and a shielding interconnect coupling the shield to the shielding terminal of the conductive structure. In the semiconductor structure, the shielding wall defines a first compartment containing the first electronic device but not the second electronic device and a second compartment containing the second electronic device but not the first electronic device. In the semiconductor structure, the shielding interconnect includes a wire. Description of the Drawings

[0006] Figure 1A A perspective view of an example semiconductor device is shown.

[0007] Figure 1B and 1C shows a cross-sectional view of an exemplary semiconductor device.

[0008] Figures 2A to 2G shows a cross-sectional view of an exemplary method for manufacturing an exemplary semiconductor device.

[0009] Figure 3A and 3B show a perspective view and a top view of a shielded interconnect of an exemplary semiconductor device, respectively.

[0010] Figure 4A shows a perspective view of an exemplary semiconductor device.

[0011] Figure 4B and 4C shows a cross-sectional view of an exemplary semiconductor device.

[0012] Figures 5A to 5D shows a cross-sectional view of an exemplary method for manufacturing an exemplary semiconductor device.

[0013] Figure 6A shows a perspective view of an exemplary semiconductor device.

[0014] Figure 6B and 6C shows a cross-sectional view of an exemplary semiconductor device.

[0015] Figures 7A to 7D shows a cross-sectional view of an exemplary method for manufacturing an exemplary semiconductor device.

[0016] Figure 8A and 8B show a perspective view and a top view of a shielded interconnect of an exemplary semiconductor device, respectively.

[0017] Figure 9A shows a perspective view of an exemplary semiconductor device.

[0018] Figure 9B and 9C shows a cross-sectional view of an exemplary semiconductor device.

[0019] Figures 10A to 10D shows a cross-sectional view of an exemplary method for manufacturing an exemplary semiconductor device.

[0020] Figures 11A to 11B show a perspective view and a top view of a shielded interconnect of an exemplary semiconductor device, respectively.

[0021] Figures 12A to 12B shows a cross-sectional view of an exemplary semiconductor device.

[0022] Figures 13A to 13BShows a cross-sectional view of an exemplary semiconductor device.

[0023] The following discussion provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. Such examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

[0024] The drawings illustrate the general construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the disclosure. Additionally, the elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some of the elements in the drawings may be enlarged relative to other elements to facilitate understanding of the examples discussed in the disclosure. Like reference numerals in different drawings indicate like elements.

[0025] The term "or" means any one or more of the items in a list connected by "or". As an example, "x or y" means any element in the three-element set {(x), (y), (x, y)}. As another example, "x, y, or z" means any element in the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0026] The terms "comprises", "comprising", "includes", or "including" are "open" terms and specify the presence of the stated feature, but do not preclude the presence or addition of one or more other features. The terms "first", "second", etc. may be used herein to describe various elements, and these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, for example, a first element discussed in the disclosure may be referred to as a second element without departing from the teachings of the disclosure.

[0027] Unless otherwise specified, the term "coupled" may be used to describe two elements that are in direct contact with each other or two elements that are indirectly connected through one or more other elements. For example, if element A is coupled to element B, element A may be in direct contact with element B or indirectly connected to element B through an intermediate element C. Similarly, the terms "above" or "on" may be used to describe two elements that are in direct contact with each other or two elements that are indirectly connected through one or more other elements. Detailed Description

[0028] In one example, a semiconductor structure includes: a substrate including a conductive structure having a top side and a first shielding terminal on the top side of the conductive structure; an electronic component on the top side of the conductive structure; a package on the top side of the conductive structure and contacting one side of the electronic component; a shield on the top side and a side surface of the package; and a shield interconnect coupling the shield to the first shielding terminal of the conductive structure.

[0029] In another example, a method of manufacturing a semiconductor device includes: providing a substrate including a dielectric structure and a conductive structure having a top side and a shielding terminal on the top side of the conductive structure; providing an electronic component on the top side of the conductive structure; providing a package on the top side of the conductive structure and contacting one side of the electronic component; providing a via in the package from the top side of the package to the shielding terminal; and providing a shield on the top side and a side surface of the package, wherein the shield includes a shield interconnect in the via connecting the shield to the shielding terminal of the conductive structure.

[0030] In additional examples, a semiconductor structure or semiconductor device includes: a substrate including a dielectric structure and a conductive structure having a top side, a paddle, and a shielding terminal on the top side of the conductive structure; a first electronic component and a second electronic component on the paddle on the top side of the conductive structure; a package on the top side of the conductive structure and contacting one side of the first electronic component and one side of the second electronic component; a shield on the top side and a side surface of the package; a shield wall between the first electronic component and the second electronic component and contacting the shield; and a shield interconnect coupling the shield to the shielding terminal of the conductive structure.

[0031] Other examples are included in this disclosure. Such examples may be present in the figures, claims, or description of this disclosure.

[0032] Figure 1A A perspective view of an example semiconductor device 10 is shown, and Figure 1B and 1C respectively show cross-sectional views taken along Figure 1A lines 1A-1A and 1B-1B. In Figure 1A, 1B In the example shown in FIGS. 1C and 1C, the semiconductor device 10 may include a substrate 11, an electronic component 12, a component interconnect 13, a package 14, and a shield 15.

[0033] The substrate 11 may include a conductive structure 111 and a dielectric structure 112. The conductive structure 111 may include paddles 1111, paddle top pads 1111a, paddle bottom pads 1111b, interconnect terminals 1112, interconnect terminal top pads 1112a, interconnect terminal bottom pads 1112b, support bars 1113, and shield terminals 1114a on the support bars 1113 and shield terminals 1114b on the paddles 1111. In some examples, the pads 1111a, 1111b, 1112a, or 1112b may include or be referred to as plating or bumps. An adhesive 121 may be located between the electronic component 12 and the substrate 11. The component interconnect 13 may connect the electronic component 12 to the interconnect terminal top pad 1112a located on the interconnect terminal 1112. The component interconnect 13 may connect the electronic component 12 to the paddle top pad 1111a located on the paddle 1111. The component interconnect 13 may connect the paddle top pad 1111a located on the paddle 1111 to the interconnect terminal top pad 1112a located on the interconnect terminal 1112. The shield 15 may include shield layers 151 and 152, ridge protrusions 1511, ridges 1512, and shield interconnects 155A and 155B.

[0034] The substrate 11, the package 14, and the shield 15 may be referred to as a semiconductor package, and the package may provide protection for the electronic component 12 from exposure to external elements or the environment. The semiconductor package may provide an electrical coupling between an external electrical component and the substrate.

[0035] In some examples, the semiconductor device 10 may be a semiconductor structure including a substrate 11, the substrate including a conductive structure 111 having a top side and a first shield terminal 1114a or 1114b on the top side of the conductive structure 111. The semiconductor structure may include an electronic component 12 on the top side of the conductive structure 111 and a package 14 on the top side of the conductive structure 111 and contacting a side of the electronic component 12. The semiconductor structure may further include a shield 15 on the top side and the sides of the package 14 and a shield interconnect 155A or 155B coupling the shield 15 to the first shield terminal 1114a or 1114b of the conductive structure 111. In some examples, the shield 15 may include a first shield layer 151 and a second shield layer 152.

[0036] In some instances, the dielectric structure 112 can be coupled to the conductive structure 111. In some instances, the dielectric structure 112 can include a portion of the encapsulation body 14 as a continuous material. In other instances, the dielectric structure 112 can be separate from the encapsulation body 14. In some instances, the shield 15 can contact the groove 18 in the encapsulation body 14 at the side of the encapsulation body 14. In some instances, the first shield layer 151 can have a ridge 1512 and a ridge protrusion 1511 at the side of the encapsulation body 14. In such an arrangement, the second shield layer 152 can be on the ridge protrusion 1511 at the side of the encapsulation body 14. In some instances, the conductive structure 111 can include paddles 1111 adjacent to the electronic component 12. The first shield terminal 1114a or 1114b can be on the paddle 1111, and the shield interconnect 155A or 155B can couple the shield 111 to the paddle 1111.

[0037] In some instances, the conductive structure 111 can include paddles 1111 adjacent to the electronic component 12, and the first shield terminal 1114a or 1114b is on one of the support bars 1113 or leads of the conductive structure 111. The second shield terminal 1114a or 1114b can be on the paddle 1111, and the shield interconnect 155A or 155B can be coupled to the first shield terminal 1114a or 1114b, the second shield terminal 1114a or 1114b, and the shield 15.

[0038] Figures 2A to 2G A cross-sectional view of an example method for manufacturing Figure 1A the semiconductor device 10 is shown, and its description below is supplemented by Figure 1A Supplementary. Figures 2A to 2G Corresponds to a cross-sectional view taken along Figure 1A the line 1B-1B. Figure 2A A cross-sectional view of the semiconductor device 10 in an early manufacturing stage is shown.

[0039] In Figure 2A the illustrated instance, a semi-finished semiconductor device can be provided on the carrier 16. In some instances, the semi-finished semiconductor device can include a substrate 11, an electronic component 12 attached to the substrate 11 using an adhesive 121, a component interconnect 13 (see Figure 1B ) that electrically connects the substrate 11 and the electronic component 12, and an encapsulation body 14. To enhance manufacturability, multiple semiconductor devices can be arranged in a matrix configuration on one carrier 16. Here, multiple interconnected semi-finished semiconductor devices are shown.

[0040] The carrier 16 may include or may be referred to as a back tape or a lead frame tape and may secure the paddle 1111, the interconnect terminal 1112, or the support bar 1113 of the substrate 11 during the encapsulation process. The carrier 16 may have heat resistance and chemical resistance to maintain the shape of the semiconductor device 10 without deformation or warping during the manufacture of the semiconductor device. In some instances, the carrier 16 may include an adhesive layer that loses its adhesiveness due to heat or light exposure.

[0041] The substantially planar substrate 11 may be attached to the adhesive layer of the carrier 16. The substrate 11 may include or may be referred to as a lead frame, a laminated substrate, a redistribution layer (RDL) substrate, or a molded substrate. In some instances, the substrate 11 may include a conductive structure 111 that includes the paddle 1111, the interconnect terminal 1112, and the support bar 1113. The substrate 11 may further include a dielectric structure 112 coupled to the conductive structure 111. The conductive structure 111 may include or may be referred to as one or more traces, leads, paths, vias, paddles, support bars, conductors, conductive layers, or conductive materials. In some instances, the conductive structure 111 may include copper, nickel, iron, aluminum, stainless steel, or an alloy. The dielectric structure 112 may include or may be referred to as one or more dielectrics, dielectric layers, resins, epoxy resins, molding compounds, prepregs, or dielectric materials. The paddle 1111 may include a top side and a bottom side opposite the top side. The paddle 1111 may include or may be referred to as a die pad, a die mark, or a component attachment portion of the substrate 11. The thickness of the paddle 1111 may be in the range of about 125 micrometers (μm) to about 200 μm. The electronic component 12 may be coupled to the paddle 1111 using an adhesive 121 or a component interconnect 13. The paddle 1111 may then be electrically connected to an external device through the paddle bottom side or the paddle bottom pad 1111b.

[0042] The interconnect terminal 1112 can be arranged to be spaced apart from the paddle 1111. In some instances, the interconnect terminal 1112 can include or can be referred to as a lead or a pad. The thickness of the interconnect terminal 1112 can be in the range of about 125 μm to about 200 μm. The interconnect terminal 1112 can be electrically connected to the electronic component 12 through the component interconnect 13. The interconnect terminal 1112 can then be electrically connected to an external device through the paddle bottom pad 1112b. The support bar 1113 can extend from the paddle 1111. The support bar 1113 can include or can be referred to as a tie bar, a connecting bar, a pad, or a trace to which a shield can be coupled. The thickness of the support bar 1113 can be less than or equal to the thickness of the paddle 1111 or the interconnect terminal 1112, and the bottom side of the support bar 1113 can be covered by the dielectric structure 112. In some instances, the top side of the support bar 1113 can be coplanar with the top sides of the paddle 1111 and the interconnect terminal 1112. The thickness of the support bar 1113 can be in the range of about 125 μm to about 200 μm. The support bar 1113 can then be electrically connected to the shield 15. In some instances, the support bar 1113 can be electrically connected to the paddle 1111 or the interconnect terminal 1112. In some instances, the conductive structure 111 can include the support bar 1113, and the first shield terminals 1114a or 1114b can be on the support bar 1113.

[0043] The electronic component 12 can be attached to the paddle 1111 using the adhesive 121. The electronic component 12 can include or can be referred to as a chip, a die, a package, or a passive device. The thickness of the electronic component 12 can be in the range of about 75 μm to about 250 μm. If the active side or the circuitry side of the electronic component 12 faces upward, the electronic component 12 can be electrically connected to the paddle 1111 or the interconnect terminal 1112 through the component interconnect 13. In some instances, the component interconnect 13 can include or can be referred to as a wire or a bonding wire. The diameter of the component interconnect 13 can be in the range of about 10 μm to about 50 μm. If the active side or the circuitry side of the electronic component 12 faces downward, the electronic component 12 can be electrically connected to the paddle 1111 or the interconnect terminal 1112 in a flip-chip form. If the electronic component 12 is of the flip-chip type, underfill can further be located between the electronic component 12 and the substrate 11. In some instances, the component interconnect 13 can include or can be referred to as a bump or a post.

[0044] The encapsulation body 14 can cover the substrate 11, the electronic component 12, and the component interconnect 13. In some instances, the dielectric structure 112 of the substrate 11 and the encapsulation body 14 can be part of each other or can include the same or continuous dielectric material or layer. The encapsulation body 14 can include or can be referred to as an encapsulant, a molding compound, a resin, a sealant, or an organism. The encapsulation body 14 can be prepared by covering the substrate 11, the electronic component 12, and the component interconnect 13 using a compression molding process, an injection molding process, a transfer molding process, or a film-assisted molding process. The thickness of the encapsulation body 14 can be in the range of about 200 μm to about 1500 μm. The encapsulation body 14 can provide protection for the substrate 11, the electronic component 12, and the component interconnect 13 from exposure to external elements or the environment.

[0045] In some instances, the substrate 11 can be a redistribution layer (“RDL”) substrate. The RDL substrate can include one or more conductive redistribution layers and one or more dielectric layers, where the one or more conductive redistribution layers and the one or more dielectric layers (a) can be formed layer by layer above an electronic device to which the RDL substrate is to be electrically coupled or (b) can be formed layer by layer above a carrier, which can be completely removed or at least partially removed after the electronic device and the RDL substrate are coupled together. The RDL substrate can be fabricated layer by layer on a circular wafer as a wafer-level substrate in a wafer-level process or on a rectangular or square panel carrier as a panel-level substrate in a panel-level process. The RDL substrate can be formed by an additive build-up process, which can include one or more dielectric layers alternately stacked with one or more conductive layers that define respective conductive redistribution patterns or traces configured to collectively (a) fan out electrical traces outside the footprint of the electronic device or (b) fan in electrical traces into the footprint of the electronic device. The conductive patterns can be formed using a plating process, such as an electroplating process or an electroless plating process. The conductive patterns can include a conductive material, such as copper or other plating metals. A photolithographic mask can be fabricated to define the locations of the conductive patterns using a photolithographic patterning process, such as a photolithography process and a photoresist material. The dielectric layers of the RDL substrate can be patterned using a photolithographic patterning process that can include a photolithographic mask, where light is exposed through the photolithographic mask to desired features of the light pattern, such as vias in the dielectric layers. Thus, the dielectric layers can be made of a photo-definable organic dielectric material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). Such dielectric materials can be spin-coated or otherwise coated in a liquid form rather than attached in the form of a pre-formed film. To allow for proper formation of the desired photo-defined features, such photo-definable dielectric materials can omit a structural enhancer or can be filler-free, without strands, fabrics, or other particles that could interfere with the light from the photolithographic patterning process. In some instances, such filler-free characteristics of the filler-free dielectric materials can allow for a reduction in the thickness of the resulting dielectric layers. Although the photo-definable dielectric materials described above can be organic materials, in other instances, the dielectric materials of the RDL substrate can include one or more inorganic dielectric layers. Some examples of the one or more inorganic dielectric layers can include silicon nitride (Si3N4), silicon oxide (SiO2), or silicon oxynitride (SiON). The one or more inorganic dielectric layers can be formed by using an oxidation or nitridation process rather than growing the inorganic dielectric layers using a photo-definable organic dielectric material. Such inorganic dielectric layers can be filler-free, without strands, fabrics, or other distinct inorganic particles. In some instances, the RDL substrate can omit a permanent core structure or carrier, such as a dielectric material including bismaleimide triazine (BT) or FR4, and these types of RDL substrates can be referred to as coreless substrates.

[0046] In some instances, the substrate 11 can be a pre-formed substrate. The pre-formed substrate can be manufactured before being attached to the electronic device and can include a dielectric layer between corresponding conductive layers. The conductive layers can include copper and can be formed using an electroplating process. The dielectric layer can be a relatively thick non-photo-definable layer that can be attached in the form of a pre-formed film rather than in a liquid form and can contain a resin with fillers such as strands, fabrics, or other inorganic particles for rigid or structural support. Since the dielectric layer is non-photo-definable, features such as vias or openings can be formed by using drilling or lasers. In some instances, the dielectric layer can include a prepreg material or an Ajinomoto Buildup Film (ABF). The pre-formed substrate can include a permanent core structure or carrier, such as a dielectric material including bismaleimide triazine (BT) or FR4, and the dielectric layer and conductive layers can be formed on the permanent core structure. In other instances, the pre-formed substrate can be a coreless substrate that omits the permanent core structure, and the dielectric layer and conductive layers can be formed on a sacrificial carrier that is removed after the dielectric layer and conductive layers are formed and before being attached to the electronic device. The pre-formed substrate can be referred to as a printed circuit board (PCB) or a laminated substrate. Such pre-formed substrates can be formed by a semi-additive process or a modified semi-additive process.

[0047] Figure 2B A cross-sectional view of the semiconductor device 10 in a later manufacturing stage is shown. In Figure 2B the illustrated instance, vias 17 can be defined in the package 14. The vias 17 can include or can be referred to as openings or through-holes. The vias 17 can be formed by a laser beam, mechanical drilling, or chemical etching. In some instances, the vias 17 can be formed in regions corresponding to respective portions of the support bars 1113. In some instances, the diameter of the vias 17 can be maximum at the top end and can gradually decrease downward toward the lower end. The diameter of the vias 17 can be in the range of about 50 μm to about 300 μm. In some instances, the height of the vias 17 can be in the range of about 225 μm to about 1000 μm. The vias 17 can pass through the package 14 to expose the top-side region of the support bars 1113. The top-side region of the support bars 1113 exposed through the package 14 can be referred to as the shield terminals 1114a. In some instances, the vias 17 can include or be defined by one or more shield interconnects in the package 14.

[0048] Figure 2C A cross-sectional view of the semiconductor device 10 in a later manufacturing stage is shown. In Figure 2CIn the illustrated example, the groove 18 may be formed in the package 14. The groove 18 may include or may be referred to as a trench or a channel. The groove 18 may be formed by a laser beam, mechanical drilling, an impeller, or chemical etching. In some examples, the groove 18 may be formed in a region corresponding to the support bar 1113 or a region to be cut and separated in a subsequent process. Each of the grooves 18 may have a side surface 18a and a bottom surface 18b. The side surface 18a of each groove 18 may be substantially perpendicular to the top surface of the substrate 11, and the bottom surface 18b of each groove 18 may be substantially parallel to the top surface of the substrate 11. The depth of the groove 18 may be less than that of the through hole 17, and a portion of the package 14 may still be below the bottom surface 18b of the groove 18. The thickness of the region of the package 14 that is still below the bottom surface 18b of the groove 18 may be in the range of about 50 μm to about 150 μm. The width of the groove 18 (bottom surface 18b) may be in the range of about 100 μm to about 700 μm. The side surface 18a and the bottom surface 18b of the groove 18 may provide a region for forming the shield 15 in a subsequent process.

[0049] Figure 2D A cross-sectional view of the semiconductor device 10 in a later manufacturing stage is shown. In Figure 2D In the illustrated example, the seed layer 19 may be formed on the package 14. In some examples, the seed layer 19 may be formed on the package 14, the through hole 17, and the groove 18. The seed layer 19 may also be formed on the region of the support bar 1113 exposed by the through hole 17 such as the shield terminal 1114a, or on the region of the paddle 1111 exposed by the through hole 17 such as the shield terminal 1114b. The seed layer 19 may include or may be referred to as a conductive layer. In some examples, the seed layer 19 may be made of tungsten, tungsten titanium, or copper. In some examples, the seed layer 19 may be formed by electroless plating or sputtering. In some examples, before forming the seed layer 19, further cleaning may be performed to improve the adhesion to the seed layer 19 by removing epoxy resin stains that may be present in the through hole 17 or the groove 18 or by increasing the roughness. The thickness of the seed layer 19 may be in the range of about 1 μm to about 3 μm. The seed layer 19 may apply power to the plating solution in a subsequent process for forming the shield 15.

[0050] Figure 2E A cross-sectional view of the semiconductor device 10 in a later manufacturing stage is shown. In Figure 2EIn the illustrated example, the shielding layer 151 may be formed on the seed layer 19. In some examples, the shielding layer 151 may be formed on the seed layer 19 located on the top side of the package 14, the seed layer 19 on the via hole 17, and the seed layer 19 on the recess 18. In some examples, the shielding layer 151 may fill the via hole 17. The shielding layer 151 filling the via hole 17 may be electrically connected to the shielding terminal 1114a on the support bar 1113 or electrically connected to the shielding terminal 1114b on the die paddle 1111. The shielding layer 151 filling the via hole 17 may be defined as shielding interconnects 155A and 155B. The height and diameter of the shielding interconnect 155A may be similar to the height and diameter of the via hole 17 and may be in the range of about 225 μm to about 1000 μm or about 50 μm to about 300 μm. In some examples, the region of the shielding layer 151 on the side surface 18a of the recess 18 may be defined as a ridge 1512, and the region of the shielding layer 151 on the region corresponding to the bottom side 18b of the recess 18 may be defined as a ridge protrusion 1511. In some examples, the shielding layer 151 may be formed by electroplating aluminum or copper on the seed layer 19. The thickness of the shielding layer 151 may be in the range of about 10 μm to about 20 μm. The shielding layer 151 may prevent electromagnetic waves from being transmitted from external components to the electronic component 12 or may prevent electromagnetic waves from being transmitted from the electronic component 12 to external components.

[0051] Figure 2F A cross-sectional view of the semiconductor device 10 in a later manufacturing stage is shown. In Figure 2F In the illustrated example, another shielding layer 152 may be formed on the shielding layer 151. In some examples, the shielding layer 152 may be formed on the shielding layer 151 located on the package 14, the shielding layer 151 in the via hole 17, and the shielding layer 151 on the recess 18. In some examples, the shielding layer 152 may fill the recess 18. In some examples, the shielding layer 152 may also be formed on the ridge 1512 and the ridge protrusion 1511. In some examples, the shielding layer 152 may be formed by electroplating, spraying, or sputtering silver or nickel on the shielding layer 151. The thickness of the shielding layer 152 may be in the range of about 10 μm to about 20 μm. The shielding layer 152 may prevent the shielding layer 151 from being oxidized or corroded.

[0052] Figure 2G A cross-sectional view of the semiconductor device 10 in a later manufacturing stage is shown. In Figure 2GIn the illustrated example, the carrier 16 can be removed from the substrate 11, and the respective semiconductor devices 10 can be cut and separated from each other. In some examples, to remove the carrier 16, heat or light can be applied to reduce the adhesion between the carrier 16 and the substrate 11. In some examples, a physical force can be used to peel the carrier 16 from the substrate 11. The paddle bottom pad 1111b and the interconnect terminal bottom pad 1112b (see Figure 1B ) can be formed on the bottom side of the paddle 1111 and the bottom side of the interconnect terminal 1112 of the substrate 11, respectively. In some examples, the bottom pads 1111b and 1112b can include tin (Sn), Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. The cutting separation can be performed by vertically sawing the shield 15 and the substrate 11 using an impeller or a laser beam. In some examples, the cutting separation can be performed along the thickest region in the shield layers 151 and 152. In some examples, the cutting separation can be performed by sawing the shield layers 151 and 152 located between the opposing ridges 1512 and sawing the substrate 11 corresponding to the shield layers 151 and 152 located between the ridges 1512. After the cutting separation, the side surfaces of the shield layer 152, the side surfaces of the shield layer 151, and the side surface of the substrate 11 can be coplanar. Here, the ridge protrusion 1511 can be positioned between the shield layer 152 and the package 14 or the substrate 11.

[0053] As described above, since the top side and the side surfaces of the package 14 can be covered by the shield layer 151 or 152, the electromagnetic interference (EMI) shielding efficiency of the semiconductor device 10 can be improved. Since the shield layer 151 made of a metal such as copper having excellent electrical conductivity is covered by the shield layer 152 made of a metal such as nickel having excellent oxidation resistance and corrosion resistance, oxidation and corrosion of the shield layer 151 can be prevented or reduced. Since the shield layers 151 and 152 are electrically connected to the shield terminals 1114a or 1114b through at least one of the shield interconnects 155A or 155B, the EMI shielding efficiency of the semiconductor device 10 can be improved.

[0054] In some examples, a method for fabricating a semiconductor device 10 may include: providing a substrate 11 including a dielectric structure 112 and a conductive structure 111 having a top side and a shield terminal 1114a or 1114b on the top side of the conductive structure 111; providing an electronic component 12 on the top side of the conductive structure 111. The method may include providing a package 14 on the top side of the conductive structure 111 and contacting one side of the electronic component 12. In some examples, the method may include: providing a via 17 in the package 14 from the top side of the package 14 to the shield terminal 1114a or 1114b; and providing a shield 15 on the top side and the side surface of the package 14.

[0055] In some examples, the shield 15 may include a shield interconnect 155A or 155B in the via 17 connecting the shield 15 to the shield terminal 1114a or 1114b of the conductive structure 111. In some examples, the method may include providing a via 17 in the package 14 to expose the shield terminal 1114a or 1114b before providing the shield 15 on the top side and the side surface of the package 14.

[0056] In some examples, the method may include providing a seed layer 19 on the package 14 before providing the shield 15 on the top side and the side surface of the package 14. In some examples, the operation of providing the shield 15 may include providing a first shield layer 151 on the top side and the side surface of the package 14. The operation of providing the shield 15 may further include providing a second shield layer 152 on the first shield layer 151. In some examples, the method may further include providing a groove in the package 14 at the side of the package 14. In some examples, the package 14 may be exposed under the shield 15 at the side of the package 14.

[0057] Figure 3A and 3B respectively show a perspective view and a top view of a shield interconnect of an example semiconductor device 10. In Figure 3A and 3BIn the illustrated example, the shielding interconnects 155A or 155B can electrically connect the shielding layers 151 and 152 to the shielding terminals 1114a or 1114b. The support bars 1113 can extend diagonally from the four corners of the paddle 1111 and can include dividing bars 1113a and 1113b that are separated in two directions at the ends of the support bars 1113. In some examples, the shielding interconnect 155A can be formed at the intersections of the support bars 1113 with the dividing bars 1113a and 1113b. Since four support bars 1113 are provided, the shielding interconnect 155A can include four shielding interconnects. Since the support bars 1113 can be grounded through the paddle 1111, the shielding layers 151 and 152 can also be grounded to improve the EMI shielding efficiency of the semiconductor device 10. The shielding interconnect 155B can be formed on the grounded paddle 1111 to improve the EMI shielding efficiency of the semiconductor device 10. In some examples, the shielding interconnect 155B can be formed at the four corners of the paddle 1111 adjacent to the support bars 1113. Since the paddle 1111 has four corners, the shielding interconnect 155B can also be provided with four shielding interconnects. In some examples, the shielding interconnect 155B can also be formed on the grounded interconnect terminal 1112. In some examples, the shielding interconnect 155A can be formed in the support bar 1113, and the shielding interconnect 155B can be formed in the grounded paddle 1111 or the interconnect terminal 1112. As described above, a plurality of shielding interconnects 155A or 155B can be formed at multiple positions according to the design of the substrate 11, and the shield 15 can be grounded to improve the EMI shielding efficiency of the semiconductor device 10 due to the shield 15. In some examples, the conductive structure 111 includes a support bar 1113 having dividing bars 1113a or 1113b, and the first shielding terminal 1114a or 1114b is on the dividing bar 1113a or 1113b or on the support bar 1113 at the junction of the dividing bars 1113a and 1113b.

[0058] Figure 4A A perspective view of an example semiconductor device 20 is shown, and Figure 4B and 4C cross-sectional views taken along lines 4A-4A and 4B-4B, respectively, are shown. In Figure 4A the examples shown in Figure 4A , 4B and 4C, the semiconductor device 20 can include a substrate 11, electronic components 12, component interconnects 13, a package 14, and a shield 25. The features or elements of the semiconductor device 20 can be similar to the corresponding features or elements of other semiconductor devices described in the present disclosure, such as the semiconductor device 10 ( Figures 1A - 3B) features or elements. The semiconductor device 20 includes a shield 25 having a shield layer 251, a ridge protrusion 2511, a ridge 2512, and a shield interconnect 255, and the shield interconnect 255 can electrically connect the ridge protrusion 2511 to the substrate 11, the shield terminal 1114a, or the support bar 1113.

[0059] Figures 5A to 5D A cross-sectional view showing an example method for manufacturing an example semiconductor device 20 is shown. Figures 5A to 5D Corresponding to a cross-sectional view taken along Figure 4A line 4B-4B. Figure 5A A cross-sectional view of the semiconductor device 20 in a later manufacturing stage is shown. Here, the operations before the operation shown in Figure 5A can be similar to the operations shown in Figure 2A shown.

[0060] In Figure 5A the illustrated example, a groove 27 can be formed in the package 14. In some examples, the groove 27 can be similar to the groove 18. The groove 27 can include or can be referred to as a trench or a channel. The groove 27 can be formed by a laser beam, mechanical drilling, a blade wheel, or chemical etching. In some examples, the groove 27 can be formed in a region corresponding to the support bar 1113 or a region to be cut and separated in a subsequent process. Each groove in the groove 27 can have a side 27a and a bottom side 27b. The side 27a of each groove 27 can be substantially perpendicular to the longitudinal direction of the substrate 11, and the bottom side 27b of each groove 27 can be substantially parallel to the longitudinal direction of the substrate 11. In some examples, the region of the package 14 can still be below the bottom side 27b of the groove 27. The thickness of the region of the package 14 can be in the range of about 50 μm to about 150 μm. The width of the groove 27 (bottom side 27b) can be in the range of about 100 μm to about 700 μm. The side 27a and the bottom side 27b of the groove 27 can provide a potential region for forming the shield 25 in a subsequent process.

[0061] Figure 5B A cross-sectional view of the semiconductor device 20 in a later manufacturing stage is shown. In Figure 5BIn the illustrated example, the via hole 28 may be formed in the package 14. In some examples, the via hole 28 may be formed in the bottom side 27b of the recess 27 in the package 14. The via hole 28 may include or may be referred to as an opening or a through hole. The via hole 28 may be formed by a laser beam, mechanical drilling, or chemical etching. In some examples, the diameter of the via hole 28 may be the largest at the top end and may gradually decrease in diameter downward. The height of the via hole 28 may be in the range of about 50 μm to about 150 μm or the diameter may be in the range of about 50 μm to about 100 μm. The via hole 28 may pass through the package 14 to expose the shield terminal 1114a.

[0062] Figure 5C A cross-sectional view of the semiconductor device 20 in a later manufacturing stage is shown. In Figure 5C In the illustrated example, the shielding layer 251 may be formed on the package 14. In some examples, the shielding layer 251 may be formed on the package 14, the recess 27 in the package 14, and the via hole 28 in the package 14. The shielding layer 251 may also be formed on the shield terminal 1114a exposed by the via hole 28. The shielding layer 251 filling the via hole 28 may be defined as the shielding interconnect 255. In some examples, the shielding layer 251 may be made of a metal or a conductive paste material, such as epoxy resin filled with silver or copper. In some examples, the shielding layer 251 may be made of copper, nickel, silver, or stainless steel. In some examples, the shielding layer 251 may be formed using spraying, jet dispensing, electroplating, electroless plating, or sputtering. In some examples, before forming the shielding layer 251, a decontamination may be performed to increase the adhesion to the shielding layer 251 by removing epoxy resin stains or increasing roughness that may be present inside the recess 27 or the via hole 28. The thickness of the shielding layer 251 may be in the range of about 1 μm to about 20 μm, the height of the shielding interconnect 255 may be in the range of about 50 μm to about 150 μm, and the diameter may be in the range of about 50 μm to about 100 μm.

[0063] Figure 5D A cross-sectional view of the semiconductor device 20 in a later manufacturing stage is shown. In Figure 5DIn the illustrated example, the carrier 16 is removed from the substrate 11, and the individual semiconductor devices 20 can be cut and separated from each other. The cut separation can be performed by vertically sawing the shield 251 and the substrate 11 using an impeller or a laser beam. In some examples, the cut separation can be performed along the outer region of the shield interconnect 255 in the shield layer 251. In some examples, the cut separation can be performed by sawing the shield layer 251 located between the opposing ridges 2512 and sawing the substrate 11 corresponding to the shield layer 251 located between the ridges 2512. The ridge protrusion 2511 of the shield layer 251 on the bottom side 27b of the groove 27 can protrude laterally further than the ridge 2512 of the shield layer 251 on the side 27a of the groove 27. The width of the ridge protrusion 2511 can be in the range of approximately 100 μm to approximately 200 μm to allow for stable positioning of the shield interconnect 255.

[0064] As described above, the shield interconnect 255 of the shield 25 can electrically connect the shield layer 251 to the shield terminal 114a. Since the support bars 1113 can extend diagonally from the four corners of the paddle 1111, four shield interconnects 255 can also be formed at the shield terminals 114a corresponding to the support bars 1113. In some examples, the support bars 1113 and the shield 25 can be grounded through the paddle 1111 to improve the EMI shielding efficiency of the semiconductor device 20.

[0065] Figure 6A A perspective view of an example semiconductor device 30 is shown, and Figure 6B and 6C show cross-sectional views taken along lines Figure 6A 6A-6A and 6B-6B, respectively. In the examples shown in Figure 6A , 6B and 6C, the semiconductor device 30 can include a substrate 11, electronic components 12, component interconnects 13, a package 14, and a shield 35. The features or elements of the semiconductor device 30 can be similar to the corresponding features or elements of other semiconductor devices described in this disclosure, such as the features or elements of the semiconductor device 20 ( Figures 4A - 5D ). The semiconductor device 30 includes a shield 35 having shield layers 151 and 152, ridge protrusions 1511, ridges 1512, and shield interconnects 355, and the shield interconnects 355 can electrically connect the ridge protrusions 1511 to the substrate 11, the shield terminal 1114a, or the support bars 1113.

[0066] Figures 7A to 7D A cross-sectional view of an example method for manufacturing the example semiconductor device 30 is shown. Figures 7A to 7D Corresponds to the cross-sectional view taken along line Figure 6A 6B-6B. Figure 7AA cross-sectional view of a semiconductor device 30 in a late manufacturing stage is shown. Here, before the operation shown in Figure 7A The operations can be similar to those shown in Figure 5A and 5B The operations shown.

[0067] In Figure 7A the example shown, a seed layer 19 can be formed on the package 14. In some examples, the seed layer 19 can be formed on the package 14, on the grooves 27 located in the package 14, and on the vias 28 located in the package 14. The seed layer 19 can also be formed on the region of the shield terminal 1114a exposed through the via 28. The seed layer 19 can be made of a metal. For example, the seed layer 19 can be made of titanium, titanium tungsten, or copper. In some examples, the seed layer 19 can be formed by electroless plating or by sputtering. In some examples, before forming the seed layer 19, decontamination can be performed to improve the adhesion to the seed layer 19 by removing epoxy resin stains that may be present inside the grooves 27 or vias 28 or by increasing the roughness. The thickness of the seed layer 19 can be in the range of about 1 μm to about 3 μm.

[0068] Figure 7B A cross-sectional view of a semiconductor device 30 in a late manufacturing stage is shown. In Figure 7B the example shown, a shielding layer 151 can be formed on the seed layer 19. In some examples, the shielding layer 151 can be formed on the seed layer 19 of the package 14, on the seed layer 19 located on the grooves 27, and on the seed layer 19 located on the vias 28. In some examples, the shielding layer 151 can fill the via 28. The shielding layer 151 filling the via 28 can be electrically connected to the shield terminal 1114a through the seed layer 19. The shielding layer 151 filling the via 28 can be defined as a shield interconnect 355. In some examples, the region of the shielding layer 151 located on the area corresponding to each side 27a of the grooves 27 in the grooves 27 can be defined as a ridge 1512, and the region of the shielding layer 151 located on the area corresponding to the bottom side 27b of each groove 27 in the grooves 27 can be defined as a ridge protrusion 1511. In some examples, the shielding layer 151 can be formed by electroplating aluminum or copper on the seed layer 19. The thickness of the shielding layer 151 can be in the range of about 10 μm to about 20 μm. The shielding layer 151 can prevent electromagnetic waves from being transmitted from external components to the electronic components 12 or can prevent electromagnetic waves from being transmitted from the electronic components 12 to external components.

[0069] Figure 7C A cross-sectional view of a semiconductor device 30 in a late manufacturing stage is shown. In Figure 7CIn the illustrated example, the shielding layer 152 may be formed on the shielding layer 151. In some examples, the shielding layer 152 may be formed on the shielding layer 151 located on the package 14, the shielding layer 151 located on the groove 27, and the shielding layer 151 filling the vias 28. In some examples, the shielding layer 152 may fill the groove 27. In some examples, the shielding layer 152 may also be formed on the ridges 1512 and the ridge protrusions 1511. In some examples, the shielding layer 152 may be formed by electroplating silver or nickel on the shielding layer 151. The thickness of the shielding layer 152 may be in the range of about 10 μm to about 20 μm. The shielding layer 152 may prevent the shielding layer 151 from being oxidized or corroded.

[0070] Figure 7D A cross-sectional view of the semiconductor device 30 in a later manufacturing stage is shown. In Figure 7D the illustrated example, the carrier 16 is removed from the substrate 11, and the individual semiconductor devices 30 may be singulated from each other. Singulation may be performed by using a dicing blade or a laser beam to cut the shielding layers 151 and 152 and the substrate 11. In some examples, singulation may be performed along the thickest region of the outer area of the shielding interconnect 355 of the shielding layers 151 and 152. In some examples, singulation may be performed by cutting the shielding layers 151 and 152 located between the opposing ridges 1512 and cutting the substrate 11 corresponding to the shielding layers 151 and 152 located between the ridges 1512. After singulation, the sides of the shielding layer 151, the sides of the shielding layer 152, and the sides of the substrate 11 may be coplanar.

[0071] Figure 8A and 8B perspective and top views of the shielding interconnect of the semiconductor device 30 are shown, respectively. In Figure 8A and 8B the illustrated example, the shielding interconnect 355 may electrically connect the shielding layers 151 and 152 to the shielding terminal 1114a. The shielding interconnect 355 connected to the support bar 1113 may include at least one or more shielding interconnects. Since the support bar 1113 may extend diagonally from the four corners of the paddle 1111, the shielding interconnect 355 may also be provided with four shielding interconnects in the regions corresponding to the support bar 1113. In some examples, the support bar 1113 may include dividing bars 1113a and 1113b that are separated in two directions at the ends of the support bar 1113. The shielding interconnects 355a and 355b may be formed in the dividing bars 1113a and 1113b, respectively. In some examples, since the support bar 1113 may be grounded through the paddle 1111, the shield 35 may also be grounded to improve the EMI shielding efficiency of the semiconductor device 30.

[0072] Figure 9AA perspective view of an exemplary semiconductor device 40 is shown, and Figure 9B and Figure 9C show cross-sectional views taken along lines 9A-9A, 9B-9B of Figure 9A respectively. In the examples shown in Figure 9A , 9B and 9C, the semiconductor device 40 may include a substrate 11, electronic components 12, component interconnects 13, a package 14, and a shield 45. The features or elements of the semiconductor device 40 may be similar to the corresponding features or elements of other semiconductor devices described in this disclosure. The semiconductor device 40 may include a shield 45 having a shield layer 251, ridge protrusions 2511, or ridges 2512. Shield interconnects 455A, 455B, or 455C may electrically connect the shield 45 to ground or shield terminals 1114a, 1114b, or 1114c of the substrate 11. In some examples, the shield terminal 1114a may be on a support bar 1113 or may be part of the support bar, the shield terminal 1114b may be on a paddle 1111 or may be part of the paddle, or the shield terminal 1114c may be on an interconnect terminal 1112 or may be part of the interconnect terminal. In some examples, the shield interconnects 455A, 455B, or 455C may include or define vias in the package 14.

[0073] Figures 10A to 10D A cross-sectional view of an exemplary method for manufacturing the exemplary semiconductor device 40 is shown. Figure 10A A cross-sectional view of the semiconductor device 40 in an early manufacturing stage is shown.

[0074] Figure 10AShows a shield interconnect 455 that couples a shield 45 to a substrate 11. In some instances, the shield interconnect 455 may be formed between a shield terminal 1114a of a support bar 1113 and a shield terminal 1114b of a paddle 1111. The shield interconnect 455 may include or may be referred to as a wire or bond wire. The shield interconnect 455 may include gold, silver, copper, or aluminum. In some instances, a first end of the shield interconnect 455 may be ball bonded to the shield terminal 1114a, and a second end of the shield interconnect 455 may be stitch bonded to the shield terminal 1114a, such that the loop height of the shield interconnect 455 may be maximum adjacent to the shield terminal 1114a. In some instances, a first end of the shield interconnect 455 may be ball bonded to the shield terminal 1114b, and a second end of the shield interconnect 455 may be stitch bonded to the shield terminal 1114a, such that the loop height of the shield interconnect 455 may be maximum adjacent to the shield terminal 1114b. The loop height of the shield interconnect 455 may be in the range of about 50 μm to about 300 μm and the diameter may be in the range of about 10 μm to about 50 μm. The shield interconnect 455 may be separated into two shield interconnects 455A and 455B in a subsequent process and may be electrically connected to a shield layer 251, respectively. After forming the shield interconnect 455, the electronic component 12 and the shield interconnect 455 may be covered by a package 14.

[0075] Figure 10B Shows a cross-sectional view of a semiconductor device 40 in a later manufacturing stage. In Figure 10BIn the illustrated example, the groove 27 can be formed in the package 14. The groove 27 can include or can be referred to as a trench or a channel. The groove 27 can be formed by a laser beam, mechanical drilling, or chemical etching. In some examples, the groove 27 can be formed in a region corresponding to the shield interconnect 455 or in a region to be cut and separated in a subsequent process. Thus, the shield interconnect 455 can be separated into corresponding shield interconnects 455A, 455B, or 455C. Each groove in the groove 27 can have a side 27a and a bottom side 27b. The edge of the shield interconnect 455A can be exposed through the bottom side 27b of the groove 27, and the edge of the shield interconnect 455B can be exposed through the side 27a of the groove 27. In some examples, the shield interconnect 455A can define a via hole in the package 14 by extending from the top side of the package 14 (at the bottom side 27b of the groove 27) to the shield terminal 1114a or 1114c. The side 27a of each groove 27 can be substantially perpendicular to the top side of the substrate 11, and the bottom side 27b of each groove 27 can be substantially parallel to the top side of the substrate 11. The region of the package 14 can still be below the bottom side 27b of the groove 27. The thickness of the region of the package 14 that is still below the bottom side 27b of the groove 27 can be in the range of about 50 μm to about 150 μm. The width of the groove 27 (bottom side 27b) can be in the range of about 100 μm to about 700 μm. The side 27a and the bottom side 27b of the groove 27 can provide a potential region for forming the shield 45 in a subsequent process.

[0076] Figure 10C A cross-sectional view of a semiconductor device 40 in a later manufacturing stage is shown. In Figure 10C In the illustrated example, the shield layer 251 can be formed on the package 14. In some examples, the shield layer 251 can be formed on the package 14 and on the groove 27 located in the package 14. The shield layer 251 can be electrically connected to the edge of the shield interconnect 455A exposed through the bottom side 27b of the groove 27 and can be electrically connected to the edge of the shield interconnect 455B exposed through the side 27a of the groove 27. The shield layer 251 can be made of a metal or a conductive paste material, such as epoxy resin filled with silver or copper. In some examples, the shield layer 251 can be made of copper, nickel, silver, or stainless steel. In some examples, before forming the shield layer 251, a decontamination can be performed to improve the adhesion to the shield layer 251 by removing epoxy resin stains that may be present inside the groove 27 or increasing the roughness. The thickness of the shield layer 251 can be in the range of about 1 μm to about 20 μm.

[0077] Figure 10D A cross-sectional view of a semiconductor device 40 in a later manufacturing stage is shown. In Figure 10DIn the illustrated example, the carrier 16 is removed, and the individual semiconductor devices 40 can be cut and separated from each other. The cutting separation can be performed by vertically sawing the shield 251 and the substrate 11 using a blade wheel or a laser beam. In some examples, the cutting separation can be performed by sawing the shield layer 251 located between the opposing ridges 2512 and sawing the substrate 11 corresponding to the shield layer 251 located between the ridges 2512.

[0078] As described above, the shield interconnect 455A can electrically connect the shield layer 251 to the shield terminal 1114a, and the shield interconnect 455B can electrically connect the shield layer 251 to the shield terminal 1114b. Since the shield terminal 1114b at the paddle 1111 and the shield terminal 1114a at the support bar 1113 can be grounded, the shield 45 can also be grounded to improve the EMI shielding efficiency of the semiconductor device 40.

[0079] Figure 11A and 11B respectively show a perspective view and a top view of the shield interconnect of the example semiconductor device 40. In Figure 11A and 11B In the illustrated example, as described above, the shield interconnect 455 can electrically connect the shield layer 251 to the paddle 1111 and the support bar 1113. The shield interconnect 455 connected to the paddle 1111 and the support bar 1113 can be provided with at least one or more shield interconnects. Since the support bar 1113 can extend diagonally from the four corners of the paddle 1111, four shield interconnects 455 can also be formed in the regions corresponding to the support bar 1113. In some examples, the first-end shield interconnect 455 can be connected between the partition bar 1113a and the paddle 1111, and the second-end shield interconnect 455 can be connected between the partition bar 1113b and the paddle 1111. In some examples, the support bar 1113 can be grounded through the paddle 1111, and the shield 45 can also be grounded to improve the EMI shielding efficiency of the semiconductor device 40.

[0080] Figures 12A - 12B shows a cross-sectional view of an example semiconductor device 50. The features or elements of the semiconductor device 50 can be similar to the corresponding features or elements of other semiconductor devices described in the present disclosure. For example, in terms of structure or formation, the semiconductor device 50 can be similar to the semiconductor device 40 ( Figures 9A - 11B ), Figure 12A The view of Figure 9B can correspond to Figure 12B Aspects of Figure 9C And

[0081] The semiconductor device 50 may include a substrate 11, electronic components 12, electronic components 52, component interconnects 13, a package 14, and a shield 55. The shield 55 may include a shield layer 251, ridge protrusions 2511, ridges 2512, shield interconnects 455A and 455B, and the shield interconnects 455A and 455B may electrically connect the ridge protrusions 2511 to the shield terminals 1114a of the substrate 11.

[0082] The semiconductor device 50 may be partitioned, where a compartment 58 contains one or more components, such as the electronic components 12, and where a compartment 59 contains one or more components, such as the electronic components 52. In some instances, the shield 55 may be similar to the shield 45 or other shields described herein.

[0083] The compartments 58 and 59 may be defined by a shield wall 56 or be substantially EMI shielded from each other by the shield wall. The shield wall 56 may be positioned between the compartments 58 and 59 and between the electronic components 12 and 52 and may contact the shield 55 or extend from the shield toward the substrate 11. In some instances, the shield wall 56 may extend adjacent to the substrate 11, but there may still be a gap between the bottom of the shield wall 56 and the substrate 11. In some instances, such a gap may be filled by the package 14. In some instances, the height of the gap between the bottom of the shield wall 56 and the substrate 11 may be less than half or less than a quarter of the height of the electronic components 12 or 52 above the substrate 11. In some instances, the height of the gap may be at least 150 micrometers. In some instances, the bottom of the shield wall 56 may reach or be coupled to the substrate 11.

[0084] In some instances, the formation or material of the shield wall 56 may be similar to any of the formation or material options described with respect to any of the shield layers disclosed herein, such as the shield layer 251. In some instances, a groove 57 may be defined or formed in the package 14, similar to the previously described grooves 18 or 27. The shield wall 56 may be filled into the groove 57 such that the top of the shield wall 56 remains exposed from the package 14 and is contacted by the subsequently applied shield 55. As an example, the shield wall 56 may be applied as a conductive paste into the groove 57, and the shield 55 may be applied over the package 14 and the top of the shield wall 56 by spraying, sputtering, plating, or otherwise.

[0085] Figures 13A - 13B A cross-sectional view of an example semiconductor device 60 is shown. The features or elements of the semiconductor device 60 may be similar to the corresponding features or elements of other semiconductor devices described in this disclosure. For example, in terms of structure or formation, the semiconductor device 60 may be similar to the semiconductor device 50 ( Figures 12A - 12B ) or the semiconductor device 20 (Figures 4A - 5D ) Figure 13A The view of Figure 4B or Figure 12A can correspond to aspects of Figure 13B and the view of Figure 4C or aspects of 12B.

[0086] The semiconductor device 60 may include a substrate 11, electronic components 12, electronic components 52, component interconnects 13, a package 14, and a shield 65. The shield 65 may include a shield layer 251, ridge protrusions 2511, ridges 2512, and shield interconnects 255, and the shield interconnects 255 may electrically connect the ridge protrusions 2511 to a shield terminal 1114a of the substrate 11.

[0087] The semiconductor device 60 may be partitioned such that a compartment 58 contains one or more components, such as the electronic components 12, and a compartment 59 contains one or more components, such as the electronic components 52. In some instances, the shield 65 may be similar to the shield 45 or other shields described herein.

[0088] The compartments 58 and 59 may be defined by a shield wall 56 or be substantially EMI shielded from each other by the shield wall. The shield wall 56 may be positioned between the compartments 58 and 59 and between the electronic components 12 and 52 and may contact the shield 65 or extend from the shield toward the substrate 11. In some instances, the shield wall 56 may extend adjacent to the substrate 11, but there may still be a gap between the bottom of the shield wall 56 and the substrate 11. In some instances, such a gap may be filled by the package 14. In some instances, the height of the gap between the bottom of the shield wall 56 and the substrate 11 may be less than half or less than a quarter of the height of the electronic components 12 or 52 above the substrate 11. In some instances, the height of the gap may be at least 150 micrometers. In some instances, the bottom of the shield wall 56 may reach or be coupled to the substrate 11.

[0089] In some instances, the formation or material of the shield wall 56 may be similar to any of the formation or material options described with respect to any of the shield layers disclosed herein, such as the shield layer 251. In some instances, a groove 57 may be defined or formed in the package 14, similar to the previously described grooves 18 or 27. The shield wall 56 may be filled into the groove 57 such that the top of the shield wall 56 remains exposed from the package 14 and is contacted by a subsequently applied shield 55. As an example, the shield wall 56 may be applied as a conductive paste into the groove 57, and the shield 55 may be applied by spraying, sputtering, plating, or otherwise over the package 14 and the top of the shield wall 56.

[0090] In some examples, the semiconductor device 60 can be a semiconductor structure including a substrate 11 that includes a dielectric structure 112 and a conductive structure 111. The conductive structure 111 can have a top side, paddles 1111, and a shield terminal 1114a on the top side of the conductive structure 111. The semiconductor device 60 can include a first electronic component 12 on the paddles 1111 on the top side of the conductive structure 111 and a second electronic component 52 on the paddles 1111 on the top side of the conductive structure 111. In some examples, an encapsulation body 14 can be on the top side of the conductive structure 111 and contact one side of the first electronic component 12 and one side of the second electronic component 52.

[0091] The semiconductor device 60 can include a shield 65 on the top side of the encapsulation body 14 and on a side surface of the encapsulation body 14 and a shield wall 56 between the first electronic component 12 and the second electronic component 52 and in contact with the shield 65. The semiconductor device 60 can further include a shield interconnect 255 that couples the shield 65 to the shield terminal 1114a of the conductive structure 111. In some examples, the shield wall 56 defines a first compartment 58 that contains the first electronic device 12 but does not contain the second electronic device 52 and a second compartment 59 that contains the second electronic device 52 but does not contain the first electronic device 12. In some examples, the shield interconnect 255 includes a wire 13.

[0092] This disclosure includes references to certain examples. However, those skilled in the art will understand that various changes can be made and equivalents can be substituted without departing from the scope of this disclosure. Additionally, the disclosed examples can be modified without departing from the scope of this disclosure. Therefore, this disclosure is intended to cover not limited to the disclosed examples, but rather this disclosure will include all examples that fall within the scope of the appended claims.

Claims

1. A semiconductor structure, which comprises: a substrate, the substrate comprising a conductive structure having a top side and a first shielding terminal on the top side of the conductive structure; an electronic component on the top side of the conductive structure; a package on the top side of the conductive structure and contacting one side of the electronic component; a shield on the top side and the side surface of the package; and a shielding interconnect coupling the shield to the first shielding terminal of the conductive structure; wherein the conductive structure includes a horizontally extending tie bar having a horizontal width and a vertical height, the horizontal width being greater than the vertical height; and the first shielding terminal is on the horizontally extending tie bar; and wherein: the conductive structure includes a die pad adjacent to the electronic component; the first shielding terminal is on one of the tie bar or the lead of the conductive structure; a second shielding terminal is on the die pad; and the shielding interconnect is coupled to the first shielding terminal, the second shielding terminal, and the shield.

2. The semiconductor structure according to claim 1, wherein the shield includes a first shielding layer and a second shielding layer on the first shielding layer.

3. The semiconductor structure according to claim 1, which further includes a dielectric structure coupled to the conductive structure.

4. The semiconductor structure according to claim 3, wherein the dielectric structure includes a part of the package as a continuous material.

5. The semiconductor structure according to claim 3, wherein the dielectric structure is separate from the package.

6. The semiconductor structure according to claim 1, wherein the shield contacts a groove in the package at the side of the package.

7. The semiconductor structure according to claim 2, wherein the first shielding layer includes ridges and ridge protrusions at the side of the package, and the second shielding layer is on the ridge protrusions at the side of the package.

8. The semiconductor structure according to claim 1, wherein the conductive structure includes a tie bar having a separating bar, and the first shielding terminal is on the separating bar.

9. The semiconductor structure according to claim 1, wherein the shielding interconnect includes a wiring.

10. A method, which comprises: providing a substrate including a dielectric structure and a conductive structure, the conductive structure having a top side and a shielding terminal on the top side of the conductive structure; providing an electronic component on the top side of the conductive structure; providing a package on the top side of the conductive structure and contacting one side of the electronic component; providing a via hole in the package, the via hole being from the top side of the package to the shielding terminal; and providing a shield on the top side and the side surface of the package, wherein the shield includes a shielding interconnect in the via hole connecting the shield to the shielding terminal of the conductive structure; and at least one of the following: (a) Expose the shielding terminal from the package body before providing the shielding member on the top side of the package body and the side surface of the package body; Or (b) Provide a groove in the package body at the side surface of the package body, wherein the groove includes the side surface and the bottom side of the package body.

11. The method according to claim 10, further comprising providing a via hole in the package body to expose the shielding terminal from the package body before providing the shielding member on the top side of the package body and the side surface of the package body.

12. The method according to claim 10, further comprising providing a seed layer on the package body before providing the shielding member on the top side of the package body and the side surface of the package body.

13. The method according to claim 10, wherein providing the shielding member includes providing a first shielding layer on the top side of the package body and the side surface of the package body and providing a second shielding layer on the first shielding layer.

14. The method according to claim 13, further comprising providing a groove in the package body at the side surface of the package body, wherein the package body is exposed below the shielding member at the side surface of the package body, and wherein the groove includes the side surface and the bottom side of the package body.

15. A semiconductor structure, which Comprises: A substrate, the substrate includes a dielectric structure and a conductive structure, the conductive structure has a top side, a die pad, and a first shielding terminal on the top side of the conductive structure; A first electronic component on the top side of the conductive structure on the die pad, and a second electronic component on the top side of the conductive structure on the die pad; A package body on the top side of the conductive structure and contacting one side of the first electronic component and one side of the second electronic component; A shielding member on the top side of the package body and the side surface of the package body; A shielding wall between the first electronic component and the second electronic component and contacting the package body and the shielding member; And A shielding interconnect that couples the shielding member to the first shielding terminal of the conductive structure; and Wherein the conductive structure includes a horizontally extending tie bar, the horizontally extending tie bar has a horizontal width and a vertical height, the horizontal width is greater than the vertical height; and the first shielding terminal is on the horizontally extending tie bar; and Wherein: The first shielding terminal is on one of the tie bar or the lead of the conductive structure; A second shielding terminal is on the die pad; And The shielding interconnect is coupled to the first shielding terminal, the second shielding terminal, and the shielding member.

16. The semiconductor structure according to claim 15, wherein the shielding wall defines a first compartment containing the first electronic component but not the second electronic component and a second compartment containing the second electronic component but not the first electronic component.

17. The semiconductor structure according to claim 15, wherein the shielding interconnect includes a wiring.

18. The semiconductor structure according to claim 15, wherein the shielding interconnect includes a via structure.

19. The semiconductor structure according to claim 15, wherein the horizontally extending tie bar has a dividing bar that extends at an angle with respect to the horizontally extending tie bar, and the first shielding terminal is on the dividing bar.

20. The semiconductor structure according to claim 15, wherein the horizontally extending tie bar has a first dividing bar and a second dividing bar, wherein the first shielding terminal is on the first dividing bar and the second shielding terminal is on the second dividing bar, and wherein the shielding interconnect includes a first wiring coupled to the first shielding terminal and a second wiring coupled to the second shielding terminal.

21. The semiconductor structure according to claim 15, wherein the package includes a groove, and the shielding wall is in the groove.

22. The semiconductor structure according to claim 21, wherein the shielding wall completely fills the groove.

23. The semiconductor structure according to claim 15, wherein the package extends below the shielding wall.

24. A method of manufacturing a semiconductor structure, comprising: providing a substrate including a dielectric structure and a conductive structure, the conductive structure having a top side, a die pad, and a first shielding terminal on the top side of the conductive structure; providing a first electronic component on the top side of the conductive structure on the die pad, and providing a second electronic component on the top side of the conductive structure on the die pad; providing a package on the top side of the conductive structure and contacting one side of the first electronic component and one side of the second electronic component; providing a shielding wall between the first electronic component and the second electronic component and contacting the package; providing a shield on the top side and a side surface of the package and contacting the shielding wall; and providing a shielding interconnect that couples the shield to the shielding terminal of the conductive structure; wherein the conductive structure includes a horizontally extending tie bar having a horizontal width and a vertical height, the horizontal width being greater than the vertical height; and the first shielding terminal is on the horizontally extending tie bar; and wherein: the conductive structure includes the die pad adjacent to the first electronic component; the first shielding terminal is on one of a tie bar or a lead of the conductive structure; a second shielding terminal is on the die pad; and the shielding interconnect is coupled to the first shielding terminal, the second shielding terminal, and the shield.

25. The method according to claim 24, wherein the shielding wall defines a first compartment containing the first electronic component but not the second electronic component and a second compartment containing the second electronic component but not the first electronic component.

26. The method according to claim 24, comprising: providing a groove in the package before providing the shielding wall, and the shielding wall is provided in the groove.

Images