Semiconductor Devices

Abstract

A semiconductor device includes: an active pattern extending in a first direction on a substrate, divided into a plurality of regions by a separation region, and having a first edge portion exposed toward the separation region; a first channel layer, a second channel layer, and a third channel layer, which are vertically separated and sequentially arranged on the active pattern; a first gate electrode extending in a second direction, intersecting the active pattern, and surrounding the first channel layer, the second channel layer, and the third channel layer; a source / drain region, which is arranged on the active pattern, at least on one side of the first gate electrode, and contacts the first channel layer, the second channel layer, and the third channel layer; a semiconductor structure, including a first semiconductor layer and a second semiconductor layer alternately stacked on the active pattern, and having a second edge portion exposed toward the separation region; and a barrier layer covering at least one of an upper surface, a side surface, and a second edge portion of the semiconductor structure.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor device. Background Art

[0002] As the demand for high performance, high speed and / or multi-function in semiconductor devices increases, the integration of semiconductor devices also increases. In manufacturing semiconductor devices with fine patterns corresponding to the current trend towards high integration, it is desirable to achieve patterns with fine widths or fine separation distances. In addition, efforts are being made to develop semiconductor devices including fin field effect transistors (FinFETs) with channels having three-dimensional structures to overcome the limitations of operating characteristics caused by the continuous downscaling of planar metal oxide semiconductor field effect transistors (MOSFETs). In addition, in order to overcome the physical scaling and performance limitations of FinFETs, full-surround gate (GAA) transistors are being developed, which are characterized by gates on all four sides of the channel. Summary of the invention

[0003] Example embodiments of the inventive concepts provide semiconductor devices having enhanced reliability.

[0004] According to an example embodiment of the inventive concept, a semiconductor device includes: an active pattern extending in a first direction on a substrate and having a pair of first side surfaces opposite to each other and a first edge portion connected to the first side surface; a plurality of channel layers vertically spaced apart from each other on the active pattern; a first gate electrode extending in a second direction on the substrate while intersecting the active pattern and the plurality of channel layers and surrounding the plurality of channel layers; a source / drain region disposed on the active pattern, at least on one side of the first gate electrode, and in contact with the plurality of channel layers; a semiconductor structure disposed adjacent to the first edge portion of the active pattern and having a pair of second side surfaces opposite to each other and a second edge portion connected to the second side surface, the semiconductor structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on the active pattern; a second gate electrode extending in the second direction on the substrate and covering the first edge portion of the active pattern and the second edge portion of the semiconductor structure; and a barrier layer disposed between the semiconductor structure and the second gate electrode.

[0005] According to an example embodiment of the present invention, a semiconductor device includes: an active pattern extending in a first direction on a substrate, divided into a plurality of regions by a separation region, and having a first edge portion exposed toward the separation region; a first channel layer, a second channel layer, and a third channel layer, which are vertically spaced apart from each other and sequentially disposed on the active pattern; a first gate electrode extending in a second direction on the substrate while intersecting the active pattern and surrounding the first channel layer, the second channel layer, and the third channel layer; a source / drain region disposed on the active pattern, at least on one side of the first gate electrode, and contacting the first channel layer, the second channel layer, and the third channel layer; a semiconductor structure including a first semiconductor layer and a second semiconductor layer alternately stacked on the active pattern and having a second edge portion exposed toward the separation region; and a barrier layer covering at least one of an upper surface, a side surface, and a second edge portion of the semiconductor structure.

[0006] According to an example embodiment of the present invention, a semiconductor device includes: an active pattern extending in a first direction on a substrate and divided into a plurality of regions by a separation region; a semiconductor structure disposed on the active pattern adjacent to the separation region; a first gate electrode extending in a second direction on the substrate while intersecting the active pattern; a second gate electrode extending in the second direction on the substrate while intersecting the semiconductor structure and covering the semiconductor structure; a source / drain region disposed on the active pattern and on at least one side of the first gate electrode; and a barrier layer covering the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects and features of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a top view showing a semiconductor device according to an example embodiment of the inventive concept;

[0009] Figure 2 is a cross-sectional view showing a semiconductor device according to an example embodiment of the inventive concept;

[0010] Figure 3 is a top view showing a semiconductor device according to an example embodiment of the inventive concept;

[0011] Figures 4 to 8 , 9A to 9C and Fig.10 are cross-sectional views each illustrating a semiconductor device according to an example embodiment of the inventive concept; and

[0012] FIG. 11A to FIG. 11B , FIG. 12A to FIG. 12B , FIG. 13A to FIG. 13B , FIG. 14A to FIG. 14D , FIG. 15A to FIG. 15B, FIG. 16A to FIG. 16C , FIG. 17A to FIG. 17B , FIG. 18A to FIG. 18B as well as FIG. 19A to FIG. 19B is a diagram according to a process sequence to describe a method of fabricating a semiconductor device according to an example embodiment of the inventive concept.

[0013] because Figures 1 to 19B The accompanying drawings in the drawings are intended for illustrative purposes, so the elements in the drawings are not necessarily drawn to scale. For example, some of the elements may be enlarged or exaggerated for clarity. DETAILED DESCRIPTION

[0014] Hereinafter, example embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0015] Figure 1 is a top plan view illustrating a semiconductor device according to an example embodiment of the inventive concept.

[0016] Figure 2 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concept.

[0017] Figure 2 Show Figure 1 The cross-sections of the semiconductor device taken along lines II', II-II' and III-III' are shown in FIG. Figure 1 and Figure 2 Only main components of the semiconductor device are shown.

[0018] Figure 3 is a top plan view illustrating a semiconductor device according to an example embodiment of the inventive concept. Figure 3 yes Figure 1 Magnified view of area "A".

[0019] First, refer to Figure 1 and Figure 2, the semiconductor device 100 may include: a substrate 101; an active pattern 105 having a line shape or a strip shape on the substrate 101; a channel structure 140 including a plurality of channel layers 141, 142, and 143 vertically spaced apart from each other on the active pattern 105; a source / drain region 150 in contact with the plurality of channel layers 141, 142, and 143; a first gate structure 160 and a second gate structure 170 extending while intersecting the active pattern 105; and a contact plug 180 connected to the source / drain region 150. The first gate structure 160 may vertically overlap the plurality of channel layers 141, 142, and 143, for example, in the Z direction. The semiconductor device 100 may further include a device isolation layer 110, a semiconductor structure 120, a barrier layer 130, and an interlayer insulating layer 190. The semiconductor structure 120 may include a first semiconductor layer 121 and a second semiconductor layer 122 alternately stacked. The first gate structure 160 includes a first gate dielectric layer 162 , a first gate electrode 165 , a first spacer layer 164 and a first gate capping layer 166 , and the second gate structure 170 includes a second gate dielectric layer 172 , a second gate electrode 175 , a second spacer layer 174 and a second gate capping layer 176 .

[0020] In the semiconductor device 100, the active pattern 105 has a fin structure, and the first gate electrode 165 may be disposed between the active pattern 105 and the channel structure 140, between the plurality of channel layers 141, 142, and 143 of the channel structure 140, and on the channel structure 140. Therefore, the semiconductor device 100 may include a multi-bridge channel field effect transistor (MBCFET) consisting of the channel structure 140, the source / drain region 150, and the first gate structure 160. TM ). The first gate electrode 165 may three-dimensionally surround the plurality of channel layers 141, 142, and 143 of the channel structure 140. Since the first gate electrode 165 may be wrapped around the plurality of channel layers 141, 142, and 143, the semiconductor device 100 may include a gate-all-around (GAA) transistor structure. However, the inventive concept is not limited thereto. For example, the active pattern 105 may have a fin structure and may be a fin field effect transistor (FinFET), which is a transistor in which a channel region of the transistor is formed in a portion of the active pattern 105 intersecting with the gate electrode.

[0021] The substrate 101 may have an upper surface extending in the X direction and the Y direction, and may include a semiconductor material such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may include silicon (Si), germanium (Ge), or silicon germanium (SiGe). Group III-V compound semiconductors may include, for example, gallium phosphide (GaP), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), gallium antimonide (GaSb), indium antimonide (InSb), or indium gallium arsenide (InGaAs). Group II-VI compound semiconductors may include, for example, cadmium selenide (CdSe), cadmium sulfide (CdS), cadmium telluride (CdTe), zinc oxide (ZnO), zinc selenide (ZnSe), zinc sulfide (ZnS), or zinc telluride (ZnTe). The substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon on insulator (SOI) layer, or a semiconductor on insulator (SeOI) layer.

[0022] The active pattern 105 is defined by the device isolation layer 110 formed in the substrate 101, and may be arranged to extend in a first direction (e.g., in the X direction). However, the inventive concept is not limited thereto. For example, the active pattern 105 may be arranged to be an inclined strip extending in directions other than the X direction and the Y direction. The active pattern 105 may have a structure protruding upward from the substrate 101. The upper end of the active pattern 105 may be arranged to protrude from the upper surface (or top surface) of the device isolation layer 110 to a predetermined height. The device isolation layer 110 may not cover the upper portion of the active pattern 105, and may cover the sidewall of the lower portion of the active pattern 105. The active pattern 105 may be divided into a plurality of regions in a first direction (e.g., in the X direction) by a separation region SR, and may include a pair of first side surfaces S1 opposite to each other in a second direction (e.g., in the Y direction) and a first edge portion E1 connected to the first side surface S1 and exposed toward the separation region SR. The separation region SR may separate transistors from each other in a first direction (e.g., in the X direction). The active pattern 105 may be formed of a portion of the substrate 101 or may include an epitaxial layer grown from the substrate 101. The active pattern 105 formed on the substrate 101 may be partially recessed on at least one side of the first gate structure 160 and on one side of the second gate structure 170, and the source / drain region 150 may be provided on the recessed active pattern 105. Therefore, the source / drain region 150 may be provided in the recessed upper portion of the active pattern 105. For example, the source / drain region 150 may be provided on the active pattern 105 and may be provided on at least one side of the first gate structure 160 (or the first gate electrode 165). Therefore, as Figure 2As shown, the active pattern 105 may have a relatively high height below the channel structure 140 and the first and second gate structures 160 and 170. According to an example embodiment of the inventive concept, the active pattern 105 may include impurities, and at least a portion of the active pattern 105 may include impurities of different conductivity types from each other, but the inventive concept is not limited thereto.

[0023] The device isolation layer 110 may define an active pattern 105 on the substrate 101 and may be formed by, for example, a shallow trench isolation (STI) process. For example, the active pattern 105 may be defined by a shallow trench formed in the upper portion of the substrate 101, and the device isolation layer 110 may fill the shallow trench. The device isolation layer 110 may expose the upper sidewall of the active pattern 105. According to an exemplary embodiment of the present invention, the device isolation layer 110 may also include an area extending relatively deeper to the lower portion of the substrate 101 between the active patterns 105. The device isolation layer 110 may have a curved upper surface with a higher level as it is closer to the active pattern 105, but the shape of the upper surface of the device isolation layer 110 is not limited thereto. The device isolation layer 110 may be formed of an insulating material and may be formed of, for example, an oxide, a nitride, or a combination thereof. In an exemplary embodiment of the present invention, the device isolation layer 110 may include an insulating material such as, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), or a combination thereof. Figure 2 As shown, the device isolation layer 110 may have different heights on the lower and outer sides of the first gate structure 160 and the second gate structure 170, but the shape is a shape depending on the manufacturing process, and therefore, the height difference of the upper surface may be variously changed according to an example embodiment of the present invention.

[0024] The channel structure 140 may include two or more channel layers (e.g., a first channel layer 141, a second channel layer 142, and a third channel layer 143) disposed on the active pattern 105 to be spaced apart from each other in a direction perpendicular to the upper surface of the active pattern 105 (e.g., in the Z direction), wherein three channel layers are shown here as an example. The first channel layer 141, the second channel layer 142, and the third channel layer 143 may be spaced apart from the upper surface of the active pattern 105 while being connected to the source / drain region 150. The first channel layer 141, the second channel layer 142, and the third channel layer 143 may have a width that is the same as or similar to that of the active pattern 105 in the Y direction, and may have a width that is the same as or similar to that of the first gate structure 160 in the X direction. However, according to an exemplary embodiment of the inventive concept, the first channel layer 141, the second channel layer 142, and the third channel layer 143 may have a reduced width so that the side surfaces thereof are positioned below the first gate structure 160 in the X direction. The first channel layer 141, the second channel layer 142, and the third channel layer 143 may be formed of a semiconductor material and may include, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). Alternatively, a III-V compound semiconductor may be used for the first channel layer 141, the second channel layer 142, and the third channel layer 143. The first channel layer 141, the second channel layer 142, and the third channel layer 143 may be formed of, for example, the same material as the material of the substrate 101. However, any suitable material may be used for the first channel layer 141, the second channel layer 142, and the third channel layer 143, and the material used may be different from the material of the substrate 101. In an exemplary embodiment of the inventive concept, the number and shape of the channel layers 141, 142, and 143 constituting one channel structure 140 may be variously changed.

[0025] The source / drain region 150 may be disposed on the active pattern 105, on both sides of the channel structure 140, and may be provided as a source region or a drain region of a transistor. The source / drain region 150 may be disposed on the corresponding side surfaces of the first channel layer 141, the second channel layer 142, and the third channel layer 143 of the channel structure 140, and may be disposed so that its lower end covers the upper surface of the active pattern 105. The source / drain region 150 may be disposed by partially concavely concave the upper portion of the active pattern 105, but the inventive concept is not limited thereto. For example, in an exemplary embodiment of the inventive concept, a depression may not be formed, or the depth of the depression may be variously changed. The source / drain region 150 may be a semiconductor layer including silicon (Si), and may be formed by an epitaxial layer. The source / drain region 150 may include impurities of different types and / or concentrations from each other. For example, the source / drain region 150 may include n-type doped silicon (Si) and / or p-type doped silicon germanium (SiGe). The p-type dopant may include, for example, boron (B), aluminum (Al), gallium (Ga), indium (In), or a combination thereof, and the n-type dopant may include, for example, phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), or a combination thereof. In an example embodiment of the inventive concept, the source / drain region 150 may include a plurality of regions including elements and / or doping elements having different concentrations from each other. In an example embodiment of the inventive concept, the dopant may be in-situ injected into the source / drain region 150 during a selective epitaxial growth (SEG) process for forming the source / drain region 150. In an example embodiment of the inventive concept, the dopant may be injected or implanted into the source / drain region 150 after the SEG process for forming the source / drain region 150. For example, after the SEG process, an ion implantation process may be used to inject the dopant into the source / drain region 150.

[0026] The first gate structure 160 may be disposed to extend in one direction (e.g., in the Y direction) on the active pattern 105 and the channel structure 140 while intersecting the active pattern 105 and the channel structure 140. A channel region of the transistor may be formed in the active pattern 105 and the channel structure 140 at a location where the active pattern 105 intersects with the first gate structure 160. The first gate structure 160 may include a first gate electrode 165, a first gate dielectric layer 162 disposed between the first gate electrode 165 and the plurality of channel layers 141, 142, and 143, a first spacer layer 164 disposed on a side surface of the first gate electrode 165, and a first gate capping layer 166 disposed on an upper surface of the first gate electrode 165.

[0027] The first gate dielectric layer 162 may be disposed between the active pattern 105 and the first gate electrode 165 and between the channel structure 140 and the first gate electrode 165, and may be disposed to cover at least a portion of the surface of the first gate electrode 165. For example, the first gate dielectric layer 162 may be disposed to surround all surfaces of the first gate electrode 165 except the uppermost surface of the first gate electrode 165. The first gate dielectric layer 162 may extend between the first gate electrode 165 and the first spacer layer 164, but the inventive concept is not limited thereto. The first gate dielectric layer 162 may include, for example, an oxide, a nitride, or a high-k material. The high-k material may refer to a material having a higher dielectric constant than silicon oxide (SiO 2 ) film has a high dielectric constant. The high-k material can be, for example, aluminum oxide (Al 2 O 3 ), Tantalum Oxide (Ta 2 O 5 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), zirconium silicon oxide (ZrSi x O y ), hafnium oxide (HfO 2 ), Hafnium Silicon Oxide (HfSi x O y ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium zirconium oxide (HfZr x O y ), Hafnium Tantalum Oxide (HfTa x O y ), hafnium aluminum oxide (HfAl x O y ), barium titanium oxide (BaTi x O y ), Strontium Titanium Oxide (SrTi x O y ) or praseodymium oxide (Pr 2 O 3 ). The first gate dielectric layer 162 may be formed of a single layer or may be formed of a plurality of layers. For example, in an exemplary embodiment of the present inventive concept, the first gate dielectric layer 162 may be formed of at least one silicon oxide (SiO 2 ) layer and at least one high-k dielectric layer.

[0028] The first gate electrode 165 may be disposed on the active pattern 105 to fill between the plurality of channel layers 141, 142, and 143, and extend to an upper portion of the channel structure 140, and may be spaced apart from the plurality of channel layers 141, 142, and 143 by the first gate dielectric layer 162. The first gate electrode 165 may include a conductive material, such as a metal nitride (such as, for example, titanium nitride (TiN), tantalum nitride (TaN), molybdenum nitride (MoN), niobium nitride (NbN), or tungsten nitride (WN)) and / or a metal material (such as, for example, aluminum (Al), titanium (Ti), tantalum (Ta), copper (Cu), tungsten (W), or molybdenum (Mo)) or a semiconductor material (such as, for example, doped polysilicon (p-Si)). The first gate electrode 165 may be formed of two or more layers. For example, in an exemplary embodiment of the present inventive concept, the first gate electrode 165 may be formed of two layers including a metal nitride layer and a metal layer, wherein the metal nitride layer serves as a work function adjustment layer for adjusting the threshold voltage of the transistor and the metal layer has a lower resistance than the metal nitride layer. Alternatively, the first gate electrode 165 may be formed of two layers including a metal carbide layer and a metal layer.

[0029] The first spacer layer 164 may be disposed on both sides of the first gate electrode 165 and may extend in the Z direction perpendicular to the upper surface of the substrate 101. The first spacer layer 164 may insulate the source / drain region 150 and the first gate electrode 165 and may extend along the first gate electrode 165 in the second direction (e.g., the Y direction). In an exemplary embodiment of the present invention, the first spacer layer 164 may also be formed as a multilayer structure. The first spacer layer 164 may be formed of, for example, an oxide, a nitride, or a nitride oxide, and specifically, may be formed of a low dielectric constant film. For example, in an exemplary embodiment of the present invention, each first spacer layer 164 may have a dielectric constant composed of silicon oxide (SiO 2 ) layer, silicon oxynitride (SiON) layer, silicon oxycarbide (SiOC) layer, silicon carbon nitride (SiCN) layer, silicon oxycarbon nitride (SiOCN) layer and silicon nitride (Si 3 N 4 ) layers to form a multilayer structure of at least two of the above layers.

[0030] The first gate capping layer 166 may be disposed on the first gate electrode 165 and may be disposed to extend along the upper surface of the first gate electrode 165 in the second direction (e.g., in the Y direction). The side surface of the first gate capping layer 166 may be surrounded by the first spacer layer 164. The upper surface of the first gate capping layer 166 may be substantially coplanar with the upper surface of the first spacer layer 164, but the inventive concept is not limited thereto. The first gate capping layer 166 may be formed of oxide, nitride, or oxynitride, and specifically, may include, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), at least one of silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxynitride (SiON) and silicon oxycarbon nitride (SiOCN).

[0031] Refer to Figure 1 , Figure 2 and Figure 3 , the semiconductor structure 120 may be disposed on the active pattern 105 adjacent to the first edge portion E1 of the active pattern 105 and have a pair of second side surfaces S2 opposite to each other in a second direction (e.g., the Y direction). The semiconductor structure 120 may have a second edge portion E2 connected to the second side surface S2 and exposed toward the separation region SR. The opposite side of the second edge portion E2 of the semiconductor structure 120 may be disposed to contact the source / drain region 150. The second edge portion E2 of the semiconductor structure 120 may be at least partially coplanar with the first edge portion E1 of the active pattern 105, for example, on a plane parallel to the YZ plane, and the second side surface S2 of the semiconductor structure 120 may be at least partially coplanar with the first side surface S1 of the active pattern 105, for example, on a plane parallel to the XZ plane, but the inventive concept is not limited thereto.

[0032] The semiconductor structure 120 may include a first semiconductor layer 121 and a second semiconductor layer 122 alternately stacked on the active pattern 105. Both the first semiconductor layer 121 and the second semiconductor layer 122 may be arranged to be spaced apart from each other in a direction perpendicular to the upper surface of the active pattern 105 (e.g., in the Z direction), and may be connected to the source / drain region 150. For example, the first semiconductor layers 121 adjacent to each other may be spaced apart from each other in the Z direction and the second semiconductor layer 122 may be interposed therebetween. The alternately stacked first semiconductor layers 121 and the second semiconductor layers 122 may overlap each other vertically. The second semiconductor layer 122 may be arranged to have a thickness substantially the same as that of the first channel layer 141, the second channel layer 142, and the third channel layer 143 and a height from the upper surface of the active pattern 105, respectively, and a height from the upper surface of the active pattern 105. In an example embodiment of the present inventive concept, each second semiconductor layer 122 is disposed at the same height as the height of a corresponding one of the first channel layer 141, the second channel layer 142, and the third channel layer 143, and is in contact with the source / drain region 150. In an example embodiment of the present inventive concept, the second semiconductor layer 122 may be a dummy channel layer that is not used as a channel layer in a transistor. The first semiconductor layer 121 may be disposed at a height substantially the same as the height of the first gate electrode 165 and the first gate dielectric layer 162 disposed between the active pattern 105 and the first channel layer 141, between the first channel layer 141 and the second channel layer 142, and between the second channel layer and the third channel layer 143, respectively. In an example embodiment of the present inventive concept, the first semiconductor layer 121 may be a dummy gate electrode that is not used as a gate electrode in a transistor. In an example embodiment of the present inventive concept, a lower surface (or bottom surface) of the lowermost one of the first semiconductor layers 121 may be higher than an upper surface of the device isolation layer 110.

[0033] The first semiconductor layer 121 and the second semiconductor layer 122 include a semiconductor material (the semiconductor material includes, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge)), but may include different materials and may include impurities or may not include impurities. The first semiconductor layer 121 may be formed of a material having an etching selectivity relative to the material of the second semiconductor layer 122. The second semiconductor layer 122 may be formed of the same material as the plurality of channel layers 141, 142, and 143, or may also be formed of the same material as the substrate 101.

[0034] The barrier layer 130 may be a layer covering the semiconductor structure 120, and may cover at least one of the upper surface, the second side surface S2, and the second edge portion E2 of the semiconductor structure 120. For example, in an example embodiment of the present inventive concept, the barrier layer 130 may cover the upper surface and the second side surface S2 of the semiconductor structure 120. The barrier layer 130 may cover the first side surface S1 of the active pattern 105 and the second side surface S2 of the semiconductor structure 120. In an example embodiment of the present inventive concept, the barrier layer 130 may partially cover the second side surface S2 of the semiconductor structure 120, or may cover the entire second side surface S2. For example, the barrier layer 130 may extend between the first side surface S1 of the active pattern 105 and the second gate electrode 175, and between the second side surface S2 of the semiconductor structure 120 and the second gate electrode 175. The barrier layer 130 may be disposed between the semiconductor structure 120 and the second gate electrode 175 covering the semiconductor structure 120. The barrier layer 130 may have a portion covering the upper surface of the semiconductor structure 120 and a portion extending between the first edge portion E1 of the active pattern 105 and the second gate electrode 175 and between the second edge portion E2 of the semiconductor structure 120 and the second gate electrode 175. The lower portion of the barrier layer 130 may further extend downward below the upper surface of the semiconductor structure 120 and / or the active pattern 105 to contact the device isolation layer 110, but the inventive concept is not limited thereto. The device isolation layer 110 may contact the first side surface S1 and the first edge portion E1 of the active pattern 105, wherein the lower surface of the barrier layer 130 may contact the upper surface of the device isolation layer 110. In an example embodiment of the inventive concept, the shape, thickness, and area of ​​the barrier layer 130 covering the semiconductor structure 120 may be variously changed. For example, the thickness of the barrier layer 130 covering the second side surface S2 of the semiconductor structure 120 and the thickness of the barrier layer 130 covering the second edge portion E2 of the semiconductor structure 120 may be the same as or different from each other. The thickness of the barrier layer 130 covering the upper surface of the semiconductor structure 120 may be relatively thin.

[0035] According to an example embodiment of the inventive concept, when the semiconductor device is a FinFET transistor, the semiconductor structure 120 may be a portion of the active pattern 105, or may be a portion of the source / drain region 150. For example, the semiconductor structure 120 may not include the first semiconductor layer 121 and the second semiconductor layer 122 alternately stacked on the active pattern 105. In this case, the barrier layer 130 may cover the active pattern 105 or the source / drain region 150.

[0036] The barrier layer 130 may include a semiconductor material such as, for example, silicon (Si), germanium (Ge), silicon carbide (SiC), or silicon germanium (SiGe). In an exemplary embodiment of the present inventive concept, the barrier layer 130 may be formed of oxide, nitride, or oxynitride, and specifically, may include, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), at least one of silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxynitride (SiON), and silicon oxycarbon nitride (SiOCN), but the inventive concept is not limited thereto. The barrier layer 130 may include a material different from that of the first semiconductor layer 121, and may include a material the same as that of the second semiconductor layer 122. The barrier layer 130 may include a material having an etching selectivity relative to the material of the first semiconductor layer 121 and / or the material of the second semiconductor layer 122, for example, the first semiconductor layer 121 may include silicon germanium (SiGe), and the barrier layer 130 may include silicon (Si). In an example embodiment of the inventive concept, the barrier layer 130 may include an epitaxial layer grown from the semiconductor structure 120, or may also be formed of a plurality of layers doped with impurities of different concentrations. The barrier layer 130 may be an epitaxial layer grown from the semiconductor structure 120, and the impurities may be in-situ injected into the barrier layer 130 during a selective epitaxial growth (SEG) process for forming the barrier layer 130.

[0037] The barrier layer 130 may be a layer that protects the semiconductor structure 120 and the source / drain region 150 during the gate replacement process. In the separation region SR, the second side surface S2 and / or the second edge portion E2 of the semiconductor structure 120 are exposed, but since the barrier layer 130 covers the semiconductor structure 120, when the sacrificial gate electrode layer is removed in a process described later, the barrier layer 130 may prevent the source / drain region 150 adjacent to the separation region SR from being damaged, and if the semiconductor structure 120 is not covered by the barrier layer 130, the first semiconductor layer 121 and / or the second semiconductor layer 122 will be removed. For example, the sacrificial gate electrode layer to be described may have an etching selectivity with respect to the barrier layer 130, and the barrier layer 130 may not be etched by an etchant used to etch the sacrificial gate electrode layer to be described, and as a result, the semiconductor structure 120 covered by the barrier layer 130 may be prevented from being etched. Therefore, a semiconductor device with enhanced reliability may be provided.

[0038] The second gate structure 170 may be disposed to extend in one direction (e.g., in the Y direction) on the active pattern 105 and the semiconductor structure 120 while intersecting the active pattern 105 and the semiconductor structure 120. The second gate structure 170 may include a second gate electrode 175, a second gate dielectric layer 172 disposed between the second gate electrode 175 and the semiconductor structure 120, a second spacer layer 174 disposed on a side surface of the second gate electrode 175, and a second gate capping layer 176 disposed on an upper surface of the second gate electrode 175. In the case where the technical features of the second gate structure 170 are the same as those of the first gate structure 160, the description thereof will be omitted, and the differences will be mainly described.

[0039] The second gate dielectric layer 172 may be disposed between the barrier layer 130 and the second gate electrode 175, may cover the upper surface and the side surface of the barrier layer 130, and may have a portion further extending downward between the barrier layer 130 and the second gate electrode 175 to be lower than the upper surface of the semiconductor structure 120 or the upper surface of the active pattern 105. Therefore, in the second gate dielectric layer 172, the portion disposed between the barrier layer 130 and the second gate electrode 175 may further extend downward below the semiconductor structure 120, for example, below the lower surface of the semiconductor structure 120. The lower surface of the second gate dielectric layer 172 may contact the upper surface of the device isolation layer 110. The second gate dielectric layer 172 may be disposed between the second gate electrode 175 and the device isolation layer 110, but the inventive concept is not limited thereto.

[0040] The second spacer layer 174 may be disposed on both sides of the second gate electrode 175 and may contact the upper portion of the barrier layer 130. The second spacer layer 174 is shown as being in contact with the barrier layer 130 through the inner surface, but the inventive concept is not limited thereto. For example, the lower surface of the second spacer layer 174 may be in contact with the upper surface of the barrier layer 130, or the second spacer layer 174 may not be in contact with the barrier layer 130. At least one of the second spacer layers 174 may be in contact with the semiconductor structure 120. At least one of the second spacer layers 174 may further extend downwardly below the upper surface of the semiconductor structure 120 or the upper surface of the active pattern 105, and at least one of the lower surfaces of the second spacer layers 174 may be in contact with the device isolation layer 110 in the separation region SR. Therefore, at least one of the second spacer layers 174 may further extend to be lower than the semiconductor structure 120, for example, lower than the lower surface of the semiconductor structure 120. However, the inventive concept is not limited thereto.

[0041] The second gate electrode 175 may cover the first edge portion E1 of the active pattern 105 and the second edge portion E2 of the semiconductor structure 120. For example, the second gate electrode 175 may include a portion vertically overlapping the first edge portion E1 of the active pattern 105 and the second edge portion E2 of the semiconductor structure 120. The second gate electrode 175 may cover at least a portion of the semiconductor structure 120, and may include a portion further extending downwardly below the upper surface of the semiconductor structure 120 or the upper surface of the active pattern 105. In an example embodiment of the inventive concept, the second gate electrode 175 may be a dummy gate electrode that is not used as a gate electrode in a transistor.

[0042] The interlayer insulating layer 190 may be disposed to cover the upper surface of the device isolation layer 110, the upper surface of the source / drain region 150, and the upper surfaces of the first gate structure 160 and the second gate structure 170. The interlayer insulating layer 190 may be disposed between the second gate structures 170 in the separation region SR. The interlayer insulating layer 190 may include, for example, at least one of an oxide, a nitride, and an oxynitride, and may include a low dielectric constant material. In an example embodiment of the present inventive concept, the interlayer insulating layer 190 may include silicon oxide (SiO 2 )layer.

[0043] The contact plug 180 may penetrate the interlayer insulating layer 190 to be connected to the source / drain region 150, and may apply an electrical signal to the source / drain region 150. The contact plug 180 may have a strip shape extending in the Y direction when viewed in a top view, and may be formed as shown in FIG. Figure 1As shown, the contact plug 180 is disposed on the source / drain region 150, for example, having a length smaller than the length of the source / drain region 150 in the Y direction. However, the inventive concept is not limited thereto. For example, in an exemplary embodiment of the inventive concept, the contact plug 180 may be disposed to have a length longer than the length of the source / drain region 150 in the Y direction. The contact plug 180 may have an inclined side surface depending on the aspect ratio, wherein the width of the lower portion becomes narrower than the width of the upper portion, but the inventive concept is not limited thereto. The contact plug 180 may extend from the upper portion to, for example, a portion lower than the third channel layer 143, and may extend to a height corresponding to the height of the upper surface of the second channel layer 142, but the inventive concept is not limited thereto. In an exemplary embodiment of the inventive concept, the contact plug 180 may also be disposed to contact along the upper surface of the source / drain region 150 without recessing the source / drain region 150. For example, the lower surface of the contact plug 180 may be formed on the same plane as the plane of the upper surface of the source / drain region 150. The contact plug 180 may include, for example, a metal nitride material such as, for example, titanium nitride (TiN), tantalum nitride (TaN), molybdenum nitride (MoN), niobium nitride (NbN) or tungsten nitride (WN) and / or a metal material such as, for example, aluminum (Al), titanium (Ti), tantalum (Ta), copper (Cu), tungsten (W) or molybdenum (Mo).

[0044] Next, refer to Figures 4 to 10 Each of the semiconductor devices described in one exemplary embodiment of the inventive concept. Figure 1 and Figure 2 The same description as described above will be omitted. Figure 1 and Figure 2 The differences in semiconductor devices are shown.

[0045] Figure 4 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concept. Figure 4 Shown with along Figure 1 The areas corresponding to the cross sections taken by lines II', II-II' and III-III'.

[0046] Reference Figure 4, in the semiconductor device 100A, the lower portion of the barrier layer 130a may cover a portion of the lower surface of the second gate electrode 175. The barrier layer 130a may extend from above the second edge portion E2 of the semiconductor structure 120 and downward to the first edge portion E1 of the active pattern 105 to contact the device isolation layer 110. The barrier layer 130a may include an extension portion extending in parallel with the upper surface of the substrate 101 in a first direction (e.g., X direction). The extension portion may be disposed below the lowermost surface of the second gate electrode 175 and may contact the lower surface of at least one of the second spacer layers 174. After the barrier layer 130a is formed to cover the upper surface, the side surface, and the edge portion of the semiconductor structure 120, the barrier layer 130a may be formed to have a partially concave shape, and the barrier layer 130a may cover the upper surface of the device isolation layer 110 in the separation region SR by a deposition process.

[0047] Since the barrier layer 130a covers the semiconductor structure 120, the barrier layer 130a can prevent the source / drain region 150 adjacent to the separation region SR from being damaged by preventing the semiconductor structure 120 from being etched during a process of removing the sacrificial gate electrode layer to be described. Therefore, a semiconductor device 100A having enhanced reliability can be provided.

[0048] Figure 5 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concept. Figure 5 Shown with along Figure 1 The areas corresponding to the cross sections taken by lines II', II-II' and III-III'.

[0049] Reference Figure 5 , and the above reference Figure 2 Compared to the example embodiments described above, the semiconductor device 100B may be configured in such a manner that a surface of the barrier layer 130b (the surface being disposed on the opposite side of the surface of the barrier layer 130b covering the second edge portion E2 of the semiconductor structure 120) may contact the second spacer layer 174. For example, the second gate electrode 175 may not include a portion that further extends downward below the upper surface of the semiconductor structure 120 or the upper surface of the active pattern 105. The barrier layer 130b may extend from the second side surface S2 and the second edge portion E2 of the semiconductor structure 120 toward the second spacer layer 174 to contact the second spacer layer 174. The barrier layer 130b may be disposed to fill a region between the semiconductor structure 120 and an inner wall of the second spacer layer 174 facing the second edge portion E2 of the semiconductor structure 120. The second gate dielectric layer 172 and the second gate electrode 175 may not be formed between the barrier layer 130b and the inner wall of the second spacer layer 174 facing the second edge portion E2 of the semiconductor structure 120.

[0050] The width of the barrier layer 130b in the X direction between the semiconductor structure 120 and the second spacer layer 174 may be relatively large, and the barrier layer 130b may protect the semiconductor structure 120 and the source / drain region 150 adjacent to the separation region SR. Since the barrier layer 130b having a large width in the X direction covers the semiconductor structure 120 and protects the semiconductor structure 120 and the source / drain region 150, a semiconductor device 100B having enhanced reliability may be provided. According to an example embodiment of the inventive concept, the first width of the semiconductor structure 120 in the X direction and the second width of the barrier layer 130b in the X direction may be variously changed, and the ratio of the first width to the second width may also be variously changed.

[0051] Figure 6 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concept. Figure 6 Shown with along Figure 1 The areas corresponding to the cross sections taken by lines II', II-II' and III-III'.

[0052] Reference Figure 6 , and the above reference Figure 5 Compared to the barrier layer 130b shown in the described example embodiment, the semiconductor device 100C may include an extension portion of the barrier layer 130c extending in parallel to the upper surface of the substrate 101 in the first direction (e.g., in the X direction). The extension portion may contact the lower surface of at least one of the second spacer layers 174. The barrier layer 130c may be formed to have a shape in which the upper surface, the side surface, and the edge portion of the semiconductor structure 120 are covered by the barrier layer 130c in the deposition process and the upper surface of the device isolation layer 110 is covered in the separation region SR by the formation of the barrier layer 130c, and then the barrier layer 130c is partially removed. Since the barrier layer 130c covers the semiconductor structure 120, the barrier layer 130c can prevent the source / drain region 150 adjacent to the separation region SR from being damaged by preventing the semiconductor structure 120 from being etched during the process of removing the sacrificial gate electrode layer to be described. Therefore, a semiconductor device 100C with enhanced reliability can be provided.

[0053] Figure 7 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concept. Figure 7 Shown with along Figure 1 The areas corresponding to the cross sections taken by lines II', II-II' and III-III'.

[0054] Reference Figure 7 , and the above reference Figure 2Compared to the example embodiment described above, the semiconductor device 100D may be configured in such a manner that the barrier layer 130d does not cover the upper surface of the semiconductor structure 120 but may cover the first edge portion E1 and the first side surface S1 of the active pattern 105 and the second edge portion E2 and the second side surface S2 of the semiconductor structure 120. In an example embodiment of the present inventive concept, the barrier layer 130d does not cover the upper surface of the semiconductor structure 120 and may be disposed to fill a region between the semiconductor structure 120 and an inner wall of the second spacer layer 174 facing the second edge portion E2 of the semiconductor structure 120. Since the barrier layer 130d covers the semiconductor structure 120, the barrier layer 130d may prevent the source / drain region 150 adjacent to the separation region SR from being damaged by preventing the semiconductor structure 120 from being etched during a process of removing the sacrificial gate electrode layer to be described. Therefore, a semiconductor device 100D having enhanced reliability may be provided.

[0055] Figure 8 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concept. Figure 8 Shown with along Figure 1 The areas corresponding to the cross sections taken by lines II', II-II' and III-III'.

[0056] Reference Figure 8 , and the above reference Figure 2 Compared to the example embodiments described above, the semiconductor device 100E may be configured in such a manner that the opposite side surface of the surface of the barrier layer 130e in contact with the second edge portion E2 of the semiconductor structure 120 may have a concavo-convex shape. The barrier layer 130e may be an epitaxial layer grown from the semiconductor structure 120, and may have a difference in growth rate at different portions of the semiconductor structure 120 due to different materials being included in the first semiconductor layer 121 and the second semiconductor layer 122. For example, when the first semiconductor layer 121 includes silicon germanium (SiGe) and the second semiconductor layer 122 includes silicon (Si), the growth rate of silicon (Si) at the second semiconductor layer 122 may be faster than the growth rate of silicon (Si) at the first semiconductor layer 121. Therefore, a portion of the barrier layer 130e adjacent to the second semiconductor layer 122 may relatively protrude outward to have a convex shape, and a portion of the barrier layer 130e adjacent to the first semiconductor layer 121 does not relatively protrude outward to have a shape that is concave inward toward the first semiconductor layer 121. However, the shape of the barrier layer 130e may vary depending on the epitaxial layer growth process conditions and is therefore not limited to Figure 8Since the barrier layer 130e covers the semiconductor structure 120, the barrier layer 130e can prevent the source / drain region 150 adjacent to the separation region SR from being damaged by preventing the semiconductor structure 120 from being etched during a process of removing the sacrificial gate electrode layer to be described. Therefore, a semiconductor device 100E with enhanced reliability can be provided.

[0057] Fig.9A is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concept. Fig.9A Shown with along Figure 1 The areas corresponding to the cross sections taken by lines II', II-II' and III-III'.

[0058] Reference Fig.9A , and the above reference Figure 2 Compared to the example embodiments described above, the semiconductor device 100F may be configured in such a manner that the first gate structure 160 may further include an internal spacer layer 161. The internal spacer layer 161 may be disposed between the plurality of channel layers 141, 142, and 143 of the channel structure 140 and between the first channel layer 141 and the active pattern 105 in parallel with the first gate electrode 165, and may be disposed on both sides of the first gate structure 160 in a first direction (e.g., X direction) on the lower surfaces of the first channel layer 141, the second channel layer 142, and the third channel layer 143, respectively. The internal spacer layer 161 may have an outer surface that is substantially coplanar with outer surfaces of the first channel layer 141, the second channel layer 142, and the third channel layer 143. On a lower portion of the third channel layer 143, the first gate electrode 165 may be separated from the source / drain region 150 by the internal spacer layer 161 to be electrically separated therefrom. Similarly, the first gate electrode 165 may be separated from the source / drain region 150 by an internal spacer layer 161 disposed on a lower portion of the second channel layer 142 and by an internal spacer layer 161 disposed on a lower portion of the first channel layer 141. The internal spacer layer 161 may have a shape in which a side facing the first gate electrode 165 is convexly rounded toward the first gate electrode 165 to bulge inwardly, but the inventive concept is not limited thereto. The internal spacer layer 161 may be formed of, for example, an oxide, a nitride, or a nitride oxide, and specifically, may be formed of a low dielectric constant film. In an exemplary embodiment of the inventive concept, the internal spacer layer 161 may include, for example, silicon nitride (Si 3 N 4 ), silicon carbon nitride (SiCN), silicon boron nitride (SiBN), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), silicon boron carbon nitride (SiBCN), silicon oxycarbide (SiOC), silicon oxide (SiO 2) or a combination thereof. In an exemplary embodiment of the present inventive concept, the inner spacer layers 161 may each include an air gap. The inner spacer layers 161 are not limited to Fig.9A In an example embodiment, and in another example embodiment, the semiconductor device may further include an inner spacer layer 161. For example, the above-described semiconductor devices 100A to 100E may each include the inner spacer layer 161.

[0059] Fig. 9B is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concept. Fig. 9B Shown with along Figure 1 The areas corresponding to the cross sections taken by lines II', II-II' and III-III'.

[0060] Fig. 9B FIG. 1 shows a cross section of a semiconductor device 100G including a FinFET, wherein the first gate structure 160 surrounds three surfaces of the active pattern 105 , such as the upper surface of the active pattern 105 and the side surfaces thereof in the Y direction. Figure 2 Compared to the example embodiments of the present invention, the semiconductor device 100G may not include a plurality of channel layers, and a channel region of the transistor may be formed in a portion of the active pattern 105 intersecting the first gate structure 160 .

[0061] In this example embodiment, the semiconductor structure 120 may be disposed on the active pattern 105 adjacent to the separation region SR, and may form a continuous structure with the active pattern 105. The semiconductor structure 120 may also be understood as a region of the active pattern 105 that intersects with the second gate structure 170. The barrier layer 130 may cover at least one of the upper surface and the side surface of the semiconductor structure 120. Since the barrier layer 130 covers the semiconductor structure 120, the barrier layer 130 may prevent the source / drain region 150 adjacent to the separation region SR from being damaged by preventing the semiconductor structure 120 from being etched during the process of removing the sacrificial gate electrode layer to be described. Therefore, a semiconductor device 100G with enhanced reliability may be provided.

[0062] Fig. 9C is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concept. Fig. 9C Shown with along Figure 1 The areas corresponding to the cross sections taken by lines II', II-II' and III-III'.

[0063] Reference Fig. 9C , and the above reference Fig. 9BCompared to the described example embodiments, the semiconductor device 100H including the FinFET may include a fin structure 107 between the source / drain regions 150 on the active pattern 105. The fin structure 107 may include a plurality of first silicon germanium layers 108 and a plurality of first silicon layers 109, and may be provided as a channel region of the transistor. The semiconductor device 100H may include a semiconductor structure 120 adjacent to the separation region SR on the active pattern 105, and the semiconductor structure 120 may include first semiconductor layers 121 and second semiconductor layers 122 that are alternately stacked.

[0064] A plurality of first silicon germanium layers 108 and a plurality of first silicon layers 109 may be alternately stacked on the active pattern 105. Both the plurality of first silicon germanium layers 108 and the plurality of first silicon layers 109 may be disposed to be spaced apart from each other in the Z direction and may be connected to the source / drain region 150 in the X direction. For example, the first silicon germanium layers 108 adjacent to each other may be spaced apart from each other in the Z direction and the first silicon layer 109 may be interposed therebetween. The alternately stacked plurality of first silicon germanium layers 108 and the plurality of first silicon layers 109 may overlap vertically with each other. The lowest first silicon germanium layer 108 of the plurality of first silicon germanium layers 108 may contact the active pattern 105.

[0065] The semiconductor structure 120 may include a first semiconductor layer 121 and a second semiconductor layer 122 alternately stacked on the active pattern 105. The first semiconductor layer 121 and the second semiconductor layer 122 may be arranged to be spaced apart from each other in a direction perpendicular to the upper surface of the active pattern 105 (e.g., in the Z direction), and may be connected to the source / drain region 150 in the X direction. For example, the first semiconductor layers 121 adjacent to each other may be spaced apart from each other in the Z direction and the second semiconductor layer 122 may be interposed between them. The alternately stacked first semiconductor layers 121 and the second semiconductor layers 122 may overlap each other vertically. The first semiconductor layer 121 and the second semiconductor layer 122 may include a semiconductor material (the semiconductor material includes at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge)), but may include different materials and may include impurities or may not include impurities. For example, the first semiconductor layer 121 may include silicon germanium (SiGe), and the second semiconductor layer 122 may include silicon (Si). The barrier layer 130 may cover at least one of the upper surface and the side surface of the semiconductor structure 120. Since the barrier layer 130 covers the semiconductor structure 120, the barrier layer 130 can prevent the source / drain region 150 adjacent to the separation region SR from being damaged by preventing the semiconductor structure 120 from being etched during a process of removing the sacrificial gate electrode layer to be described. Therefore, a semiconductor device 100H having enhanced reliability can be provided.

[0066] In an exemplary embodiment of the present invention, the above reference Fig. 9B and Fig. 9C The semiconductor device described may include an MBCFET as described above in different example embodiments. TM For example, the semiconductor device may include a first transistor region and a second transistor region, and the first transistor region may include the above reference Fig. 9B and / or Fig. 9C The FinFET described above, the second transistor region may include Figures 1 to 9A Description of MBCFET TM .

[0067] Fig.10 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concept. Fig.10 Shown with along Figure 1 The area corresponding to the cross section taken by line II-II'.

[0068] Reference Fig.10 In the case of the semiconductor device 100I, the width of the active pattern 105a and the width of the channel structure 140a may be Figure 2 The active pattern 105a and the channel structure 140a may have relatively small widths, and thus, the plurality of channel layers 141a, 142a, and 143a of the channel structure 140a may have a circular shape or an elliptical shape having a relatively small length difference between a major axis and a minor axis in each cross section along the Y direction. The active pattern 105 may have a rounded top below the plurality of channel layers 141a, 142a, and 143a of the channel structure 140a. For example, in Figure 2 In an example embodiment of the present invention, the plurality of channel layers 141, 142, and 143 may have a width of about 20 nm to 50 nm in the Y direction, and the plurality of channel layers 141a, 142a, and 143a of this embodiment may have a width of about 3 nm to 12 nm in the Y direction. Thus, in an example embodiment of the present inventive concept, the widths of the active pattern 105a and the channel structure 140a and their shapes may be variously changed.

[0069] FIG. 11A to FIG. 19B is a diagram according to a process sequence to describe a method of fabricating a semiconductor device according to an example embodiment of the inventive concept. FIG. 11A to FIG. 19B Show manufacturing Figure 2 An example implementation of a method for a semiconductor device.

[0070] Reference Fig.11A and Fig. 11B, the sacrificial layers 121 ′ and the channel layers 141 , 142 , and 143 may be alternately stacked on the substrate 101 .

[0071] The sacrificial layers 121′ may each be a layer replaced by the first gate dielectric layer 162 and the first gate electrode 165 through a subsequent process, and a portion thereof may be a layer remaining as the first semiconductor layer 121 of the semiconductor structure 120. Some of the channel layers 141, 142, and 143 may be similar to the above-described Figure 2 The sacrificial layer 121' may be formed of a material having an etching selectivity relative to the material of the channel layers 141, 142, and 143. The channel layers 141, 142, and 143 may include a material different from the material of the sacrificial layer 121'. The sacrificial layer 121' and the channel layers 141, 142, and 143 may include, for example, a semiconductor material (the semiconductor material includes at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge)), but may include different materials, or may include impurities or may not include impurities. For example, the sacrificial layer 121' may include silicon germanium (SiGe), and the channel layers 141, 142, and 143 may include silicon (Si).

[0072] The sacrificial layer 121' and the channel layers 141, 142, and 143 may be formed by performing an epitaxial growth process using the substrate 101 as a seed. Each of the sacrificial layer 121' and the channel layers 141, 142, and 143 may have a thickness ranging from about 1.1 to about 1.1. To a thickness in the range of about 100 nm. In an example embodiment of the present inventive concept, the number of layers of the channel layers 141 , 142 , and 143 alternately stacked with the sacrificial layer 121 ′ may be variously changed.

[0073] Reference Fig. 12A and Fig. 12B An active structure may be formed by patterning the stack structure of the sacrificial layer 121 ′ and the channel layers 141 , 142 , and 143 and by removing a portion of the substrate 101 .

[0074] The active structure may include sacrificial layers 121' and channel layers 141, 142, and 143 that are alternately stacked. The active pattern 105 may be formed to protrude from the upper surface of the substrate 101 by removing a portion of the substrate 101. The active structure may be formed in a linear shape extending in one direction (e.g., in the X direction), and may be disposed to be spaced apart from each other in the Y direction. Both the active structure and the active pattern 105 may be disposed to be spaced apart from each other by a predetermined distance in the X direction, and a region from which a portion of the substrate 101 is removed so that the active structure and the active pattern 105 are spaced apart from each other in the X direction may be defined as a separation region SR. The active structure and the active pattern 105 may be divided into a plurality of regions by the separation region SR. A region of the active structure disposed adjacent to the separation region SR may be a region having a shape similar to that of the active structure. Figure 2 The semiconductor structure 120 shown has regions of the same structure.

[0075] The active pattern 105 may protrude from the upper surface of the substrate 101 to have a first side surface S1 and a first edge portion E1 connected to the first side surface S1. When a portion of the substrate 101 is removed, the first side surface S1 and the first edge portion E1 of the active pattern 105 may be exposed.

[0076] In the region where a portion of the substrate 101 is removed, the device isolation layer 110 may be formed by filling an insulating material and recessing the insulating material so that the active pattern 105 protrudes. The upper surface of the device isolation layer 110 may be formed to be lower than the upper surface of the active pattern 105. Therefore, the upper portion of the active pattern 105 may protrude vertically upward from the upper surface of the device isolation layer 110.

[0077] Reference Fig.13A and Fig. 13B , a mask layer 125 may be formed to cover the active pattern 105 , the active structure, and the device isolation layer 110 .

[0078] The mask layer 125 may cover the upper surface and the side surface of the active structure, but may not cover the portion of the active structure adjacent to the separation region SR. The portion of the active structure not covered by the mask layer 125 may be a region in which a semiconductor structure described later will be formed. The mask layer 125 may cover a portion of the first side surface S1 of the active pattern 105, and may cover a portion of the upper surface of the device isolation layer 110 extending in the X direction between the active patterns 105. The mask layer 125 may be formed of, for example, oxide, nitride, or oxynitride, and specifically, may include, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4), at least one of silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxynitride (SiON), and silicon oxycarbon nitride (SiOCN), but the inventive concept is not limited thereto.

[0079] Reference Fig.14A and Fig. 14B , a barrier layer 130 may be formed to cover the exposed region of the active structure and the exposed region of the active pattern 105 .

[0080] The barrier layer 130 may cover the exposed ends and sides of the channel layers 141, 142, and 143, and may be formed to cover the exposed ends and sides of the sacrificial layer 121'. An upper portion of the barrier layer 130 may cover a portion of an upper surface of the third channel layer 143, and a lower portion of the barrier layer 130 may extend downwardly below an upper surface of the active pattern 105 to cover a side surface of the active pattern 105 and contact an upper surface of the device isolation layer 110. The barrier layer 130 may be formed to conformally cover the active pattern 105 and the active structure.

[0081] The barrier layer 130 may be formed by performing an epitaxial growth process using a portion of the active pattern 105 protruding above the upper surface of the device isolation layer 110, the channel layers 141, 142, and 143, and the sacrificial layer 121' as a seed. In an example embodiment of the present inventive concept, the barrier layer 130 may be a layer in which silicon (Si) is grown as an epitaxial layer. In an example embodiment of the present inventive concept, the barrier layer 130 may be formed by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process.

[0082] Reference Fig. 14C and Fig.14D According to an example embodiment of the inventive concept, the initial barrier layer 130' may be formed to completely cover the region not covered by the mask layer 125. The entire upper surface of the device isolation layer 110 not covered by the mask layer 125 may be covered by the initial barrier layer 130'. The initial barrier layer 130' may cover one end and side surfaces of the channel layers 141, 142, and 143, and may cover one end and side surfaces of the sacrificial layer 121'. Subsequently, a portion of the initial barrier layer 130' covering the upper surface of the device isolation layer 110 in the separation region SR may be recessed to form the initial barrier layer 130' and the initial barrier layer 130' having the channel layers 141, 142, and 143, respectively. Figure 4 An extension of Figure 6 The extended portion of the barrier layer 130a or the barrier layer 130c.

[0083] Reference Fig.15A and Fig. 15B, the mask layer 125 is removed, and a first sacrificial gate structure 160 ′, a first spacer layer 164 , a second sacrificial gate structure 170 ′, and a second spacer layer 174 may be formed on the active structure.

[0084] The first sacrificial gate structure 160' may be a sacrificial structure on the channel structure 140, the sacrificial structure being formed on the channel structure 140. Figure 2 The first gate dielectric layer 162 and the first gate electrode 165 are provided in the region shown by subsequent processes. The first sacrificial gate structure 160' may include a first sacrificial gate layer 162' and a second sacrificial gate layer 165' stacked sequentially, and a first gate mask pattern layer 166'. The first sacrificial gate layer 162' and the second sacrificial gate layer 165' may be patterned in an etching process using, for example, the first gate mask pattern layer 166' as an etching mask. The first sacrificial gate layer 162' and the second sacrificial gate layer 165' may be an insulating layer and a conductive layer, respectively, but the inventive concept is not limited thereto, for example, the first sacrificial gate layer 162' and the second sacrificial gate layer 165 may be formed of one layer. For example, the first sacrificial gate layer 162' may include silicon oxide (SiO 2 ), the second sacrificial gate layer 165' may include polysilicon (p-Si). The first gate mask pattern layer 166' may include silicon oxide (SiO 2 ) and / or silicon nitride (Si 3 N 4 ). The first sacrificial gate structure 160' may have a linear shape intersecting the active structure and extending in one direction. The first sacrificial gate structures 160' may extend, for example, in the Y direction and may be spaced apart from each other in the X direction.

[0085] The first spacer layer 164 may be formed on both sidewalls of the first sacrificial gate structure 160'. The first spacer layer 164 may be formed by conformally forming a first spacer film having a uniform thickness along the upper and side surfaces of the first sacrificial gate structure 160' and the active structure, and then performing anisotropic etching. In order to form the first spacer film, a process such as, for example, an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or a combination thereof may be used. The first spacer layer 164 may be formed of a material with a low dielectric constant, and may include, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxynitride (SiON), and silicon oxycarbon nitride (SiOCN). In an exemplary embodiment of the present inventive concept, the first spacer layer 164 may be made of silicon oxide (SiO 2 ) layer, silicon nitride (Si3 N 4 ) layer, a silicon carbon nitride (SiCN) layer, a silicon oxycarbide (SiOC) layer, a silicon oxynitride (SiON) layer, and a silicon oxycarbon nitride (SiOCN) layer are formed as a multilayer of at least two of the following:

[0086] The second sacrificial gate structure 170 ′ may be a sacrificial structure formed in a region on the semiconductor structure 120 , in which the ... Figure 2 A second gate dielectric layer 172 and a second gate electrode 175 are provided as shown. The second sacrificial gate structure 170' may include a third sacrificial gate layer 172' and a fourth sacrificial gate layer 175' stacked sequentially, and a second gate mask pattern layer 176'. The third sacrificial gate layer 172' and the fourth sacrificial gate layer 175' may be patterned in an etching process using, for example, the second gate mask pattern layer 176' as an etching mask. When describing the second sacrificial gate structure 170', the description of the same parts as the first sacrificial gate structure 160' will be omitted. On the other hand, the third sacrificial gate layer 172' and the fourth sacrificial gate layer 175' may be formed to extend toward the upper surface of the device isolation layer 110 between the barrier layer 130 and the second spacer layer 174, respectively. The third sacrificial gate layer 172' may be formed to cover the upper surface and side surfaces of the barrier layer 130.

[0087] The second spacer layers 174 may be formed on both sidewalls of the second sacrificial gate structure 170'. The same description as the first spacer layer 164 will be omitted. At least one of the second spacer layers 174 may be formed to extend further downward below the upper surface of the active pattern 105, and a lower surface of at least one of the second spacer layers 174 may contact the device isolation layer 110 in the separation region SR, but the inventive concept is not limited thereto.

[0088] Reference Fig.16A and Fig. 16B The exposed sacrificial layer 121 ′ and the channel layers 141 , 142 , and 143 between the first sacrificial gate structure 160 ′ and the second sacrificial gate structure 170 ′ are removed, thereby forming the channel structure 140 and the semiconductor structure 120 .

[0089] The exposed sacrificial layer 121' and the channel layers 141, 142, and 143 may be removed using the first sacrificial gate structure 160' and the first spacer layer 164 as an etching mask. As a result, the channel layers 141, 142, and 143 have a defined length in the X direction and form the channel structure 140. According to an example embodiment of the inventive concept, under the first sacrificial gate structure 160', the sacrificial layer 121' and the channel structure 140 are partially removed from the side surface so that both sides thereof in the X direction may be located under the first sacrificial gate structure 160' and the first spacer layer 164.

[0090] In the process of removing the exposed sacrificial layer 121' and the channel layers 141, 142, and 143, the sacrificial layer 121' and the channel layers 141, 142, and 143 adjacent to the separation region SR may remain as shown in FIG. Figure 2 The semiconductor structure 120 adjacent to the separation region SR is shown to include a first semiconductor layer 121 corresponding to the remaining sacrificial layer 121 ′ and a second semiconductor layer 122 corresponding to the remaining channel layers 141 , 142 , and 143 .

[0091] Reference Fig. 16C , the exposed sacrificial layer 121 ′ may be partially removed from the side surface.

[0092] The sacrificial layer 121' may be selectively etched relative to the channel structure 140 by, for example, a wet etching process, and may be removed from the side surface to a predetermined depth in the X direction. The sacrificial layer 121' may have a side surface that is inwardly concave by the side etching as described above. However, the inventive concept is not limited thereto. For example, the shape of the side surface of the sacrificial layer 121' may be different from those shown and described above.

[0093] In a subsequent process, an inner spacer layer 161 may be formed in the region where the sacrificial layer 121' has been removed to obtain Fig.9A The inner spacer layer 161 may be formed by filling the insulating material in the region where the sacrificial layer 121' is removed and removing the insulating material deposited on the outer surface of the channel structure 140. Therefore, each inner spacer layer 161 may be formed as shown in FIG. Fig.9A The inner spacer layer 161 may be formed of the same material as the first spacer layer 164, but the inventive concept is not limited thereto. For example, the inner spacer layer 161 may include, for example, silicon nitride (Si 3 N 4The inner spacer layer 161 may protect the source / drain region 150 .

[0094] Reference Fig.17A and Fig. 17B , on both sides of the first sacrificial gate structure 160', the source / drain region 150 is formed on the active pattern 105, and the interlayer insulating layer 190 can be formed on the source / drain region 150 and on the device isolation layer 110 in the separation region SR, and the sacrificial layer 121' and the first and second sacrificial gate structures 160' and 170' can be removed.

[0095] The source / drain region 150 may be formed by performing an epitaxial growth process. For example, the source / drain region 150 may be formed by performing a selective epitaxial growth (SEG) process using the inner surface of the recessed region of the active pattern 105 as a seed layer. For example, the SEG process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process. The source / drain region 150 may be connected to the plurality of channel layers 141, 142, and 143 of the channel structure 140 through the side surface. The source / drain region 150 may include impurities by in-situ doping, and may also include a plurality of layers having different doping elements and / or doping concentrations. In an exemplary embodiment of the inventive concept, impurities may be included in the source / drain region 150 by in-situ doping during the SEG process for forming the source / drain region 150.

[0096] The interlayer insulating layer 190 may be formed by forming an insulating layer covering the first and second sacrificial gate structures 160' and 170' and the source / drain regions 150 and performing a planarization process. The planarization process of the interlayer insulating layer 190 may be performed using an etch-back process or a chemical mechanical polishing (CMP) process.

[0097] The sacrificial layer 121' and the first and second sacrificial gate structures 160' and 170' may be selectively removed relative to the first and second spacer layers 164 and 174, the interlayer insulating layer 190, and the channel structure 140. First, the first and second sacrificial gate structures 160' and 170' are removed to form an upper gap region UR, and then the sacrificial layer 121' exposed by the upper gap region UR is removed to form a lower gap region LR. The lower gap region LR may be formed by removing the sacrificial layer 121' below the upper gap region UR (which is formed by removing the first sacrificial gate structure 160'), and may not be formed below or beside the upper gap region UR formed by removing the second sacrificial gate structure 170'. For example, when the sacrificial layer 121' includes silicon germanium (SiGe) and the channel structure 140 includes silicon (Si), the sacrificial layer 121' may be selectively removed by performing a wet etching process using peracetic acid (PAA or CH 3 CO 3 H) (which is acetic acid (CH 3 COOH) and hydrogen peroxide (H 2 O 2 ) as an etchant.

[0098] During the removal process, the source / drain region 150 may be protected by the interlayer insulating layer 190 and the barrier layer 130. Since the barrier layer 130 covers the semiconductor structure 120, the barrier layer 130 may prevent the etchant from penetrating through the semiconductor structure 120 from the exposed second side surface S2 or the second edge portion E2 of the semiconductor structure 120 in the separation region SR. Therefore, a portion of the first semiconductor layer 121 whose side surface is exposed by the second side surface S2 or the second edge portion E2 of the semiconductor structure 120 is not etched, thereby preventing the source / drain region 150 from being damaged. Since the barrier layer 130 covering the semiconductor structure 120 to protect the source / drain region 150 is formed, a semiconductor device with enhanced reliability may be manufactured.

[0099] Reference Fig.18A and Fig.18B , a first gate dielectric layer 162 and a second gate dielectric layer 172 may be formed in the upper gap region UR and the lower gap region LR, respectively, for the first gate structure 160 and the second gate structure 170. The first gate dielectric layer 162 may include, for example, oxide, nitride, or high-k material, and may be formed of a single layer or multiple layers.

[0100] The first gate dielectric layer 162 and the second gate dielectric layer 172 may be formed to conformally cover the inner surface of the upper gap region UR and the inner surface of the lower gap region LR. For example, the first gate dielectric layer 162 and the second gate dielectric layer 172 may be formed by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process.

[0101] Reference Fig.19A and Fig.19B , a first gate electrode 165 and a second gate electrode 175 may be formed on the first gate dielectric layer 162 and the second gate dielectric layer 172 , respectively, to fill the upper gap region UR and the lower gap region LR, and a first gate cap layer 166 and a second gate cap layer 176 may be formed on the first gate electrode 165 and the second gate electrode 175 , respectively.

[0102] The first gate electrode 165 and the second gate electrode 175 are formed to completely fill the upper gap region UR and the lower gap region LR, and then may be removed from the upper portion of the upper gap region UR to a predetermined depth. The first gate capping layer 166 and the second gate capping layer 176 may be formed in the region where the first gate electrode 165 and the second gate electrode 175 are removed from the upper gap region UR. The side surfaces of the first gate capping layer 166 and the side surfaces of the second gate capping layer 176 may be surrounded by the first spacer layer 164 and the second spacer layer 174, respectively. The upper surfaces of the first gate capping layer 166 and the second gate capping layer 176 may be substantially coplanar with the upper surfaces of the first spacer layer 164 and the second spacer layer 174. Therefore, a first gate structure 160 and a second gate structure 170 can be formed, the first gate structure 160 includes a first gate dielectric layer 162, a first gate electrode 165, a first spacer layer 164 and a first gate cap layer 166, and the second gate structure 170 includes a second gate dielectric layer 172, a second gate electrode 175, a second spacer layer 174 and a second gate cap layer 176.

[0103] Next, refer to Figure 2 , a contact plug 180 may be formed.

[0104] First, the interlayer insulating layer 190 may be patterned to form a contact hole, and the contact hole may be filled with a conductive material to form a contact plug 180. The contact hole may be formed by removing a portion of the interlayer insulating layer 190 on at least one side of the first gate structure 160 and on one side of the second gate structure 170 using a separate mask layer such as a photoresist pattern as an etching mask in an etching process. The photoresist pattern may be formed by a photolithography process. The lower surface of the contact hole may be recessed into the source / drain region 150, or may have a curved shape along the upper surface of the source / drain region 150. In an exemplary embodiment of the inventive concept, the shape and arrangement of the contact plug 180 may be variously changed.

[0105] As set forth above, according to an example embodiment of the inventive concept, a semiconductor device having enhanced reliability may be provided by providing a barrier layer covering a semiconductor structure exposed in a separation region to protect a source / drain region.

[0106] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the spirit and scope of the inventive concept as defined by the appended claims.

[0107] This application claims the benefit of Korean Patent Application No. 10-2019-0171517 filed on December 20, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: an active pattern extending in a first direction on the substrate and having a pair of first side surfaces opposite to each other and a first edge portion connected to the first side surfaces; a plurality of channel layers vertically spaced apart from each other on the active pattern; a first gate electrode extending in a second direction on the substrate while intersecting the active pattern and the plurality of channel layers and surrounding the plurality of channel layers; a source / drain region disposed on the active pattern, on at least one side of the first gate electrode, and in contact with the plurality of channel layers; a semiconductor structure disposed adjacent to the first edge portion of the active pattern and having a pair of second side surfaces opposite to each other and a second edge portion connected to the second side surface, the semiconductor structure comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on the active pattern; a second gate electrode extending in the second direction on the substrate and covering the first edge portion of the active pattern and the second edge portion of the semiconductor structure; as well as A barrier layer is disposed between the semiconductor structure and the second gate electrode. 2 . The semiconductor device of claim 1 , wherein the barrier layer extends between the first edge portion of the active pattern and the second gate electrode and between the second edge portion of the semiconductor structure and the second gate electrode. 3 . The semiconductor device according to claim 1 , wherein the barrier layer covers an upper surface and the second side surface of the semiconductor structure. 4 . The semiconductor device according to claim 1 , wherein a lower portion of the barrier layer is disposed to cover a portion of a lower surface of the second gate electrode. 5 . The semiconductor device according to claim 1 , wherein the barrier layer has a concavo-convex shape on one surface opposite to a surface contacting the second edge portion of the semiconductor structure. 6 . The semiconductor device according to claim 1 , wherein the barrier layer comprises a material different from a material of the plurality of first semiconductor layers. 7 . The semiconductor device according to claim 1 , wherein the barrier layer comprises a same material as that of the plurality of second semiconductor layers. 8 . The semiconductor device of claim 1 , wherein the barrier layer comprises an epitaxial layer grown from the semiconductor structure. 9 . The semiconductor device according to claim 1 , wherein the barrier layer comprises at least one of silicon, germanium, silicon germanium, silicon carbide, and silicon nitride. 10 . The semiconductor device according to claim 1 , further comprising a contact plug disposed on the source / drain region and connected to the source / drain region.

11. The semiconductor device according to claim 1 , further comprising a device isolation layer contacting the first side surface and the first edge portion of the active pattern, The lower surface of the barrier layer contacts the upper surface of the device isolation layer.

12. The semiconductor device according to claim 1, further comprising an internal spacer layer, which is arranged on both sides of the first gate electrode in the first direction, and has an outer surface coplanar with outer surfaces of the plurality of channel layers on respective lower surfaces of the plurality of channel layers.

13. A semiconductor device comprising: an active pattern extending in a first direction on the substrate, divided into a plurality of regions by a separation region, and having a first edge portion exposed toward the separation region; a first channel layer, a second channel layer, and a third channel layer, which are vertically spaced apart from each other and are sequentially disposed on the active pattern; a first gate electrode extending in a second direction on the substrate while intersecting the active pattern and surrounding the first channel layer, the second channel layer and the third channel layer; a source / drain region disposed on the active pattern, on at least one side of the first gate electrode, and contacting the first channel layer, the second channel layer, and the third channel layer; a semiconductor structure including a first semiconductor layer and a second semiconductor layer alternately stacked on the active pattern and having a second edge portion exposed toward the separation region; as well as A barrier layer covers at least one of an upper surface, a side surface and the second edge portion of the semiconductor structure. The semiconductor device according to claim 13 , wherein the barrier layer covers the upper surface of the semiconductor structure. 15 . The semiconductor device according to claim 13 , wherein the barrier layer comprises a material different from a material of the first semiconductor layer.

16. The semiconductor device according to claim 13, further comprising: a second gate electrode extending in the second direction on the substrate while intersecting the active pattern and covering at least a portion of the semiconductor structure; a gate dielectric layer disposed between the barrier layer and the second gate electrode; and A spacer layer is disposed on both side surfaces of the second gate electrode. 17 . The semiconductor device according to claim 16 , wherein the gate dielectric layer covers an upper surface and side surfaces of the barrier layer and includes a portion disposed between the barrier layer and the second gate electrode and further extending downwardly below the semiconductor structure. 18 . The semiconductor device of claim 16 , wherein at least one of the spacer layers further extends below the semiconductor structure. 19 . The semiconductor device according to claim 13 , wherein each of the second semiconductor layers is disposed at the same height as a height of a corresponding one of the first channel layer, the second channel layer, and the third channel layer, and is in contact with the source / drain region.

20. A semiconductor device comprising: an active pattern extending in a first direction on the substrate and divided into a plurality of regions by separation regions; a semiconductor structure disposed on the active pattern adjacent to the separation region; a first gate electrode extending in a second direction on the substrate while intersecting the active pattern; a second gate electrode extending in the second direction on the substrate while intersecting the semiconductor structure and covering the semiconductor structure; a source / drain region disposed on the active pattern and on at least one side of the first gate electrode; as well as A barrier layer covers the semiconductor structure.

Images